1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac_private.h,v 1.2 2006/10/06 18:59:27 ariff Exp $ 27 * $DragonFly: src/sys/dev/sound/pci/hda/hdac_private.h,v 1.2 2007/01/20 21:32:36 swildner Exp $ 28 */ 29 30 #ifndef _HDAC_PRIVATE_H_ 31 #define _HDAC_PRIVATE_H_ 32 33 34 /**************************************************************************** 35 * Miscellanious defines 36 ****************************************************************************/ 37 #define HDAC_DMA_ALIGNMENT 128 38 #define HDAC_CODEC_MAX 16 39 40 #define HDAC_MTX_NAME "hdac driver mutex" 41 42 /**************************************************************************** 43 * Helper Macros 44 ****************************************************************************/ 45 #define HDAC_READ_1(mem, offset) \ 46 bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset)) 47 #define HDAC_READ_2(mem, offset) \ 48 bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset)) 49 #define HDAC_READ_4(mem, offset) \ 50 bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset)) 51 #define HDAC_WRITE_1(mem, offset, value) \ 52 bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 53 #define HDAC_WRITE_2(mem, offset, value) \ 54 bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 55 #define HDAC_WRITE_4(mem, offset, value) \ 56 bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 57 58 #define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss)) 59 #define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss)) 60 #define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss)) 61 #define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss)) 62 #define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss)) 63 #define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 64 #define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss)) 65 #define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 66 #define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 67 68 #define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss)) 69 #define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss)) 70 #define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss)) 71 #define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss)) 72 #define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss)) 73 #define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 74 #define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 75 #define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 76 77 #define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss)) 78 #define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss)) 79 #define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss)) 80 #define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss)) 81 #define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss)) 82 #define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 83 #define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 84 #define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 85 86 87 /**************************************************************************** 88 * struct hdac_mem 89 * 90 * Holds the resources necessary to describe the physical memory associated 91 * with the device. 92 ****************************************************************************/ 93 struct hdac_mem { 94 struct resource *mem_res; 95 int mem_rid; 96 bus_space_tag_t mem_tag; 97 bus_space_handle_t mem_handle; 98 }; 99 100 /**************************************************************************** 101 * struct hdac_irq 102 * 103 * Holds the resources necessary to describe the irq associated with the 104 * device. 105 ****************************************************************************/ 106 struct hdac_irq { 107 struct resource *irq_res; 108 int irq_rid; 109 void *irq_handle; 110 }; 111 112 /**************************************************************************** 113 * struct hdac_dma 114 * 115 * This structure is used to hold all the information to manage the dma 116 * states. 117 ****************************************************************************/ 118 struct hdac_dma { 119 bus_dma_tag_t dma_tag; 120 bus_dmamap_t dma_map; 121 bus_addr_t dma_paddr; 122 caddr_t dma_vaddr; 123 }; 124 125 /**************************************************************************** 126 * struct hdac_rirb 127 * 128 * Hold a response from a verb sent to a codec received via the rirb. 129 ****************************************************************************/ 130 struct hdac_rirb { 131 uint32_t response; 132 uint32_t response_ex; 133 }; 134 135 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f 136 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0 137 #define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010 138 139 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \ 140 (((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \ 141 HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET) 142 143 /**************************************************************************** 144 * struct hdac_command_list 145 * 146 * This structure holds the list of verbs that are to be sent to the codec 147 * via the corb and the responses received via the rirb. It's allocated by 148 * the codec driver and is owned by it. 149 ****************************************************************************/ 150 struct hdac_command_list { 151 int num_commands; 152 uint32_t *verbs; 153 uint32_t *responses; 154 }; 155 156 typedef int nid_t; 157 158 struct hdac_softc; 159 /**************************************************************************** 160 * struct hdac_codec 161 * 162 ****************************************************************************/ 163 struct hdac_codec { 164 int verbs_sent; 165 int responses_received; 166 nid_t cad; 167 struct hdac_command_list *commands; 168 struct hdac_softc *sc; 169 }; 170 171 struct hdac_bdle { 172 volatile uint32_t addrl; 173 volatile uint32_t addrh; 174 volatile uint32_t len; 175 volatile uint32_t ioc; 176 } __packed; 177 178 #define HDA_MAX_CONNS 32 179 #define HDA_MAX_NAMELEN 32 180 181 struct hdac_devinfo; 182 183 struct hdac_widget { 184 nid_t nid; 185 int type; 186 int enable; 187 int nconns, selconn; 188 uint32_t pflags, ctlflags; 189 nid_t conns[HDA_MAX_CONNS]; 190 char name[HDA_MAX_NAMELEN]; 191 struct hdac_devinfo *devinfo; 192 struct { 193 uint32_t widget_cap; 194 uint32_t outamp_cap; 195 uint32_t inamp_cap; 196 uint32_t supp_stream_formats; 197 uint32_t supp_pcm_size_rate; 198 uint32_t eapdbtl; 199 int outpath; 200 } param; 201 union { 202 struct { 203 uint32_t config; 204 uint32_t cap; 205 uint32_t ctrl; 206 } pin; 207 } wclass; 208 }; 209 210 struct hdac_audio_ctl { 211 struct hdac_widget *widget, *childwidget; 212 int enable; 213 int index; 214 int mute, step, size, offset; 215 int left, right; 216 uint32_t muted; 217 int ossdev; 218 uint32_t dir, ossmask, ossval; 219 }; 220 221 /**************************************************************************** 222 * struct hdac_devinfo 223 * 224 * Holds all the parameters of a given codec function group. This is stored 225 * in the ivar of each child of the hdac bus 226 ****************************************************************************/ 227 struct hdac_devinfo { 228 device_t dev; 229 uint16_t vendor_id; 230 uint16_t device_id; 231 uint8_t revision_id; 232 uint8_t stepping_id; 233 uint8_t node_type; 234 nid_t nid; 235 nid_t startnode, endnode; 236 int nodecnt; 237 struct hdac_codec *codec; 238 struct hdac_widget *widget; 239 union { 240 struct { 241 uint32_t outamp_cap; 242 uint32_t inamp_cap; 243 uint32_t supp_stream_formats; 244 uint32_t supp_pcm_size_rate; 245 int ctlcnt, pcnt, rcnt; 246 struct hdac_audio_ctl *ctl; 247 uint32_t mvol; 248 uint32_t quirks; 249 int ossidx; 250 int playcnt, reccnt; 251 int parsing_strategy; 252 } audio; 253 /* XXX undefined: modem, hdmi. */ 254 } function; 255 }; 256 257 struct hdac_chan { 258 struct snd_dbuf *b; 259 struct pcm_channel *c; 260 struct pcmchan_caps caps; 261 struct hdac_devinfo *devinfo; 262 struct hdac_dma bdl_dma; 263 uint32_t spd, fmt, fmtlist[8], pcmrates[16]; 264 uint32_t supp_stream_formats, supp_pcm_size_rate; 265 int ptr, prevptr, blkcnt, blksz; 266 int dir; 267 int off; 268 int sid; 269 int bit16, bit32; 270 nid_t io[16]; 271 }; 272 273 /**************************************************************************** 274 * struct hdac_softc 275 * 276 * This structure holds the current state of the hdac driver. 277 ****************************************************************************/ 278 struct hdac_softc { 279 device_t dev; 280 device_t hdabus; 281 struct spinlock *lock; 282 283 struct intr_config_hook intrhook; 284 285 struct hdac_mem mem; 286 struct hdac_irq irq; 287 uint32_t pci_subvendor; 288 289 290 int num_iss; 291 int num_oss; 292 int num_bss; 293 int support_64bit; 294 int streamcnt; 295 296 int corb_size; 297 struct hdac_dma corb_dma; 298 int corb_wp; 299 300 int rirb_size; 301 struct hdac_dma rirb_dma; 302 int rirb_rp; 303 304 struct hdac_chan play, rec; 305 bus_dma_tag_t chan_dmat; 306 int chan_size; 307 int chan_blkcnt; 308 309 #define HDAC_UNSOLQ_MAX 64 310 #define HDAC_UNSOLQ_READY 0 311 #define HDAC_UNSOLQ_BUSY 1 312 int unsolq_rp; 313 int unsolq_wp; 314 int unsolq_st; 315 uint32_t unsolq[HDAC_UNSOLQ_MAX]; 316 317 struct hdac_codec *codecs[HDAC_CODEC_MAX]; 318 319 int registered; 320 }; 321 322 /**************************************************************************** 323 * struct hdac_command flags 324 ****************************************************************************/ 325 #define HDAC_COMMAND_FLAG_WAITOK 0x0000 326 #define HDAC_COMMAND_FLAG_NOWAIT 0x0001 327 328 #endif 329