1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac_private.h,v 1.6.2.3 2007/07/12 06:39:08 ariff Exp $ 27 */ 28 29 #ifndef _HDAC_PRIVATE_H_ 30 #define _HDAC_PRIVATE_H_ 31 32 33 /**************************************************************************** 34 * Miscellaneous defines 35 ****************************************************************************/ 36 #define HDAC_DMA_ALIGNMENT 128 37 #define HDAC_CODEC_MAX 16 38 39 #define HDAC_MTX_NAME "hdac driver mutex" 40 41 /**************************************************************************** 42 * Helper Macros 43 ****************************************************************************/ 44 #define HDAC_READ_1(mem, offset) \ 45 bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset)) 46 #define HDAC_READ_2(mem, offset) \ 47 bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset)) 48 #define HDAC_READ_4(mem, offset) \ 49 bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset)) 50 #define HDAC_WRITE_1(mem, offset, value) \ 51 bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 52 #define HDAC_WRITE_2(mem, offset, value) \ 53 bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 54 #define HDAC_WRITE_4(mem, offset, value) \ 55 bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 56 57 #define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss)) 58 #define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss)) 59 #define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss)) 60 #define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss)) 61 #define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss)) 62 #define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 63 #define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss)) 64 #define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 65 #define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 66 67 #define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss)) 68 #define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss)) 69 #define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss)) 70 #define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss)) 71 #define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss)) 72 #define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 73 #define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 74 #define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 75 76 #define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss)) 77 #define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss)) 78 #define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss)) 79 #define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss)) 80 #define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss)) 81 #define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 82 #define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 83 #define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 84 85 86 /**************************************************************************** 87 * Custom hdac malloc type 88 ****************************************************************************/ 89 MALLOC_DECLARE(M_HDAC); 90 91 /**************************************************************************** 92 * struct hdac_mem 93 * 94 * Holds the resources necessary to describe the physical memory associated 95 * with the device. 96 ****************************************************************************/ 97 struct hdac_mem { 98 struct resource *mem_res; 99 int mem_rid; 100 bus_space_tag_t mem_tag; 101 bus_space_handle_t mem_handle; 102 }; 103 104 /**************************************************************************** 105 * struct hdac_irq 106 * 107 * Holds the resources necessary to describe the irq associated with the 108 * device. 109 ****************************************************************************/ 110 struct hdac_irq { 111 struct resource *irq_res; 112 int irq_rid; 113 int irq_type; 114 void *irq_handle; 115 }; 116 117 /**************************************************************************** 118 * struct hdac_dma 119 * 120 * This structure is used to hold all the information to manage the dma 121 * states. 122 ****************************************************************************/ 123 struct hdac_dma { 124 bus_dma_tag_t dma_tag; 125 bus_dmamap_t dma_map; 126 bus_addr_t dma_paddr; 127 bus_size_t dma_size; 128 caddr_t dma_vaddr; 129 }; 130 131 /**************************************************************************** 132 * struct hdac_rirb 133 * 134 * Hold a response from a verb sent to a codec received via the rirb. 135 ****************************************************************************/ 136 struct hdac_rirb { 137 uint32_t response; 138 uint32_t response_ex; 139 }; 140 141 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f 142 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0 143 #define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010 144 145 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \ 146 (((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \ 147 HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET) 148 149 /**************************************************************************** 150 * struct hdac_command_list 151 * 152 * This structure holds the list of verbs that are to be sent to the codec 153 * via the corb and the responses received via the rirb. It's allocated by 154 * the codec driver and is owned by it. 155 ****************************************************************************/ 156 struct hdac_command_list { 157 int num_commands; 158 uint32_t *verbs; 159 uint32_t *responses; 160 }; 161 162 typedef int nid_t; 163 164 struct hdac_softc; 165 /**************************************************************************** 166 * struct hdac_codec 167 * 168 ****************************************************************************/ 169 struct hdac_codec { 170 int verbs_sent; 171 int responses_received; 172 nid_t cad; 173 struct hdac_command_list *commands; 174 struct hdac_softc *sc; 175 }; 176 177 struct hdac_bdle { 178 volatile uint32_t addrl; 179 volatile uint32_t addrh; 180 volatile uint32_t len; 181 volatile uint32_t ioc; 182 } __packed; 183 184 #define HDA_MAX_CONNS 32 185 #define HDA_MAX_NAMELEN 32 186 187 struct hdac_devinfo; 188 189 struct hdac_widget { 190 nid_t nid; 191 int type; 192 int enable; 193 int nconns, selconn; 194 uint32_t pflags, ctlflags; 195 nid_t conns[HDA_MAX_CONNS]; 196 char name[HDA_MAX_NAMELEN]; 197 struct hdac_devinfo *devinfo; 198 struct { 199 uint32_t widget_cap; 200 uint32_t outamp_cap; 201 uint32_t inamp_cap; 202 uint32_t supp_stream_formats; 203 uint32_t supp_pcm_size_rate; 204 uint32_t eapdbtl; 205 int outpath; 206 } param; 207 union { 208 struct { 209 uint32_t config; 210 uint32_t cap; 211 uint32_t ctrl; 212 } pin; 213 } wclass; 214 }; 215 216 struct hdac_audio_ctl { 217 struct hdac_widget *widget, *childwidget; 218 int enable; 219 int index; 220 int mute, step, size, offset; 221 int left, right; 222 uint32_t muted; 223 int ossdev; 224 uint32_t dir, ossmask, ossval; 225 }; 226 227 /**************************************************************************** 228 * struct hdac_devinfo 229 * 230 * Holds all the parameters of a given codec function group. This is stored 231 * in the ivar of each child of the hdac bus 232 ****************************************************************************/ 233 struct hdac_devinfo { 234 device_t dev; 235 uint16_t vendor_id; 236 uint16_t device_id; 237 uint8_t revision_id; 238 uint8_t stepping_id; 239 uint8_t node_type; 240 nid_t nid; 241 nid_t startnode, endnode; 242 int nodecnt; 243 struct hdac_codec *codec; 244 struct hdac_widget *widget; 245 union { 246 struct { 247 uint32_t outamp_cap; 248 uint32_t inamp_cap; 249 uint32_t supp_stream_formats; 250 uint32_t supp_pcm_size_rate; 251 int ctlcnt, pcnt, rcnt; 252 struct hdac_audio_ctl *ctl; 253 uint32_t mvol; 254 uint32_t quirks; 255 uint32_t gpio; 256 int ossidx; 257 int playcnt, reccnt; 258 int parsing_strategy; 259 } audio; 260 /* XXX undefined: modem, hdmi. */ 261 } function; 262 }; 263 264 #define HDAC_CHN_RUNNING 0x00000001 265 #define HDAC_CHN_SUSPEND 0x00000002 266 267 struct hdac_chan { 268 struct snd_dbuf *b; 269 struct pcm_channel *c; 270 struct pcmchan_caps caps; 271 struct hdac_devinfo *devinfo; 272 struct hdac_dma bdl_dma; 273 uint32_t spd, fmt, fmtlist[8], pcmrates[16]; 274 uint32_t supp_stream_formats, supp_pcm_size_rate; 275 uint32_t ptr, prevptr, blkcnt, blksz; 276 uint32_t *dmapos; 277 uint32_t flags; 278 int dir; 279 int off; 280 int sid; 281 int bit16, bit32; 282 nid_t io[16]; 283 }; 284 285 /**************************************************************************** 286 * struct hdac_softc 287 * 288 * This structure holds the current state of the hdac driver. 289 ****************************************************************************/ 290 291 #define HDAC_F_DMA_NOCACHE 0x00000001 292 #define HDAC_F_MSI 0x00000002 293 294 struct hdac_softc { 295 device_t dev; 296 device_t hdabus; 297 sndlock_t lock; 298 299 struct intr_config_hook intrhook; 300 301 struct hdac_mem mem; 302 struct hdac_irq irq; 303 uint32_t pci_subvendor; 304 305 uint32_t flags; 306 307 int num_iss; 308 int num_oss; 309 int num_bss; 310 int support_64bit; 311 int streamcnt; 312 313 int corb_size; 314 struct hdac_dma corb_dma; 315 int corb_wp; 316 317 int rirb_size; 318 struct hdac_dma rirb_dma; 319 int rirb_rp; 320 321 struct hdac_dma pos_dma; 322 323 struct hdac_chan play, rec; 324 bus_dma_tag_t chan_dmat; 325 int chan_size; 326 int chan_blkcnt; 327 328 /* 329 * Polling 330 */ 331 int polling; 332 int poll_ticks; 333 int poll_ival; 334 struct callout poll_hda; 335 struct callout poll_hdac; 336 struct callout poll_jack; 337 338 struct task unsolq_task; 339 340 #define HDAC_UNSOLQ_MAX 64 341 #define HDAC_UNSOLQ_READY 0 342 #define HDAC_UNSOLQ_BUSY 1 343 int unsolq_rp; 344 int unsolq_wp; 345 int unsolq_st; 346 uint32_t unsolq[HDAC_UNSOLQ_MAX]; 347 348 struct hdac_codec *codecs[HDAC_CODEC_MAX]; 349 350 int registered; 351 }; 352 353 /**************************************************************************** 354 * struct hdac_command flags 355 ****************************************************************************/ 356 #define HDAC_COMMAND_FLAG_WAITOK 0x0000 357 #define HDAC_COMMAND_FLAG_NOWAIT 0x0001 358 359 #endif 360