1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac_reg.h,v 1.1 2006/10/01 11:12:59 ariff Exp $ 27 * $DragonFly: src/sys/dev/sound/pci/hda/hdac_reg.h,v 1.1 2007/01/04 21:47:03 corecode Exp $ 28 */ 29 30 #ifndef _HDAC_REG_H_ 31 #define _HDAC_REG_H_ 32 33 /**************************************************************************** 34 * HDA Controller Register Set 35 ****************************************************************************/ 36 #define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/ 37 #define HDAC_VMIN 0x02 /* 1 - Minor Version */ 38 #define HDAC_VMAJ 0x03 /* 1 - Major Version */ 39 #define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */ 40 #define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */ 41 #define HDAC_GCTL 0x08 /* 4 - Global Control */ 42 #define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */ 43 #define HDAC_STATESTS 0x0e /* 2 - State Change Status */ 44 #define HDAC_GSTS 0x10 /* 2 - Global Status */ 45 #define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */ 46 #define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */ 47 #define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */ 48 #define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */ 49 #define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */ 50 #define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */ 51 #define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */ 52 #define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */ 53 #define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */ 54 #define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */ 55 #define HDAC_CORBCTL 0x4c /* 1 - CORB Control */ 56 #define HDAC_CORBSTS 0x4d /* 1 - CORB Status */ 57 #define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */ 58 #define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */ 59 #define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */ 60 #define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */ 61 #define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */ 62 #define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */ 63 #define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */ 64 #define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */ 65 #define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */ 66 #define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */ 67 #define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */ 68 #define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */ 69 #define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */ 70 #define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */ 71 #define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */ 72 #define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */ 73 #define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */ 74 #define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */ 75 #define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */ 76 #define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */ 77 #define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */ 78 #define HDAC_SDFMT 0x92 /* 2 - fmt */ 79 #define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */ 80 #define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */ 81 82 #define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20)) 83 #define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss)) 84 #define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss)) 85 #define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss)) 86 #define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss)) 87 #define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss)) 88 #define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss)) 89 #define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss)) 90 #define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss)) 91 #define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss)) 92 93 #define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20)) 94 #define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss)) 95 #define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss)) 96 #define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss)) 97 #define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss)) 98 #define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss)) 99 #define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss)) 100 #define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) 101 #define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss)) 102 #define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss)) 103 104 #define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20)) 105 #define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss)) 106 #define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss)) 107 #define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss)) 108 #define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss)) 109 #define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss)) 110 #define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss)) 111 #define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) 112 #define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss)) 113 #define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) 114 115 /**************************************************************************** 116 * HDA Controller Register Fields 117 ****************************************************************************/ 118 119 /* GCAP - Global Capabilities */ 120 #define HDAC_GCAP_64OK 0x0001 121 #define HDAC_GCAP_NSDO_MASK 0x0006 122 #define HDAC_GCAP_NSDO_SHIFT 1 123 #define HDAC_GCAP_BSS_MASK 0x00f8 124 #define HDAC_GCAP_BSS_SHIFT 3 125 #define HDAC_GCAP_ISS_MASK 0x0f00 126 #define HDAC_GCAP_ISS_SHIFT 8 127 #define HDAC_GCAP_OSS_MASK 0xf000 128 #define HDAC_GCAP_OSS_SHIFT 12 129 130 #define HDAC_GCAP_NSDO_1SDO 0x00 131 #define HDAC_GCAP_NSDO_2SDO 0x02 132 #define HDAC_GCAP_NSDO_4SDO 0x04 133 134 #define HDAC_GCAP_BSS(gcap) \ 135 (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT) 136 #define HDAC_GCAP_ISS(gcap) \ 137 (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT) 138 #define HDAC_GCAP_OSS(gcap) \ 139 (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT) 140 141 /* GCTL - Global Control */ 142 #define HDAC_GCTL_CRST 0x00000001 143 #define HDAC_GCTL_FCNTRL 0x00000002 144 #define HDAC_GCTL_UNSOL 0x00000100 145 146 /* WAKEEN - Wake Enable */ 147 #define HDAC_WAKEEN_SDIWEN_MASK 0x7fff 148 #define HDAC_WAKEEN_SDIWEN_SHIFT 0 149 150 /* STATESTS - State Change Status */ 151 #define HDAC_STATESTS_SDIWAKE_MASK 0x7fff 152 #define HDAC_STATESTS_SDIWAKE_SHIFT 0 153 154 #define HDAC_STATESTS_SDIWAKE(statests, n) \ 155 (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \ 156 HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001) 157 158 /* GSTS - Global Status */ 159 #define HDAC_GSTS_FSTS 0x0002 160 161 /* INTCTL - Interrut Control */ 162 #define HDAC_INTCTL_SIE_MASK 0x3fffffff 163 #define HDAC_INTCTL_SIE_SHIFT 0 164 #define HDAC_INTCTL_CIE 0x40000000 165 #define HDAC_INTCTL_GIE 0x80000000 166 167 /* INTSTS - Interrupt Status */ 168 #define HDAC_INTSTS_SIS_MASK 0x3fffffff 169 #define HDAC_INTSTS_SIS_SHIFT 0 170 #define HDAC_INTSTS_CIS 0x40000000 171 #define HDAC_INTSTS_GIS 0x80000000 172 173 /* SSYNC - Stream Synchronization */ 174 #define HDAC_SSYNC_SSYNC_MASK 0x3fffffff 175 #define HDAC_SSYNC_SSYNC_SHIFT 0 176 177 /* CORBWP - CORB Write Pointer */ 178 #define HDAC_CORBWP_CORBWP_MASK 0x00ff 179 #define HDAC_CORBWP_CORBWP_SHIFT 0 180 181 /* CORBRP - CORB Read Pointer */ 182 #define HDAC_CORBRP_CORBRP_MASK 0x00ff 183 #define HDAC_CORBRP_CORBRP_SHIFT 0 184 #define HDAC_CORBRP_CORBRPRST 0x8000 185 186 /* CORBCTL - CORB Control */ 187 #define HDAC_CORBCTL_CMEIE 0x01 188 #define HDAC_CORBCTL_CORBRUN 0x02 189 190 /* CORBSTS - CORB Status */ 191 #define HDAC_CORBSTS_CMEI 0x01 192 193 /* CORBSIZE - CORB Size */ 194 #define HDAC_CORBSIZE_CORBSIZE_MASK 0x03 195 #define HDAC_CORBSIZE_CORBSIZE_SHIFT 0 196 #define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0 197 #define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4 198 199 #define HDAC_CORBSIZE_CORBSIZE_2 0x00 200 #define HDAC_CORBSIZE_CORBSIZE_16 0x01 201 #define HDAC_CORBSIZE_CORBSIZE_256 0x02 202 203 #define HDAC_CORBSIZE_CORBSZCAP_2 0x10 204 #define HDAC_CORBSIZE_CORBSZCAP_16 0x20 205 #define HDAC_CORBSIZE_CORBSZCAP_256 0x40 206 207 #define HDAC_CORBSIZE_CORBSIZE(corbsize) \ 208 (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT) 209 210 /* RIRBWP - RIRB Write Pointer */ 211 #define HDAC_RIRBWP_RIRBWP_MASK 0x00ff 212 #define HDAC_RIRBWP_RIRBWP_SHIFT 0 213 #define HDAC_RIRBWP_RIRBWPRST 0x8000 214 215 /* RINTCTN - Response Interrupt Count */ 216 #define HDAC_RINTCNT_MASK 0x00ff 217 #define HDAC_RINTCNT_SHIFT 0 218 219 /* RIRBCTL - RIRB Control */ 220 #define HDAC_RIRBCTL_RINTCTL 0x01 221 #define HDAC_RIRBCTL_RIRBDMAEN 0x02 222 #define HDAC_RIRBCTL_RIRBOIC 0x04 223 224 /* RIRBSTS - RIRB Status */ 225 #define HDAC_RIRBSTS_RINTFL 0x01 226 #define HDAC_RIRBSTS_RIRBOIS 0x04 227 228 /* RIRBSIZE - RIRB Size */ 229 #define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03 230 #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0 231 #define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0 232 #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4 233 234 #define HDAC_RIRBSIZE_RIRBSIZE_2 0x00 235 #define HDAC_RIRBSIZE_RIRBSIZE_16 0x01 236 #define HDAC_RIRBSIZE_RIRBSIZE_256 0x02 237 238 #define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10 239 #define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20 240 #define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40 241 242 #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \ 243 (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT) 244 245 /* DPLBASE - DMA Position Lower Base Address */ 246 #define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80 247 #define HDAC_DPLBASE_DPLBASE_SHIFT 7 248 #define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001 249 250 /* SDCTL - Stream Descriptor Control */ 251 #define HDAC_SDCTL_SRST 0x000001 252 #define HDAC_SDCTL_RUN 0x000002 253 #define HDAC_SDCTL_IOCE 0x000004 254 #define HDAC_SDCTL_FEIE 0x000008 255 #define HDAC_SDCTL_DEIE 0x000010 256 #define HDAC_SDCTL_STRIPE_MASK 0x030000 257 #define HDAC_SDCTL_STRIPE_SHIFT 16 258 #define HDAC_SDCTL_TP 0x040000 259 #define HDAC_SDCTL_DIR 0x080000 260 #define HDAC_SDCTL2_STRM_MASK 0xf0 261 #define HDAC_SDCTL2_STRM_SHIFT 4 262 263 #define HDAC_SDSTS_DESE (1 << 4) 264 #define HDAC_SDSTS_FIFOE (1 << 3) 265 #define HDAC_SDSTS_BCIS (1 << 2) 266 267 #endif 268