1 /*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.53.2.12 2007/07/12 06:39:38 ariff Exp $ 28 * $DragonFly: src/sys/dev/sound/pci/ich.c,v 1.17 2007/11/30 07:48:57 hasso Exp $ 29 */ 30 31 #include <dev/sound/pcm/sound.h> 32 #include <dev/sound/pcm/ac97.h> 33 #include <dev/sound/pci/ich.h> 34 35 #include <bus/pci/pcireg.h> 36 #include <bus/pci/pcivar.h> 37 38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/ich.c,v 1.17 2007/11/30 07:48:57 hasso Exp $"); 39 40 /* -------------------------------------------------------------------- */ 41 42 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 43 #define ICH_DTBL_LENGTH 32 44 #define ICH_DEFAULT_BUFSZ 16384 45 #define ICH_MAX_BUFSZ 65536 46 #define ICH_MIN_BUFSZ 4096 47 #define ICH_DEFAULT_BLKCNT 2 48 #define ICH_MAX_BLKCNT 32 49 #define ICH_MIN_BLKCNT 2 50 #define ICH_MIN_BLKSZ 64 51 52 #define INTEL_VENDORID 0x8086 53 #define SIS_VENDORID 0x1039 54 #define NVIDIA_VENDORID 0x10de 55 #define AMD_VENDORID 0x1022 56 57 #define INTEL_82440MX 0x7195 58 #define INTEL_82801AA 0x2415 59 #define INTEL_82801AB 0x2425 60 #define INTEL_82801BA 0x2445 61 #define INTEL_82801CA 0x2485 62 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 63 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 64 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 65 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 66 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 67 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 68 #define NVIDIA_NFORCE 0x01b1 69 #define NVIDIA_NFORCE2 0x006a 70 #define NVIDIA_NFORCE2_400 0x008a 71 #define NVIDIA_NFORCE3 0x00da 72 #define NVIDIA_NFORCE3_250 0x00ea 73 #define NVIDIA_NFORCE4 0x0059 74 #define NVIDIA_NFORCE_410_MCP 0x026b 75 #define NVIDIA_NFORCE4_MCP 0x003a 76 #define AMD_768 0x7445 77 #define AMD_8111 0x746d 78 79 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 80 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 81 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 82 83 #if 0 84 #define ICH_DEBUG(stmt) do { \ 85 stmt \ 86 } while(0) 87 #else 88 #define ICH_DEBUG(...) 89 #endif 90 91 #define ICH_CALIBRATE_DONE (1 << 0) 92 #define ICH_IGNORE_PCR (1 << 1) 93 #define ICH_IGNORE_RESET (1 << 2) 94 #define ICH_FIXED_RATE (1 << 3) 95 #define ICH_DMA_NOCACHE (1 << 4) 96 #define ICH_HIGH_LATENCY (1 << 5) 97 98 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 99 #include <machine/specialreg.h> 100 #define ICH_DMA_ATTR(sc, v, s, attr) do { \ 101 vm_offset_t va = (vm_offset_t)(v); \ 102 vm_size_t sz = (vm_size_t)(s); \ 103 if ((sc) != NULL && ((sc)->flags & ICH_DMA_NOCACHE) && \ 104 va != 0 && sz != 0) \ 105 (void)pmap_change_attr(va, sz, (attr)); \ 106 } while(0) 107 #else 108 #define ICH_DMA_ATTR(...) 109 #endif 110 111 static const struct ich_type { 112 uint16_t vendor; 113 uint16_t devid; 114 uint32_t options; 115 #define PROBE_LOW 0x01 116 char *name; 117 } ich_devs[] = { 118 { INTEL_VENDORID, INTEL_82440MX, 0, 119 "Intel 440MX" }, 120 { INTEL_VENDORID, INTEL_82801AA, 0, 121 "Intel ICH (82801AA)" }, 122 { INTEL_VENDORID, INTEL_82801AB, 0, 123 "Intel ICH (82801AB)" }, 124 { INTEL_VENDORID, INTEL_82801BA, 0, 125 "Intel ICH2 (82801BA)" }, 126 { INTEL_VENDORID, INTEL_82801CA, 0, 127 "Intel ICH3 (82801CA)" }, 128 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 129 "Intel ICH4 (82801DB)" }, 130 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 131 "Intel ICH5 (82801EB)" }, 132 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 133 "Intel 6300ESB" }, 134 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 135 "Intel ICH6 (82801FB)" }, 136 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 137 "Intel ICH7 (82801GB)" }, 138 { SIS_VENDORID, SIS_7012, 0, 139 "SiS 7012" }, 140 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 141 "nVidia nForce" }, 142 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 143 "nVidia nForce2" }, 144 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 145 "nVidia nForce2 400" }, 146 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 147 "nVidia nForce3" }, 148 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 149 "nVidia nForce3 250" }, 150 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 151 "nVidia nForce4" }, 152 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 153 "nVidia nForce 410 MCP" }, 154 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0, 155 "nVidia nForce 4 MCP" }, 156 { AMD_VENDORID, AMD_768, 0, 157 "AMD-768" }, 158 { AMD_VENDORID, AMD_8111, 0, 159 "AMD-8111" } 160 }; 161 162 /* buffer descriptor */ 163 struct ich_desc { 164 volatile uint32_t buffer; 165 volatile uint32_t length; 166 }; 167 168 struct sc_info; 169 170 /* channel registers */ 171 struct sc_chinfo { 172 uint32_t num:8, run:1, run_save:1; 173 uint32_t blksz, blkcnt, spd; 174 uint32_t regbase, spdreg; 175 uint32_t imask; 176 uint32_t civ; 177 178 struct snd_dbuf *buffer; 179 struct pcm_channel *channel; 180 struct sc_info *parent; 181 182 struct ich_desc *dtbl; 183 bus_addr_t desc_addr; 184 }; 185 186 /* device private data */ 187 struct sc_info { 188 device_t dev; 189 int hasvra, hasvrm, hasmic; 190 unsigned int chnum, bufsz, blkcnt; 191 int sample_size, swap_reg; 192 193 struct resource *nambar, *nabmbar, *irq; 194 int regtype, nambarid, nabmbarid, irqid; 195 bus_space_tag_t nambart, nabmbart; 196 bus_space_handle_t nambarh, nabmbarh; 197 bus_dma_tag_t dmat, chan_dmat; 198 bus_dmamap_t dtmap; 199 void *ih; 200 201 struct ac97_info *codec; 202 struct sc_chinfo ch[3]; 203 int ac97rate; 204 struct ich_desc *dtbl; 205 unsigned int dtbl_size; 206 bus_addr_t desc_addr; 207 struct intr_config_hook intrhook; 208 uint16_t vendor; 209 uint16_t devid; 210 uint32_t flags; 211 sndlock_t ich_lock; 212 }; 213 214 #define IGNORE_PCR 0x01 215 216 /* -------------------------------------------------------------------- */ 217 218 static uint32_t ich_fmt[] = { 219 AFMT_STEREO | AFMT_S16_LE, 220 0 221 }; 222 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 223 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 224 225 /* -------------------------------------------------------------------- */ 226 /* Hardware */ 227 static __inline uint32_t 228 ich_rd(struct sc_info *sc, int regno, int size) 229 { 230 switch (size) { 231 case 1: 232 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno)); 233 case 2: 234 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno)); 235 case 4: 236 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno)); 237 default: 238 return (0xffffffff); 239 } 240 } 241 242 static __inline void 243 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size) 244 { 245 switch (size) { 246 case 1: 247 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 248 break; 249 case 2: 250 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 251 break; 252 case 4: 253 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 254 break; 255 } 256 } 257 258 /* ac97 codec */ 259 static int 260 ich_waitcd(void *devinfo) 261 { 262 struct sc_info *sc = (struct sc_info *)devinfo; 263 uint32_t data; 264 int i; 265 266 for (i = 0; i < ICH_TIMEOUT; i++) { 267 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 268 if ((data & 0x01) == 0) 269 return (0); 270 DELAY(1); 271 } 272 if ((sc->flags & ICH_IGNORE_PCR) != 0) 273 return (0); 274 device_printf(sc->dev, "CODEC semaphore timeout\n"); 275 return (ETIMEDOUT); 276 } 277 278 static int 279 ich_rdcd(kobj_t obj, void *devinfo, int regno) 280 { 281 struct sc_info *sc = (struct sc_info *)devinfo; 282 283 regno &= 0xff; 284 ich_waitcd(sc); 285 286 return (bus_space_read_2(sc->nambart, sc->nambarh, regno)); 287 } 288 289 static int 290 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data) 291 { 292 struct sc_info *sc = (struct sc_info *)devinfo; 293 294 regno &= 0xff; 295 ich_waitcd(sc); 296 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 297 298 return (0); 299 } 300 301 static kobj_method_t ich_ac97_methods[] = { 302 KOBJMETHOD(ac97_read, ich_rdcd), 303 KOBJMETHOD(ac97_write, ich_wrcd), 304 { 0, 0 } 305 }; 306 AC97_DECLARE(ich_ac97); 307 308 /* -------------------------------------------------------------------- */ 309 /* common routines */ 310 311 static void 312 ich_filldtbl(struct sc_chinfo *ch) 313 { 314 struct sc_info *sc = ch->parent; 315 uint32_t base; 316 int i; 317 318 base = sndbuf_getbufaddr(ch->buffer); 319 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer)) 320 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 321 if ((sndbuf_getblksz(ch->buffer) != ch->blksz || 322 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) && 323 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0) 324 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 325 __func__, ch->blksz, ch->blkcnt); 326 ch->blksz = sndbuf_getblksz(ch->buffer); 327 328 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 329 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 330 ch->dtbl[i].length = ICH_BDC_IOC 331 | (ch->blksz / ch->parent->sample_size); 332 } 333 } 334 335 static int 336 ich_resetchan(struct sc_info *sc, int num) 337 { 338 int i, cr, regbase; 339 340 if (num == 0) 341 regbase = ICH_REG_PO_BASE; 342 else if (num == 1) 343 regbase = ICH_REG_PI_BASE; 344 else if (num == 2) 345 regbase = ICH_REG_MC_BASE; 346 else 347 return (ENXIO); 348 349 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 350 #if 1 351 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 352 DELAY(100); 353 #else 354 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 355 #endif 356 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 357 for (i = 0; i < ICH_TIMEOUT; i++) { 358 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 359 if (cr == 0) 360 return (0); 361 DELAY(1); 362 } 363 364 if (sc->flags & ICH_IGNORE_RESET) 365 return (0); 366 #if 0 367 else if (sc->vendor == NVIDIA_VENDORID) { 368 sc->flags |= ICH_IGNORE_RESET; 369 device_printf(sc->dev, "ignoring reset failure!\n"); 370 return (0); 371 } 372 #endif 373 374 device_printf(sc->dev, "cannot reset channel %d\n", num); 375 return (ENXIO); 376 } 377 378 /* -------------------------------------------------------------------- */ 379 /* channel interface */ 380 381 static void * 382 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 383 { 384 struct sc_info *sc = devinfo; 385 struct sc_chinfo *ch; 386 unsigned int num; 387 388 ICH_LOCK(sc); 389 num = sc->chnum++; 390 ch = &sc->ch[num]; 391 ch->num = num; 392 ch->buffer = b; 393 ch->channel = c; 394 ch->parent = sc; 395 ch->run = 0; 396 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 397 ch->desc_addr = sc->desc_addr + 398 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc)); 399 ch->blkcnt = sc->blkcnt; 400 ch->blksz = sc->bufsz / ch->blkcnt; 401 402 switch(ch->num) { 403 case 0: /* play */ 404 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 405 ch->regbase = ICH_REG_PO_BASE; 406 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0; 407 ch->imask = ICH_GLOB_STA_POINT; 408 break; 409 410 case 1: /* record */ 411 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 412 ch->regbase = ICH_REG_PI_BASE; 413 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0; 414 ch->imask = ICH_GLOB_STA_PIINT; 415 break; 416 417 case 2: /* mic */ 418 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 419 ch->regbase = ICH_REG_MC_BASE; 420 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0; 421 ch->imask = ICH_GLOB_STA_MINT; 422 break; 423 424 default: 425 return (NULL); 426 } 427 428 if (sc->flags & ICH_FIXED_RATE) 429 ch->spdreg = 0; 430 431 ICH_UNLOCK(sc); 432 if (sndbuf_alloc(ch->buffer, sc->chan_dmat, sc->bufsz) != 0) 433 return (NULL); 434 435 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer), 436 sndbuf_getmaxsize(ch->buffer), PAT_UNCACHEABLE); 437 438 ICH_LOCK(sc); 439 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 440 ICH_UNLOCK(sc); 441 442 return (ch); 443 } 444 445 static int 446 ichchan_free(kobj_t obj, void *data) 447 { 448 struct sc_chinfo *ch; 449 struct sc_info *sc; 450 451 ch = (struct sc_chinfo *)data; 452 sc = (ch != NULL) ? ch->parent : NULL; 453 if (ch != NULL && sc != NULL) { 454 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer), 455 sndbuf_getmaxsize(ch->buffer), PAT_WRITE_BACK); 456 } 457 458 return (1); 459 } 460 461 static int 462 ichchan_setformat(kobj_t obj, void *data, uint32_t format) 463 { 464 465 ICH_DEBUG( 466 struct sc_chinfo *ch = data; 467 struct sc_info *sc = ch->parent; 468 if (!(sc->flags & ICH_CALIBRATE_DONE)) 469 device_printf(sc->dev, 470 "WARNING: %s() called before calibration!\n", 471 __func__); 472 ); 473 474 return (0); 475 } 476 477 static int 478 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed) 479 { 480 struct sc_chinfo *ch = data; 481 struct sc_info *sc = ch->parent; 482 483 ICH_DEBUG( 484 if (!(sc->flags & ICH_CALIBRATE_DONE)) 485 device_printf(sc->dev, 486 "WARNING: %s() called before calibration!\n", 487 __func__); 488 ); 489 490 if (ch->spdreg) { 491 int r, ac97rate; 492 493 ICH_LOCK(sc); 494 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 495 sc->ac97rate = 48000; 496 ac97rate = sc->ac97rate; 497 ICH_UNLOCK(sc); 498 r = (speed * 48000) / ac97rate; 499 /* 500 * Cast the return value of ac97_setrate() to uint64 so that 501 * the math don't overflow into the negative range. 502 */ 503 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) * 504 ac97rate) / 48000; 505 } else { 506 ch->spd = 48000; 507 } 508 return (ch->spd); 509 } 510 511 static int 512 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 513 { 514 struct sc_chinfo *ch = data; 515 struct sc_info *sc = ch->parent; 516 517 ICH_DEBUG( 518 if (!(sc->flags & ICH_CALIBRATE_DONE)) 519 device_printf(sc->dev, 520 "WARNING: %s() called before calibration!\n", 521 __func__); 522 ); 523 524 if (sc->flags & ICH_HIGH_LATENCY) 525 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 526 527 if (blocksize < ICH_MIN_BLKSZ) 528 blocksize = ICH_MIN_BLKSZ; 529 blocksize &= ~(ICH_MIN_BLKSZ - 1); 530 ch->blksz = blocksize; 531 ich_filldtbl(ch); 532 ICH_LOCK(sc); 533 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 534 ICH_UNLOCK(sc); 535 536 return (ch->blksz); 537 } 538 539 static int 540 ichchan_trigger(kobj_t obj, void *data, int go) 541 { 542 struct sc_chinfo *ch = data; 543 struct sc_info *sc = ch->parent; 544 545 ICH_DEBUG( 546 if (!(sc->flags & ICH_CALIBRATE_DONE)) 547 device_printf(sc->dev, 548 "WARNING: %s() called before calibration!\n", 549 __func__); 550 ); 551 552 switch (go) { 553 case PCMTRIG_START: 554 ch->run = 1; 555 ICH_LOCK(sc); 556 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 557 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 558 ICH_UNLOCK(sc); 559 break; 560 case PCMTRIG_STOP: 561 case PCMTRIG_ABORT: 562 ICH_LOCK(sc); 563 ich_resetchan(sc, ch->num); 564 ICH_UNLOCK(sc); 565 ch->run = 0; 566 break; 567 default: 568 break; 569 } 570 return (0); 571 } 572 573 static int 574 ichchan_getptr(kobj_t obj, void *data) 575 { 576 struct sc_chinfo *ch = data; 577 struct sc_info *sc = ch->parent; 578 uint32_t pos; 579 580 ICH_DEBUG( 581 if (!(sc->flags & ICH_CALIBRATE_DONE)) 582 device_printf(sc->dev, 583 "WARNING: %s() called before calibration!\n", 584 __func__); 585 ); 586 587 ICH_LOCK(sc); 588 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 589 ICH_UNLOCK(sc); 590 591 pos = ch->civ * ch->blksz; 592 593 return (pos); 594 } 595 596 static struct pcmchan_caps * 597 ichchan_getcaps(kobj_t obj, void *data) 598 { 599 struct sc_chinfo *ch = data; 600 601 ICH_DEBUG( 602 struct sc_info *sc = ch->parent; 603 604 if (!(sc->flags & ICH_CALIBRATE_DONE)) 605 device_printf(ch->parent->dev, 606 "WARNING: %s() called before calibration!\n", 607 __func__); 608 ); 609 610 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps); 611 } 612 613 static kobj_method_t ichchan_methods[] = { 614 KOBJMETHOD(channel_init, ichchan_init), 615 KOBJMETHOD(channel_free, ichchan_free), 616 KOBJMETHOD(channel_setformat, ichchan_setformat), 617 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 618 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 619 KOBJMETHOD(channel_trigger, ichchan_trigger), 620 KOBJMETHOD(channel_getptr, ichchan_getptr), 621 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 622 { 0, 0 } 623 }; 624 CHANNEL_DECLARE(ichchan); 625 626 /* -------------------------------------------------------------------- */ 627 /* The interrupt handler */ 628 629 static void 630 ich_intr(void *p) 631 { 632 struct sc_info *sc = (struct sc_info *)p; 633 struct sc_chinfo *ch; 634 uint32_t cbi, lbi, lvi, st, gs; 635 int i; 636 637 ICH_LOCK(sc); 638 639 ICH_DEBUG( 640 if (!(sc->flags & ICH_CALIBRATE_DONE)) 641 device_printf(sc->dev, 642 "WARNING: %s() called before calibration!\n", 643 __func__); 644 ); 645 646 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 647 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 648 /* Clear resume interrupt(s) - nothing doing with them */ 649 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 650 } 651 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 652 653 for (i = 0; i < 3; i++) { 654 ch = &sc->ch[i]; 655 if ((ch->imask & gs) == 0) 656 continue; 657 gs &= ~ch->imask; 658 st = ich_rd(sc, ch->regbase + 659 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 660 2); 661 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 662 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 663 /* block complete - update buffer */ 664 if (ch->run) { 665 ICH_UNLOCK(sc); 666 chn_intr(ch->channel); 667 ICH_LOCK(sc); 668 } 669 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 670 cbi = ch->civ % ch->blkcnt; 671 if (cbi == 0) 672 cbi = ch->blkcnt - 1; 673 else 674 cbi--; 675 lbi = lvi % ch->blkcnt; 676 if (cbi >= lbi) 677 lvi += cbi - lbi; 678 else 679 lvi += cbi + ch->blkcnt - lbi; 680 lvi %= ICH_DTBL_LENGTH; 681 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 682 683 } 684 /* clear status bit */ 685 ich_wr(sc, ch->regbase + 686 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 687 st, 2); 688 } 689 ICH_UNLOCK(sc); 690 if (gs != 0) { 691 device_printf(sc->dev, 692 "Unhandled interrupt, gs_intr = %x\n", gs); 693 } 694 } 695 696 /* ------------------------------------------------------------------------- */ 697 /* Sysctl to control ac97 speed (some boards appear to end up using 698 * XTAL_IN rather than BIT_CLK for link timing). 699 */ 700 701 static int 702 ich_initsys(struct sc_info* sc) 703 { 704 #ifdef SND_DYNSYSCTL 705 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 706 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 707 OID_AUTO, "ac97rate", CTLFLAG_RW, 708 &sc->ac97rate, 48000, 709 "AC97 link rate (default = 48000)"); 710 #endif /* SND_DYNSYSCTL */ 711 return (0); 712 } 713 714 static void 715 ich_setstatus(struct sc_info *sc) 716 { 717 char status[SND_STATUSLEN]; 718 719 ksnprintf(status, SND_STATUSLEN, 720 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 721 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), 722 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 723 724 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE)) 725 device_printf(sc->dev, 726 "PCI Master abort workaround enabled\n"); 727 728 pcm_setstatus(sc->dev, status); 729 } 730 731 /* -------------------------------------------------------------------- */ 732 /* Calibrate card to determine the clock source. The source maybe a 733 * function of the ac97 codec initialization code (to be investigated). 734 */ 735 736 static void 737 ich_calibrate(void *arg) 738 { 739 struct sc_info *sc; 740 struct sc_chinfo *ch; 741 struct timeval t1, t2; 742 uint8_t ociv, nciv; 743 uint32_t wait_us, actual_48k_rate, oblkcnt; 744 745 sc = (struct sc_info *)arg; 746 ICH_LOCK(sc); 747 ch = &sc->ch[1]; 748 749 if (sc->intrhook.ich_func != NULL) { 750 config_intrhook_disestablish(&sc->intrhook); 751 sc->intrhook.ich_func = NULL; 752 } 753 754 /* 755 * Grab audio from input for fixed interval and compare how 756 * much we actually get with what we expect. Interval needs 757 * to be sufficiently short that no interrupts are 758 * generated. 759 */ 760 761 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 762 763 oblkcnt = ch->blkcnt; 764 ch->blkcnt = 2; 765 sc->flags |= ICH_CALIBRATE_DONE; 766 ICH_UNLOCK(sc); 767 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1); 768 ICH_LOCK(sc); 769 sc->flags &= ~ICH_CALIBRATE_DONE; 770 771 /* 772 * our data format is stereo, 16 bit so each sample is 4 bytes. 773 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 774 * we're going to start recording with interrupts disabled and measure 775 * the time taken for one block to complete. we know the block size, 776 * we know the time in microseconds, we calculate the sample rate: 777 * 778 * actual_rate [bps] = bytes / (time [s] * 4) 779 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 780 * actual_rate [Hz] = (bytes * 250000) / time [us] 781 */ 782 783 /* prepare */ 784 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 785 nciv = ociv; 786 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 787 788 /* start */ 789 microtime(&t1); 790 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 791 792 /* wait */ 793 do { 794 microtime(&t2); 795 if (t2.tv_sec - t1.tv_sec > 1) 796 break; 797 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 798 } while (nciv == ociv); 799 800 /* stop */ 801 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 802 803 /* reset */ 804 DELAY(100); 805 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 806 ch->blkcnt = oblkcnt; 807 808 /* turn time delta into us */ 809 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 810 811 if (nciv == ociv) { 812 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 813 sc->flags |= ICH_CALIBRATE_DONE; 814 ICH_UNLOCK(sc); 815 ich_setstatus(sc); 816 return; 817 } 818 819 /* Just in case the timecounter screwed. It is possible, really. */ 820 if (wait_us > 0) 821 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us; 822 else 823 actual_48k_rate = 48000; 824 825 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 826 sc->ac97rate = actual_48k_rate; 827 } else { 828 sc->ac97rate = 48000; 829 } 830 831 if (bootverbose || sc->ac97rate != 48000) { 832 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 833 if (sc->ac97rate != actual_48k_rate) 834 kprintf(", will use %d Hz", sc->ac97rate); 835 kprintf("\n"); 836 } 837 sc->flags |= ICH_CALIBRATE_DONE; 838 ICH_UNLOCK(sc); 839 840 ich_setstatus(sc); 841 842 return; 843 } 844 845 /* -------------------------------------------------------------------- */ 846 /* Probe and attach the card */ 847 848 static void 849 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 850 { 851 struct sc_info *sc = (struct sc_info *)arg; 852 sc->desc_addr = segs->ds_addr; 853 return; 854 } 855 856 static int 857 ich_init(struct sc_info *sc) 858 { 859 uint32_t stat; 860 861 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 862 DELAY(600000); 863 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 864 865 if ((stat & ICH_GLOB_STA_PCR) == 0) { 866 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 867 if (sc->vendor == INTEL_VENDORID && ( 868 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 869 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 870 sc->devid == INTEL_82801GB)) { 871 sc->flags |= ICH_IGNORE_PCR; 872 device_printf(sc->dev, "primary codec not ready!\n"); 873 } 874 } 875 876 #if 0 877 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 878 #else 879 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 880 #endif 881 882 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 883 return (ENXIO); 884 if (sc->hasmic && ich_resetchan(sc, 2)) 885 return (ENXIO); 886 887 return (0); 888 } 889 890 static int 891 ich_pci_probe(device_t dev) 892 { 893 int i; 894 uint16_t devid, vendor; 895 896 vendor = pci_get_vendor(dev); 897 devid = pci_get_device(dev); 898 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 899 if (vendor == ich_devs[i].vendor && 900 devid == ich_devs[i].devid) { 901 device_set_desc(dev, ich_devs[i].name); 902 /* allow a better driver to override us */ 903 if ((ich_devs[i].options & PROBE_LOW) != 0) 904 return (BUS_PROBE_LOW_PRIORITY); 905 return (BUS_PROBE_DEFAULT); 906 } 907 } 908 return (ENXIO); 909 } 910 911 static int 912 ich_pci_attach(device_t dev) 913 { 914 uint32_t subdev; 915 uint16_t extcaps; 916 uint16_t devid, vendor; 917 struct sc_info *sc; 918 int i; 919 920 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 921 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc"); 922 sc->dev = dev; 923 924 vendor = sc->vendor = pci_get_vendor(dev); 925 devid = sc->devid = pci_get_device(dev); 926 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 927 /* 928 * The SiS 7012 register set isn't quite like the standard ich. 929 * There really should be a general "quirks" mechanism. 930 */ 931 if (vendor == SIS_VENDORID && devid == SIS_7012) { 932 sc->swap_reg = 1; 933 sc->sample_size = 1; 934 } else { 935 sc->swap_reg = 0; 936 sc->sample_size = 2; 937 } 938 939 /* 940 * Intel 440MX Errata #36 941 * - AC97 Soft Audio and Soft Modem Master Abort Errata 942 * 943 * http://www.intel.com/design/chipsets/specupdt/245051.htm 944 */ 945 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX) 946 sc->flags |= ICH_DMA_NOCACHE; 947 948 /* 949 * Enable bus master. On ich4/5 this may prevent the detection of 950 * the primary codec becoming ready in ich_init(). 951 */ 952 pci_enable_busmaster(dev); 953 954 /* 955 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 956 * read-only. Need to enable "legacy support", by poking into 957 * pci config space. The driver should use MMBAR and MBBAR, 958 * but doing so will mess things up here. ich4 has enough new 959 * features it warrants it's own driver. 960 */ 961 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 962 devid == INTEL_82801EB || devid == INTEL_6300ESB || 963 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 964 sc->nambarid = PCIR_MMBAR; 965 sc->nabmbarid = PCIR_MBBAR; 966 sc->regtype = SYS_RES_MEMORY; 967 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 968 } else { 969 sc->nambarid = PCIR_NAMBAR; 970 sc->nabmbarid = PCIR_NABMBAR; 971 sc->regtype = SYS_RES_IOPORT; 972 } 973 974 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 975 &sc->nambarid, RF_ACTIVE); 976 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 977 &sc->nabmbarid, RF_ACTIVE); 978 979 if (!sc->nambar || !sc->nabmbar) { 980 device_printf(dev, "unable to map IO port space\n"); 981 goto bad; 982 } 983 984 sc->nambart = rman_get_bustag(sc->nambar); 985 sc->nambarh = rman_get_bushandle(sc->nambar); 986 sc->nabmbart = rman_get_bustag(sc->nabmbar); 987 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 988 989 sc->bufsz = pcm_getbuffersize(dev, 990 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 991 992 if (resource_int_value(device_get_name(dev), 993 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 994 sc->blkcnt = sc->bufsz / i; 995 i = 0; 996 while (sc->blkcnt >> i) 997 i++; 998 sc->blkcnt = 1 << (i - 1); 999 if (sc->blkcnt < ICH_MIN_BLKCNT) 1000 sc->blkcnt = ICH_MIN_BLKCNT; 1001 else if (sc->blkcnt > ICH_MAX_BLKCNT) 1002 sc->blkcnt = ICH_MAX_BLKCNT; 1003 } else 1004 sc->blkcnt = ICH_DEFAULT_BLKCNT; 1005 1006 if (resource_int_value(device_get_name(dev), 1007 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) { 1008 sc->flags |= ICH_HIGH_LATENCY; 1009 sc->blkcnt = ICH_MIN_BLKCNT; 1010 } 1011 1012 if (resource_int_value(device_get_name(dev), 1013 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0) 1014 sc->flags |= ICH_FIXED_RATE; 1015 1016 sc->irqid = 0; 1017 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1018 RF_ACTIVE | RF_SHAREABLE); 1019 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, 1020 sc, &sc->ih)) { 1021 device_printf(dev, "unable to map interrupt\n"); 1022 goto bad; 1023 } 1024 1025 if (ich_init(sc)) { 1026 device_printf(dev, "unable to initialize the card\n"); 1027 goto bad; 1028 } 1029 1030 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 1031 if (sc->codec == NULL) 1032 goto bad; 1033 1034 /* 1035 * Turn on inverted external amplifier sense flags for few 1036 * 'special' boards. 1037 */ 1038 switch (subdev) { 1039 case 0x202f161f: /* Gateway 7326GZ */ 1040 case 0x203a161f: /* Gateway 4028GZ */ 1041 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 1042 case 0x8144104d: /* Sony VAIO PCG-TR* */ 1043 case 0x8197104d: /* Sony S1XP */ 1044 case 0x81c0104d: /* Sony VAIO type T */ 1045 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 1046 case 0x3089103c: /* Compaq Presario B3800 */ 1047 case 0x309a103c: /* HP Compaq nx4300 */ 1048 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 1049 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 1050 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 1051 break; 1052 default: 1053 break; 1054 } 1055 1056 mixer_init(dev, ac97_getmixerclass(), sc->codec); 1057 1058 /* check and set VRA function */ 1059 extcaps = ac97_getextcaps(sc->codec); 1060 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 1061 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 1062 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 1063 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1064 1065 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 1066 ((sc->hasmic) ? 3 : 2); 1067 1068 /* BDL tag */ 1069 if (bus_dma_tag_create(NULL, 8, 0, 1070 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1071 sc->dtbl_size, 1, 0x3ffff, 0, &sc->dmat) != 0) { 1072 device_printf(dev, "unable to create dma tag\n"); 1073 goto bad; 1074 } 1075 1076 /* PCM channel tag */ 1077 if (bus_dma_tag_create(NULL, ICH_MIN_BLKSZ, 0, 1078 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1079 sc->bufsz, 1, 0x3ffff, 0, &sc->chan_dmat) != 0) { 1080 device_printf(dev, "unable to create dma tag\n"); 1081 goto bad; 1082 } 1083 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 1084 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT | 1085 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1086 &sc->dtmap)) 1087 #else 1088 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, 1089 &sc->dtmap)) 1090 #endif 1091 goto bad; 1092 1093 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size, 1094 ich_setmap, sc, 0)) 1095 goto bad; 1096 1097 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1)) 1098 goto bad; 1099 1100 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 1101 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 1102 if (sc->hasmic) 1103 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 1104 1105 if (sc->flags & ICH_FIXED_RATE) { 1106 sc->flags |= ICH_CALIBRATE_DONE; 1107 ich_setstatus(sc); 1108 } else { 1109 ich_initsys(sc); 1110 1111 sc->intrhook.ich_func = ich_calibrate; 1112 sc->intrhook.ich_arg = sc; 1113 if (cold == 0 || 1114 config_intrhook_establish(&sc->intrhook) != 0) { 1115 sc->intrhook.ich_func = NULL; 1116 ich_calibrate(sc); 1117 } 1118 } 1119 1120 return (0); 1121 1122 bad: 1123 if (sc->codec) 1124 ac97_destroy(sc->codec); 1125 if (sc->ih) 1126 bus_teardown_intr(dev, sc->irq, sc->ih); 1127 if (sc->irq) 1128 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1129 if (sc->nambar) 1130 bus_release_resource(dev, sc->regtype, 1131 sc->nambarid, sc->nambar); 1132 if (sc->nabmbar) 1133 bus_release_resource(dev, sc->regtype, 1134 sc->nabmbarid, sc->nabmbar); 1135 if (sc->dtmap) 1136 bus_dmamap_unload(sc->dmat, sc->dtmap); 1137 if (sc->dtbl) 1138 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1139 if (sc->chan_dmat) 1140 bus_dma_tag_destroy(sc->chan_dmat); 1141 if (sc->dmat) 1142 bus_dma_tag_destroy(sc->dmat); 1143 if (sc->ich_lock) 1144 snd_mtxfree(sc->ich_lock); 1145 kfree(sc, M_DEVBUF); 1146 return (ENXIO); 1147 } 1148 1149 static int 1150 ich_pci_detach(device_t dev) 1151 { 1152 struct sc_info *sc; 1153 int r; 1154 1155 r = pcm_unregister(dev); 1156 if (r) 1157 return (r); 1158 sc = pcm_getdevinfo(dev); 1159 1160 bus_teardown_intr(dev, sc->irq, sc->ih); 1161 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1162 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 1163 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 1164 bus_dmamap_unload(sc->dmat, sc->dtmap); 1165 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1166 bus_dma_tag_destroy(sc->chan_dmat); 1167 bus_dma_tag_destroy(sc->dmat); 1168 snd_mtxfree(sc->ich_lock); 1169 kfree(sc, M_DEVBUF); 1170 return (0); 1171 } 1172 1173 static void 1174 ich_pci_codec_reset(struct sc_info *sc) 1175 { 1176 int i; 1177 uint32_t control; 1178 1179 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 1180 control &= ~(ICH_GLOB_CTL_SHUT); 1181 control |= (control & ICH_GLOB_CTL_COLD) ? 1182 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 1183 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 1184 1185 for (i = 500000; i; i--) { 1186 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 1187 break; /* or ICH_SCR? */ 1188 DELAY(1); 1189 } 1190 1191 if (i <= 0) 1192 kprintf("%s: time out\n", __func__); 1193 } 1194 1195 static int 1196 ich_pci_suspend(device_t dev) 1197 { 1198 struct sc_info *sc; 1199 int i; 1200 1201 sc = pcm_getdevinfo(dev); 1202 ICH_LOCK(sc); 1203 for (i = 0 ; i < 3; i++) { 1204 sc->ch[i].run_save = sc->ch[i].run; 1205 if (sc->ch[i].run) { 1206 ICH_UNLOCK(sc); 1207 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 1208 ICH_LOCK(sc); 1209 } 1210 } 1211 ICH_UNLOCK(sc); 1212 return (0); 1213 } 1214 1215 static int 1216 ich_pci_resume(device_t dev) 1217 { 1218 struct sc_info *sc; 1219 int i; 1220 1221 sc = pcm_getdevinfo(dev); 1222 1223 if (sc->regtype == SYS_RES_IOPORT) 1224 pci_enable_io(dev, SYS_RES_IOPORT); 1225 else 1226 pci_enable_io(dev, SYS_RES_MEMORY); 1227 pci_enable_busmaster(dev); 1228 1229 ICH_LOCK(sc); 1230 /* Reinit audio device */ 1231 if (ich_init(sc) == -1) { 1232 device_printf(dev, "unable to reinitialize the card\n"); 1233 ICH_UNLOCK(sc); 1234 return (ENXIO); 1235 } 1236 /* Reinit mixer */ 1237 ich_pci_codec_reset(sc); 1238 ICH_UNLOCK(sc); 1239 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1240 if (mixer_reinit(dev) == -1) { 1241 device_printf(dev, "unable to reinitialize the mixer\n"); 1242 return (ENXIO); 1243 } 1244 /* Re-start DMA engines */ 1245 for (i = 0 ; i < 3; i++) { 1246 struct sc_chinfo *ch = &sc->ch[i]; 1247 if (sc->ch[i].run_save) { 1248 ichchan_setblocksize(0, ch, ch->blksz); 1249 ichchan_setspeed(0, ch, ch->spd); 1250 ichchan_trigger(0, ch, PCMTRIG_START); 1251 } 1252 } 1253 return (0); 1254 } 1255 1256 static device_method_t ich_methods[] = { 1257 /* Device interface */ 1258 DEVMETHOD(device_probe, ich_pci_probe), 1259 DEVMETHOD(device_attach, ich_pci_attach), 1260 DEVMETHOD(device_detach, ich_pci_detach), 1261 DEVMETHOD(device_suspend, ich_pci_suspend), 1262 DEVMETHOD(device_resume, ich_pci_resume), 1263 { 0, 0 } 1264 }; 1265 1266 static driver_t ich_driver = { 1267 "pcm", 1268 ich_methods, 1269 PCM_SOFTC_SIZE, 1270 }; 1271 1272 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1273 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1274 MODULE_VERSION(snd_ich, 1); 1275