1 /*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.53.2.12 2007/07/12 06:39:38 ariff Exp $ 28 */ 29 30 #include <dev/sound/pcm/sound.h> 31 #include <dev/sound/pcm/ac97.h> 32 #include <dev/sound/pci/ich.h> 33 34 #include <bus/pci/pcireg.h> 35 #include <bus/pci/pcivar.h> 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 #define ICH_MIN_BUFSZ 4096 44 #define ICH_DEFAULT_BLKCNT 2 45 #define ICH_MAX_BLKCNT 32 46 #define ICH_MIN_BLKCNT 2 47 #define ICH_MIN_BLKSZ 64 48 49 #define INTEL_VENDORID 0x8086 50 #define SIS_VENDORID 0x1039 51 #define NVIDIA_VENDORID 0x10de 52 #define AMD_VENDORID 0x1022 53 54 #define INTEL_82440MX 0x7195 55 #define INTEL_82801AA 0x2415 56 #define INTEL_82801AB 0x2425 57 #define INTEL_82801BA 0x2445 58 #define INTEL_82801CA 0x2485 59 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 60 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 61 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 62 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 63 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 64 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 65 #define NVIDIA_NFORCE 0x01b1 66 #define NVIDIA_NFORCE2 0x006a 67 #define NVIDIA_NFORCE2_400 0x008a 68 #define NVIDIA_NFORCE3 0x00da 69 #define NVIDIA_NFORCE3_250 0x00ea 70 #define NVIDIA_NFORCE4 0x0059 71 #define NVIDIA_NFORCE_410_MCP 0x026b 72 #define NVIDIA_NFORCE4_MCP 0x003a 73 #define AMD_768 0x7445 74 #define AMD_8111 0x746d 75 76 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 77 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 78 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 79 80 #if 0 81 #define ICH_DEBUG(stmt) do { \ 82 stmt \ 83 } while(0) 84 #else 85 #define ICH_DEBUG(...) 86 #endif 87 88 #define ICH_CALIBRATE_DONE (1 << 0) 89 #define ICH_IGNORE_PCR (1 << 1) 90 #define ICH_IGNORE_RESET (1 << 2) 91 #define ICH_FIXED_RATE (1 << 3) 92 #define ICH_DMA_NOCACHE (1 << 4) 93 #define ICH_HIGH_LATENCY (1 << 5) 94 95 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 96 #include <machine/specialreg.h> 97 #define ICH_DMA_ATTR(sc, v, s, attr) do { \ 98 vm_offset_t va = (vm_offset_t)(v); \ 99 vm_size_t sz = (vm_size_t)(s); \ 100 if ((sc) != NULL && ((sc)->flags & ICH_DMA_NOCACHE) && \ 101 va != 0 && sz != 0) \ 102 (void)pmap_change_attr(va, sz, (attr)); \ 103 } while(0) 104 #else 105 #define ICH_DMA_ATTR(...) 106 #endif 107 108 static const struct ich_type { 109 uint16_t vendor; 110 uint16_t devid; 111 uint32_t options; 112 #define PROBE_LOW 0x01 113 char *name; 114 } ich_devs[] = { 115 { INTEL_VENDORID, INTEL_82440MX, 0, 116 "Intel 440MX" }, 117 { INTEL_VENDORID, INTEL_82801AA, 0, 118 "Intel ICH (82801AA)" }, 119 { INTEL_VENDORID, INTEL_82801AB, 0, 120 "Intel ICH (82801AB)" }, 121 { INTEL_VENDORID, INTEL_82801BA, 0, 122 "Intel ICH2 (82801BA)" }, 123 { INTEL_VENDORID, INTEL_82801CA, 0, 124 "Intel ICH3 (82801CA)" }, 125 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 126 "Intel ICH4 (82801DB)" }, 127 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 128 "Intel ICH5 (82801EB)" }, 129 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 130 "Intel 6300ESB" }, 131 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 132 "Intel ICH6 (82801FB)" }, 133 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 134 "Intel ICH7 (82801GB)" }, 135 { SIS_VENDORID, SIS_7012, 0, 136 "SiS 7012" }, 137 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 138 "nVidia nForce" }, 139 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 140 "nVidia nForce2" }, 141 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 142 "nVidia nForce2 400" }, 143 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 144 "nVidia nForce3" }, 145 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 146 "nVidia nForce3 250" }, 147 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 148 "nVidia nForce4" }, 149 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 150 "nVidia nForce 410 MCP" }, 151 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0, 152 "nVidia nForce 4 MCP" }, 153 { AMD_VENDORID, AMD_768, 0, 154 "AMD-768" }, 155 { AMD_VENDORID, AMD_8111, 0, 156 "AMD-8111" } 157 }; 158 159 /* buffer descriptor */ 160 struct ich_desc { 161 volatile uint32_t buffer; 162 volatile uint32_t length; 163 }; 164 165 struct sc_info; 166 167 /* channel registers */ 168 struct sc_chinfo { 169 uint32_t num:8, run:1, run_save:1; 170 uint32_t blksz, blkcnt, spd; 171 uint32_t regbase, spdreg; 172 uint32_t imask; 173 uint32_t civ; 174 175 struct snd_dbuf *buffer; 176 struct pcm_channel *channel; 177 struct sc_info *parent; 178 179 struct ich_desc *dtbl; 180 bus_addr_t desc_addr; 181 }; 182 183 /* device private data */ 184 struct sc_info { 185 device_t dev; 186 int hasvra, hasvrm, hasmic; 187 unsigned int chnum, bufsz, blkcnt; 188 int sample_size, swap_reg; 189 190 struct resource *nambar, *nabmbar, *irq; 191 int regtype, nambarid, nabmbarid, irqid; 192 bus_space_tag_t nambart, nabmbart; 193 bus_space_handle_t nambarh, nabmbarh; 194 bus_dma_tag_t dmat, chan_dmat; 195 bus_dmamap_t dtmap; 196 void *ih; 197 198 struct ac97_info *codec; 199 struct sc_chinfo ch[3]; 200 int ac97rate; 201 struct ich_desc *dtbl; 202 unsigned int dtbl_size; 203 bus_addr_t desc_addr; 204 struct intr_config_hook intrhook; 205 uint16_t vendor; 206 uint16_t devid; 207 uint32_t flags; 208 sndlock_t ich_lock; 209 }; 210 211 #define IGNORE_PCR 0x01 212 213 /* -------------------------------------------------------------------- */ 214 215 static uint32_t ich_fmt[] = { 216 AFMT_STEREO | AFMT_S16_LE, 217 0 218 }; 219 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 220 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 221 222 /* -------------------------------------------------------------------- */ 223 /* Hardware */ 224 static __inline uint32_t 225 ich_rd(struct sc_info *sc, int regno, int size) 226 { 227 switch (size) { 228 case 1: 229 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno)); 230 case 2: 231 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno)); 232 case 4: 233 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno)); 234 default: 235 return (0xffffffff); 236 } 237 } 238 239 static __inline void 240 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size) 241 { 242 switch (size) { 243 case 1: 244 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 245 break; 246 case 2: 247 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 248 break; 249 case 4: 250 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 251 break; 252 } 253 } 254 255 /* ac97 codec */ 256 static int 257 ich_waitcd(void *devinfo) 258 { 259 struct sc_info *sc = (struct sc_info *)devinfo; 260 uint32_t data; 261 int i; 262 263 for (i = 0; i < ICH_TIMEOUT; i++) { 264 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 265 if ((data & 0x01) == 0) 266 return (0); 267 DELAY(1); 268 } 269 if ((sc->flags & ICH_IGNORE_PCR) != 0) 270 return (0); 271 device_printf(sc->dev, "CODEC semaphore timeout\n"); 272 return (ETIMEDOUT); 273 } 274 275 static int 276 ich_rdcd(kobj_t obj, void *devinfo, int regno) 277 { 278 struct sc_info *sc = (struct sc_info *)devinfo; 279 280 regno &= 0xff; 281 ich_waitcd(sc); 282 283 return (bus_space_read_2(sc->nambart, sc->nambarh, regno)); 284 } 285 286 static int 287 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data) 288 { 289 struct sc_info *sc = (struct sc_info *)devinfo; 290 291 regno &= 0xff; 292 ich_waitcd(sc); 293 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 294 295 return (0); 296 } 297 298 static kobj_method_t ich_ac97_methods[] = { 299 KOBJMETHOD(ac97_read, ich_rdcd), 300 KOBJMETHOD(ac97_write, ich_wrcd), 301 { 0, 0 } 302 }; 303 AC97_DECLARE(ich_ac97); 304 305 /* -------------------------------------------------------------------- */ 306 /* common routines */ 307 308 static void 309 ich_filldtbl(struct sc_chinfo *ch) 310 { 311 struct sc_info *sc = ch->parent; 312 uint32_t base; 313 int i; 314 315 base = sndbuf_getbufaddr(ch->buffer); 316 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer)) 317 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 318 if ((sndbuf_getblksz(ch->buffer) != ch->blksz || 319 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) && 320 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0) 321 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 322 __func__, ch->blksz, ch->blkcnt); 323 ch->blksz = sndbuf_getblksz(ch->buffer); 324 325 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 326 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 327 ch->dtbl[i].length = ICH_BDC_IOC 328 | (ch->blksz / ch->parent->sample_size); 329 } 330 } 331 332 static int 333 ich_resetchan(struct sc_info *sc, int num) 334 { 335 int i, cr, regbase; 336 337 if (num == 0) 338 regbase = ICH_REG_PO_BASE; 339 else if (num == 1) 340 regbase = ICH_REG_PI_BASE; 341 else if (num == 2) 342 regbase = ICH_REG_MC_BASE; 343 else 344 return (ENXIO); 345 346 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 347 #if 1 348 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 349 DELAY(100); 350 #else 351 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 352 #endif 353 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 354 for (i = 0; i < ICH_TIMEOUT; i++) { 355 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 356 if (cr == 0) 357 return (0); 358 DELAY(1); 359 } 360 361 if (sc->flags & ICH_IGNORE_RESET) 362 return (0); 363 #if 0 364 else if (sc->vendor == NVIDIA_VENDORID) { 365 sc->flags |= ICH_IGNORE_RESET; 366 device_printf(sc->dev, "ignoring reset failure!\n"); 367 return (0); 368 } 369 #endif 370 371 device_printf(sc->dev, "cannot reset channel %d\n", num); 372 return (ENXIO); 373 } 374 375 /* -------------------------------------------------------------------- */ 376 /* channel interface */ 377 378 static void * 379 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 380 { 381 struct sc_info *sc = devinfo; 382 struct sc_chinfo *ch; 383 unsigned int num; 384 385 ICH_LOCK(sc); 386 num = sc->chnum++; 387 ch = &sc->ch[num]; 388 ch->num = num; 389 ch->buffer = b; 390 ch->channel = c; 391 ch->parent = sc; 392 ch->run = 0; 393 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 394 ch->desc_addr = sc->desc_addr + 395 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc)); 396 ch->blkcnt = sc->blkcnt; 397 ch->blksz = sc->bufsz / ch->blkcnt; 398 399 switch(ch->num) { 400 case 0: /* play */ 401 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 402 ch->regbase = ICH_REG_PO_BASE; 403 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0; 404 ch->imask = ICH_GLOB_STA_POINT; 405 break; 406 407 case 1: /* record */ 408 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 409 ch->regbase = ICH_REG_PI_BASE; 410 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0; 411 ch->imask = ICH_GLOB_STA_PIINT; 412 break; 413 414 case 2: /* mic */ 415 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 416 ch->regbase = ICH_REG_MC_BASE; 417 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0; 418 ch->imask = ICH_GLOB_STA_MINT; 419 break; 420 421 default: 422 return (NULL); 423 } 424 425 if (sc->flags & ICH_FIXED_RATE) 426 ch->spdreg = 0; 427 428 ICH_UNLOCK(sc); 429 if (sndbuf_alloc(ch->buffer, sc->chan_dmat, sc->bufsz) != 0) 430 return (NULL); 431 432 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer), 433 sndbuf_getmaxsize(ch->buffer), PAT_UNCACHEABLE); 434 435 ICH_LOCK(sc); 436 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 437 ICH_UNLOCK(sc); 438 439 return (ch); 440 } 441 442 static int 443 ichchan_free(kobj_t obj, void *data) 444 { 445 struct sc_chinfo *ch; 446 struct sc_info *sc; 447 448 ch = (struct sc_chinfo *)data; 449 sc = (ch != NULL) ? ch->parent : NULL; 450 if (ch != NULL && sc != NULL) { 451 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer), 452 sndbuf_getmaxsize(ch->buffer), PAT_WRITE_BACK); 453 } 454 455 return (1); 456 } 457 458 static int 459 ichchan_setformat(kobj_t obj, void *data, uint32_t format) 460 { 461 462 ICH_DEBUG( 463 struct sc_chinfo *ch = data; 464 struct sc_info *sc = ch->parent; 465 if (!(sc->flags & ICH_CALIBRATE_DONE)) 466 device_printf(sc->dev, 467 "WARNING: %s() called before calibration!\n", 468 __func__); 469 ); 470 471 return (0); 472 } 473 474 static int 475 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed) 476 { 477 struct sc_chinfo *ch = data; 478 struct sc_info *sc = ch->parent; 479 480 ICH_DEBUG( 481 if (!(sc->flags & ICH_CALIBRATE_DONE)) 482 device_printf(sc->dev, 483 "WARNING: %s() called before calibration!\n", 484 __func__); 485 ); 486 487 if (ch->spdreg) { 488 int r, ac97rate; 489 490 ICH_LOCK(sc); 491 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 492 sc->ac97rate = 48000; 493 ac97rate = sc->ac97rate; 494 ICH_UNLOCK(sc); 495 r = (speed * 48000) / ac97rate; 496 /* 497 * Cast the return value of ac97_setrate() to uint64 so that 498 * the math don't overflow into the negative range. 499 */ 500 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) * 501 ac97rate) / 48000; 502 } else { 503 ch->spd = 48000; 504 } 505 return (ch->spd); 506 } 507 508 static int 509 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 510 { 511 struct sc_chinfo *ch = data; 512 struct sc_info *sc = ch->parent; 513 514 ICH_DEBUG( 515 if (!(sc->flags & ICH_CALIBRATE_DONE)) 516 device_printf(sc->dev, 517 "WARNING: %s() called before calibration!\n", 518 __func__); 519 ); 520 521 if (sc->flags & ICH_HIGH_LATENCY) 522 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 523 524 if (blocksize < ICH_MIN_BLKSZ) 525 blocksize = ICH_MIN_BLKSZ; 526 blocksize &= ~(ICH_MIN_BLKSZ - 1); 527 ch->blksz = blocksize; 528 ich_filldtbl(ch); 529 ICH_LOCK(sc); 530 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 531 ICH_UNLOCK(sc); 532 533 return (ch->blksz); 534 } 535 536 static int 537 ichchan_trigger(kobj_t obj, void *data, int go) 538 { 539 struct sc_chinfo *ch = data; 540 struct sc_info *sc = ch->parent; 541 542 ICH_DEBUG( 543 if (!(sc->flags & ICH_CALIBRATE_DONE)) 544 device_printf(sc->dev, 545 "WARNING: %s() called before calibration!\n", 546 __func__); 547 ); 548 549 switch (go) { 550 case PCMTRIG_START: 551 ch->run = 1; 552 ICH_LOCK(sc); 553 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 554 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 555 ICH_UNLOCK(sc); 556 break; 557 case PCMTRIG_STOP: 558 case PCMTRIG_ABORT: 559 ICH_LOCK(sc); 560 ich_resetchan(sc, ch->num); 561 ICH_UNLOCK(sc); 562 ch->run = 0; 563 break; 564 default: 565 break; 566 } 567 return (0); 568 } 569 570 static int 571 ichchan_getptr(kobj_t obj, void *data) 572 { 573 struct sc_chinfo *ch = data; 574 struct sc_info *sc = ch->parent; 575 uint32_t pos; 576 577 ICH_DEBUG( 578 if (!(sc->flags & ICH_CALIBRATE_DONE)) 579 device_printf(sc->dev, 580 "WARNING: %s() called before calibration!\n", 581 __func__); 582 ); 583 584 ICH_LOCK(sc); 585 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 586 ICH_UNLOCK(sc); 587 588 pos = ch->civ * ch->blksz; 589 590 return (pos); 591 } 592 593 static struct pcmchan_caps * 594 ichchan_getcaps(kobj_t obj, void *data) 595 { 596 struct sc_chinfo *ch = data; 597 598 ICH_DEBUG( 599 struct sc_info *sc = ch->parent; 600 601 if (!(sc->flags & ICH_CALIBRATE_DONE)) 602 device_printf(ch->parent->dev, 603 "WARNING: %s() called before calibration!\n", 604 __func__); 605 ); 606 607 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps); 608 } 609 610 static kobj_method_t ichchan_methods[] = { 611 KOBJMETHOD(channel_init, ichchan_init), 612 KOBJMETHOD(channel_free, ichchan_free), 613 KOBJMETHOD(channel_setformat, ichchan_setformat), 614 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 615 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 616 KOBJMETHOD(channel_trigger, ichchan_trigger), 617 KOBJMETHOD(channel_getptr, ichchan_getptr), 618 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 619 { 0, 0 } 620 }; 621 CHANNEL_DECLARE(ichchan); 622 623 /* -------------------------------------------------------------------- */ 624 /* The interrupt handler */ 625 626 static void 627 ich_intr(void *p) 628 { 629 struct sc_info *sc = (struct sc_info *)p; 630 struct sc_chinfo *ch; 631 uint32_t cbi, lbi, lvi, st, gs; 632 int i; 633 634 ICH_LOCK(sc); 635 636 ICH_DEBUG( 637 if (!(sc->flags & ICH_CALIBRATE_DONE)) 638 device_printf(sc->dev, 639 "WARNING: %s() called before calibration!\n", 640 __func__); 641 ); 642 643 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 644 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 645 /* Clear resume interrupt(s) - nothing doing with them */ 646 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 647 } 648 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 649 650 for (i = 0; i < 3; i++) { 651 ch = &sc->ch[i]; 652 if ((ch->imask & gs) == 0) 653 continue; 654 gs &= ~ch->imask; 655 st = ich_rd(sc, ch->regbase + 656 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 657 2); 658 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 659 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 660 /* block complete - update buffer */ 661 if (ch->run) { 662 ICH_UNLOCK(sc); 663 chn_intr(ch->channel); 664 ICH_LOCK(sc); 665 } 666 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 667 cbi = ch->civ % ch->blkcnt; 668 if (cbi == 0) 669 cbi = ch->blkcnt - 1; 670 else 671 cbi--; 672 lbi = lvi % ch->blkcnt; 673 if (cbi >= lbi) 674 lvi += cbi - lbi; 675 else 676 lvi += cbi + ch->blkcnt - lbi; 677 lvi %= ICH_DTBL_LENGTH; 678 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 679 680 } 681 /* clear status bit */ 682 ich_wr(sc, ch->regbase + 683 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 684 st, 2); 685 } 686 ICH_UNLOCK(sc); 687 if (gs != 0) { 688 device_printf(sc->dev, 689 "Unhandled interrupt, gs_intr = %x\n", gs); 690 } 691 } 692 693 /* ------------------------------------------------------------------------- */ 694 /* Sysctl to control ac97 speed (some boards appear to end up using 695 * XTAL_IN rather than BIT_CLK for link timing). 696 */ 697 698 static int 699 ich_initsys(struct sc_info* sc) 700 { 701 #ifdef SND_DYNSYSCTL 702 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 703 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 704 OID_AUTO, "ac97rate", CTLFLAG_RW, 705 &sc->ac97rate, 48000, 706 "AC97 link rate (default = 48000)"); 707 #endif /* SND_DYNSYSCTL */ 708 return (0); 709 } 710 711 static void 712 ich_setstatus(struct sc_info *sc) 713 { 714 char status[SND_STATUSLEN]; 715 716 ksnprintf(status, SND_STATUSLEN, 717 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 718 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), 719 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 720 721 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE)) 722 device_printf(sc->dev, 723 "PCI Master abort workaround enabled\n"); 724 725 pcm_setstatus(sc->dev, status); 726 } 727 728 /* -------------------------------------------------------------------- */ 729 /* Calibrate card to determine the clock source. The source maybe a 730 * function of the ac97 codec initialization code (to be investigated). 731 */ 732 733 static void 734 ich_calibrate(void *arg) 735 { 736 struct sc_info *sc; 737 struct sc_chinfo *ch; 738 struct timeval t1, t2; 739 uint8_t ociv, nciv; 740 uint32_t wait_us, actual_48k_rate, oblkcnt; 741 742 sc = (struct sc_info *)arg; 743 ICH_LOCK(sc); 744 ch = &sc->ch[1]; 745 746 if (sc->intrhook.ich_func != NULL) { 747 config_intrhook_disestablish(&sc->intrhook); 748 sc->intrhook.ich_func = NULL; 749 } 750 751 /* 752 * Grab audio from input for fixed interval and compare how 753 * much we actually get with what we expect. Interval needs 754 * to be sufficiently short that no interrupts are 755 * generated. 756 */ 757 758 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 759 760 oblkcnt = ch->blkcnt; 761 ch->blkcnt = 2; 762 sc->flags |= ICH_CALIBRATE_DONE; 763 ICH_UNLOCK(sc); 764 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1); 765 ICH_LOCK(sc); 766 sc->flags &= ~ICH_CALIBRATE_DONE; 767 768 /* 769 * our data format is stereo, 16 bit so each sample is 4 bytes. 770 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 771 * we're going to start recording with interrupts disabled and measure 772 * the time taken for one block to complete. we know the block size, 773 * we know the time in microseconds, we calculate the sample rate: 774 * 775 * actual_rate [bps] = bytes / (time [s] * 4) 776 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 777 * actual_rate [Hz] = (bytes * 250000) / time [us] 778 */ 779 780 /* prepare */ 781 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 782 nciv = ociv; 783 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 784 785 /* start */ 786 microtime(&t1); 787 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 788 789 /* wait */ 790 do { 791 microtime(&t2); 792 if (t2.tv_sec - t1.tv_sec > 1) 793 break; 794 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 795 } while (nciv == ociv); 796 797 /* stop */ 798 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 799 800 /* reset */ 801 DELAY(100); 802 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 803 ch->blkcnt = oblkcnt; 804 805 /* turn time delta into us */ 806 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 807 808 if (nciv == ociv) { 809 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 810 sc->flags |= ICH_CALIBRATE_DONE; 811 ICH_UNLOCK(sc); 812 ich_setstatus(sc); 813 return; 814 } 815 816 /* Just in case the timecounter screwed. It is possible, really. */ 817 if (wait_us > 0) 818 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us; 819 else 820 actual_48k_rate = 48000; 821 822 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 823 sc->ac97rate = actual_48k_rate; 824 } else { 825 sc->ac97rate = 48000; 826 } 827 828 if (bootverbose || sc->ac97rate != 48000) { 829 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 830 if (sc->ac97rate != actual_48k_rate) 831 kprintf(", will use %d Hz", sc->ac97rate); 832 kprintf("\n"); 833 } 834 sc->flags |= ICH_CALIBRATE_DONE; 835 ICH_UNLOCK(sc); 836 837 ich_setstatus(sc); 838 839 return; 840 } 841 842 /* -------------------------------------------------------------------- */ 843 /* Probe and attach the card */ 844 845 static void 846 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 847 { 848 struct sc_info *sc = (struct sc_info *)arg; 849 sc->desc_addr = segs->ds_addr; 850 return; 851 } 852 853 static int 854 ich_init(struct sc_info *sc) 855 { 856 uint32_t stat; 857 858 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 859 DELAY(600000); 860 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 861 862 if ((stat & ICH_GLOB_STA_PCR) == 0) { 863 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 864 if (sc->vendor == INTEL_VENDORID && ( 865 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 866 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 867 sc->devid == INTEL_82801GB)) { 868 sc->flags |= ICH_IGNORE_PCR; 869 device_printf(sc->dev, "primary codec not ready!\n"); 870 } 871 } 872 873 #if 0 874 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 875 #else 876 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 877 #endif 878 879 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 880 return (ENXIO); 881 if (sc->hasmic && ich_resetchan(sc, 2)) 882 return (ENXIO); 883 884 return (0); 885 } 886 887 static int 888 ich_pci_probe(device_t dev) 889 { 890 int i; 891 uint16_t devid, vendor; 892 893 vendor = pci_get_vendor(dev); 894 devid = pci_get_device(dev); 895 for (i = 0; i < NELEM(ich_devs); i++) { 896 if (vendor == ich_devs[i].vendor && 897 devid == ich_devs[i].devid) { 898 device_set_desc(dev, ich_devs[i].name); 899 /* allow a better driver to override us */ 900 if ((ich_devs[i].options & PROBE_LOW) != 0) 901 return (BUS_PROBE_LOW_PRIORITY); 902 return (BUS_PROBE_DEFAULT); 903 } 904 } 905 return (ENXIO); 906 } 907 908 static int 909 ich_pci_attach(device_t dev) 910 { 911 uint32_t subdev; 912 uint16_t extcaps; 913 uint16_t devid, vendor; 914 struct sc_info *sc; 915 int i; 916 917 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 918 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc"); 919 sc->dev = dev; 920 921 vendor = sc->vendor = pci_get_vendor(dev); 922 devid = sc->devid = pci_get_device(dev); 923 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 924 /* 925 * The SiS 7012 register set isn't quite like the standard ich. 926 * There really should be a general "quirks" mechanism. 927 */ 928 if (vendor == SIS_VENDORID && devid == SIS_7012) { 929 sc->swap_reg = 1; 930 sc->sample_size = 1; 931 } else { 932 sc->swap_reg = 0; 933 sc->sample_size = 2; 934 } 935 936 /* 937 * Intel 440MX Errata #36 938 * - AC97 Soft Audio and Soft Modem Master Abort Errata 939 * 940 * http://www.intel.com/design/chipsets/specupdt/245051.htm 941 */ 942 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX) 943 sc->flags |= ICH_DMA_NOCACHE; 944 945 /* 946 * Enable bus master. On ich4/5 this may prevent the detection of 947 * the primary codec becoming ready in ich_init(). 948 */ 949 pci_enable_busmaster(dev); 950 951 /* 952 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 953 * read-only. Need to enable "legacy support", by poking into 954 * pci config space. The driver should use MMBAR and MBBAR, 955 * but doing so will mess things up here. ich4 has enough new 956 * features it warrants it's own driver. 957 */ 958 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 959 devid == INTEL_82801EB || devid == INTEL_6300ESB || 960 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 961 sc->nambarid = PCIR_MMBAR; 962 sc->nabmbarid = PCIR_MBBAR; 963 sc->regtype = SYS_RES_MEMORY; 964 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 965 } else { 966 sc->nambarid = PCIR_NAMBAR; 967 sc->nabmbarid = PCIR_NABMBAR; 968 sc->regtype = SYS_RES_IOPORT; 969 } 970 971 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 972 &sc->nambarid, RF_ACTIVE); 973 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 974 &sc->nabmbarid, RF_ACTIVE); 975 976 if (!sc->nambar || !sc->nabmbar) { 977 device_printf(dev, "unable to map IO port space\n"); 978 goto bad; 979 } 980 981 sc->nambart = rman_get_bustag(sc->nambar); 982 sc->nambarh = rman_get_bushandle(sc->nambar); 983 sc->nabmbart = rman_get_bustag(sc->nabmbar); 984 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 985 986 sc->bufsz = pcm_getbuffersize(dev, 987 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 988 989 if (resource_int_value(device_get_name(dev), 990 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 991 sc->blkcnt = sc->bufsz / i; 992 i = 0; 993 while (sc->blkcnt >> i) 994 i++; 995 sc->blkcnt = 1 << (i - 1); 996 if (sc->blkcnt < ICH_MIN_BLKCNT) 997 sc->blkcnt = ICH_MIN_BLKCNT; 998 else if (sc->blkcnt > ICH_MAX_BLKCNT) 999 sc->blkcnt = ICH_MAX_BLKCNT; 1000 } else 1001 sc->blkcnt = ICH_DEFAULT_BLKCNT; 1002 1003 if (resource_int_value(device_get_name(dev), 1004 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) { 1005 sc->flags |= ICH_HIGH_LATENCY; 1006 sc->blkcnt = ICH_MIN_BLKCNT; 1007 } 1008 1009 if (resource_int_value(device_get_name(dev), 1010 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0) 1011 sc->flags |= ICH_FIXED_RATE; 1012 1013 sc->irqid = 0; 1014 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1015 RF_ACTIVE | RF_SHAREABLE); 1016 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, 1017 sc, &sc->ih)) { 1018 device_printf(dev, "unable to map interrupt\n"); 1019 goto bad; 1020 } 1021 1022 if (ich_init(sc)) { 1023 device_printf(dev, "unable to initialize the card\n"); 1024 goto bad; 1025 } 1026 1027 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 1028 if (sc->codec == NULL) 1029 goto bad; 1030 1031 /* 1032 * Turn on inverted external amplifier sense flags for few 1033 * 'special' boards. 1034 */ 1035 switch (subdev) { 1036 case 0x202f161f: /* Gateway 7326GZ */ 1037 case 0x203a161f: /* Gateway 4028GZ */ 1038 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 1039 case 0x8144104d: /* Sony VAIO PCG-TR* */ 1040 case 0x8197104d: /* Sony S1XP */ 1041 case 0x81c0104d: /* Sony VAIO type T */ 1042 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 1043 case 0x3089103c: /* Compaq Presario B3800 */ 1044 case 0x309a103c: /* HP Compaq nx4300 */ 1045 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 1046 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 1047 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 1048 break; 1049 default: 1050 break; 1051 } 1052 1053 mixer_init(dev, ac97_getmixerclass(), sc->codec); 1054 1055 /* check and set VRA function */ 1056 extcaps = ac97_getextcaps(sc->codec); 1057 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 1058 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 1059 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 1060 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1061 1062 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 1063 ((sc->hasmic) ? 3 : 2); 1064 1065 /* BDL tag */ 1066 if (bus_dma_tag_create(NULL, 8, 0, 1067 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1068 sc->dtbl_size, 1, 0x3ffff, 0, &sc->dmat) != 0) { 1069 device_printf(dev, "unable to create dma tag\n"); 1070 goto bad; 1071 } 1072 1073 /* PCM channel tag */ 1074 if (bus_dma_tag_create(NULL, ICH_MIN_BLKSZ, 0, 1075 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1076 sc->bufsz, 1, 0x3ffff, 0, &sc->chan_dmat) != 0) { 1077 device_printf(dev, "unable to create dma tag\n"); 1078 goto bad; 1079 } 1080 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */ 1081 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT | 1082 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1083 &sc->dtmap)) 1084 #else 1085 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, 1086 &sc->dtmap)) 1087 #endif 1088 goto bad; 1089 1090 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size, 1091 ich_setmap, sc, 0)) 1092 goto bad; 1093 1094 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1)) 1095 goto bad; 1096 1097 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 1098 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 1099 if (sc->hasmic) 1100 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 1101 1102 if (sc->flags & ICH_FIXED_RATE) { 1103 sc->flags |= ICH_CALIBRATE_DONE; 1104 ich_setstatus(sc); 1105 } else { 1106 ich_initsys(sc); 1107 1108 sc->intrhook.ich_func = ich_calibrate; 1109 sc->intrhook.ich_arg = sc; 1110 if (cold == 0 || 1111 config_intrhook_establish(&sc->intrhook) != 0) { 1112 sc->intrhook.ich_func = NULL; 1113 ich_calibrate(sc); 1114 } 1115 } 1116 1117 return (0); 1118 1119 bad: 1120 if (sc->codec) 1121 ac97_destroy(sc->codec); 1122 if (sc->ih) 1123 bus_teardown_intr(dev, sc->irq, sc->ih); 1124 if (sc->irq) 1125 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1126 if (sc->nambar) 1127 bus_release_resource(dev, sc->regtype, 1128 sc->nambarid, sc->nambar); 1129 if (sc->nabmbar) 1130 bus_release_resource(dev, sc->regtype, 1131 sc->nabmbarid, sc->nabmbar); 1132 if (sc->dtmap) 1133 bus_dmamap_unload(sc->dmat, sc->dtmap); 1134 if (sc->dtbl) 1135 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1136 if (sc->chan_dmat) 1137 bus_dma_tag_destroy(sc->chan_dmat); 1138 if (sc->dmat) 1139 bus_dma_tag_destroy(sc->dmat); 1140 if (sc->ich_lock) 1141 snd_mtxfree(sc->ich_lock); 1142 kfree(sc, M_DEVBUF); 1143 return (ENXIO); 1144 } 1145 1146 static int 1147 ich_pci_detach(device_t dev) 1148 { 1149 struct sc_info *sc; 1150 int r; 1151 1152 r = pcm_unregister(dev); 1153 if (r) 1154 return (r); 1155 sc = pcm_getdevinfo(dev); 1156 1157 bus_teardown_intr(dev, sc->irq, sc->ih); 1158 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1159 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 1160 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 1161 bus_dmamap_unload(sc->dmat, sc->dtmap); 1162 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1163 bus_dma_tag_destroy(sc->chan_dmat); 1164 bus_dma_tag_destroy(sc->dmat); 1165 snd_mtxfree(sc->ich_lock); 1166 kfree(sc, M_DEVBUF); 1167 return (0); 1168 } 1169 1170 static void 1171 ich_pci_codec_reset(struct sc_info *sc) 1172 { 1173 int i; 1174 uint32_t control; 1175 1176 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 1177 control &= ~(ICH_GLOB_CTL_SHUT); 1178 control |= (control & ICH_GLOB_CTL_COLD) ? 1179 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 1180 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 1181 1182 for (i = 500000; i; i--) { 1183 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 1184 break; /* or ICH_SCR? */ 1185 DELAY(1); 1186 } 1187 1188 if (i <= 0) 1189 kprintf("%s: time out\n", __func__); 1190 } 1191 1192 static int 1193 ich_pci_suspend(device_t dev) 1194 { 1195 struct sc_info *sc; 1196 int i; 1197 1198 sc = pcm_getdevinfo(dev); 1199 ICH_LOCK(sc); 1200 for (i = 0 ; i < 3; i++) { 1201 sc->ch[i].run_save = sc->ch[i].run; 1202 if (sc->ch[i].run) { 1203 ICH_UNLOCK(sc); 1204 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 1205 ICH_LOCK(sc); 1206 } 1207 } 1208 ICH_UNLOCK(sc); 1209 return (0); 1210 } 1211 1212 static int 1213 ich_pci_resume(device_t dev) 1214 { 1215 struct sc_info *sc; 1216 int i; 1217 1218 sc = pcm_getdevinfo(dev); 1219 1220 if (sc->regtype == SYS_RES_IOPORT) 1221 pci_enable_io(dev, SYS_RES_IOPORT); 1222 else 1223 pci_enable_io(dev, SYS_RES_MEMORY); 1224 pci_enable_busmaster(dev); 1225 1226 ICH_LOCK(sc); 1227 /* Reinit audio device */ 1228 if (ich_init(sc) == -1) { 1229 device_printf(dev, "unable to reinitialize the card\n"); 1230 ICH_UNLOCK(sc); 1231 return (ENXIO); 1232 } 1233 /* Reinit mixer */ 1234 ich_pci_codec_reset(sc); 1235 ICH_UNLOCK(sc); 1236 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1237 if (mixer_reinit(dev) == -1) { 1238 device_printf(dev, "unable to reinitialize the mixer\n"); 1239 return (ENXIO); 1240 } 1241 /* Re-start DMA engines */ 1242 for (i = 0 ; i < 3; i++) { 1243 struct sc_chinfo *ch = &sc->ch[i]; 1244 if (sc->ch[i].run_save) { 1245 ichchan_setblocksize(0, ch, ch->blksz); 1246 ichchan_setspeed(0, ch, ch->spd); 1247 ichchan_trigger(0, ch, PCMTRIG_START); 1248 } 1249 } 1250 return (0); 1251 } 1252 1253 static device_method_t ich_methods[] = { 1254 /* Device interface */ 1255 DEVMETHOD(device_probe, ich_pci_probe), 1256 DEVMETHOD(device_attach, ich_pci_attach), 1257 DEVMETHOD(device_detach, ich_pci_detach), 1258 DEVMETHOD(device_suspend, ich_pci_suspend), 1259 DEVMETHOD(device_resume, ich_pci_resume), 1260 { 0, 0 } 1261 }; 1262 1263 static driver_t ich_driver = { 1264 "pcm", 1265 ich_methods, 1266 PCM_SOFTC_SIZE, 1267 }; 1268 1269 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, NULL, NULL); 1270 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1271 MODULE_VERSION(snd_ich, 1); 1272