1 /*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.53.2.9 2006/12/24 05:44:10 ariff Exp $ 28 * $DragonFly: src/sys/dev/sound/pci/ich.c,v 1.14 2007/01/08 01:38:02 swildner Exp $ 29 */ 30 31 #include <dev/sound/pcm/sound.h> 32 #include <dev/sound/pcm/ac97.h> 33 #include <dev/sound/pci/ich.h> 34 35 #include <bus/pci/pcireg.h> 36 #include <bus/pci/pcivar.h> 37 38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/ich.c,v 1.14 2007/01/08 01:38:02 swildner Exp $"); 39 40 /* -------------------------------------------------------------------- */ 41 42 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 43 #define ICH_DTBL_LENGTH 32 44 #define ICH_DEFAULT_BUFSZ 16384 45 #define ICH_MAX_BUFSZ 65536 46 47 #define INTEL_VENDORID 0x8086 48 #define SIS_VENDORID 0x1039 49 #define NVIDIA_VENDORID 0x10de 50 #define AMD_VENDORID 0x1022 51 52 #define INTEL_82440MX 0x7195 53 #define INTEL_82801AA 0x2415 54 #define INTEL_82801AB 0x2425 55 #define INTEL_82801BA 0x2445 56 #define INTEL_82801CA 0x2485 57 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 58 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 59 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 60 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 61 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 62 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 63 #define NVIDIA_NFORCE 0x01b1 64 #define NVIDIA_NFORCE2 0x006a 65 #define NVIDIA_NFORCE2_400 0x008a 66 #define NVIDIA_NFORCE3 0x00da 67 #define NVIDIA_NFORCE3_250 0x00ea 68 #define NVIDIA_NFORCE4 0x0059 69 #define NVIDIA_NFORCE_410_MCP 0x026b 70 #define NVIDIA_NFORCE4_MCP 0x003a 71 #define AMD_768 0x7445 72 #define AMD_8111 0x746d 73 74 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 75 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 76 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 77 78 static const struct ich_type { 79 uint16_t vendor; 80 uint16_t devid; 81 uint32_t options; 82 #define PROBE_LOW 0x01 83 char *name; 84 } ich_devs[] = { 85 { INTEL_VENDORID, INTEL_82440MX, 0, 86 "Intel 440MX" }, 87 { INTEL_VENDORID, INTEL_82801AA, 0, 88 "Intel ICH (82801AA)" }, 89 { INTEL_VENDORID, INTEL_82801AB, 0, 90 "Intel ICH (82801AB)" }, 91 { INTEL_VENDORID, INTEL_82801BA, 0, 92 "Intel ICH2 (82801BA)" }, 93 { INTEL_VENDORID, INTEL_82801CA, 0, 94 "Intel ICH3 (82801CA)" }, 95 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 96 "Intel ICH4 (82801DB)" }, 97 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 98 "Intel ICH5 (82801EB)" }, 99 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 100 "Intel 6300ESB" }, 101 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 102 "Intel ICH6 (82801FB)" }, 103 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 104 "Intel ICH7 (82801GB)" }, 105 { SIS_VENDORID, SIS_7012, 0, 106 "SiS 7012" }, 107 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 108 "nVidia nForce" }, 109 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 110 "nVidia nForce2" }, 111 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 112 "nVidia nForce2 400" }, 113 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 114 "nVidia nForce3" }, 115 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 116 "nVidia nForce3 250" }, 117 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 118 "nVidia nForce4" }, 119 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 120 "nVidia nForce 410 MCP" }, 121 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0, 122 "nVidia nForce 4 MCP" }, 123 { AMD_VENDORID, AMD_768, 0, 124 "AMD-768" }, 125 { AMD_VENDORID, AMD_8111, 0, 126 "AMD-8111" } 127 }; 128 129 /* buffer descriptor */ 130 struct ich_desc { 131 volatile u_int32_t buffer; 132 volatile u_int32_t length; 133 }; 134 135 struct sc_info; 136 137 /* channel registers */ 138 struct sc_chinfo { 139 u_int32_t num:8, run:1, run_save:1; 140 u_int32_t blksz, blkcnt, spd; 141 u_int32_t regbase, spdreg; 142 u_int32_t imask; 143 u_int32_t civ; 144 145 struct snd_dbuf *buffer; 146 struct pcm_channel *channel; 147 struct sc_info *parent; 148 149 struct ich_desc *dtbl; 150 bus_addr_t desc_addr; 151 }; 152 153 /* device private data */ 154 struct sc_info { 155 device_t dev; 156 int hasvra, hasvrm, hasmic; 157 unsigned int chnum, bufsz; 158 int sample_size, swap_reg; 159 160 struct resource *nambar, *nabmbar, *irq; 161 int regtype, nambarid, nabmbarid, irqid; 162 bus_space_tag_t nambart, nabmbart; 163 bus_space_handle_t nambarh, nabmbarh; 164 bus_dma_tag_t dmat; 165 bus_dmamap_t dtmap; 166 void *ih; 167 168 struct ac97_info *codec; 169 struct sc_chinfo ch[3]; 170 int ac97rate; 171 struct ich_desc *dtbl; 172 bus_addr_t desc_addr; 173 struct intr_config_hook intrhook; 174 int use_intrhook; 175 uint16_t vendor; 176 uint16_t devid; 177 uint32_t flags; 178 #define IGNORE_PCR 0x01 179 struct spinlock *ich_lock; 180 }; 181 182 /* -------------------------------------------------------------------- */ 183 184 static u_int32_t ich_fmt[] = { 185 AFMT_STEREO | AFMT_S16_LE, 186 0 187 }; 188 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 189 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 190 191 /* -------------------------------------------------------------------- */ 192 /* Hardware */ 193 static __inline u_int32_t 194 ich_rd(struct sc_info *sc, int regno, int size) 195 { 196 switch (size) { 197 case 1: 198 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 199 case 2: 200 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 201 case 4: 202 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 203 default: 204 return 0xffffffff; 205 } 206 } 207 208 static __inline void 209 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 210 { 211 switch (size) { 212 case 1: 213 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 214 break; 215 case 2: 216 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 217 break; 218 case 4: 219 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 220 break; 221 } 222 } 223 224 /* ac97 codec */ 225 static int 226 ich_waitcd(void *devinfo) 227 { 228 int i; 229 u_int32_t data; 230 struct sc_info *sc = (struct sc_info *)devinfo; 231 232 for (i = 0; i < ICH_TIMEOUT; i++) { 233 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 234 if ((data & 0x01) == 0) 235 return 0; 236 DELAY(1); 237 } 238 if ((sc->flags & IGNORE_PCR) != 0) 239 return (0); 240 device_printf(sc->dev, "CODEC semaphore timeout\n"); 241 return ETIMEDOUT; 242 } 243 244 static int 245 ich_rdcd(kobj_t obj, void *devinfo, int regno) 246 { 247 struct sc_info *sc = (struct sc_info *)devinfo; 248 249 regno &= 0xff; 250 ich_waitcd(sc); 251 252 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 253 } 254 255 static int 256 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 257 { 258 struct sc_info *sc = (struct sc_info *)devinfo; 259 260 regno &= 0xff; 261 ich_waitcd(sc); 262 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 263 264 return 0; 265 } 266 267 static kobj_method_t ich_ac97_methods[] = { 268 KOBJMETHOD(ac97_read, ich_rdcd), 269 KOBJMETHOD(ac97_write, ich_wrcd), 270 { 0, 0 } 271 }; 272 AC97_DECLARE(ich_ac97); 273 274 /* -------------------------------------------------------------------- */ 275 /* common routines */ 276 277 static void 278 ich_filldtbl(struct sc_chinfo *ch) 279 { 280 struct sc_info *sc = ch->parent; 281 u_int32_t base; 282 int i; 283 284 base = sndbuf_getbufaddr(ch->buffer); 285 if (ch->blksz > sc->bufsz / ch->blkcnt) 286 ch->blksz = sc->bufsz / ch->blkcnt; 287 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz); 288 ch->blksz = sndbuf_getblksz(ch->buffer); 289 290 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 291 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 292 ch->dtbl[i].length = ICH_BDC_IOC 293 | (ch->blksz / ch->parent->sample_size); 294 } 295 } 296 297 static int 298 ich_resetchan(struct sc_info *sc, int num) 299 { 300 int i, cr, regbase; 301 302 if (num == 0) 303 regbase = ICH_REG_PO_BASE; 304 else if (num == 1) 305 regbase = ICH_REG_PI_BASE; 306 else if (num == 2) 307 regbase = ICH_REG_MC_BASE; 308 else 309 return ENXIO; 310 311 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 312 #if 1 313 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 314 DELAY(100); 315 #else 316 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 317 #endif 318 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 319 for (i = 0; i < ICH_TIMEOUT; i++) { 320 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 321 if (cr == 0) 322 return 0; 323 } 324 325 device_printf(sc->dev, "cannot reset channel %d\n", num); 326 return ENXIO; 327 } 328 329 /* -------------------------------------------------------------------- */ 330 /* channel interface */ 331 332 static void * 333 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 334 { 335 struct sc_info *sc = devinfo; 336 struct sc_chinfo *ch; 337 unsigned int num; 338 339 ICH_LOCK(sc); 340 num = sc->chnum++; 341 ch = &sc->ch[num]; 342 ch->num = num; 343 ch->buffer = b; 344 ch->channel = c; 345 ch->parent = sc; 346 ch->run = 0; 347 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 348 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 349 sizeof(struct ich_desc); 350 ch->blkcnt = 2; 351 ch->blksz = sc->bufsz / ch->blkcnt; 352 353 switch(ch->num) { 354 case 0: /* play */ 355 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 356 ch->regbase = ICH_REG_PO_BASE; 357 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 358 ch->imask = ICH_GLOB_STA_POINT; 359 break; 360 361 case 1: /* record */ 362 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 363 ch->regbase = ICH_REG_PI_BASE; 364 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 365 ch->imask = ICH_GLOB_STA_PIINT; 366 break; 367 368 case 2: /* mic */ 369 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 370 ch->regbase = ICH_REG_MC_BASE; 371 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 372 ch->imask = ICH_GLOB_STA_MINT; 373 break; 374 375 default: 376 return NULL; 377 } 378 379 ICH_UNLOCK(sc); 380 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 381 return NULL; 382 383 ICH_LOCK(sc); 384 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 385 ICH_UNLOCK(sc); 386 387 return ch; 388 } 389 390 static int 391 ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 392 { 393 return 0; 394 } 395 396 static int 397 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 398 { 399 struct sc_chinfo *ch = data; 400 struct sc_info *sc = ch->parent; 401 402 if (ch->spdreg) { 403 int r, ac97rate; 404 405 ICH_LOCK(sc); 406 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 407 sc->ac97rate = 48000; 408 ac97rate = sc->ac97rate; 409 ICH_UNLOCK(sc); 410 r = (speed * 48000) / ac97rate; 411 /* 412 * Cast the return value of ac97_setrate() to u_int so that 413 * the math don't overflow into the negative range. 414 */ 415 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 416 ac97rate) / 48000; 417 } else { 418 ch->spd = 48000; 419 } 420 return ch->spd; 421 } 422 423 static int 424 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 425 { 426 struct sc_chinfo *ch = data; 427 struct sc_info *sc = ch->parent; 428 429 ch->blksz = blocksize; 430 ich_filldtbl(ch); 431 ICH_LOCK(sc); 432 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 433 ICH_UNLOCK(sc); 434 435 return ch->blksz; 436 } 437 438 static int 439 ichchan_trigger(kobj_t obj, void *data, int go) 440 { 441 struct sc_chinfo *ch = data; 442 struct sc_info *sc = ch->parent; 443 444 switch (go) { 445 case PCMTRIG_START: 446 ch->run = 1; 447 ICH_LOCK(sc); 448 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 449 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 450 ICH_UNLOCK(sc); 451 break; 452 453 case PCMTRIG_ABORT: 454 ICH_LOCK(sc); 455 ich_resetchan(sc, ch->num); 456 ICH_UNLOCK(sc); 457 ch->run = 0; 458 break; 459 } 460 return 0; 461 } 462 463 static int 464 ichchan_getptr(kobj_t obj, void *data) 465 { 466 struct sc_chinfo *ch = data; 467 struct sc_info *sc = ch->parent; 468 u_int32_t pos; 469 470 ICH_LOCK(sc); 471 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 472 ICH_UNLOCK(sc); 473 474 pos = ch->civ * ch->blksz; 475 476 return pos; 477 } 478 479 static struct pcmchan_caps * 480 ichchan_getcaps(kobj_t obj, void *data) 481 { 482 struct sc_chinfo *ch = data; 483 484 return ch->spdreg? &ich_vrcaps : &ich_caps; 485 } 486 487 static kobj_method_t ichchan_methods[] = { 488 KOBJMETHOD(channel_init, ichchan_init), 489 KOBJMETHOD(channel_setformat, ichchan_setformat), 490 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 491 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 492 KOBJMETHOD(channel_trigger, ichchan_trigger), 493 KOBJMETHOD(channel_getptr, ichchan_getptr), 494 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 495 { 0, 0 } 496 }; 497 CHANNEL_DECLARE(ichchan); 498 499 /* -------------------------------------------------------------------- */ 500 /* The interrupt handler */ 501 502 static void 503 ich_intr(void *p) 504 { 505 struct sc_info *sc = (struct sc_info *)p; 506 struct sc_chinfo *ch; 507 u_int32_t cbi, lbi, lvi, st, gs; 508 int i; 509 510 ICH_LOCK(sc); 511 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 512 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 513 /* Clear resume interrupt(s) - nothing doing with them */ 514 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 515 } 516 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 517 518 for (i = 0; i < 3; i++) { 519 ch = &sc->ch[i]; 520 if ((ch->imask & gs) == 0) 521 continue; 522 gs &= ~ch->imask; 523 st = ich_rd(sc, ch->regbase + 524 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 525 2); 526 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 527 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 528 /* block complete - update buffer */ 529 if (ch->run) { 530 ICH_UNLOCK(sc); 531 chn_intr(ch->channel); 532 ICH_LOCK(sc); 533 } 534 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 535 cbi = ch->civ % ch->blkcnt; 536 if (cbi == 0) 537 cbi = ch->blkcnt - 1; 538 else 539 cbi--; 540 lbi = lvi % ch->blkcnt; 541 if (cbi >= lbi) 542 lvi += cbi - lbi; 543 else 544 lvi += cbi + ch->blkcnt - lbi; 545 lvi %= ICH_DTBL_LENGTH; 546 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 547 548 } 549 /* clear status bit */ 550 ich_wr(sc, ch->regbase + 551 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 552 st, 2); 553 } 554 ICH_UNLOCK(sc); 555 if (gs != 0) { 556 device_printf(sc->dev, 557 "Unhandled interrupt, gs_intr = %x\n", gs); 558 } 559 } 560 561 /* ------------------------------------------------------------------------- */ 562 /* Sysctl to control ac97 speed (some boards appear to end up using 563 * XTAL_IN rather than BIT_CLK for link timing). 564 */ 565 566 static int 567 ich_initsys(struct sc_info* sc) 568 { 569 #ifdef SND_DYNSYSCTL 570 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 571 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 572 OID_AUTO, "ac97rate", CTLFLAG_RW, 573 &sc->ac97rate, 48000, 574 "AC97 link rate (default = 48000)"); 575 #endif /* SND_DYNSYSCTL */ 576 return 0; 577 } 578 579 /* -------------------------------------------------------------------- */ 580 /* Calibrate card to determine the clock source. The source maybe a 581 * function of the ac97 codec initialization code (to be investigated). 582 */ 583 584 static 585 void ich_calibrate(void *arg) 586 { 587 struct sc_info *sc; 588 struct sc_chinfo *ch; 589 struct timeval t1, t2; 590 u_int8_t ociv, nciv; 591 u_int32_t wait_us, actual_48k_rate, bytes; 592 593 sc = (struct sc_info *)arg; 594 ch = &sc->ch[1]; 595 596 if (sc->use_intrhook) 597 config_intrhook_disestablish(&sc->intrhook); 598 599 /* 600 * Grab audio from input for fixed interval and compare how 601 * much we actually get with what we expect. Interval needs 602 * to be sufficiently short that no interrupts are 603 * generated. 604 */ 605 606 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 607 608 bytes = sndbuf_getsize(ch->buffer) / 2; 609 ichchan_setblocksize(0, ch, bytes); 610 611 /* 612 * our data format is stereo, 16 bit so each sample is 4 bytes. 613 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 614 * we're going to start recording with interrupts disabled and measure 615 * the time taken for one block to complete. we know the block size, 616 * we know the time in microseconds, we calculate the sample rate: 617 * 618 * actual_rate [bps] = bytes / (time [s] * 4) 619 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 620 * actual_rate [Hz] = (bytes * 250000) / time [us] 621 */ 622 623 /* prepare */ 624 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 625 nciv = ociv; 626 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 627 628 /* start */ 629 microtime(&t1); 630 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 631 632 /* wait */ 633 while (nciv == ociv) { 634 microtime(&t2); 635 if (t2.tv_sec - t1.tv_sec > 1) 636 break; 637 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 638 } 639 microtime(&t2); 640 641 /* stop */ 642 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 643 644 /* reset */ 645 DELAY(100); 646 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 647 648 /* turn time delta into us */ 649 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 650 651 if (nciv == ociv) { 652 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 653 return; 654 } 655 656 actual_48k_rate = (bytes * 250000) / wait_us; 657 658 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 659 sc->ac97rate = actual_48k_rate; 660 } else { 661 sc->ac97rate = 48000; 662 } 663 664 if (bootverbose || sc->ac97rate != 48000) { 665 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 666 if (sc->ac97rate != actual_48k_rate) 667 kprintf(", will use %d Hz", sc->ac97rate); 668 kprintf("\n"); 669 } 670 671 return; 672 } 673 674 /* -------------------------------------------------------------------- */ 675 /* Probe and attach the card */ 676 677 static void 678 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 679 { 680 struct sc_info *sc = (struct sc_info *)arg; 681 sc->desc_addr = segs->ds_addr; 682 return; 683 } 684 685 static int 686 ich_init(struct sc_info *sc) 687 { 688 u_int32_t stat; 689 690 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 691 DELAY(600000); 692 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 693 694 if ((stat & ICH_GLOB_STA_PCR) == 0) { 695 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 696 if (sc->vendor == INTEL_VENDORID && ( 697 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 698 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 699 sc->devid == INTEL_82801GB)) { 700 sc->flags |= IGNORE_PCR; 701 device_printf(sc->dev, "primary codec not ready!\n"); 702 } 703 } 704 705 #if 0 706 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 707 #else 708 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 709 #endif 710 711 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 712 return ENXIO; 713 if (sc->hasmic && ich_resetchan(sc, 2)) 714 return ENXIO; 715 716 return 0; 717 } 718 719 static int 720 ich_pci_probe(device_t dev) 721 { 722 int i; 723 uint16_t devid, vendor; 724 725 vendor = pci_get_vendor(dev); 726 devid = pci_get_device(dev); 727 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 728 if (vendor == ich_devs[i].vendor && 729 devid == ich_devs[i].devid) { 730 device_set_desc(dev, ich_devs[i].name); 731 /* allow a better driver to override us */ 732 if ((ich_devs[i].options & PROBE_LOW) != 0) 733 return (BUS_PROBE_LOW_PRIORITY); 734 return (BUS_PROBE_DEFAULT); 735 } 736 } 737 return (ENXIO); 738 } 739 740 static int 741 ich_pci_attach(device_t dev) 742 { 743 uint32_t subdev; 744 u_int16_t extcaps; 745 uint16_t devid, vendor; 746 struct sc_info *sc; 747 char status[SND_STATUSLEN]; 748 749 if ((sc = kmalloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 750 device_printf(dev, "cannot allocate softc\n"); 751 return ENXIO; 752 } 753 754 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 755 sc->dev = dev; 756 757 vendor = sc->vendor = pci_get_vendor(dev); 758 devid = sc->devid = pci_get_device(dev); 759 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 760 /* 761 * The SiS 7012 register set isn't quite like the standard ich. 762 * There really should be a general "quirks" mechanism. 763 */ 764 if (vendor == SIS_VENDORID && devid == SIS_7012) { 765 sc->swap_reg = 1; 766 sc->sample_size = 1; 767 } else { 768 sc->swap_reg = 0; 769 sc->sample_size = 2; 770 } 771 772 /* 773 * Enable bus master. On ich4/5 this may prevent the detection of 774 * the primary codec becoming ready in ich_init(). 775 */ 776 pci_enable_busmaster(dev); 777 778 /* 779 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 780 * read-only. Need to enable "legacy support", by poking into 781 * pci config space. The driver should use MMBAR and MBBAR, 782 * but doing so will mess things up here. ich4 has enough new 783 * features it warrants it's own driver. 784 */ 785 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 786 devid == INTEL_82801EB || devid == INTEL_6300ESB || 787 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 788 sc->nambarid = PCIR_MMBAR; 789 sc->nabmbarid = PCIR_MBBAR; 790 sc->regtype = SYS_RES_MEMORY; 791 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 792 } else { 793 sc->nambarid = PCIR_NAMBAR; 794 sc->nabmbarid = PCIR_NABMBAR; 795 sc->regtype = SYS_RES_IOPORT; 796 } 797 798 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 799 &sc->nambarid, RF_ACTIVE); 800 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 801 &sc->nabmbarid, RF_ACTIVE); 802 803 if (!sc->nambar || !sc->nabmbar) { 804 device_printf(dev, "unable to map IO port space\n"); 805 goto bad; 806 } 807 808 sc->nambart = rman_get_bustag(sc->nambar); 809 sc->nambarh = rman_get_bushandle(sc->nambar); 810 sc->nabmbart = rman_get_bustag(sc->nabmbar); 811 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 812 813 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 814 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 815 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 816 &sc->dmat) != 0) { 817 device_printf(dev, "unable to create dma tag\n"); 818 goto bad; 819 } 820 821 sc->irqid = 0; 822 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 823 RF_ACTIVE | RF_SHAREABLE); 824 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 825 device_printf(dev, "unable to map interrupt\n"); 826 goto bad; 827 } 828 829 if (ich_init(sc)) { 830 device_printf(dev, "unable to initialize the card\n"); 831 goto bad; 832 } 833 834 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, 835 BUS_DMA_NOWAIT, &sc->dtmap)) 836 goto bad; 837 838 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, 839 sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3, 840 ich_setmap, sc, 0)) 841 goto bad; 842 843 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 844 if (sc->codec == NULL) 845 goto bad; 846 847 /* 848 * Turn on inverted external amplifier sense flags for few 849 * 'special' boards. 850 */ 851 switch (subdev) { 852 case 0x202f161f: /* Gateway 7326GZ */ 853 case 0x203a161f: /* Gateway 4028GZ */ 854 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 855 case 0x8144104d: /* Sony VAIO PCG-TR* */ 856 case 0x8197104d: /* Sony S1XP */ 857 case 0x81c0104d: /* Sony VAIO type T */ 858 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 859 case 0x3089103c: /* Compaq Presario B3800 */ 860 case 0x309a103c: /* HP Compaq nx4300 */ 861 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 862 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 863 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 864 break; 865 default: 866 break; 867 } 868 869 mixer_init(dev, ac97_getmixerclass(), sc->codec); 870 871 /* check and set VRA function */ 872 extcaps = ac97_getextcaps(sc->codec); 873 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 874 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 875 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 876 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 877 878 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 879 goto bad; 880 881 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 882 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 883 if (sc->hasmic) 884 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 885 886 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 887 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 888 889 pcm_setstatus(dev, status); 890 891 ich_initsys(sc); 892 893 sc->intrhook.ich_func = ich_calibrate; 894 sc->intrhook.ich_arg = sc; 895 sc->use_intrhook = 1; 896 if (config_intrhook_establish(&sc->intrhook) != 0) { 897 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 898 sc->use_intrhook = 0; 899 ich_calibrate(sc); 900 } 901 902 return 0; 903 904 bad: 905 if (sc->codec) 906 ac97_destroy(sc->codec); 907 if (sc->ih) 908 bus_teardown_intr(dev, sc->irq, sc->ih); 909 if (sc->irq) 910 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 911 if (sc->nambar) 912 bus_release_resource(dev, sc->regtype, 913 sc->nambarid, sc->nambar); 914 if (sc->nabmbar) 915 bus_release_resource(dev, sc->regtype, 916 sc->nabmbarid, sc->nabmbar); 917 if (sc->dtmap) 918 bus_dmamap_unload(sc->dmat, sc->dtmap); 919 if (sc->dmat) 920 bus_dma_tag_destroy(sc->dmat); 921 if (sc->ich_lock) 922 snd_mtxfree(sc->ich_lock); 923 kfree(sc, M_DEVBUF); 924 return ENXIO; 925 } 926 927 static int 928 ich_pci_detach(device_t dev) 929 { 930 struct sc_info *sc; 931 int r; 932 933 r = pcm_unregister(dev); 934 if (r) 935 return r; 936 sc = pcm_getdevinfo(dev); 937 938 bus_teardown_intr(dev, sc->irq, sc->ih); 939 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 940 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 941 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 942 bus_dmamap_unload(sc->dmat, sc->dtmap); 943 bus_dma_tag_destroy(sc->dmat); 944 snd_mtxfree(sc->ich_lock); 945 kfree(sc, M_DEVBUF); 946 return 0; 947 } 948 949 static void 950 ich_pci_codec_reset(struct sc_info *sc) 951 { 952 int i; 953 uint32_t control; 954 955 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 956 control &= ~(ICH_GLOB_CTL_SHUT); 957 control |= (control & ICH_GLOB_CTL_COLD) ? 958 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 959 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 960 961 for (i = 500000; i; i--) { 962 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 963 break; /* or ICH_SCR? */ 964 DELAY(1); 965 } 966 967 if (i <= 0) 968 kprintf("%s: time out\n", __func__); 969 } 970 971 static int 972 ich_pci_suspend(device_t dev) 973 { 974 struct sc_info *sc; 975 int i; 976 977 sc = pcm_getdevinfo(dev); 978 ICH_LOCK(sc); 979 for (i = 0 ; i < 3; i++) { 980 sc->ch[i].run_save = sc->ch[i].run; 981 if (sc->ch[i].run) { 982 ICH_UNLOCK(sc); 983 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 984 ICH_LOCK(sc); 985 } 986 } 987 ICH_UNLOCK(sc); 988 return 0; 989 } 990 991 static int 992 ich_pci_resume(device_t dev) 993 { 994 struct sc_info *sc; 995 int i; 996 997 sc = pcm_getdevinfo(dev); 998 999 if (sc->regtype == SYS_RES_IOPORT) 1000 pci_enable_io(dev, SYS_RES_IOPORT); 1001 else 1002 pci_enable_io(dev, SYS_RES_MEMORY); 1003 pci_enable_busmaster(dev); 1004 1005 ICH_LOCK(sc); 1006 /* Reinit audio device */ 1007 if (ich_init(sc) == -1) { 1008 device_printf(dev, "unable to reinitialize the card\n"); 1009 ICH_UNLOCK(sc); 1010 return ENXIO; 1011 } 1012 /* Reinit mixer */ 1013 ich_pci_codec_reset(sc); 1014 ICH_UNLOCK(sc); 1015 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1016 if (mixer_reinit(dev) == -1) { 1017 device_printf(dev, "unable to reinitialize the mixer\n"); 1018 return ENXIO; 1019 } 1020 /* Re-start DMA engines */ 1021 for (i = 0 ; i < 3; i++) { 1022 struct sc_chinfo *ch = &sc->ch[i]; 1023 if (sc->ch[i].run_save) { 1024 ichchan_setblocksize(0, ch, ch->blksz); 1025 ichchan_setspeed(0, ch, ch->spd); 1026 ichchan_trigger(0, ch, PCMTRIG_START); 1027 } 1028 } 1029 return 0; 1030 } 1031 1032 static device_method_t ich_methods[] = { 1033 /* Device interface */ 1034 DEVMETHOD(device_probe, ich_pci_probe), 1035 DEVMETHOD(device_attach, ich_pci_attach), 1036 DEVMETHOD(device_detach, ich_pci_detach), 1037 DEVMETHOD(device_suspend, ich_pci_suspend), 1038 DEVMETHOD(device_resume, ich_pci_resume), 1039 { 0, 0 } 1040 }; 1041 1042 static driver_t ich_driver = { 1043 "pcm", 1044 ich_methods, 1045 PCM_SOFTC_SIZE, 1046 }; 1047 1048 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1049 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1050 MODULE_VERSION(snd_ich, 1); 1051