1 /*- 2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifdef HAVE_KERNEL_OPTION_HEADERS 28 #include "opt_snd.h" 29 #endif 30 31 #include <dev/sound/pcm/sound.h> 32 #include <dev/sound/pcm/ac97.h> 33 #include <dev/sound/pci/t4dwave.h> 34 35 #include <bus/pci/pcireg.h> 36 #include <bus/pci/pcivar.h> 37 38 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/t4dwave.c 254263 2013-08-12 23:30:01Z scottl $"); 39 40 /* -------------------------------------------------------------------- */ 41 42 #define TDX_PCI_ID 0x20001023 43 #define TNX_PCI_ID 0x20011023 44 #define ALI_PCI_ID 0x545110b9 45 #define SPA_PCI_ID 0x70181039 46 47 #define TR_DEFAULT_BUFSZ 0x1000 48 /* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */ 49 #define ALI_BUFSZ 0x10000 50 #define TR_BUFALGN 0x8 51 #define TR_TIMEOUT_CDC 0xffff 52 #define TR_MAXHWCH 64 53 #define ALI_MAXHWCH 32 54 #define TR_MAXPLAYCH 4 55 #define ALI_MAXPLAYCH 1 56 /* 57 * Though, it's not clearly documented in the 4DWAVE datasheet, the 58 * DX and NX chips can't handle DMA addresses located above 1GB as the 59 * LBA (loop begin address) register which holds the DMA base address 60 * is 32-bit, but the two MSBs are used for other purposes. 61 */ 62 #define TR_MAXADDR ((1U << 30) - 1) 63 #define ALI_MAXADDR ((1U << 31) - 1) 64 65 struct tr_info; 66 67 /* channel registers */ 68 struct tr_chinfo { 69 u_int32_t cso, alpha, fms, fmc, ec; 70 u_int32_t lba; 71 u_int32_t eso, delta; 72 u_int32_t rvol, cvol; 73 u_int32_t gvsel, pan, vol, ctrl; 74 u_int32_t active:1, was_active:1; 75 int index, bufhalf; 76 struct snd_dbuf *buffer; 77 struct pcm_channel *channel; 78 struct tr_info *parent; 79 }; 80 81 struct tr_rchinfo { 82 u_int32_t delta; 83 u_int32_t active:1, was_active:1; 84 struct snd_dbuf *buffer; 85 struct pcm_channel *channel; 86 struct tr_info *parent; 87 }; 88 89 /* device private data */ 90 struct tr_info { 91 u_int32_t type; 92 u_int32_t rev; 93 94 bus_space_tag_t st; 95 bus_space_handle_t sh; 96 bus_dma_tag_t parent_dmat; 97 98 struct resource *reg, *irq; 99 int regtype, regid, irqid; 100 void *ih; 101 102 struct lock *lock; 103 104 u_int32_t hwchns; 105 u_int32_t playchns; 106 unsigned int bufsz; 107 108 struct tr_chinfo chinfo[TR_MAXPLAYCH]; 109 struct tr_rchinfo recchinfo; 110 }; 111 112 /* -------------------------------------------------------------------- */ 113 114 static u_int32_t tr_recfmt[] = { 115 SND_FORMAT(AFMT_U8, 1, 0), 116 SND_FORMAT(AFMT_U8, 2, 0), 117 SND_FORMAT(AFMT_S8, 1, 0), 118 SND_FORMAT(AFMT_S8, 2, 0), 119 SND_FORMAT(AFMT_S16_LE, 1, 0), 120 SND_FORMAT(AFMT_S16_LE, 2, 0), 121 SND_FORMAT(AFMT_U16_LE, 1, 0), 122 SND_FORMAT(AFMT_U16_LE, 2, 0), 123 0 124 }; 125 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0}; 126 127 static u_int32_t tr_playfmt[] = { 128 SND_FORMAT(AFMT_U8, 1, 0), 129 SND_FORMAT(AFMT_U8, 2, 0), 130 SND_FORMAT(AFMT_S8, 1, 0), 131 SND_FORMAT(AFMT_S8, 2, 0), 132 SND_FORMAT(AFMT_S16_LE, 1, 0), 133 SND_FORMAT(AFMT_S16_LE, 2, 0), 134 SND_FORMAT(AFMT_U16_LE, 1, 0), 135 SND_FORMAT(AFMT_U16_LE, 2, 0), 136 0 137 }; 138 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0}; 139 140 /* -------------------------------------------------------------------- */ 141 142 /* Hardware */ 143 144 static u_int32_t 145 tr_rd(struct tr_info *tr, int regno, int size) 146 { 147 switch(size) { 148 case 1: 149 return bus_space_read_1(tr->st, tr->sh, regno); 150 case 2: 151 return bus_space_read_2(tr->st, tr->sh, regno); 152 case 4: 153 return bus_space_read_4(tr->st, tr->sh, regno); 154 default: 155 return 0xffffffff; 156 } 157 } 158 159 static void 160 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size) 161 { 162 switch(size) { 163 case 1: 164 bus_space_write_1(tr->st, tr->sh, regno, data); 165 break; 166 case 2: 167 bus_space_write_2(tr->st, tr->sh, regno, data); 168 break; 169 case 4: 170 bus_space_write_4(tr->st, tr->sh, regno, data); 171 break; 172 } 173 } 174 175 /* -------------------------------------------------------------------- */ 176 /* ac97 codec */ 177 178 static int 179 tr_rdcd(kobj_t obj, void *devinfo, int regno) 180 { 181 struct tr_info *tr = (struct tr_info *)devinfo; 182 int i, j, treg, trw; 183 184 switch (tr->type) { 185 case SPA_PCI_ID: 186 treg=SPA_REG_CODECRD; 187 trw=SPA_CDC_RWSTAT; 188 break; 189 case ALI_PCI_ID: 190 if (tr->rev > 0x01) 191 treg=TDX_REG_CODECWR; 192 else 193 treg=TDX_REG_CODECRD; 194 trw=TDX_CDC_RWSTAT; 195 break; 196 case TDX_PCI_ID: 197 treg=TDX_REG_CODECRD; 198 trw=TDX_CDC_RWSTAT; 199 break; 200 case TNX_PCI_ID: 201 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD; 202 trw=TNX_CDC_RWSTAT; 203 break; 204 default: 205 kprintf("!!! tr_rdcd defaulted !!!\n"); 206 return -1; 207 } 208 209 i = j = 0; 210 211 regno &= 0x7f; 212 snd_mtxlock(tr->lock); 213 if (tr->type == ALI_PCI_ID) { 214 u_int32_t chk1, chk2; 215 j = trw; 216 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 217 j = tr_rd(tr, treg, 4); 218 if (i > 0) { 219 chk1 = tr_rd(tr, 0xc8, 4); 220 chk2 = tr_rd(tr, 0xc8, 4); 221 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 222 i--) 223 chk2 = tr_rd(tr, 0xc8, 4); 224 } 225 } 226 if (tr->type != ALI_PCI_ID || i > 0) { 227 tr_wr(tr, treg, regno | trw, 4); 228 j=trw; 229 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 230 j=tr_rd(tr, treg, 4); 231 } 232 snd_mtxunlock(tr->lock); 233 if (i == 0) kprintf("codec timeout during read of register %x\n", regno); 234 return (j >> TR_CDC_DATA) & 0xffff; 235 } 236 237 static int 238 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 239 { 240 struct tr_info *tr = (struct tr_info *)devinfo; 241 int i, j, treg, trw; 242 243 switch (tr->type) { 244 case SPA_PCI_ID: 245 treg=SPA_REG_CODECWR; 246 trw=SPA_CDC_RWSTAT; 247 break; 248 case ALI_PCI_ID: 249 case TDX_PCI_ID: 250 treg=TDX_REG_CODECWR; 251 trw=TDX_CDC_RWSTAT; 252 break; 253 case TNX_PCI_ID: 254 treg=TNX_REG_CODECWR; 255 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0); 256 break; 257 default: 258 kprintf("!!! tr_wrcd defaulted !!!"); 259 return -1; 260 } 261 262 i = 0; 263 264 regno &= 0x7f; 265 #if 0 266 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno)); 267 #endif 268 j=trw; 269 snd_mtxlock(tr->lock); 270 if (tr->type == ALI_PCI_ID) { 271 j = trw; 272 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 273 j = tr_rd(tr, treg, 4); 274 if (i > 0) { 275 u_int32_t chk1, chk2; 276 chk1 = tr_rd(tr, 0xc8, 4); 277 chk2 = tr_rd(tr, 0xc8, 4); 278 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 279 i--) 280 chk2 = tr_rd(tr, 0xc8, 4); 281 } 282 } 283 if (tr->type != ALI_PCI_ID || i > 0) { 284 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--) 285 j=tr_rd(tr, treg, 4); 286 if (tr->type == ALI_PCI_ID && tr->rev > 0x01) 287 trw |= 0x0100; 288 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4); 289 } 290 #if 0 291 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno)); 292 #endif 293 snd_mtxunlock(tr->lock); 294 if (i==0) kprintf("codec timeout writing %x, data %x\n", regno, data); 295 return (i > 0)? 0 : -1; 296 } 297 298 static kobj_method_t tr_ac97_methods[] = { 299 KOBJMETHOD(ac97_read, tr_rdcd), 300 KOBJMETHOD(ac97_write, tr_wrcd), 301 KOBJMETHOD_END 302 }; 303 AC97_DECLARE(tr_ac97); 304 305 /* -------------------------------------------------------------------- */ 306 /* playback channel interrupts */ 307 308 #if 0 309 static u_int32_t 310 tr_testint(struct tr_chinfo *ch) 311 { 312 struct tr_info *tr = ch->parent; 313 int bank, chan; 314 315 bank = (ch->index & 0x20) ? 1 : 0; 316 chan = ch->index & 0x1f; 317 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan); 318 } 319 #endif 320 321 static void 322 tr_clrint(struct tr_chinfo *ch) 323 { 324 struct tr_info *tr = ch->parent; 325 int bank, chan; 326 327 bank = (ch->index & 0x20) ? 1 : 0; 328 chan = ch->index & 0x1f; 329 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4); 330 } 331 332 static void 333 tr_enaint(struct tr_chinfo *ch, int enable) 334 { 335 struct tr_info *tr = ch->parent; 336 u_int32_t i, reg; 337 int bank, chan; 338 339 snd_mtxlock(tr->lock); 340 bank = (ch->index & 0x20) ? 1 : 0; 341 chan = ch->index & 0x1f; 342 reg = bank? TR_REG_INTENB : TR_REG_INTENA; 343 344 i = tr_rd(tr, reg, 4); 345 i &= ~(1 << chan); 346 i |= (enable? 1 : 0) << chan; 347 348 tr_clrint(ch); 349 tr_wr(tr, reg, i, 4); 350 snd_mtxunlock(tr->lock); 351 } 352 353 /* playback channels */ 354 355 static void 356 tr_selch(struct tr_chinfo *ch) 357 { 358 struct tr_info *tr = ch->parent; 359 int i; 360 361 i = tr_rd(tr, TR_REG_CIR, 4); 362 i &= ~TR_CIR_MASK; 363 i |= ch->index & 0x3f; 364 tr_wr(tr, TR_REG_CIR, i, 4); 365 } 366 367 static void 368 tr_startch(struct tr_chinfo *ch) 369 { 370 struct tr_info *tr = ch->parent; 371 int bank, chan; 372 373 bank = (ch->index & 0x20) ? 1 : 0; 374 chan = ch->index & 0x1f; 375 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4); 376 } 377 378 static void 379 tr_stopch(struct tr_chinfo *ch) 380 { 381 struct tr_info *tr = ch->parent; 382 int bank, chan; 383 384 bank = (ch->index & 0x20) ? 1 : 0; 385 chan = ch->index & 0x1f; 386 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4); 387 } 388 389 static void 390 tr_wrch(struct tr_chinfo *ch) 391 { 392 struct tr_info *tr = ch->parent; 393 u_int32_t cr[TR_CHN_REGS], i; 394 395 ch->gvsel &= 0x00000001; 396 ch->fmc &= 0x00000003; 397 ch->fms &= 0x0000000f; 398 ch->ctrl &= 0x0000000f; 399 ch->pan &= 0x0000007f; 400 ch->rvol &= 0x0000007f; 401 ch->cvol &= 0x0000007f; 402 ch->vol &= 0x000000ff; 403 ch->ec &= 0x00000fff; 404 ch->alpha &= 0x00000fff; 405 ch->delta &= 0x0000ffff; 406 if (tr->type == ALI_PCI_ID) 407 ch->lba &= ALI_MAXADDR; 408 else 409 ch->lba &= TR_MAXADDR; 410 411 cr[1]=ch->lba; 412 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol); 413 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec); 414 415 switch (tr->type) { 416 case SPA_PCI_ID: 417 case ALI_PCI_ID: 418 case TDX_PCI_ID: 419 ch->cso &= 0x0000ffff; 420 ch->eso &= 0x0000ffff; 421 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms); 422 cr[2]=(ch->eso<<16) | (ch->delta); 423 break; 424 case TNX_PCI_ID: 425 ch->cso &= 0x00ffffff; 426 ch->eso &= 0x00ffffff; 427 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso); 428 cr[2]=((ch->delta>>8)<<24) | (ch->eso); 429 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14); 430 break; 431 } 432 snd_mtxlock(tr->lock); 433 tr_selch(ch); 434 for (i=0; i<TR_CHN_REGS; i++) 435 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4); 436 snd_mtxunlock(tr->lock); 437 } 438 439 static void 440 tr_rdch(struct tr_chinfo *ch) 441 { 442 struct tr_info *tr = ch->parent; 443 u_int32_t cr[5], i; 444 445 snd_mtxlock(tr->lock); 446 tr_selch(ch); 447 for (i=0; i<5; i++) 448 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4); 449 snd_mtxunlock(tr->lock); 450 451 452 if (tr->type == ALI_PCI_ID) 453 ch->lba=(cr[1] & ALI_MAXADDR); 454 else 455 ch->lba=(cr[1] & TR_MAXADDR); 456 ch->fmc= (cr[3] & 0x0000c000) >> 14; 457 ch->rvol= (cr[3] & 0x00003f80) >> 7; 458 ch->cvol= (cr[3] & 0x0000007f); 459 ch->gvsel= (cr[4] & 0x80000000) >> 31; 460 ch->pan= (cr[4] & 0x7f000000) >> 24; 461 ch->vol= (cr[4] & 0x00ff0000) >> 16; 462 ch->ctrl= (cr[4] & 0x0000f000) >> 12; 463 ch->ec= (cr[4] & 0x00000fff); 464 switch(tr->type) { 465 case SPA_PCI_ID: 466 case ALI_PCI_ID: 467 case TDX_PCI_ID: 468 ch->cso= (cr[0] & 0xffff0000) >> 16; 469 ch->alpha= (cr[0] & 0x0000fff0) >> 4; 470 ch->fms= (cr[0] & 0x0000000f); 471 ch->eso= (cr[2] & 0xffff0000) >> 16; 472 ch->delta= (cr[2] & 0x0000ffff); 473 break; 474 case TNX_PCI_ID: 475 ch->cso= (cr[0] & 0x00ffffff); 476 ch->eso= (cr[2] & 0x00ffffff); 477 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24); 478 ch->alpha= (cr[3] & 0xfff00000) >> 20; 479 ch->fms= (cr[3] & 0x000f0000) >> 16; 480 break; 481 } 482 } 483 484 static u_int32_t 485 tr_fmttobits(u_int32_t fmt) 486 { 487 u_int32_t bits; 488 489 bits = 0; 490 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0; 491 bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0; 492 bits |= (fmt & AFMT_16BIT)? 0x8 : 0; 493 494 return bits; 495 } 496 497 /* -------------------------------------------------------------------- */ 498 /* channel interface */ 499 500 static void * 501 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 502 { 503 struct tr_info *tr = devinfo; 504 struct tr_chinfo *ch; 505 506 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction")); 507 ch = &tr->chinfo[tr->playchns]; 508 ch->index = tr->playchns++; 509 ch->buffer = b; 510 ch->parent = tr; 511 ch->channel = c; 512 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 513 return NULL; 514 515 return ch; 516 } 517 518 static int 519 trpchan_setformat(kobj_t obj, void *data, u_int32_t format) 520 { 521 struct tr_chinfo *ch = data; 522 523 ch->ctrl = tr_fmttobits(format) | 0x01; 524 525 return 0; 526 } 527 528 static u_int32_t 529 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 530 { 531 struct tr_chinfo *ch = data; 532 533 ch->delta = (speed << 12) / 48000; 534 return (ch->delta * 48000) >> 12; 535 } 536 537 static u_int32_t 538 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 539 { 540 struct tr_chinfo *ch = data; 541 542 sndbuf_resize(ch->buffer, 2, blocksize); 543 return blocksize; 544 } 545 546 static int 547 trpchan_trigger(kobj_t obj, void *data, int go) 548 { 549 struct tr_chinfo *ch = data; 550 551 if (!PCMTRIG_COMMON(go)) 552 return 0; 553 554 if (go == PCMTRIG_START) { 555 ch->fmc = 3; 556 ch->fms = 0; 557 ch->ec = 0; 558 ch->alpha = 0; 559 ch->lba = sndbuf_getbufaddr(ch->buffer); 560 ch->cso = 0; 561 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1; 562 ch->rvol = ch->cvol = 0x7f; 563 ch->gvsel = 0; 564 ch->pan = 0; 565 ch->vol = 0; 566 ch->bufhalf = 0; 567 tr_wrch(ch); 568 tr_enaint(ch, 1); 569 tr_startch(ch); 570 ch->active = 1; 571 } else { 572 tr_stopch(ch); 573 ch->active = 0; 574 } 575 576 return 0; 577 } 578 579 static u_int32_t 580 trpchan_getptr(kobj_t obj, void *data) 581 { 582 struct tr_chinfo *ch = data; 583 584 tr_rdch(ch); 585 return ch->cso * sndbuf_getalign(ch->buffer); 586 } 587 588 static struct pcmchan_caps * 589 trpchan_getcaps(kobj_t obj, void *data) 590 { 591 return &tr_playcaps; 592 } 593 594 static kobj_method_t trpchan_methods[] = { 595 KOBJMETHOD(channel_init, trpchan_init), 596 KOBJMETHOD(channel_setformat, trpchan_setformat), 597 KOBJMETHOD(channel_setspeed, trpchan_setspeed), 598 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize), 599 KOBJMETHOD(channel_trigger, trpchan_trigger), 600 KOBJMETHOD(channel_getptr, trpchan_getptr), 601 KOBJMETHOD(channel_getcaps, trpchan_getcaps), 602 KOBJMETHOD_END 603 }; 604 CHANNEL_DECLARE(trpchan); 605 606 /* -------------------------------------------------------------------- */ 607 /* rec channel interface */ 608 609 static void * 610 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 611 { 612 struct tr_info *tr = devinfo; 613 struct tr_rchinfo *ch; 614 615 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction")); 616 ch = &tr->recchinfo; 617 ch->buffer = b; 618 ch->parent = tr; 619 ch->channel = c; 620 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 621 return NULL; 622 623 return ch; 624 } 625 626 static int 627 trrchan_setformat(kobj_t obj, void *data, u_int32_t format) 628 { 629 struct tr_rchinfo *ch = data; 630 struct tr_info *tr = ch->parent; 631 u_int32_t i, bits; 632 633 bits = tr_fmttobits(format); 634 /* set # of samples between interrupts */ 635 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1; 636 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4); 637 /* set sample format */ 638 i = 0x18 | (bits << 4); 639 tr_wr(tr, TR_REG_SBCTRL, i, 1); 640 641 return 0; 642 } 643 644 static u_int32_t 645 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 646 { 647 struct tr_rchinfo *ch = data; 648 struct tr_info *tr = ch->parent; 649 650 /* setup speed */ 651 ch->delta = (48000 << 12) / speed; 652 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2); 653 654 /* return closest possible speed */ 655 return (48000 << 12) / ch->delta; 656 } 657 658 static u_int32_t 659 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 660 { 661 struct tr_rchinfo *ch = data; 662 663 sndbuf_resize(ch->buffer, 2, blocksize); 664 665 return blocksize; 666 } 667 668 static int 669 trrchan_trigger(kobj_t obj, void *data, int go) 670 { 671 struct tr_rchinfo *ch = data; 672 struct tr_info *tr = ch->parent; 673 u_int32_t i; 674 675 if (!PCMTRIG_COMMON(go)) 676 return 0; 677 678 if (go == PCMTRIG_START) { 679 /* set up dma mode regs */ 680 tr_wr(tr, TR_REG_DMAR15, 0, 1); 681 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03; 682 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1); 683 /* set up base address */ 684 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4); 685 /* set up buffer size */ 686 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff; 687 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4); 688 /* start */ 689 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1); 690 ch->active = 1; 691 } else { 692 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1); 693 ch->active = 0; 694 } 695 696 /* return 0 if ok */ 697 return 0; 698 } 699 700 static u_int32_t 701 trrchan_getptr(kobj_t obj, void *data) 702 { 703 struct tr_rchinfo *ch = data; 704 struct tr_info *tr = ch->parent; 705 706 /* return current byte offset of channel */ 707 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer); 708 } 709 710 static struct pcmchan_caps * 711 trrchan_getcaps(kobj_t obj, void *data) 712 { 713 return &tr_reccaps; 714 } 715 716 static kobj_method_t trrchan_methods[] = { 717 KOBJMETHOD(channel_init, trrchan_init), 718 KOBJMETHOD(channel_setformat, trrchan_setformat), 719 KOBJMETHOD(channel_setspeed, trrchan_setspeed), 720 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize), 721 KOBJMETHOD(channel_trigger, trrchan_trigger), 722 KOBJMETHOD(channel_getptr, trrchan_getptr), 723 KOBJMETHOD(channel_getcaps, trrchan_getcaps), 724 KOBJMETHOD_END 725 }; 726 CHANNEL_DECLARE(trrchan); 727 728 /* -------------------------------------------------------------------- */ 729 /* The interrupt handler */ 730 731 static void 732 tr_intr(void *p) 733 { 734 struct tr_info *tr = (struct tr_info *)p; 735 struct tr_chinfo *ch; 736 u_int32_t active, mask, bufhalf, chnum, intsrc; 737 int tmp; 738 739 intsrc = tr_rd(tr, TR_REG_MISCINT, 4); 740 if (intsrc & TR_INT_ADDR) { 741 chnum = 0; 742 while (chnum < tr->hwchns) { 743 mask = 0x00000001; 744 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); 745 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); 746 if (active) { 747 do { 748 if (active & mask) { 749 tmp = (bufhalf & mask)? 1 : 0; 750 if (chnum < tr->playchns) { 751 ch = &tr->chinfo[chnum]; 752 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */ 753 if (ch->bufhalf != tmp) { 754 chn_intr(ch->channel); 755 ch->bufhalf = tmp; 756 } 757 } 758 } 759 chnum++; 760 mask <<= 1; 761 } while (chnum & 31); 762 } else 763 chnum += 32; 764 765 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4); 766 } 767 } 768 if (intsrc & TR_INT_SB) { 769 chn_intr(tr->recchinfo.channel); 770 tr_rd(tr, TR_REG_SBR9, 1); 771 tr_rd(tr, TR_REG_SBR10, 1); 772 } 773 } 774 775 /* -------------------------------------------------------------------- */ 776 777 /* 778 * Probe and attach the card 779 */ 780 781 static int 782 tr_init(struct tr_info *tr) 783 { 784 switch (tr->type) { 785 case SPA_PCI_ID: 786 tr_wr(tr, SPA_REG_GPIO, 0, 4); 787 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); 788 break; 789 case TDX_PCI_ID: 790 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); 791 break; 792 case TNX_PCI_ID: 793 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4); 794 break; 795 } 796 797 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4); 798 return 0; 799 } 800 801 static int 802 tr_pci_probe(device_t dev) 803 { 804 switch (pci_get_devid(dev)) { 805 case SPA_PCI_ID: 806 device_set_desc(dev, "SiS 7018"); 807 return BUS_PROBE_DEFAULT; 808 case ALI_PCI_ID: 809 device_set_desc(dev, "Acer Labs M5451"); 810 return BUS_PROBE_DEFAULT; 811 case TDX_PCI_ID: 812 device_set_desc(dev, "Trident 4DWave DX"); 813 return BUS_PROBE_DEFAULT; 814 case TNX_PCI_ID: 815 device_set_desc(dev, "Trident 4DWave NX"); 816 return BUS_PROBE_DEFAULT; 817 } 818 819 return ENXIO; 820 } 821 822 static int 823 tr_pci_attach(device_t dev) 824 { 825 struct tr_info *tr; 826 struct ac97_info *codec = 0; 827 bus_addr_t lowaddr; 828 int i, dacn; 829 char status[SND_STATUSLEN]; 830 #ifdef __sparc64__ 831 device_t *children; 832 int nchildren; 833 u_int32_t data; 834 #endif 835 836 tr = kmalloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO); 837 tr->type = pci_get_devid(dev); 838 tr->rev = pci_get_revid(dev); 839 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc"); 840 841 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 842 "dac", &i) == 0) { 843 if (i < 1) 844 dacn = 1; 845 else if (i > TR_MAXPLAYCH) 846 dacn = TR_MAXPLAYCH; 847 else 848 dacn = i; 849 } else { 850 switch (tr->type) { 851 case ALI_PCI_ID: 852 dacn = ALI_MAXPLAYCH; 853 break; 854 default: 855 dacn = TR_MAXPLAYCH; 856 break; 857 } 858 } 859 860 pci_enable_busmaster(dev); 861 862 tr->regid = PCIR_BAR(0); 863 tr->regtype = SYS_RES_IOPORT; 864 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid, 865 RF_ACTIVE); 866 if (tr->reg) { 867 tr->st = rman_get_bustag(tr->reg); 868 tr->sh = rman_get_bushandle(tr->reg); 869 } else { 870 device_printf(dev, "unable to map register space\n"); 871 goto bad; 872 } 873 874 if (tr_init(tr) == -1) { 875 device_printf(dev, "unable to initialize the card\n"); 876 goto bad; 877 } 878 tr->playchns = 0; 879 880 codec = AC97_CREATE(dev, tr, tr_ac97); 881 if (codec == NULL) goto bad; 882 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 883 884 tr->irqid = 0; 885 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid, 886 RF_ACTIVE | RF_SHAREABLE); 887 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) { 888 device_printf(dev, "unable to map interrupt\n"); 889 goto bad; 890 } 891 892 if (tr->type == ALI_PCI_ID) { 893 /* 894 * The M5451 generates 31 bit of DMA and in order to do 895 * 32-bit DMA, the 31st bit can be set via its accompanying 896 * ISA bridge. Note that we can't predict whether bus_dma(9) 897 * will actually supply us with a 32-bit buffer and even when 898 * using a low address of BUS_SPACE_MAXADDR_32BIT for both 899 * we might end up with the play buffer being in the 32-bit 900 * range while the record buffer isn't or vice versa. So we 901 * limit enabling the 31st bit to sparc64, where the IOMMU 902 * guarantees that we're using a 32-bit address (and in turn 903 * requires it). 904 */ 905 lowaddr = ALI_MAXADDR; 906 #ifdef __sparc64__ 907 if (device_get_children(device_get_parent(dev), &children, 908 &nchildren) == 0) { 909 for (i = 0; i < nchildren; i++) { 910 if (pci_get_devid(children[i]) == 0x153310b9) { 911 lowaddr = BUS_SPACE_MAXADDR_32BIT; 912 data = pci_read_config(children[i], 913 0x7e, 1); 914 if (bootverbose) 915 device_printf(dev, 916 "M1533 0x7e: 0x%x -> ", 917 data); 918 data |= 0x1; 919 if (bootverbose) 920 kprintf("0x%x\n", data); 921 pci_write_config(children[i], 0x7e, 922 data, 1); 923 break; 924 } 925 } 926 } 927 kfree(children, M_TEMP); 928 #endif 929 tr->hwchns = ALI_MAXHWCH; 930 tr->bufsz = ALI_BUFSZ; 931 } else { 932 lowaddr = TR_MAXADDR; 933 tr->hwchns = TR_MAXHWCH; 934 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 935 65536); 936 } 937 938 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), 939 /*alignment*/TR_BUFALGN, 940 /*boundary*/0, 941 /*lowaddr*/lowaddr, 942 /*highaddr*/BUS_SPACE_MAXADDR, 943 /*filter*/NULL, /*filterarg*/NULL, 944 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz, 945 /*flags*/0, 946 &tr->parent_dmat) != 0) { 947 device_printf(dev, "unable to create dma tag\n"); 948 goto bad; 949 } 950 951 ksnprintf(status, 64, "at io 0x%lx irq %ld %s", 952 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave)); 953 954 if (pcm_register(dev, tr, dacn, 1)) 955 goto bad; 956 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr); 957 for (i = 0; i < dacn; i++) 958 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr); 959 pcm_setstatus(dev, status); 960 961 return 0; 962 963 bad: 964 if (codec) ac97_destroy(codec); 965 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 966 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih); 967 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 968 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat); 969 if (tr->lock) snd_mtxfree(tr->lock); 970 kfree(tr, M_DEVBUF); 971 return ENXIO; 972 } 973 974 static int 975 tr_pci_detach(device_t dev) 976 { 977 int r; 978 struct tr_info *tr; 979 980 r = pcm_unregister(dev); 981 if (r) 982 return r; 983 984 tr = pcm_getdevinfo(dev); 985 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 986 bus_teardown_intr(dev, tr->irq, tr->ih); 987 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 988 bus_dma_tag_destroy(tr->parent_dmat); 989 snd_mtxfree(tr->lock); 990 kfree(tr, M_DEVBUF); 991 992 return 0; 993 } 994 995 static int 996 tr_pci_suspend(device_t dev) 997 { 998 int i; 999 struct tr_info *tr; 1000 1001 tr = pcm_getdevinfo(dev); 1002 1003 for (i = 0; i < tr->playchns; i++) { 1004 tr->chinfo[i].was_active = tr->chinfo[i].active; 1005 if (tr->chinfo[i].active) { 1006 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP); 1007 } 1008 } 1009 1010 tr->recchinfo.was_active = tr->recchinfo.active; 1011 if (tr->recchinfo.active) { 1012 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP); 1013 } 1014 1015 return 0; 1016 } 1017 1018 static int 1019 tr_pci_resume(device_t dev) 1020 { 1021 int i; 1022 struct tr_info *tr; 1023 1024 tr = pcm_getdevinfo(dev); 1025 1026 if (tr_init(tr) == -1) { 1027 device_printf(dev, "unable to initialize the card\n"); 1028 return ENXIO; 1029 } 1030 1031 if (mixer_reinit(dev) == -1) { 1032 device_printf(dev, "unable to initialize the mixer\n"); 1033 return ENXIO; 1034 } 1035 1036 for (i = 0; i < tr->playchns; i++) { 1037 if (tr->chinfo[i].was_active) { 1038 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START); 1039 } 1040 } 1041 1042 if (tr->recchinfo.was_active) { 1043 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START); 1044 } 1045 1046 return 0; 1047 } 1048 1049 static device_method_t tr_methods[] = { 1050 /* Device interface */ 1051 DEVMETHOD(device_probe, tr_pci_probe), 1052 DEVMETHOD(device_attach, tr_pci_attach), 1053 DEVMETHOD(device_detach, tr_pci_detach), 1054 DEVMETHOD(device_suspend, tr_pci_suspend), 1055 DEVMETHOD(device_resume, tr_pci_resume), 1056 { 0, 0 } 1057 }; 1058 1059 static driver_t tr_driver = { 1060 "pcm", 1061 tr_methods, 1062 PCM_SOFTC_SIZE, 1063 }; 1064 1065 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, NULL, NULL); 1066 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1067 MODULE_VERSION(snd_t4dwave, 1); 1068