1 /* 2 * Copyright (c) 2003, 2004, 2005 3 * John Wehle <john@feith.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by John Wehle. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _CXM_H 33 #define _CXM_H 34 35 /* 36 * Header file for the Conexant MPEG-2 Codec driver. 37 */ 38 39 #include <sys/selinfo.h> 40 41 #include <bus/pci/pcidevs.h> 42 43 #define bswap32(X) ntohl(X) 44 45 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 46 47 /* 48 * For simplicity several large buffers allocate during 49 * driver attachment which normally occurs early on 50 * (when large areas of memory are available) are used 51 * to move data to / from the card. It's not unusual 52 * for the memory allocation to fail due to fragmentation 53 * if the driver is loaded after the system has been 54 * running for a while. One solution is to allocate 55 * several PAGE_SIZE buffers instead, however it doesn't 56 * seem worth the trouble. 57 */ 58 enum cxm_byte_order { cxm_unknown_byte_order, 59 cxm_device_mpeg_byte_order, cxm_device_yuv12_byte_order, 60 cxm_host_byte_order }; 61 62 struct cxm_buffer { 63 char *vaddr; 64 bus_addr_t baddr; 65 bus_dmamap_t dmamap; 66 size_t size; 67 enum cxm_byte_order byte_order; 68 }; 69 70 #define CXM_SG_BUFFERS 50 71 72 struct cxm_buffer_pool { 73 bus_dma_tag_t dmat; 74 size_t offset; 75 unsigned int read; 76 volatile unsigned int write; 77 struct cxm_buffer bufs[CXM_SG_BUFFERS]; 78 }; 79 80 /* 81 * Audio format encoding 82 * 83 * 7 6 5 4 3 2 1 0 84 * 85 * 0 0 44.1 kHz 86 * 0 1 48 kHz 87 * 1 0 32 kHz 88 * 89 * 0 1 Layer 1 90 * 1 0 Layer 2 91 * 1 1 Layer 3 92 * 93 * L1 / L2 94 * 0 0 0 0 Free fmt 95 * 0 0 0 1 32k / 32k 96 * 0 0 1 0 64k / 48k 97 * 0 0 1 1 96k / 56k 98 * 0 1 0 0 128k / 64k 99 * 0 1 0 1 160k / 80k 100 * 0 1 1 0 192k / 96k 101 * 0 1 1 1 224k / 112k 102 * 1 0 0 0 256k / 128k 103 * 1 0 0 1 288k / 160k 104 * 1 0 1 0 320k / 192k 105 * 1 0 1 1 352k / 224k 106 * 1 1 0 0 384k / 256k 107 * 1 1 0 1 416k / 320k 108 * 1 1 1 0 448k / 384k 109 */ 110 struct cxm_codec_audio_format { 111 unsigned int sample_rate; 112 uint32_t format; 113 }; 114 115 struct cxm_codec_profile { 116 const char *name; 117 uint32_t stream_type; 118 uint32_t fps; 119 uint32_t width; 120 uint32_t height; 121 uint32_t source_height; 122 struct { 123 uint32_t start; 124 uint32_t nlines; 125 uint32_t cc; 126 } vbi; 127 uint32_t aspect; 128 uint32_t pulldown; 129 struct { 130 uint32_t mode; 131 uint32_t average; 132 uint32_t peak; 133 } bitrate; 134 struct { 135 uint32_t closure; 136 uint32_t frames; 137 uint32_t bframes; 138 } gop; 139 struct { 140 uint32_t mode; 141 uint32_t type; 142 uint32_t spatial; 143 uint32_t temporal; 144 } dnr; 145 146 unsigned int audio_sample_rate; 147 }; 148 149 struct cxm_dev { 150 uint16_t vid; 151 uint16_t did; 152 char *name; 153 }; 154 155 #define CXM_MBX_FW_CMD_MAILBOX 0 156 #define CXM_MBX_FW_CMD_MAILBOXES 6 157 158 #define CXM_MBX_FW_DMA_MAILBOX 9 159 160 #define CXM_MBX_MAX_PARAMETERS 16 161 162 /* Mailbox flags bit definitions */ 163 #define CXM_MBX_FLAG_DRV_DONE 0x00000002 164 #define CXM_MBX_FLAG_FW_DONE 0x00000004 165 #define CXM_MBX_FLAG_IN_USE 0x00000001 166 167 struct cxm_mailbox { 168 uint32_t flags; 169 uint32_t command; 170 uint32_t result; 171 uint32_t timeout; 172 uint32_t parameters[CXM_MBX_MAX_PARAMETERS]; 173 } __attribute__ ((packed)); 174 175 enum cxm_mailbox_name { cxm_unknown_mailbox, 176 cxm_dec_mailbox, cxm_enc_mailbox }; 177 178 /* 179 * Scatter / gather is supported with the restriction 180 * that the size of each piece must be a multiple of 181 * 256 and less than 64k. 182 */ 183 #define CXM_SG_SEGMENT (0xff00 & ~(PAGE_SIZE - 1)) 184 185 struct cxm_sg_entry { 186 uint32_t src; 187 uint32_t dst; 188 uint32_t size; 189 } __attribute__ ((packed)); 190 191 struct cxm_sg_list { 192 bus_dma_tag_t dmat; 193 struct cxm_sg_entry *vaddr; 194 bus_addr_t baddr; 195 bus_dmamap_t dmamap; 196 197 }; 198 199 enum cxm_source { cxm_unknown_source, cxm_fm_source, cxm_tuner_source, 200 cxm_line_in_source_composite, cxm_line_in_source_svideo }; 201 202 enum cxm_source_format { cxm_unknown_source_format, 203 cxm_bw_50hz_source_format, 204 cxm_bw_60hz_source_format, 205 cxm_ntsc_50hz_source_format, 206 cxm_ntsc_60hz_source_format, 207 cxm_pal_50hz_source_format, 208 cxm_pal_60hz_source_format, 209 cxm_secam_50hz_source_format }; 210 211 enum cxm_type { cxm_unknown_type, cxm_iTVC15_type, cxm_iTVC16_type }; 212 213 /* 214 * Conexant iTVC15 / iTVC16 info structure, one per card installed. 215 */ 216 struct cxm_softc { 217 enum cxm_type type; 218 219 struct resource *mem_res; /* Resource descriptor for registers */ 220 bus_space_tag_t btag; /* Bus space access functions */ 221 bus_space_handle_t bhandle; /* Bus space access functions */ 222 223 struct resource *irq_res; /* Resource descriptor for interrupt */ 224 void *ih_cookie; /* Newbus interrupt handler cookie */ 225 226 uint32_t irq_mask; 227 228 bus_dma_tag_t parent_dmat; 229 230 struct cxm_buffer_pool enc_pool; 231 struct cxm_sg_list enc_sg; 232 233 struct selinfo enc_sel; 234 235 struct proc *enc_proc; 236 int enc_signal; 237 238 unsigned int dec_mbx; 239 unsigned int enc_mbx; 240 241 device_t cxm_iic; 242 device_t iicbus; 243 244 const struct cxm_tuner *tuner; 245 const struct cxm_tuner_channels *tuner_channels; 246 int tuner_afc; 247 unsigned long tuner_freq; 248 249 char msp_name[10]; 250 251 const struct cxm_codec_profile *profile; 252 253 enum cxm_source source; 254 255 device_t dev; /* bus attachment */ 256 cdev_t cxm_dev_t; /* control device */ 257 int is_opened; 258 int mpeg; 259 260 int encoding; 261 int encoding_dma; 262 int encoding_eos; 263 int video_std; 264 }; 265 266 /* 267 * Conexant iTVC15 / iTVC16 I2C info structure, one per card installed. 268 */ 269 struct cxm_iic_softc { 270 bus_space_tag_t btag; /* Bus space access functions */ 271 bus_space_handle_t bhandle; /* Bus space access functions */ 272 273 device_t iicbb; 274 275 }; 276 277 /* 278 * List of IVARS available to the I2C device driver 279 */ 280 #define CXM_IVAR_BHANDLE 0 281 #define CXM_IVAR_BTAG 1 282 #define CXM_IVAR_IICBUS 2 283 284 /* 285 * Bus resource id 286 */ 287 #define CXM_RID PCIR_MAPS 288 289 /* 290 * Access macros 291 */ 292 #define CSR_WRITE_4(sc, reg, val) \ 293 bus_space_write_4((sc)->btag, (sc)->bhandle, (reg), (val)) 294 #define CSR_WRITE_2(sc, reg, val) \ 295 bus_space_write_2((sc)->btag, (sc)->bhandle, (reg), val)) 296 #define CSR_WRITE_1(sc, reg, val) \ 297 bus_space_write_1((sc)->btag, (sc)->bhandle, (reg), val)) 298 #define CSR_READ_4(sc, reg) \ 299 bus_space_read_4((sc)->btag, (sc)->bhandle, (reg)) 300 #define CSR_READ_2(sc, reg) \ 301 bus_space_read_2((sc)->btag, (sc)->bhandle, (reg)) 302 #define CSR_READ_1(sc, reg) \ 303 bus_space_read_1((sc)->btag, (sc)->bhandle, (reg)) 304 305 /* 306 * Decoder / encoder firmware 307 */ 308 extern const char cxm_dec_fw[]; 309 extern const char cxm_enc_fw[]; 310 311 #define CXM_FW_SIZE (256 * 1024) 312 313 /* 314 * Decoder / encoder memory offsets 315 */ 316 #define CXM_MEM_DEC 0x01000000 317 #define CXM_MEM_ENC 0x00000000 318 319 #define CXM_MEM_DEC_SIZE 0x01000000 320 #define CXM_MEM_ENC_SIZE 0x01000000 321 322 /* 323 * Register offsets 324 */ 325 #define CXM_REG_AO 0x2002d00 326 #define CXM_REG_APU 0x200a064 327 #define CXM_REG_DEC_SDRAM_PRECHARGE 0x20008fc 328 #define CXM_REG_DEC_SDRAM_REFRESH 0x20008f8 329 #define CXM_REG_DMA_STATUS 0x2000004 330 #define CXM_REG_ENC_SDRAM_PRECHARGE 0x20007fc 331 #define CXM_REG_ENC_SDRAM_REFRESH 0x20007f8 332 #define CXM_REG_HW_BLOCKS 0x2009054 333 #define CXM_REG_I2C_GETSCL 0x2007008 334 #define CXM_REG_I2C_GETSDA 0x200700c 335 #define CXM_REG_I2C_SETSCL 0x2007000 336 #define CXM_REG_I2C_SETSDA 0x2007004 337 #define CXM_REG_IRQ_MASK 0x2000048 338 #define CXM_REG_IRQ_STATUS 0x2000040 339 #define CXM_REG_SPU 0x2009050 340 #define CXM_REG_VDM 0x2002800 341 #define CXM_REG_VPU 0x2009058 342 343 /* 344 * Register values 345 */ 346 #define CXM_CMD_AO_STOP 0x00000005 347 #define CXM_CMD_APU_PING 0x00000000 348 #define CXM_CMD_HW_BLOCKS_RST 0xffffffff 349 #define CXM_CMD_SDRAM_PRECHARGE_INIT 0x0000001a 350 #define CXM_CMD_SDRAM_REFRESH_INIT 0x80000640 351 #define CXM_CMD_SPU_STOP 0x00000001 352 #define CXM_CMD_VDM_STOP 0x00000000 353 #define CXM_CMD_VPU_STOP15 0xfffffffe 354 #define CXM_CMD_VPU_STOP16 0xffffffee 355 356 #define CXM_DMA_ERROR_LIST 0x00000008 357 #define CXM_DMA_ERROR_READ 0x00000002 358 #define CXM_DMA_ERROR_WRITE 0x00000004 359 #define CXM_DMA_SUCCESS 0x00000001 360 361 #define CXM_IRQ_DEC_DMA_DONE (1 << 20) 362 #define CXM_IRQ_DEC_DMA_REQUEST (1 << 22) 363 #define CXM_IRQ_DEC_VSYNC (1 << 10) 364 #define CXM_IRQ_ENC_DMA_DONE (1 << 27) 365 #define CXM_IRQ_ENC_DMA_REQUEST (1 << 31) 366 #define CXM_IRQ_ENC_EOS (1 << 30) 367 #define CXM_IRQ_ENC_EVENT (1 << 28) 368 369 #define CXM_IRQ_ENC (CXM_IRQ_ENC_DMA_REQUEST | CXM_IRQ_ENC_DMA_DONE \ 370 | CXM_IRQ_ENC_EOS | CXM_IRQ_ENC_EVENT) 371 372 /* 373 * Register masks 374 */ 375 #define CXM_MASK_SPU_ENABLE 0xfffffffe 376 #define CXM_MASK_VPU_ENABLE15 0xfffffff6 377 #define CXM_MASK_VPU_ENABLE16 0xfffffffb 378 379 /* 380 * Firmware commands 381 */ 382 #define CXM_FW_CMD_ASSIGN_3_2_PULLDOWN 0x000000b1 383 #define CXM_FW_CMD_ASSIGN_ASPECT_RATIO 0x00000099 384 #define CXM_FW_CMD_ASSIGN_AUDIO_PROPERTIES 0x000000bd 385 #define CXM_FW_CMD_ASSIGN_BITRATES 0x00000095 386 #define CXM_FW_CMD_ASSIGN_CORING_LEVELS 0x0000009f 387 #define CXM_FW_CMD_ASSIGN_DMA_BLOCKLEN 0x000000c9 388 #define CXM_FW_CMD_ASSIGN_DNR_FILTER_MODE 0x0000009b 389 #define CXM_FW_CMD_ASSIGN_DNR_FILTER_PROPERTIES 0x0000009d 390 #define CXM_FW_CMD_ASSIGN_FRAME_DROP_RATE 0x000000d0 391 #define CXM_FW_CMD_ASSIGN_FRAME_RATE 0x0000008f 392 #define CXM_FW_CMD_ASSIGN_FRAME_SIZE 0x00000091 393 #define CXM_FW_CMD_ASSIGN_GOP_CLOSURE 0x000000c5 394 #define CXM_FW_CMD_ASSIGN_GOP_PROPERTIES 0x00000097 395 #define CXM_FW_CMD_ASSIGN_NUM_VSYNC_LINES 0x000000d6 396 #define CXM_FW_CMD_ASSIGN_OUTPUT_PORT 0x000000bb 397 #define CXM_FW_CMD_ASSIGN_PGM_INDEX_INFO 0x000000c7 398 #define CXM_FW_CMD_ASSIGN_PLACEHOLDER 0x000000d8 399 #define CXM_FW_CMD_ASSIGN_SPATIAL_FILTER_TYPE 0x000000a1 400 #define CXM_FW_CMD_ASSIGN_STREAM_TYPE 0x000000b9 401 #define CXM_FW_CMD_ASSIGN_VBI_LINE 0x000000b7 402 #define CXM_FW_CMD_ASSIGN_VBI_PROPERTIES 0x000000c8 403 #define CXM_FW_CMD_BEGIN_CAPTURE 0x00000081 404 #define CXM_FW_CMD_DEC_EVENT_NOTIFICATION 0x00000017 405 #define CXM_FW_CMD_DEC_GET_FW_VER 0x00000011 406 #define CXM_FW_CMD_DEC_HALT_FW 0x0000000e 407 #define CXM_FW_CMD_ENC_EVENT_NOTIFICATION 0x000000d5 408 #define CXM_FW_CMD_ENC_GET_FW_VER 0x000000c4 409 #define CXM_FW_CMD_ENC_HALT_FW 0x000000c3 410 #define CXM_FW_CMD_END_CAPTURE 0x00000082 411 #define CXM_FW_CMD_INITIALIZE_VIDEO_INPUT 0x000000cd 412 #define CXM_FW_CMD_MUTE_VIDEO_INPUT 0x000000d9 413 #define CXM_FW_CMD_PAUSE_ENCODER 0x000000d2 414 #define CXM_FW_CMD_SCHED_DMA_TO_HOST 0x000000cc 415 416 #define CXM_FW_STD_TIMEOUT 0x00010000 417 418 #define CXM_FW_CAPTURE_STREAM_TYPE_MPEG 0x00000000 419 #define CXM_FW_CAPTURE_STREAM_TYPE_RAW 0x00000001 420 #define CXM_FW_CAPTURE_STREAM_TYPE_RAW_PASSTHROUGH 0x00000002 421 #define CXM_FW_CAPTURE_STREAM_TYPE_VBI 0x00000003 422 423 #define CXM_FW_CAPTURE_STREAM_YUV 0x00000001 424 #define CXM_FW_CAPTURE_STREAM_PCM_AUDIO 0x00000002 425 #define CXM_FW_CAPTURE_STREAM_VBI 0x00000004 426 427 #define CXM_FW_STREAM_TYPE_DVD 0x0000000a 428 #define CXM_FW_STREAM_TYPE_MPEG1 0x00000002 429 #define CXM_FW_STREAM_TYPE_MPEG2_PROGRAM 0x00000000 430 #define CXM_FW_STREAM_TYPE_SVCD 0x0000000c 431 #define CXM_FW_STREAM_TYPE_VCD 0x0000000b 432 433 #define CXM_MACROBLOCK_HEIGHT 16 434 #define CXM_MACROBLOCK_WIDTH 16 435 #define CXM_MACROBLOCK_SIZE (CXM_MACROBLOCK_HEIGHT * CXM_MACROBLOCK_WIDTH) 436 437 /* 438 * I2C addresses 439 */ 440 #define CXM_I2C_CX2584x 0x88 441 #define CXM_I2C_EEPROM 0xa0 442 #define CXM_I2C_IR 0x30 443 #define CXM_I2C_MSP3400 0x80 444 #define CXM_I2C_SAA7115 0x42 445 #define CXM_I2C_TDA988x_W (0x43 << 1) /* Write address */ 446 #define CXM_I2C_TDA988x_R ((0x43 << 1) | 0x01) /* Read address */ 447 #define CXM_I2C_TUNER 0xc2 448 #define CXM_I2C_TUNER_IF 0x86 449 #define CXM_I2C_WM8775 0x36 450 451 #define CXM_I2C_TIMEOUT 1000 452 453 /* 454 * EEPROM 455 */ 456 int cxm_eeprom_init(struct cxm_softc *sc); 457 int cxm_eeprom_tuner_type(struct cxm_softc *sc); 458 459 /* 460 * Infrared remote 461 */ 462 int cxm_ir_init(struct cxm_softc *sc); 463 int cxm_ir_key(struct cxm_softc *sc, char *buf, int len); 464 465 /* 466 * msp34xxx Audio decoder 467 */ 468 #define CXM_MSP3400C_DEM 0x10 469 #define CXM_MSP3400C_DFP 0x12 470 471 struct cxm_msp_setting { 472 unsigned char dev; 473 unsigned int addr; 474 char value[2]; 475 }; 476 477 struct cxm_msp_command { 478 unsigned int nsettings; 479 struct cxm_msp_setting settings[5]; 480 }; 481 482 int cxm_msp_init(struct cxm_softc *sc); 483 int cxm_msp_mute(struct cxm_softc *sc); 484 int cxm_msp_unmute(struct cxm_softc *sc); 485 int cxm_msp_is_muted(struct cxm_softc *sc); 486 int cxm_msp_select_source(struct cxm_softc *sc, enum cxm_source source); 487 enum cxm_source cxm_msp_selected_source(struct cxm_softc *sc); 488 int cxm_msp_autodetect_standard(struct cxm_softc *sc); 489 int cxm_msp_is_locked(struct cxm_softc *sc); 490 int cxm_msp_wait_for_lock(struct cxm_softc *sc); 491 492 /* 493 * wm8775 Audio ADC 494 */ 495 struct cxm_wm8775_setting { 496 unsigned char addr; 497 uint16_t value; 498 }; 499 500 struct cxm_wm8775_command { 501 unsigned int nsettings; 502 struct cxm_wm8775_setting settings[13]; 503 }; 504 505 int cxm_wm8775_init(struct cxm_softc *sc); 506 507 /* 508 * tda988x Demodulator 509 */ 510 int cxm_tda988x_init(struct cxm_softc *sc); 511 int cxm_tda988x_diag(struct cxm_softc *sc); 512 513 /* 514 * cx2584x Decoder 515 */ 516 struct cxm_cx2584x_setting { 517 uint16_t addr; 518 unsigned char value; 519 }; 520 521 struct cxm_cx2584x_command { 522 unsigned int nsettings; 523 struct cxm_cx2584x_setting settings[21]; 524 }; 525 526 int cxm_cx2584x_init(struct cxm_softc *sc); 527 int cxm_cx2584x_mute(struct cxm_softc *sc); 528 int cxm_cx2584x_unmute(struct cxm_softc *sc); 529 int cxm_cx2584x_select_source(struct cxm_softc *sc, enum cxm_source source); 530 int cxm_cx2584x_set_std(struct cxm_softc *sc); 531 532 /* 533 * Tuner 534 */ 535 #define CXM_TUNER_PHILIPS_FI1216_MK2 0 536 #define CXM_TUNER_PHILIPS_FM1216 1 537 #define CXM_TUNER_PHILIPS_FQ1216ME 2 538 #define CXM_TUNER_PHILIPS_FQ1216ME_MK3 3 539 #define CXM_TUNER_PHILIPS_FM1216ME_MK3 4 540 #define CXM_TUNER_PHILIPS_FI1236_MK2 5 541 #define CXM_TUNER_PHILIPS_FM1236 6 542 #define CXM_TUNER_PHILIPS_FI1246_MK2 7 543 #define CXM_TUNER_PHILIPS_FM1246 8 544 #define CXM_TUNER_TEMIC_4006_FH5 9 545 #define CXM_TUNER_TEMIC_4009_FR5 10 546 #define CXM_TUNER_TEMIC_4036_FY5 11 547 #define CXM_TUNER_TEMIC_4039_FR5 12 548 #define CXM_TUNER_TEMIC_4066_FY5 13 549 #define CXM_TUNER_LG_TPI8PSB11D 14 550 #define CXM_TUNER_LG_TPI8PSB01N 15 551 #define CXM_TUNER_LG_TAPC_H701F 16 552 #define CXM_TUNER_LG_TAPC_H001F 17 553 #define CXM_TUNER_LG_TAPE_H001F 18 554 #define CXM_TUNER_MICROTUNE_4049_FM5 19 555 #define CXM_TUNER_TCL_2002N_6A 20 556 #define CXM_TUNER_TYPES 21 557 558 #define CXM_TUNER_AFC_MASK 0x07 559 560 #define CXM_TUNER_AFC_FREQ_MINUS_125 0x00 561 #define CXM_TUNER_AFC_FREQ_MINUS_62 0x01 562 #define CXM_TUNER_AFC_FREQ_CENTERED 0x02 563 #define CXM_TUNER_AFC_FREQ_PLUS_62 0x03 564 #define CXM_TUNER_AFC_FREQ_PLUS_125 0x04 565 566 #define CXM_TUNER_PHASE_LOCKED 0x40 567 568 #define CXM_TUNER_FM_SYSTEM 0x01 569 #define CXM_TUNER_TV_SYSTEM_BG 0x02 570 #define CXM_TUNER_TV_SYSTEM_DK 0x04 571 #define CXM_TUNER_TV_SYSTEM_I 0x08 572 #define CXM_TUNER_TV_SYSTEM_MN 0x10 573 #define CXM_TUNER_TV_SYSTEM_L 0x20 574 #define CXM_TUNER_TV_SYSTEM_L_PRIME 0x40 575 576 struct cxm_tuner_band_code { 577 unsigned long freq; 578 unsigned char codes[2]; 579 }; 580 581 struct cxm_tuner_channel_assignment { 582 unsigned int channel; 583 unsigned long freq; 584 unsigned long step; 585 }; 586 587 struct cxm_tuner_channels { 588 const char *name; 589 unsigned int chnlset; 590 unsigned int system; 591 unsigned int min_channel; 592 unsigned int max_channel; 593 unsigned long if_freq; 594 struct cxm_tuner_channel_assignment assignments[17]; 595 }; 596 597 struct cxm_tuner_system_code { 598 unsigned int system; 599 unsigned char codes[4]; 600 }; 601 602 enum cxm_tuner_system_code_style { cxm_unknown_system_code_style, 603 cxm_none_system_code_style, 604 cxm_port_system_code_style, 605 cxm_if_system_code_style, 606 cxm_if_system_with_aux_code_style }; 607 608 struct cxm_tuner_system { 609 unsigned int supported; 610 enum cxm_tuner_system_code_style code_style; 611 struct cxm_tuner_system_code codes[6]; 612 }; 613 614 struct cxm_tuner { 615 const char *name; 616 struct cxm_tuner_system systems; 617 unsigned long min_freq; 618 unsigned long max_freq; 619 struct cxm_tuner_band_code band_codes[3]; 620 unsigned long fm_min_freq; 621 unsigned long fm_max_freq; 622 struct cxm_tuner_band_code fm_band_code; 623 const struct cxm_tuner_channels *default_channels; 624 }; 625 626 enum cxm_tuner_freq_type { cxm_tuner_unknown_freq_type, cxm_tuner_fm_freq_type, 627 cxm_tuner_tv_freq_type }; 628 629 extern const struct cxm_tuner cxm_tuners[]; 630 631 int cxm_tuner_init(struct cxm_softc *sc); 632 int cxm_tuner_select_channel_set(struct cxm_softc *sc, 633 unsigned int channel_set); 634 unsigned int cxm_tuner_selected_channel_set(struct cxm_softc *sc); 635 int cxm_tuner_select_frequency(struct cxm_softc *sc, 636 enum cxm_tuner_freq_type type, 637 unsigned long freq); 638 int cxm_tuner_select_channel(struct cxm_softc *sc, unsigned int channel); 639 int cxm_tuner_apply_afc(struct cxm_softc *sc); 640 int cxm_tuner_is_locked(struct cxm_softc *sc); 641 int cxm_tuner_wait_for_lock(struct cxm_softc *sc); 642 int cxm_tuner_status(struct cxm_softc *sc); 643 644 /* 645 * Video decoder 646 */ 647 struct cxm_saa7115_setting { 648 unsigned char addr; 649 unsigned int nvalues; 650 char values[32]; 651 }; 652 653 struct cxm_saa7115_command { 654 unsigned int nsettings; 655 struct cxm_saa7115_setting settings[20]; 656 }; 657 658 struct cxm_saa7115_audio_clock { 659 unsigned int sample_rate; 660 unsigned int fps; 661 const struct cxm_saa7115_command *clock; 662 }; 663 664 struct cxm_saa7115_scaling { 665 unsigned int width; 666 unsigned int height; 667 unsigned int fps; 668 const struct cxm_saa7115_command *scaling; 669 }; 670 671 int cxm_saa7115_init(struct cxm_softc *sc); 672 int cxm_saa7115_mute(struct cxm_softc *sc); 673 int cxm_saa7115_unmute(struct cxm_softc *sc); 674 int cxm_saa7115_select_source(struct cxm_softc *sc, enum cxm_source source); 675 int cxm_saa7115_configure(struct cxm_softc *sc, 676 unsigned int width, unsigned int height, 677 unsigned int fps, unsigned int audio_sample_rate); 678 enum cxm_source_format cxm_saa7115_detected_format(struct cxm_softc *sc); 679 int cxm_saa7115_detected_fps(struct cxm_softc *sc); 680 int cxm_saa7115_get_brightness(struct cxm_softc *sc); 681 int cxm_saa7115_set_brightness(struct cxm_softc *sc, 682 unsigned char brightness); 683 int cxm_saa7115_get_chroma_saturation(struct cxm_softc *sc); 684 int cxm_saa7115_set_chroma_saturation(struct cxm_softc *sc, 685 unsigned char chroma_saturation); 686 int cxm_saa7115_get_contrast(struct cxm_softc *sc); 687 int cxm_saa7115_set_contrast(struct cxm_softc *sc, unsigned char contrast); 688 int cxm_saa7115_get_hue(struct cxm_softc *sc); 689 int cxm_saa7115_set_hue(struct cxm_softc *sc, unsigned char hue); 690 int cxm_saa7115_is_locked(struct cxm_softc *sc); 691 int cxm_saa7115_wait_for_lock(struct cxm_softc *sc); 692 693 #endif /* !_CXM_H */ 694