1*394324d3SSascha Wildner /*-
2*394324d3SSascha Wildner * BSD LICENSE
3*394324d3SSascha Wildner *
4*394324d3SSascha Wildner * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5*394324d3SSascha Wildner * All rights reserved.
6*394324d3SSascha Wildner *
7*394324d3SSascha Wildner * Redistribution and use in source and binary forms, with or without
8*394324d3SSascha Wildner * modification, are permitted provided that the following conditions
9*394324d3SSascha Wildner * are met:
10*394324d3SSascha Wildner *
11*394324d3SSascha Wildner * * Redistributions of source code must retain the above copyright
12*394324d3SSascha Wildner * notice, this list of conditions and the following disclaimer.
13*394324d3SSascha Wildner * * Redistributions in binary form must reproduce the above copyright
14*394324d3SSascha Wildner * notice, this list of conditions and the following disclaimer in
15*394324d3SSascha Wildner * the documentation and/or other materials provided with the
16*394324d3SSascha Wildner * distribution.
17*394324d3SSascha Wildner * * Neither the name of copyright holder nor the names of its
18*394324d3SSascha Wildner * contributors may be used to endorse or promote products derived
19*394324d3SSascha Wildner * from this software without specific prior written permission.
20*394324d3SSascha Wildner *
21*394324d3SSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22*394324d3SSascha Wildner * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23*394324d3SSascha Wildner * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24*394324d3SSascha Wildner * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25*394324d3SSascha Wildner * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26*394324d3SSascha Wildner * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27*394324d3SSascha Wildner * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28*394324d3SSascha Wildner * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29*394324d3SSascha Wildner * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30*394324d3SSascha Wildner * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31*394324d3SSascha Wildner * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*394324d3SSascha Wildner */
33*394324d3SSascha Wildner
34*394324d3SSascha Wildner #include "ena_com.h"
35*394324d3SSascha Wildner #ifdef ENA_INTERNAL
36*394324d3SSascha Wildner #include "ena_gen_info.h"
37*394324d3SSascha Wildner #endif
38*394324d3SSascha Wildner
39*394324d3SSascha Wildner /*****************************************************************************/
40*394324d3SSascha Wildner /*****************************************************************************/
41*394324d3SSascha Wildner
42*394324d3SSascha Wildner /* Timeout in micro-sec */
43*394324d3SSascha Wildner #define ADMIN_CMD_TIMEOUT_US (3000000)
44*394324d3SSascha Wildner
45*394324d3SSascha Wildner #define ENA_ASYNC_QUEUE_DEPTH 16
46*394324d3SSascha Wildner #define ENA_ADMIN_QUEUE_DEPTH 32
47*394324d3SSascha Wildner
48*394324d3SSascha Wildner #ifdef ENA_EXTENDED_STATS
49*394324d3SSascha Wildner
50*394324d3SSascha Wildner #define ENA_HISTOGRAM_ACTIVE_MASK_OFFSET 0xF08
51*394324d3SSascha Wildner #define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF)
52*394324d3SSascha Wildner #define ENA_EXTENDED_STAT_GET_QUEUE(_funct_queue) (_funct_queue >> 16)
53*394324d3SSascha Wildner
54*394324d3SSascha Wildner #endif /* ENA_EXTENDED_STATS */
55*394324d3SSascha Wildner #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
56*394324d3SSascha Wildner ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
57*394324d3SSascha Wildner | (ENA_COMMON_SPEC_VERSION_MINOR))
58*394324d3SSascha Wildner
59*394324d3SSascha Wildner #define ENA_CTRL_MAJOR 0
60*394324d3SSascha Wildner #define ENA_CTRL_MINOR 0
61*394324d3SSascha Wildner #define ENA_CTRL_SUB_MINOR 1
62*394324d3SSascha Wildner
63*394324d3SSascha Wildner #define MIN_ENA_CTRL_VER \
64*394324d3SSascha Wildner (((ENA_CTRL_MAJOR) << \
65*394324d3SSascha Wildner (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
66*394324d3SSascha Wildner ((ENA_CTRL_MINOR) << \
67*394324d3SSascha Wildner (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
68*394324d3SSascha Wildner (ENA_CTRL_SUB_MINOR))
69*394324d3SSascha Wildner
70*394324d3SSascha Wildner #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
71*394324d3SSascha Wildner #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
72*394324d3SSascha Wildner
73*394324d3SSascha Wildner #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
74*394324d3SSascha Wildner
75*394324d3SSascha Wildner #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
76*394324d3SSascha Wildner
77*394324d3SSascha Wildner #define ENA_REGS_ADMIN_INTR_MASK 1
78*394324d3SSascha Wildner
79*394324d3SSascha Wildner /*****************************************************************************/
80*394324d3SSascha Wildner /*****************************************************************************/
81*394324d3SSascha Wildner /*****************************************************************************/
82*394324d3SSascha Wildner
83*394324d3SSascha Wildner enum ena_cmd_status {
84*394324d3SSascha Wildner ENA_CMD_SUBMITTED,
85*394324d3SSascha Wildner ENA_CMD_COMPLETED,
86*394324d3SSascha Wildner /* Abort - canceled by the driver */
87*394324d3SSascha Wildner ENA_CMD_ABORTED,
88*394324d3SSascha Wildner };
89*394324d3SSascha Wildner
90*394324d3SSascha Wildner struct ena_comp_ctx {
91*394324d3SSascha Wildner ena_wait_event_t wait_event;
92*394324d3SSascha Wildner struct ena_admin_acq_entry *user_cqe;
93*394324d3SSascha Wildner u32 comp_size;
94*394324d3SSascha Wildner enum ena_cmd_status status;
95*394324d3SSascha Wildner /* status from the device */
96*394324d3SSascha Wildner u8 comp_status;
97*394324d3SSascha Wildner u8 cmd_opcode;
98*394324d3SSascha Wildner bool occupied;
99*394324d3SSascha Wildner };
100*394324d3SSascha Wildner
101*394324d3SSascha Wildner struct ena_com_stats_ctx {
102*394324d3SSascha Wildner struct ena_admin_aq_get_stats_cmd get_cmd;
103*394324d3SSascha Wildner struct ena_admin_acq_get_stats_resp get_resp;
104*394324d3SSascha Wildner };
105*394324d3SSascha Wildner
ena_com_mem_addr_set(struct ena_com_dev * ena_dev,struct ena_common_mem_addr * ena_addr,dma_addr_t addr)106*394324d3SSascha Wildner static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
107*394324d3SSascha Wildner struct ena_common_mem_addr *ena_addr,
108*394324d3SSascha Wildner dma_addr_t addr)
109*394324d3SSascha Wildner {
110*394324d3SSascha Wildner if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
111*394324d3SSascha Wildner ena_trc_err("dma address has more bits that the device supports\n");
112*394324d3SSascha Wildner return ENA_COM_INVAL;
113*394324d3SSascha Wildner }
114*394324d3SSascha Wildner
115*394324d3SSascha Wildner ena_addr->mem_addr_low = (u32)addr;
116*394324d3SSascha Wildner ena_addr->mem_addr_high = (u16)((u64)addr >> 32);
117*394324d3SSascha Wildner
118*394324d3SSascha Wildner return 0;
119*394324d3SSascha Wildner }
120*394324d3SSascha Wildner
ena_com_admin_init_sq(struct ena_com_admin_queue * queue)121*394324d3SSascha Wildner static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
122*394324d3SSascha Wildner {
123*394324d3SSascha Wildner struct ena_com_admin_sq *sq = &queue->sq;
124*394324d3SSascha Wildner u16 size = ADMIN_SQ_SIZE(queue->q_depth);
125*394324d3SSascha Wildner
126*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
127*394324d3SSascha Wildner sq->mem_handle);
128*394324d3SSascha Wildner
129*394324d3SSascha Wildner if (!sq->entries) {
130*394324d3SSascha Wildner ena_trc_err("memory allocation failed");
131*394324d3SSascha Wildner return ENA_COM_NO_MEM;
132*394324d3SSascha Wildner }
133*394324d3SSascha Wildner
134*394324d3SSascha Wildner sq->head = 0;
135*394324d3SSascha Wildner sq->tail = 0;
136*394324d3SSascha Wildner sq->phase = 1;
137*394324d3SSascha Wildner
138*394324d3SSascha Wildner sq->db_addr = NULL;
139*394324d3SSascha Wildner
140*394324d3SSascha Wildner return 0;
141*394324d3SSascha Wildner }
142*394324d3SSascha Wildner
ena_com_admin_init_cq(struct ena_com_admin_queue * queue)143*394324d3SSascha Wildner static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
144*394324d3SSascha Wildner {
145*394324d3SSascha Wildner struct ena_com_admin_cq *cq = &queue->cq;
146*394324d3SSascha Wildner u16 size = ADMIN_CQ_SIZE(queue->q_depth);
147*394324d3SSascha Wildner
148*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
149*394324d3SSascha Wildner cq->mem_handle);
150*394324d3SSascha Wildner
151*394324d3SSascha Wildner if (!cq->entries) {
152*394324d3SSascha Wildner ena_trc_err("memory allocation failed");
153*394324d3SSascha Wildner return ENA_COM_NO_MEM;
154*394324d3SSascha Wildner }
155*394324d3SSascha Wildner
156*394324d3SSascha Wildner cq->head = 0;
157*394324d3SSascha Wildner cq->phase = 1;
158*394324d3SSascha Wildner
159*394324d3SSascha Wildner return 0;
160*394324d3SSascha Wildner }
161*394324d3SSascha Wildner
ena_com_admin_init_aenq(struct ena_com_dev * dev,struct ena_aenq_handlers * aenq_handlers)162*394324d3SSascha Wildner static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
163*394324d3SSascha Wildner struct ena_aenq_handlers *aenq_handlers)
164*394324d3SSascha Wildner {
165*394324d3SSascha Wildner struct ena_com_aenq *aenq = &dev->aenq;
166*394324d3SSascha Wildner u32 addr_low, addr_high, aenq_caps;
167*394324d3SSascha Wildner u16 size;
168*394324d3SSascha Wildner
169*394324d3SSascha Wildner dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
170*394324d3SSascha Wildner size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
171*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
172*394324d3SSascha Wildner aenq->entries,
173*394324d3SSascha Wildner aenq->dma_addr,
174*394324d3SSascha Wildner aenq->mem_handle);
175*394324d3SSascha Wildner
176*394324d3SSascha Wildner if (!aenq->entries) {
177*394324d3SSascha Wildner ena_trc_err("memory allocation failed");
178*394324d3SSascha Wildner return ENA_COM_NO_MEM;
179*394324d3SSascha Wildner }
180*394324d3SSascha Wildner
181*394324d3SSascha Wildner aenq->head = aenq->q_depth;
182*394324d3SSascha Wildner aenq->phase = 1;
183*394324d3SSascha Wildner
184*394324d3SSascha Wildner addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
185*394324d3SSascha Wildner addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
186*394324d3SSascha Wildner
187*394324d3SSascha Wildner ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
188*394324d3SSascha Wildner ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
189*394324d3SSascha Wildner
190*394324d3SSascha Wildner aenq_caps = 0;
191*394324d3SSascha Wildner aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
192*394324d3SSascha Wildner aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
193*394324d3SSascha Wildner ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
194*394324d3SSascha Wildner ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
195*394324d3SSascha Wildner ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
196*394324d3SSascha Wildner
197*394324d3SSascha Wildner if (unlikely(!aenq_handlers)) {
198*394324d3SSascha Wildner ena_trc_err("aenq handlers pointer is NULL\n");
199*394324d3SSascha Wildner return ENA_COM_INVAL;
200*394324d3SSascha Wildner }
201*394324d3SSascha Wildner
202*394324d3SSascha Wildner aenq->aenq_handlers = aenq_handlers;
203*394324d3SSascha Wildner
204*394324d3SSascha Wildner return 0;
205*394324d3SSascha Wildner }
206*394324d3SSascha Wildner
comp_ctxt_release(struct ena_com_admin_queue * queue,struct ena_comp_ctx * comp_ctx)207*394324d3SSascha Wildner static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
208*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx)
209*394324d3SSascha Wildner {
210*394324d3SSascha Wildner comp_ctx->occupied = false;
211*394324d3SSascha Wildner ATOMIC32_DEC(&queue->outstanding_cmds);
212*394324d3SSascha Wildner }
213*394324d3SSascha Wildner
get_comp_ctxt(struct ena_com_admin_queue * queue,u16 command_id,bool capture)214*394324d3SSascha Wildner static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
215*394324d3SSascha Wildner u16 command_id, bool capture)
216*394324d3SSascha Wildner {
217*394324d3SSascha Wildner if (unlikely(command_id >= queue->q_depth)) {
218*394324d3SSascha Wildner ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
219*394324d3SSascha Wildner command_id, queue->q_depth);
220*394324d3SSascha Wildner return NULL;
221*394324d3SSascha Wildner }
222*394324d3SSascha Wildner
223*394324d3SSascha Wildner if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
224*394324d3SSascha Wildner ena_trc_err("Completion context is occupied\n");
225*394324d3SSascha Wildner return NULL;
226*394324d3SSascha Wildner }
227*394324d3SSascha Wildner
228*394324d3SSascha Wildner if (capture) {
229*394324d3SSascha Wildner ATOMIC32_INC(&queue->outstanding_cmds);
230*394324d3SSascha Wildner queue->comp_ctx[command_id].occupied = true;
231*394324d3SSascha Wildner }
232*394324d3SSascha Wildner
233*394324d3SSascha Wildner return &queue->comp_ctx[command_id];
234*394324d3SSascha Wildner }
235*394324d3SSascha Wildner
__ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)236*394324d3SSascha Wildner static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
237*394324d3SSascha Wildner struct ena_admin_aq_entry *cmd,
238*394324d3SSascha Wildner size_t cmd_size_in_bytes,
239*394324d3SSascha Wildner struct ena_admin_acq_entry *comp,
240*394324d3SSascha Wildner size_t comp_size_in_bytes)
241*394324d3SSascha Wildner {
242*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx;
243*394324d3SSascha Wildner u16 tail_masked, cmd_id;
244*394324d3SSascha Wildner u16 queue_size_mask;
245*394324d3SSascha Wildner u16 cnt;
246*394324d3SSascha Wildner
247*394324d3SSascha Wildner queue_size_mask = admin_queue->q_depth - 1;
248*394324d3SSascha Wildner
249*394324d3SSascha Wildner tail_masked = admin_queue->sq.tail & queue_size_mask;
250*394324d3SSascha Wildner
251*394324d3SSascha Wildner /* In case of queue FULL */
252*394324d3SSascha Wildner cnt = ATOMIC32_READ(&admin_queue->outstanding_cmds);
253*394324d3SSascha Wildner if (cnt >= admin_queue->q_depth) {
254*394324d3SSascha Wildner ena_trc_dbg("admin queue is full.\n");
255*394324d3SSascha Wildner admin_queue->stats.out_of_space++;
256*394324d3SSascha Wildner return ERR_PTR(ENA_COM_NO_SPACE);
257*394324d3SSascha Wildner }
258*394324d3SSascha Wildner
259*394324d3SSascha Wildner cmd_id = admin_queue->curr_cmd_id;
260*394324d3SSascha Wildner
261*394324d3SSascha Wildner cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
262*394324d3SSascha Wildner ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
263*394324d3SSascha Wildner
264*394324d3SSascha Wildner cmd->aq_common_descriptor.command_id |= cmd_id &
265*394324d3SSascha Wildner ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
266*394324d3SSascha Wildner
267*394324d3SSascha Wildner comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
268*394324d3SSascha Wildner if (unlikely(!comp_ctx))
269*394324d3SSascha Wildner return ERR_PTR(ENA_COM_INVAL);
270*394324d3SSascha Wildner
271*394324d3SSascha Wildner comp_ctx->status = ENA_CMD_SUBMITTED;
272*394324d3SSascha Wildner comp_ctx->comp_size = (u32)comp_size_in_bytes;
273*394324d3SSascha Wildner comp_ctx->user_cqe = comp;
274*394324d3SSascha Wildner comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
275*394324d3SSascha Wildner
276*394324d3SSascha Wildner ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
277*394324d3SSascha Wildner
278*394324d3SSascha Wildner memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
279*394324d3SSascha Wildner
280*394324d3SSascha Wildner admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
281*394324d3SSascha Wildner queue_size_mask;
282*394324d3SSascha Wildner
283*394324d3SSascha Wildner admin_queue->sq.tail++;
284*394324d3SSascha Wildner admin_queue->stats.submitted_cmd++;
285*394324d3SSascha Wildner
286*394324d3SSascha Wildner if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
287*394324d3SSascha Wildner admin_queue->sq.phase = !admin_queue->sq.phase;
288*394324d3SSascha Wildner
289*394324d3SSascha Wildner ENA_DB_SYNC(&admin_queue->sq.mem_handle);
290*394324d3SSascha Wildner ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
291*394324d3SSascha Wildner admin_queue->sq.db_addr);
292*394324d3SSascha Wildner
293*394324d3SSascha Wildner return comp_ctx;
294*394324d3SSascha Wildner }
295*394324d3SSascha Wildner
ena_com_init_comp_ctxt(struct ena_com_admin_queue * queue)296*394324d3SSascha Wildner static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
297*394324d3SSascha Wildner {
298*394324d3SSascha Wildner size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
299*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx;
300*394324d3SSascha Wildner u16 i;
301*394324d3SSascha Wildner
302*394324d3SSascha Wildner queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
303*394324d3SSascha Wildner if (unlikely(!queue->comp_ctx)) {
304*394324d3SSascha Wildner ena_trc_err("memory allocation failed");
305*394324d3SSascha Wildner return ENA_COM_NO_MEM;
306*394324d3SSascha Wildner }
307*394324d3SSascha Wildner
308*394324d3SSascha Wildner for (i = 0; i < queue->q_depth; i++) {
309*394324d3SSascha Wildner comp_ctx = get_comp_ctxt(queue, i, false);
310*394324d3SSascha Wildner if (comp_ctx)
311*394324d3SSascha Wildner ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
312*394324d3SSascha Wildner }
313*394324d3SSascha Wildner
314*394324d3SSascha Wildner return 0;
315*394324d3SSascha Wildner }
316*394324d3SSascha Wildner
ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)317*394324d3SSascha Wildner static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
318*394324d3SSascha Wildner struct ena_admin_aq_entry *cmd,
319*394324d3SSascha Wildner size_t cmd_size_in_bytes,
320*394324d3SSascha Wildner struct ena_admin_acq_entry *comp,
321*394324d3SSascha Wildner size_t comp_size_in_bytes)
322*394324d3SSascha Wildner {
323*394324d3SSascha Wildner unsigned long flags;
324*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx;
325*394324d3SSascha Wildner
326*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
327*394324d3SSascha Wildner if (unlikely(!admin_queue->running_state)) {
328*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
329*394324d3SSascha Wildner return ERR_PTR(ENA_COM_NO_DEVICE);
330*394324d3SSascha Wildner }
331*394324d3SSascha Wildner comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
332*394324d3SSascha Wildner cmd_size_in_bytes,
333*394324d3SSascha Wildner comp,
334*394324d3SSascha Wildner comp_size_in_bytes);
335*394324d3SSascha Wildner if (unlikely(IS_ERR(comp_ctx)))
336*394324d3SSascha Wildner admin_queue->running_state = false;
337*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
338*394324d3SSascha Wildner
339*394324d3SSascha Wildner return comp_ctx;
340*394324d3SSascha Wildner }
341*394324d3SSascha Wildner
ena_com_init_io_sq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_sq * io_sq)342*394324d3SSascha Wildner static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
343*394324d3SSascha Wildner struct ena_com_create_io_ctx *ctx,
344*394324d3SSascha Wildner struct ena_com_io_sq *io_sq)
345*394324d3SSascha Wildner {
346*394324d3SSascha Wildner size_t size;
347*394324d3SSascha Wildner int dev_node = 0;
348*394324d3SSascha Wildner
349*394324d3SSascha Wildner memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
350*394324d3SSascha Wildner
351*394324d3SSascha Wildner io_sq->desc_entry_size =
352*394324d3SSascha Wildner (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
353*394324d3SSascha Wildner sizeof(struct ena_eth_io_tx_desc) :
354*394324d3SSascha Wildner sizeof(struct ena_eth_io_rx_desc);
355*394324d3SSascha Wildner
356*394324d3SSascha Wildner size = io_sq->desc_entry_size * io_sq->q_depth;
357*394324d3SSascha Wildner io_sq->bus = ena_dev->bus;
358*394324d3SSascha Wildner
359*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
360*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
361*394324d3SSascha Wildner size,
362*394324d3SSascha Wildner io_sq->desc_addr.virt_addr,
363*394324d3SSascha Wildner io_sq->desc_addr.phys_addr,
364*394324d3SSascha Wildner io_sq->desc_addr.mem_handle,
365*394324d3SSascha Wildner ctx->numa_node,
366*394324d3SSascha Wildner dev_node);
367*394324d3SSascha Wildner if (!io_sq->desc_addr.virt_addr) {
368*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
369*394324d3SSascha Wildner size,
370*394324d3SSascha Wildner io_sq->desc_addr.virt_addr,
371*394324d3SSascha Wildner io_sq->desc_addr.phys_addr,
372*394324d3SSascha Wildner io_sq->desc_addr.mem_handle);
373*394324d3SSascha Wildner }
374*394324d3SSascha Wildner
375*394324d3SSascha Wildner if (!io_sq->desc_addr.virt_addr) {
376*394324d3SSascha Wildner ena_trc_err("memory allocation failed");
377*394324d3SSascha Wildner return ENA_COM_NO_MEM;
378*394324d3SSascha Wildner }
379*394324d3SSascha Wildner }
380*394324d3SSascha Wildner
381*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
382*394324d3SSascha Wildner /* Allocate bounce buffers */
383*394324d3SSascha Wildner io_sq->bounce_buf_ctrl.buffer_size = ena_dev->llq_info.desc_list_entry_size;
384*394324d3SSascha Wildner io_sq->bounce_buf_ctrl.buffers_num = ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
385*394324d3SSascha Wildner io_sq->bounce_buf_ctrl.next_to_use = 0;
386*394324d3SSascha Wildner
387*394324d3SSascha Wildner size = io_sq->bounce_buf_ctrl.buffer_size * io_sq->bounce_buf_ctrl.buffers_num;
388*394324d3SSascha Wildner
389*394324d3SSascha Wildner ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
390*394324d3SSascha Wildner size,
391*394324d3SSascha Wildner io_sq->bounce_buf_ctrl.base_buffer,
392*394324d3SSascha Wildner ctx->numa_node,
393*394324d3SSascha Wildner dev_node);
394*394324d3SSascha Wildner if (!io_sq->bounce_buf_ctrl.base_buffer)
395*394324d3SSascha Wildner io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
396*394324d3SSascha Wildner
397*394324d3SSascha Wildner if (!io_sq->bounce_buf_ctrl.base_buffer) {
398*394324d3SSascha Wildner ena_trc_err("bounce buffer memory allocation failed");
399*394324d3SSascha Wildner return ENA_COM_NO_MEM;
400*394324d3SSascha Wildner }
401*394324d3SSascha Wildner
402*394324d3SSascha Wildner memcpy(&io_sq->llq_info, &ena_dev->llq_info, sizeof(io_sq->llq_info));
403*394324d3SSascha Wildner
404*394324d3SSascha Wildner /* Initiate the first bounce buffer */
405*394324d3SSascha Wildner io_sq->llq_buf_ctrl.curr_bounce_buf =
406*394324d3SSascha Wildner ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
407*394324d3SSascha Wildner memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
408*394324d3SSascha Wildner 0x0, io_sq->llq_info.desc_list_entry_size);
409*394324d3SSascha Wildner io_sq->llq_buf_ctrl.descs_left_in_line =
410*394324d3SSascha Wildner io_sq->llq_info.descs_num_before_header;
411*394324d3SSascha Wildner }
412*394324d3SSascha Wildner
413*394324d3SSascha Wildner io_sq->tail = 0;
414*394324d3SSascha Wildner io_sq->next_to_comp = 0;
415*394324d3SSascha Wildner io_sq->phase = 1;
416*394324d3SSascha Wildner
417*394324d3SSascha Wildner return 0;
418*394324d3SSascha Wildner }
419*394324d3SSascha Wildner
ena_com_init_io_cq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_cq * io_cq)420*394324d3SSascha Wildner static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
421*394324d3SSascha Wildner struct ena_com_create_io_ctx *ctx,
422*394324d3SSascha Wildner struct ena_com_io_cq *io_cq)
423*394324d3SSascha Wildner {
424*394324d3SSascha Wildner size_t size;
425*394324d3SSascha Wildner int prev_node = 0;
426*394324d3SSascha Wildner
427*394324d3SSascha Wildner memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
428*394324d3SSascha Wildner
429*394324d3SSascha Wildner /* Use the basic completion descriptor for Rx */
430*394324d3SSascha Wildner io_cq->cdesc_entry_size_in_bytes =
431*394324d3SSascha Wildner (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
432*394324d3SSascha Wildner sizeof(struct ena_eth_io_tx_cdesc) :
433*394324d3SSascha Wildner sizeof(struct ena_eth_io_rx_cdesc_base);
434*394324d3SSascha Wildner
435*394324d3SSascha Wildner size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
436*394324d3SSascha Wildner io_cq->bus = ena_dev->bus;
437*394324d3SSascha Wildner
438*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
439*394324d3SSascha Wildner size,
440*394324d3SSascha Wildner io_cq->cdesc_addr.virt_addr,
441*394324d3SSascha Wildner io_cq->cdesc_addr.phys_addr,
442*394324d3SSascha Wildner io_cq->cdesc_addr.mem_handle,
443*394324d3SSascha Wildner ctx->numa_node,
444*394324d3SSascha Wildner prev_node);
445*394324d3SSascha Wildner if (!io_cq->cdesc_addr.virt_addr) {
446*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
447*394324d3SSascha Wildner size,
448*394324d3SSascha Wildner io_cq->cdesc_addr.virt_addr,
449*394324d3SSascha Wildner io_cq->cdesc_addr.phys_addr,
450*394324d3SSascha Wildner io_cq->cdesc_addr.mem_handle);
451*394324d3SSascha Wildner }
452*394324d3SSascha Wildner
453*394324d3SSascha Wildner if (!io_cq->cdesc_addr.virt_addr) {
454*394324d3SSascha Wildner ena_trc_err("memory allocation failed");
455*394324d3SSascha Wildner return ENA_COM_NO_MEM;
456*394324d3SSascha Wildner }
457*394324d3SSascha Wildner
458*394324d3SSascha Wildner io_cq->phase = 1;
459*394324d3SSascha Wildner io_cq->head = 0;
460*394324d3SSascha Wildner
461*394324d3SSascha Wildner return 0;
462*394324d3SSascha Wildner }
463*394324d3SSascha Wildner
ena_com_handle_single_admin_completion(struct ena_com_admin_queue * admin_queue,struct ena_admin_acq_entry * cqe)464*394324d3SSascha Wildner static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
465*394324d3SSascha Wildner struct ena_admin_acq_entry *cqe)
466*394324d3SSascha Wildner {
467*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx;
468*394324d3SSascha Wildner u16 cmd_id;
469*394324d3SSascha Wildner
470*394324d3SSascha Wildner cmd_id = cqe->acq_common_descriptor.command &
471*394324d3SSascha Wildner ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
472*394324d3SSascha Wildner
473*394324d3SSascha Wildner comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
474*394324d3SSascha Wildner if (unlikely(!comp_ctx)) {
475*394324d3SSascha Wildner ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
476*394324d3SSascha Wildner admin_queue->running_state = false;
477*394324d3SSascha Wildner return;
478*394324d3SSascha Wildner }
479*394324d3SSascha Wildner
480*394324d3SSascha Wildner comp_ctx->status = ENA_CMD_COMPLETED;
481*394324d3SSascha Wildner comp_ctx->comp_status = cqe->acq_common_descriptor.status;
482*394324d3SSascha Wildner
483*394324d3SSascha Wildner if (comp_ctx->user_cqe)
484*394324d3SSascha Wildner memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
485*394324d3SSascha Wildner
486*394324d3SSascha Wildner if (!admin_queue->polling)
487*394324d3SSascha Wildner ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
488*394324d3SSascha Wildner }
489*394324d3SSascha Wildner
ena_com_handle_admin_completion(struct ena_com_admin_queue * admin_queue)490*394324d3SSascha Wildner static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
491*394324d3SSascha Wildner {
492*394324d3SSascha Wildner struct ena_admin_acq_entry *cqe = NULL;
493*394324d3SSascha Wildner u16 comp_num = 0;
494*394324d3SSascha Wildner u16 head_masked;
495*394324d3SSascha Wildner u8 phase;
496*394324d3SSascha Wildner
497*394324d3SSascha Wildner head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
498*394324d3SSascha Wildner phase = admin_queue->cq.phase;
499*394324d3SSascha Wildner
500*394324d3SSascha Wildner cqe = &admin_queue->cq.entries[head_masked];
501*394324d3SSascha Wildner
502*394324d3SSascha Wildner /* Go over all the completions */
503*394324d3SSascha Wildner while ((cqe->acq_common_descriptor.flags &
504*394324d3SSascha Wildner ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
505*394324d3SSascha Wildner /* Do not read the rest of the completion entry before the
506*394324d3SSascha Wildner * phase bit was validated
507*394324d3SSascha Wildner */
508*394324d3SSascha Wildner rmb();
509*394324d3SSascha Wildner ena_com_handle_single_admin_completion(admin_queue, cqe);
510*394324d3SSascha Wildner
511*394324d3SSascha Wildner head_masked++;
512*394324d3SSascha Wildner comp_num++;
513*394324d3SSascha Wildner if (unlikely(head_masked == admin_queue->q_depth)) {
514*394324d3SSascha Wildner head_masked = 0;
515*394324d3SSascha Wildner phase = !phase;
516*394324d3SSascha Wildner }
517*394324d3SSascha Wildner
518*394324d3SSascha Wildner cqe = &admin_queue->cq.entries[head_masked];
519*394324d3SSascha Wildner }
520*394324d3SSascha Wildner
521*394324d3SSascha Wildner admin_queue->cq.head += comp_num;
522*394324d3SSascha Wildner admin_queue->cq.phase = phase;
523*394324d3SSascha Wildner admin_queue->sq.head += comp_num;
524*394324d3SSascha Wildner admin_queue->stats.completed_cmd += comp_num;
525*394324d3SSascha Wildner }
526*394324d3SSascha Wildner
ena_com_comp_status_to_errno(u8 comp_status)527*394324d3SSascha Wildner static int ena_com_comp_status_to_errno(u8 comp_status)
528*394324d3SSascha Wildner {
529*394324d3SSascha Wildner if (unlikely(comp_status != 0))
530*394324d3SSascha Wildner ena_trc_err("admin command failed[%u]\n", comp_status);
531*394324d3SSascha Wildner
532*394324d3SSascha Wildner if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
533*394324d3SSascha Wildner return ENA_COM_INVAL;
534*394324d3SSascha Wildner
535*394324d3SSascha Wildner switch (comp_status) {
536*394324d3SSascha Wildner case ENA_ADMIN_SUCCESS:
537*394324d3SSascha Wildner return 0;
538*394324d3SSascha Wildner case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
539*394324d3SSascha Wildner return ENA_COM_NO_MEM;
540*394324d3SSascha Wildner case ENA_ADMIN_UNSUPPORTED_OPCODE:
541*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
542*394324d3SSascha Wildner case ENA_ADMIN_BAD_OPCODE:
543*394324d3SSascha Wildner case ENA_ADMIN_MALFORMED_REQUEST:
544*394324d3SSascha Wildner case ENA_ADMIN_ILLEGAL_PARAMETER:
545*394324d3SSascha Wildner case ENA_ADMIN_UNKNOWN_ERROR:
546*394324d3SSascha Wildner return ENA_COM_INVAL;
547*394324d3SSascha Wildner }
548*394324d3SSascha Wildner
549*394324d3SSascha Wildner return 0;
550*394324d3SSascha Wildner }
551*394324d3SSascha Wildner
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)552*394324d3SSascha Wildner static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
553*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue)
554*394324d3SSascha Wildner {
555*394324d3SSascha Wildner unsigned long flags, timeout;
556*394324d3SSascha Wildner int ret;
557*394324d3SSascha Wildner
558*394324d3SSascha Wildner timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
559*394324d3SSascha Wildner
560*394324d3SSascha Wildner while (1) {
561*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
562*394324d3SSascha Wildner ena_com_handle_admin_completion(admin_queue);
563*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
564*394324d3SSascha Wildner
565*394324d3SSascha Wildner if (comp_ctx->status != ENA_CMD_SUBMITTED)
566*394324d3SSascha Wildner break;
567*394324d3SSascha Wildner
568*394324d3SSascha Wildner if (ENA_TIME_EXPIRE(timeout)) {
569*394324d3SSascha Wildner ena_trc_err("Wait for completion (polling) timeout\n");
570*394324d3SSascha Wildner /* ENA didn't have any completion */
571*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
572*394324d3SSascha Wildner admin_queue->stats.no_completion++;
573*394324d3SSascha Wildner admin_queue->running_state = false;
574*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
575*394324d3SSascha Wildner
576*394324d3SSascha Wildner ret = ENA_COM_TIMER_EXPIRED;
577*394324d3SSascha Wildner goto err;
578*394324d3SSascha Wildner }
579*394324d3SSascha Wildner
580*394324d3SSascha Wildner ENA_MSLEEP(100);
581*394324d3SSascha Wildner }
582*394324d3SSascha Wildner
583*394324d3SSascha Wildner if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
584*394324d3SSascha Wildner ena_trc_err("Command was aborted\n");
585*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
586*394324d3SSascha Wildner admin_queue->stats.aborted_cmd++;
587*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
588*394324d3SSascha Wildner ret = ENA_COM_NO_DEVICE;
589*394324d3SSascha Wildner goto err;
590*394324d3SSascha Wildner }
591*394324d3SSascha Wildner
592*394324d3SSascha Wildner ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
593*394324d3SSascha Wildner "Invalid comp status %d\n", comp_ctx->status);
594*394324d3SSascha Wildner
595*394324d3SSascha Wildner ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
596*394324d3SSascha Wildner err:
597*394324d3SSascha Wildner comp_ctxt_release(admin_queue, comp_ctx);
598*394324d3SSascha Wildner return ret;
599*394324d3SSascha Wildner }
600*394324d3SSascha Wildner
ena_com_config_llq_info(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_desc)601*394324d3SSascha Wildner static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
602*394324d3SSascha Wildner struct ena_admin_feature_llq_desc *llq_desc)
603*394324d3SSascha Wildner {
604*394324d3SSascha Wildner struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
605*394324d3SSascha Wildner
606*394324d3SSascha Wildner memset(llq_info, 0, sizeof(*llq_info));
607*394324d3SSascha Wildner
608*394324d3SSascha Wildner switch (llq_desc->header_location_ctrl) {
609*394324d3SSascha Wildner case ENA_ADMIN_INLINE_HEADER:
610*394324d3SSascha Wildner llq_info->inline_header = true;
611*394324d3SSascha Wildner break;
612*394324d3SSascha Wildner case ENA_ADMIN_HEADER_RING:
613*394324d3SSascha Wildner llq_info->inline_header = false;
614*394324d3SSascha Wildner break;
615*394324d3SSascha Wildner default:
616*394324d3SSascha Wildner ena_trc_err("Invalid header location control\n");
617*394324d3SSascha Wildner return -EINVAL;
618*394324d3SSascha Wildner }
619*394324d3SSascha Wildner
620*394324d3SSascha Wildner switch (llq_desc->entry_size_ctrl) {
621*394324d3SSascha Wildner case ENA_ADMIN_LIST_ENTRY_SIZE_128B:
622*394324d3SSascha Wildner llq_info->desc_list_entry_size = 128;
623*394324d3SSascha Wildner break;
624*394324d3SSascha Wildner case ENA_ADMIN_LIST_ENTRY_SIZE_192B:
625*394324d3SSascha Wildner llq_info->desc_list_entry_size = 192;
626*394324d3SSascha Wildner break;
627*394324d3SSascha Wildner case ENA_ADMIN_LIST_ENTRY_SIZE_256B:
628*394324d3SSascha Wildner llq_info->desc_list_entry_size = 256;
629*394324d3SSascha Wildner break;
630*394324d3SSascha Wildner default:
631*394324d3SSascha Wildner ena_trc_err("Invalid entry_size_ctrl %d\n",
632*394324d3SSascha Wildner llq_desc->entry_size_ctrl);
633*394324d3SSascha Wildner return -EINVAL;
634*394324d3SSascha Wildner }
635*394324d3SSascha Wildner
636*394324d3SSascha Wildner if ((llq_info->desc_list_entry_size & 0x7)) {
637*394324d3SSascha Wildner /* The desc list entry size should be whole multiply of 8
638*394324d3SSascha Wildner * This requirement comes from __iowrite64_copy()
639*394324d3SSascha Wildner */
640*394324d3SSascha Wildner ena_trc_err("illegal entry size %d\n",
641*394324d3SSascha Wildner llq_info->desc_list_entry_size);
642*394324d3SSascha Wildner return -EINVAL;
643*394324d3SSascha Wildner }
644*394324d3SSascha Wildner
645*394324d3SSascha Wildner if (llq_info->inline_header) {
646*394324d3SSascha Wildner llq_info->desc_stride_ctrl = llq_desc->descriptors_stride_ctrl;
647*394324d3SSascha Wildner if ((llq_info->desc_stride_ctrl != ENA_ADMIN_SINGLE_DESC_PER_ENTRY) &&
648*394324d3SSascha Wildner (llq_info->desc_stride_ctrl != ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)) {
649*394324d3SSascha Wildner ena_trc_err("Invalid desc_stride_ctrl %d\n",
650*394324d3SSascha Wildner llq_info->desc_stride_ctrl);
651*394324d3SSascha Wildner return -EINVAL;
652*394324d3SSascha Wildner }
653*394324d3SSascha Wildner } else {
654*394324d3SSascha Wildner llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
655*394324d3SSascha Wildner }
656*394324d3SSascha Wildner
657*394324d3SSascha Wildner if (llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY)
658*394324d3SSascha Wildner llq_info->descs_per_entry = llq_info->desc_list_entry_size /
659*394324d3SSascha Wildner sizeof(struct ena_eth_io_tx_desc);
660*394324d3SSascha Wildner else
661*394324d3SSascha Wildner llq_info->descs_per_entry = 1;
662*394324d3SSascha Wildner
663*394324d3SSascha Wildner llq_info->descs_num_before_header = llq_desc->desc_num_before_header_ctrl;
664*394324d3SSascha Wildner
665*394324d3SSascha Wildner return 0;
666*394324d3SSascha Wildner }
667*394324d3SSascha Wildner
668*394324d3SSascha Wildner
669*394324d3SSascha Wildner
ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)670*394324d3SSascha Wildner static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
671*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue)
672*394324d3SSascha Wildner {
673*394324d3SSascha Wildner unsigned long flags;
674*394324d3SSascha Wildner int ret;
675*394324d3SSascha Wildner
676*394324d3SSascha Wildner ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
677*394324d3SSascha Wildner admin_queue->completion_timeout);
678*394324d3SSascha Wildner
679*394324d3SSascha Wildner /* In case the command wasn't completed find out the root cause.
680*394324d3SSascha Wildner * There might be 2 kinds of errors
681*394324d3SSascha Wildner * 1) No completion (timeout reached)
682*394324d3SSascha Wildner * 2) There is completion but the device didn't get any msi-x interrupt.
683*394324d3SSascha Wildner */
684*394324d3SSascha Wildner if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
685*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
686*394324d3SSascha Wildner ena_com_handle_admin_completion(admin_queue);
687*394324d3SSascha Wildner admin_queue->stats.no_completion++;
688*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
689*394324d3SSascha Wildner
690*394324d3SSascha Wildner if (comp_ctx->status == ENA_CMD_COMPLETED)
691*394324d3SSascha Wildner ena_trc_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
692*394324d3SSascha Wildner comp_ctx->cmd_opcode);
693*394324d3SSascha Wildner else
694*394324d3SSascha Wildner ena_trc_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
695*394324d3SSascha Wildner comp_ctx->cmd_opcode, comp_ctx->status);
696*394324d3SSascha Wildner
697*394324d3SSascha Wildner admin_queue->running_state = false;
698*394324d3SSascha Wildner ret = ENA_COM_TIMER_EXPIRED;
699*394324d3SSascha Wildner goto err;
700*394324d3SSascha Wildner }
701*394324d3SSascha Wildner
702*394324d3SSascha Wildner ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
703*394324d3SSascha Wildner err:
704*394324d3SSascha Wildner comp_ctxt_release(admin_queue, comp_ctx);
705*394324d3SSascha Wildner return ret;
706*394324d3SSascha Wildner }
707*394324d3SSascha Wildner
708*394324d3SSascha Wildner /* This method read the hardware device register through posting writes
709*394324d3SSascha Wildner * and waiting for response
710*394324d3SSascha Wildner * On timeout the function will return ENA_MMIO_READ_TIMEOUT
711*394324d3SSascha Wildner */
ena_com_reg_bar_read32(struct ena_com_dev * ena_dev,u16 offset)712*394324d3SSascha Wildner static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
713*394324d3SSascha Wildner {
714*394324d3SSascha Wildner struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
715*394324d3SSascha Wildner volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
716*394324d3SSascha Wildner mmio_read->read_resp;
717*394324d3SSascha Wildner u32 mmio_read_reg, ret, i;
718*394324d3SSascha Wildner unsigned long flags;
719*394324d3SSascha Wildner u32 timeout = mmio_read->reg_read_to;
720*394324d3SSascha Wildner
721*394324d3SSascha Wildner ENA_MIGHT_SLEEP();
722*394324d3SSascha Wildner
723*394324d3SSascha Wildner if (timeout == 0)
724*394324d3SSascha Wildner timeout = ENA_REG_READ_TIMEOUT;
725*394324d3SSascha Wildner
726*394324d3SSascha Wildner /* If readless is disabled, perform regular read */
727*394324d3SSascha Wildner if (!mmio_read->readless_supported)
728*394324d3SSascha Wildner return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
729*394324d3SSascha Wildner
730*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
731*394324d3SSascha Wildner mmio_read->seq_num++;
732*394324d3SSascha Wildner
733*394324d3SSascha Wildner read_resp->req_id = mmio_read->seq_num + 0xDEAD;
734*394324d3SSascha Wildner mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
735*394324d3SSascha Wildner ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
736*394324d3SSascha Wildner mmio_read_reg |= mmio_read->seq_num &
737*394324d3SSascha Wildner ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
738*394324d3SSascha Wildner
739*394324d3SSascha Wildner /* make sure read_resp->req_id get updated before the hw can write
740*394324d3SSascha Wildner * there
741*394324d3SSascha Wildner */
742*394324d3SSascha Wildner wmb();
743*394324d3SSascha Wildner
744*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
745*394324d3SSascha Wildner
746*394324d3SSascha Wildner for (i = 0; i < timeout; i++) {
747*394324d3SSascha Wildner if (read_resp->req_id == mmio_read->seq_num)
748*394324d3SSascha Wildner break;
749*394324d3SSascha Wildner
750*394324d3SSascha Wildner ENA_UDELAY(1);
751*394324d3SSascha Wildner }
752*394324d3SSascha Wildner
753*394324d3SSascha Wildner if (unlikely(i == timeout)) {
754*394324d3SSascha Wildner ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
755*394324d3SSascha Wildner mmio_read->seq_num,
756*394324d3SSascha Wildner offset,
757*394324d3SSascha Wildner read_resp->req_id,
758*394324d3SSascha Wildner read_resp->reg_off);
759*394324d3SSascha Wildner ret = ENA_MMIO_READ_TIMEOUT;
760*394324d3SSascha Wildner goto err;
761*394324d3SSascha Wildner }
762*394324d3SSascha Wildner
763*394324d3SSascha Wildner if (read_resp->reg_off != offset) {
764*394324d3SSascha Wildner ena_trc_err("Read failure: wrong offset provided");
765*394324d3SSascha Wildner ret = ENA_MMIO_READ_TIMEOUT;
766*394324d3SSascha Wildner } else {
767*394324d3SSascha Wildner ret = read_resp->reg_val;
768*394324d3SSascha Wildner }
769*394324d3SSascha Wildner err:
770*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
771*394324d3SSascha Wildner
772*394324d3SSascha Wildner return ret;
773*394324d3SSascha Wildner }
774*394324d3SSascha Wildner
775*394324d3SSascha Wildner /* There are two types to wait for completion.
776*394324d3SSascha Wildner * Polling mode - wait until the completion is available.
777*394324d3SSascha Wildner * Async mode - wait on wait queue until the completion is ready
778*394324d3SSascha Wildner * (or the timeout expired).
779*394324d3SSascha Wildner * It is expected that the IRQ called ena_com_handle_admin_completion
780*394324d3SSascha Wildner * to mark the completions.
781*394324d3SSascha Wildner */
ena_com_wait_and_process_admin_cq(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)782*394324d3SSascha Wildner static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
783*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue)
784*394324d3SSascha Wildner {
785*394324d3SSascha Wildner if (admin_queue->polling)
786*394324d3SSascha Wildner return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
787*394324d3SSascha Wildner admin_queue);
788*394324d3SSascha Wildner
789*394324d3SSascha Wildner return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
790*394324d3SSascha Wildner admin_queue);
791*394324d3SSascha Wildner }
792*394324d3SSascha Wildner
ena_com_destroy_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq)793*394324d3SSascha Wildner static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
794*394324d3SSascha Wildner struct ena_com_io_sq *io_sq)
795*394324d3SSascha Wildner {
796*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
797*394324d3SSascha Wildner struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
798*394324d3SSascha Wildner struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
799*394324d3SSascha Wildner u8 direction;
800*394324d3SSascha Wildner int ret;
801*394324d3SSascha Wildner
802*394324d3SSascha Wildner memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
803*394324d3SSascha Wildner
804*394324d3SSascha Wildner if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
805*394324d3SSascha Wildner direction = ENA_ADMIN_SQ_DIRECTION_TX;
806*394324d3SSascha Wildner else
807*394324d3SSascha Wildner direction = ENA_ADMIN_SQ_DIRECTION_RX;
808*394324d3SSascha Wildner
809*394324d3SSascha Wildner destroy_cmd.sq.sq_identity |= (direction <<
810*394324d3SSascha Wildner ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
811*394324d3SSascha Wildner ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
812*394324d3SSascha Wildner
813*394324d3SSascha Wildner destroy_cmd.sq.sq_idx = io_sq->idx;
814*394324d3SSascha Wildner destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
815*394324d3SSascha Wildner
816*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
817*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&destroy_cmd,
818*394324d3SSascha Wildner sizeof(destroy_cmd),
819*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&destroy_resp,
820*394324d3SSascha Wildner sizeof(destroy_resp));
821*394324d3SSascha Wildner
822*394324d3SSascha Wildner if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
823*394324d3SSascha Wildner ena_trc_err("failed to destroy io sq error: %d\n", ret);
824*394324d3SSascha Wildner
825*394324d3SSascha Wildner return ret;
826*394324d3SSascha Wildner }
827*394324d3SSascha Wildner
ena_com_io_queue_free(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,struct ena_com_io_cq * io_cq)828*394324d3SSascha Wildner static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
829*394324d3SSascha Wildner struct ena_com_io_sq *io_sq,
830*394324d3SSascha Wildner struct ena_com_io_cq *io_cq)
831*394324d3SSascha Wildner {
832*394324d3SSascha Wildner size_t size;
833*394324d3SSascha Wildner
834*394324d3SSascha Wildner if (io_cq->cdesc_addr.virt_addr) {
835*394324d3SSascha Wildner size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
836*394324d3SSascha Wildner
837*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
838*394324d3SSascha Wildner size,
839*394324d3SSascha Wildner io_cq->cdesc_addr.virt_addr,
840*394324d3SSascha Wildner io_cq->cdesc_addr.phys_addr,
841*394324d3SSascha Wildner io_cq->cdesc_addr.mem_handle);
842*394324d3SSascha Wildner
843*394324d3SSascha Wildner io_cq->cdesc_addr.virt_addr = NULL;
844*394324d3SSascha Wildner }
845*394324d3SSascha Wildner
846*394324d3SSascha Wildner if (io_sq->desc_addr.virt_addr) {
847*394324d3SSascha Wildner size = io_sq->desc_entry_size * io_sq->q_depth;
848*394324d3SSascha Wildner
849*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
850*394324d3SSascha Wildner size,
851*394324d3SSascha Wildner io_sq->desc_addr.virt_addr,
852*394324d3SSascha Wildner io_sq->desc_addr.phys_addr,
853*394324d3SSascha Wildner io_sq->desc_addr.mem_handle);
854*394324d3SSascha Wildner
855*394324d3SSascha Wildner io_sq->desc_addr.virt_addr = NULL;
856*394324d3SSascha Wildner }
857*394324d3SSascha Wildner
858*394324d3SSascha Wildner if (io_sq->bounce_buf_ctrl.base_buffer) {
859*394324d3SSascha Wildner size = io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
860*394324d3SSascha Wildner ENA_MEM_FREE(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
861*394324d3SSascha Wildner io_sq->bounce_buf_ctrl.base_buffer = NULL;
862*394324d3SSascha Wildner }
863*394324d3SSascha Wildner }
864*394324d3SSascha Wildner
wait_for_reset_state(struct ena_com_dev * ena_dev,u32 timeout,u16 exp_state)865*394324d3SSascha Wildner static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
866*394324d3SSascha Wildner u16 exp_state)
867*394324d3SSascha Wildner {
868*394324d3SSascha Wildner u32 val, i;
869*394324d3SSascha Wildner
870*394324d3SSascha Wildner for (i = 0; i < timeout; i++) {
871*394324d3SSascha Wildner val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
872*394324d3SSascha Wildner
873*394324d3SSascha Wildner if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
874*394324d3SSascha Wildner ena_trc_err("Reg read timeout occurred\n");
875*394324d3SSascha Wildner return ENA_COM_TIMER_EXPIRED;
876*394324d3SSascha Wildner }
877*394324d3SSascha Wildner
878*394324d3SSascha Wildner if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
879*394324d3SSascha Wildner exp_state)
880*394324d3SSascha Wildner return 0;
881*394324d3SSascha Wildner
882*394324d3SSascha Wildner /* The resolution of the timeout is 100ms */
883*394324d3SSascha Wildner ENA_MSLEEP(100);
884*394324d3SSascha Wildner }
885*394324d3SSascha Wildner
886*394324d3SSascha Wildner return ENA_COM_TIMER_EXPIRED;
887*394324d3SSascha Wildner }
888*394324d3SSascha Wildner
ena_com_check_supported_feature_id(struct ena_com_dev * ena_dev,enum ena_admin_aq_feature_id feature_id)889*394324d3SSascha Wildner static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
890*394324d3SSascha Wildner enum ena_admin_aq_feature_id feature_id)
891*394324d3SSascha Wildner {
892*394324d3SSascha Wildner u32 feature_mask = 1 << feature_id;
893*394324d3SSascha Wildner
894*394324d3SSascha Wildner /* Device attributes is always supported */
895*394324d3SSascha Wildner if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
896*394324d3SSascha Wildner !(ena_dev->supported_features & feature_mask))
897*394324d3SSascha Wildner return false;
898*394324d3SSascha Wildner
899*394324d3SSascha Wildner return true;
900*394324d3SSascha Wildner }
901*394324d3SSascha Wildner
ena_com_get_feature_ex(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,dma_addr_t control_buf_dma_addr,u32 control_buff_size)902*394324d3SSascha Wildner static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
903*394324d3SSascha Wildner struct ena_admin_get_feat_resp *get_resp,
904*394324d3SSascha Wildner enum ena_admin_aq_feature_id feature_id,
905*394324d3SSascha Wildner dma_addr_t control_buf_dma_addr,
906*394324d3SSascha Wildner u32 control_buff_size)
907*394324d3SSascha Wildner {
908*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue;
909*394324d3SSascha Wildner struct ena_admin_get_feat_cmd get_cmd;
910*394324d3SSascha Wildner int ret;
911*394324d3SSascha Wildner
912*394324d3SSascha Wildner if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
913*394324d3SSascha Wildner ena_trc_dbg("Feature %d isn't supported\n", feature_id);
914*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
915*394324d3SSascha Wildner }
916*394324d3SSascha Wildner
917*394324d3SSascha Wildner memset(&get_cmd, 0x0, sizeof(get_cmd));
918*394324d3SSascha Wildner admin_queue = &ena_dev->admin_queue;
919*394324d3SSascha Wildner
920*394324d3SSascha Wildner get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
921*394324d3SSascha Wildner
922*394324d3SSascha Wildner if (control_buff_size)
923*394324d3SSascha Wildner get_cmd.aq_common_descriptor.flags =
924*394324d3SSascha Wildner ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
925*394324d3SSascha Wildner else
926*394324d3SSascha Wildner get_cmd.aq_common_descriptor.flags = 0;
927*394324d3SSascha Wildner
928*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
929*394324d3SSascha Wildner &get_cmd.control_buffer.address,
930*394324d3SSascha Wildner control_buf_dma_addr);
931*394324d3SSascha Wildner if (unlikely(ret)) {
932*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
933*394324d3SSascha Wildner return ret;
934*394324d3SSascha Wildner }
935*394324d3SSascha Wildner
936*394324d3SSascha Wildner get_cmd.control_buffer.length = control_buff_size;
937*394324d3SSascha Wildner
938*394324d3SSascha Wildner get_cmd.feat_common.feature_id = feature_id;
939*394324d3SSascha Wildner
940*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
941*394324d3SSascha Wildner (struct ena_admin_aq_entry *)
942*394324d3SSascha Wildner &get_cmd,
943*394324d3SSascha Wildner sizeof(get_cmd),
944*394324d3SSascha Wildner (struct ena_admin_acq_entry *)
945*394324d3SSascha Wildner get_resp,
946*394324d3SSascha Wildner sizeof(*get_resp));
947*394324d3SSascha Wildner
948*394324d3SSascha Wildner if (unlikely(ret))
949*394324d3SSascha Wildner ena_trc_err("Failed to submit get_feature command %d error: %d\n",
950*394324d3SSascha Wildner feature_id, ret);
951*394324d3SSascha Wildner
952*394324d3SSascha Wildner return ret;
953*394324d3SSascha Wildner }
954*394324d3SSascha Wildner
ena_com_get_feature(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id)955*394324d3SSascha Wildner static int ena_com_get_feature(struct ena_com_dev *ena_dev,
956*394324d3SSascha Wildner struct ena_admin_get_feat_resp *get_resp,
957*394324d3SSascha Wildner enum ena_admin_aq_feature_id feature_id)
958*394324d3SSascha Wildner {
959*394324d3SSascha Wildner return ena_com_get_feature_ex(ena_dev,
960*394324d3SSascha Wildner get_resp,
961*394324d3SSascha Wildner feature_id,
962*394324d3SSascha Wildner 0,
963*394324d3SSascha Wildner 0);
964*394324d3SSascha Wildner }
965*394324d3SSascha Wildner
ena_com_hash_key_allocate(struct ena_com_dev * ena_dev)966*394324d3SSascha Wildner static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
967*394324d3SSascha Wildner {
968*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
969*394324d3SSascha Wildner
970*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
971*394324d3SSascha Wildner sizeof(*rss->hash_key),
972*394324d3SSascha Wildner rss->hash_key,
973*394324d3SSascha Wildner rss->hash_key_dma_addr,
974*394324d3SSascha Wildner rss->hash_key_mem_handle);
975*394324d3SSascha Wildner
976*394324d3SSascha Wildner if (unlikely(!rss->hash_key))
977*394324d3SSascha Wildner return ENA_COM_NO_MEM;
978*394324d3SSascha Wildner
979*394324d3SSascha Wildner return 0;
980*394324d3SSascha Wildner }
981*394324d3SSascha Wildner
ena_com_hash_key_destroy(struct ena_com_dev * ena_dev)982*394324d3SSascha Wildner static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
983*394324d3SSascha Wildner {
984*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
985*394324d3SSascha Wildner
986*394324d3SSascha Wildner if (rss->hash_key)
987*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
988*394324d3SSascha Wildner sizeof(*rss->hash_key),
989*394324d3SSascha Wildner rss->hash_key,
990*394324d3SSascha Wildner rss->hash_key_dma_addr,
991*394324d3SSascha Wildner rss->hash_key_mem_handle);
992*394324d3SSascha Wildner rss->hash_key = NULL;
993*394324d3SSascha Wildner }
994*394324d3SSascha Wildner
ena_com_hash_ctrl_init(struct ena_com_dev * ena_dev)995*394324d3SSascha Wildner static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
996*394324d3SSascha Wildner {
997*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
998*394324d3SSascha Wildner
999*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1000*394324d3SSascha Wildner sizeof(*rss->hash_ctrl),
1001*394324d3SSascha Wildner rss->hash_ctrl,
1002*394324d3SSascha Wildner rss->hash_ctrl_dma_addr,
1003*394324d3SSascha Wildner rss->hash_ctrl_mem_handle);
1004*394324d3SSascha Wildner
1005*394324d3SSascha Wildner if (unlikely(!rss->hash_ctrl))
1006*394324d3SSascha Wildner return ENA_COM_NO_MEM;
1007*394324d3SSascha Wildner
1008*394324d3SSascha Wildner return 0;
1009*394324d3SSascha Wildner }
1010*394324d3SSascha Wildner
ena_com_hash_ctrl_destroy(struct ena_com_dev * ena_dev)1011*394324d3SSascha Wildner static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1012*394324d3SSascha Wildner {
1013*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
1014*394324d3SSascha Wildner
1015*394324d3SSascha Wildner if (rss->hash_ctrl)
1016*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1017*394324d3SSascha Wildner sizeof(*rss->hash_ctrl),
1018*394324d3SSascha Wildner rss->hash_ctrl,
1019*394324d3SSascha Wildner rss->hash_ctrl_dma_addr,
1020*394324d3SSascha Wildner rss->hash_ctrl_mem_handle);
1021*394324d3SSascha Wildner rss->hash_ctrl = NULL;
1022*394324d3SSascha Wildner }
1023*394324d3SSascha Wildner
ena_com_indirect_table_allocate(struct ena_com_dev * ena_dev,u16 log_size)1024*394324d3SSascha Wildner static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1025*394324d3SSascha Wildner u16 log_size)
1026*394324d3SSascha Wildner {
1027*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
1028*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
1029*394324d3SSascha Wildner size_t tbl_size;
1030*394324d3SSascha Wildner int ret;
1031*394324d3SSascha Wildner
1032*394324d3SSascha Wildner ret = ena_com_get_feature(ena_dev, &get_resp,
1033*394324d3SSascha Wildner ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
1034*394324d3SSascha Wildner if (unlikely(ret))
1035*394324d3SSascha Wildner return ret;
1036*394324d3SSascha Wildner
1037*394324d3SSascha Wildner if ((get_resp.u.ind_table.min_size > log_size) ||
1038*394324d3SSascha Wildner (get_resp.u.ind_table.max_size < log_size)) {
1039*394324d3SSascha Wildner ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1040*394324d3SSascha Wildner 1 << log_size,
1041*394324d3SSascha Wildner 1 << get_resp.u.ind_table.min_size,
1042*394324d3SSascha Wildner 1 << get_resp.u.ind_table.max_size);
1043*394324d3SSascha Wildner return ENA_COM_INVAL;
1044*394324d3SSascha Wildner }
1045*394324d3SSascha Wildner
1046*394324d3SSascha Wildner tbl_size = (1ULL << log_size) *
1047*394324d3SSascha Wildner sizeof(struct ena_admin_rss_ind_table_entry);
1048*394324d3SSascha Wildner
1049*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1050*394324d3SSascha Wildner tbl_size,
1051*394324d3SSascha Wildner rss->rss_ind_tbl,
1052*394324d3SSascha Wildner rss->rss_ind_tbl_dma_addr,
1053*394324d3SSascha Wildner rss->rss_ind_tbl_mem_handle);
1054*394324d3SSascha Wildner if (unlikely(!rss->rss_ind_tbl))
1055*394324d3SSascha Wildner goto mem_err1;
1056*394324d3SSascha Wildner
1057*394324d3SSascha Wildner tbl_size = (1ULL << log_size) * sizeof(u16);
1058*394324d3SSascha Wildner rss->host_rss_ind_tbl =
1059*394324d3SSascha Wildner ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1060*394324d3SSascha Wildner if (unlikely(!rss->host_rss_ind_tbl))
1061*394324d3SSascha Wildner goto mem_err2;
1062*394324d3SSascha Wildner
1063*394324d3SSascha Wildner rss->tbl_log_size = log_size;
1064*394324d3SSascha Wildner
1065*394324d3SSascha Wildner return 0;
1066*394324d3SSascha Wildner
1067*394324d3SSascha Wildner mem_err2:
1068*394324d3SSascha Wildner tbl_size = (1ULL << log_size) *
1069*394324d3SSascha Wildner sizeof(struct ena_admin_rss_ind_table_entry);
1070*394324d3SSascha Wildner
1071*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1072*394324d3SSascha Wildner tbl_size,
1073*394324d3SSascha Wildner rss->rss_ind_tbl,
1074*394324d3SSascha Wildner rss->rss_ind_tbl_dma_addr,
1075*394324d3SSascha Wildner rss->rss_ind_tbl_mem_handle);
1076*394324d3SSascha Wildner rss->rss_ind_tbl = NULL;
1077*394324d3SSascha Wildner mem_err1:
1078*394324d3SSascha Wildner rss->tbl_log_size = 0;
1079*394324d3SSascha Wildner return ENA_COM_NO_MEM;
1080*394324d3SSascha Wildner }
1081*394324d3SSascha Wildner
ena_com_indirect_table_destroy(struct ena_com_dev * ena_dev)1082*394324d3SSascha Wildner static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1083*394324d3SSascha Wildner {
1084*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
1085*394324d3SSascha Wildner size_t tbl_size = (1ULL << rss->tbl_log_size) *
1086*394324d3SSascha Wildner sizeof(struct ena_admin_rss_ind_table_entry);
1087*394324d3SSascha Wildner
1088*394324d3SSascha Wildner if (rss->rss_ind_tbl)
1089*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1090*394324d3SSascha Wildner tbl_size,
1091*394324d3SSascha Wildner rss->rss_ind_tbl,
1092*394324d3SSascha Wildner rss->rss_ind_tbl_dma_addr,
1093*394324d3SSascha Wildner rss->rss_ind_tbl_mem_handle);
1094*394324d3SSascha Wildner rss->rss_ind_tbl = NULL;
1095*394324d3SSascha Wildner
1096*394324d3SSascha Wildner if (rss->host_rss_ind_tbl)
1097*394324d3SSascha Wildner ENA_MEM_FREE(ena_dev->dmadev, rss->host_rss_ind_tbl);
1098*394324d3SSascha Wildner rss->host_rss_ind_tbl = NULL;
1099*394324d3SSascha Wildner }
1100*394324d3SSascha Wildner
ena_com_create_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,u16 cq_idx)1101*394324d3SSascha Wildner static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1102*394324d3SSascha Wildner struct ena_com_io_sq *io_sq, u16 cq_idx)
1103*394324d3SSascha Wildner {
1104*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1105*394324d3SSascha Wildner struct ena_admin_aq_create_sq_cmd create_cmd;
1106*394324d3SSascha Wildner struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1107*394324d3SSascha Wildner u8 direction;
1108*394324d3SSascha Wildner int ret;
1109*394324d3SSascha Wildner
1110*394324d3SSascha Wildner memset(&create_cmd, 0x0, sizeof(create_cmd));
1111*394324d3SSascha Wildner
1112*394324d3SSascha Wildner create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1113*394324d3SSascha Wildner
1114*394324d3SSascha Wildner if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1115*394324d3SSascha Wildner direction = ENA_ADMIN_SQ_DIRECTION_TX;
1116*394324d3SSascha Wildner else
1117*394324d3SSascha Wildner direction = ENA_ADMIN_SQ_DIRECTION_RX;
1118*394324d3SSascha Wildner
1119*394324d3SSascha Wildner create_cmd.sq_identity |= (direction <<
1120*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1121*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1122*394324d3SSascha Wildner
1123*394324d3SSascha Wildner create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1124*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1125*394324d3SSascha Wildner
1126*394324d3SSascha Wildner create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1127*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1128*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1129*394324d3SSascha Wildner
1130*394324d3SSascha Wildner create_cmd.sq_caps_3 |=
1131*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1132*394324d3SSascha Wildner
1133*394324d3SSascha Wildner create_cmd.cq_idx = cq_idx;
1134*394324d3SSascha Wildner create_cmd.sq_depth = io_sq->q_depth;
1135*394324d3SSascha Wildner
1136*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1137*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
1138*394324d3SSascha Wildner &create_cmd.sq_ba,
1139*394324d3SSascha Wildner io_sq->desc_addr.phys_addr);
1140*394324d3SSascha Wildner if (unlikely(ret)) {
1141*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
1142*394324d3SSascha Wildner return ret;
1143*394324d3SSascha Wildner }
1144*394324d3SSascha Wildner }
1145*394324d3SSascha Wildner
1146*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
1147*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&create_cmd,
1148*394324d3SSascha Wildner sizeof(create_cmd),
1149*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&cmd_completion,
1150*394324d3SSascha Wildner sizeof(cmd_completion));
1151*394324d3SSascha Wildner if (unlikely(ret)) {
1152*394324d3SSascha Wildner ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1153*394324d3SSascha Wildner return ret;
1154*394324d3SSascha Wildner }
1155*394324d3SSascha Wildner
1156*394324d3SSascha Wildner io_sq->idx = cmd_completion.sq_idx;
1157*394324d3SSascha Wildner
1158*394324d3SSascha Wildner io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1159*394324d3SSascha Wildner (uintptr_t)cmd_completion.sq_doorbell_offset);
1160*394324d3SSascha Wildner
1161*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1162*394324d3SSascha Wildner io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1163*394324d3SSascha Wildner + cmd_completion.llq_headers_offset);
1164*394324d3SSascha Wildner
1165*394324d3SSascha Wildner io_sq->desc_addr.pbuf_dev_addr =
1166*394324d3SSascha Wildner (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1167*394324d3SSascha Wildner cmd_completion.llq_descriptors_offset);
1168*394324d3SSascha Wildner }
1169*394324d3SSascha Wildner
1170*394324d3SSascha Wildner ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1171*394324d3SSascha Wildner
1172*394324d3SSascha Wildner return ret;
1173*394324d3SSascha Wildner }
1174*394324d3SSascha Wildner
ena_com_ind_tbl_convert_to_device(struct ena_com_dev * ena_dev)1175*394324d3SSascha Wildner static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1176*394324d3SSascha Wildner {
1177*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
1178*394324d3SSascha Wildner struct ena_com_io_sq *io_sq;
1179*394324d3SSascha Wildner u16 qid;
1180*394324d3SSascha Wildner int i;
1181*394324d3SSascha Wildner
1182*394324d3SSascha Wildner for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1183*394324d3SSascha Wildner qid = rss->host_rss_ind_tbl[i];
1184*394324d3SSascha Wildner if (qid >= ENA_TOTAL_NUM_QUEUES)
1185*394324d3SSascha Wildner return ENA_COM_INVAL;
1186*394324d3SSascha Wildner
1187*394324d3SSascha Wildner io_sq = &ena_dev->io_sq_queues[qid];
1188*394324d3SSascha Wildner
1189*394324d3SSascha Wildner if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1190*394324d3SSascha Wildner return ENA_COM_INVAL;
1191*394324d3SSascha Wildner
1192*394324d3SSascha Wildner rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1193*394324d3SSascha Wildner }
1194*394324d3SSascha Wildner
1195*394324d3SSascha Wildner return 0;
1196*394324d3SSascha Wildner }
1197*394324d3SSascha Wildner
ena_com_ind_tbl_convert_from_device(struct ena_com_dev * ena_dev)1198*394324d3SSascha Wildner static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1199*394324d3SSascha Wildner {
1200*394324d3SSascha Wildner u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1201*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
1202*394324d3SSascha Wildner u8 idx;
1203*394324d3SSascha Wildner u16 i;
1204*394324d3SSascha Wildner
1205*394324d3SSascha Wildner for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1206*394324d3SSascha Wildner dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1207*394324d3SSascha Wildner
1208*394324d3SSascha Wildner for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1209*394324d3SSascha Wildner if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1210*394324d3SSascha Wildner return ENA_COM_INVAL;
1211*394324d3SSascha Wildner idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1212*394324d3SSascha Wildner
1213*394324d3SSascha Wildner if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1214*394324d3SSascha Wildner return ENA_COM_INVAL;
1215*394324d3SSascha Wildner
1216*394324d3SSascha Wildner rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1217*394324d3SSascha Wildner }
1218*394324d3SSascha Wildner
1219*394324d3SSascha Wildner return 0;
1220*394324d3SSascha Wildner }
1221*394324d3SSascha Wildner
ena_com_init_interrupt_moderation_table(struct ena_com_dev * ena_dev)1222*394324d3SSascha Wildner static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1223*394324d3SSascha Wildner {
1224*394324d3SSascha Wildner size_t size;
1225*394324d3SSascha Wildner
1226*394324d3SSascha Wildner size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1227*394324d3SSascha Wildner
1228*394324d3SSascha Wildner ena_dev->intr_moder_tbl = ENA_MEM_ALLOC(ena_dev->dmadev, size);
1229*394324d3SSascha Wildner if (!ena_dev->intr_moder_tbl)
1230*394324d3SSascha Wildner return ENA_COM_NO_MEM;
1231*394324d3SSascha Wildner
1232*394324d3SSascha Wildner ena_com_config_default_interrupt_moderation_table(ena_dev);
1233*394324d3SSascha Wildner
1234*394324d3SSascha Wildner return 0;
1235*394324d3SSascha Wildner }
1236*394324d3SSascha Wildner
ena_com_update_intr_delay_resolution(struct ena_com_dev * ena_dev,u16 intr_delay_resolution)1237*394324d3SSascha Wildner static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1238*394324d3SSascha Wildner u16 intr_delay_resolution)
1239*394324d3SSascha Wildner {
1240*394324d3SSascha Wildner struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1241*394324d3SSascha Wildner unsigned int i;
1242*394324d3SSascha Wildner
1243*394324d3SSascha Wildner if (!intr_delay_resolution) {
1244*394324d3SSascha Wildner ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1245*394324d3SSascha Wildner intr_delay_resolution = 1;
1246*394324d3SSascha Wildner }
1247*394324d3SSascha Wildner ena_dev->intr_delay_resolution = intr_delay_resolution;
1248*394324d3SSascha Wildner
1249*394324d3SSascha Wildner /* update Rx */
1250*394324d3SSascha Wildner for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1251*394324d3SSascha Wildner intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1252*394324d3SSascha Wildner
1253*394324d3SSascha Wildner /* update Tx */
1254*394324d3SSascha Wildner ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1255*394324d3SSascha Wildner }
1256*394324d3SSascha Wildner
1257*394324d3SSascha Wildner /*****************************************************************************/
1258*394324d3SSascha Wildner /******************************* API ******************************/
1259*394324d3SSascha Wildner /*****************************************************************************/
1260*394324d3SSascha Wildner
ena_com_execute_admin_command(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size,struct ena_admin_acq_entry * comp,size_t comp_size)1261*394324d3SSascha Wildner int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1262*394324d3SSascha Wildner struct ena_admin_aq_entry *cmd,
1263*394324d3SSascha Wildner size_t cmd_size,
1264*394324d3SSascha Wildner struct ena_admin_acq_entry *comp,
1265*394324d3SSascha Wildner size_t comp_size)
1266*394324d3SSascha Wildner {
1267*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx;
1268*394324d3SSascha Wildner int ret;
1269*394324d3SSascha Wildner
1270*394324d3SSascha Wildner comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1271*394324d3SSascha Wildner comp, comp_size);
1272*394324d3SSascha Wildner if (unlikely(IS_ERR(comp_ctx))) {
1273*394324d3SSascha Wildner if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1274*394324d3SSascha Wildner ena_trc_dbg("Failed to submit command [%ld]\n",
1275*394324d3SSascha Wildner PTR_ERR(comp_ctx));
1276*394324d3SSascha Wildner else
1277*394324d3SSascha Wildner ena_trc_err("Failed to submit command [%ld]\n",
1278*394324d3SSascha Wildner PTR_ERR(comp_ctx));
1279*394324d3SSascha Wildner
1280*394324d3SSascha Wildner return PTR_ERR(comp_ctx);
1281*394324d3SSascha Wildner }
1282*394324d3SSascha Wildner
1283*394324d3SSascha Wildner ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1284*394324d3SSascha Wildner if (unlikely(ret)) {
1285*394324d3SSascha Wildner if (admin_queue->running_state)
1286*394324d3SSascha Wildner ena_trc_err("Failed to process command. ret = %d\n",
1287*394324d3SSascha Wildner ret);
1288*394324d3SSascha Wildner else
1289*394324d3SSascha Wildner ena_trc_dbg("Failed to process command. ret = %d\n",
1290*394324d3SSascha Wildner ret);
1291*394324d3SSascha Wildner }
1292*394324d3SSascha Wildner return ret;
1293*394324d3SSascha Wildner }
1294*394324d3SSascha Wildner
ena_com_create_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1295*394324d3SSascha Wildner int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1296*394324d3SSascha Wildner struct ena_com_io_cq *io_cq)
1297*394324d3SSascha Wildner {
1298*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1299*394324d3SSascha Wildner struct ena_admin_aq_create_cq_cmd create_cmd;
1300*394324d3SSascha Wildner struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1301*394324d3SSascha Wildner int ret;
1302*394324d3SSascha Wildner
1303*394324d3SSascha Wildner memset(&create_cmd, 0x0, sizeof(create_cmd));
1304*394324d3SSascha Wildner
1305*394324d3SSascha Wildner create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1306*394324d3SSascha Wildner
1307*394324d3SSascha Wildner create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1308*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1309*394324d3SSascha Wildner create_cmd.cq_caps_1 |=
1310*394324d3SSascha Wildner ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1311*394324d3SSascha Wildner
1312*394324d3SSascha Wildner create_cmd.msix_vector = io_cq->msix_vector;
1313*394324d3SSascha Wildner create_cmd.cq_depth = io_cq->q_depth;
1314*394324d3SSascha Wildner
1315*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
1316*394324d3SSascha Wildner &create_cmd.cq_ba,
1317*394324d3SSascha Wildner io_cq->cdesc_addr.phys_addr);
1318*394324d3SSascha Wildner if (unlikely(ret)) {
1319*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
1320*394324d3SSascha Wildner return ret;
1321*394324d3SSascha Wildner }
1322*394324d3SSascha Wildner
1323*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
1324*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&create_cmd,
1325*394324d3SSascha Wildner sizeof(create_cmd),
1326*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&cmd_completion,
1327*394324d3SSascha Wildner sizeof(cmd_completion));
1328*394324d3SSascha Wildner if (unlikely(ret)) {
1329*394324d3SSascha Wildner ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1330*394324d3SSascha Wildner return ret;
1331*394324d3SSascha Wildner }
1332*394324d3SSascha Wildner
1333*394324d3SSascha Wildner io_cq->idx = cmd_completion.cq_idx;
1334*394324d3SSascha Wildner
1335*394324d3SSascha Wildner io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1336*394324d3SSascha Wildner cmd_completion.cq_interrupt_unmask_register_offset);
1337*394324d3SSascha Wildner
1338*394324d3SSascha Wildner if (cmd_completion.cq_head_db_register_offset)
1339*394324d3SSascha Wildner io_cq->cq_head_db_reg =
1340*394324d3SSascha Wildner (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1341*394324d3SSascha Wildner cmd_completion.cq_head_db_register_offset);
1342*394324d3SSascha Wildner
1343*394324d3SSascha Wildner if (cmd_completion.numa_node_register_offset)
1344*394324d3SSascha Wildner io_cq->numa_node_cfg_reg =
1345*394324d3SSascha Wildner (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1346*394324d3SSascha Wildner cmd_completion.numa_node_register_offset);
1347*394324d3SSascha Wildner
1348*394324d3SSascha Wildner ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1349*394324d3SSascha Wildner
1350*394324d3SSascha Wildner return ret;
1351*394324d3SSascha Wildner }
1352*394324d3SSascha Wildner
ena_com_get_io_handlers(struct ena_com_dev * ena_dev,u16 qid,struct ena_com_io_sq ** io_sq,struct ena_com_io_cq ** io_cq)1353*394324d3SSascha Wildner int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1354*394324d3SSascha Wildner struct ena_com_io_sq **io_sq,
1355*394324d3SSascha Wildner struct ena_com_io_cq **io_cq)
1356*394324d3SSascha Wildner {
1357*394324d3SSascha Wildner if (qid >= ENA_TOTAL_NUM_QUEUES) {
1358*394324d3SSascha Wildner ena_trc_err("Invalid queue number %d but the max is %d\n",
1359*394324d3SSascha Wildner qid, ENA_TOTAL_NUM_QUEUES);
1360*394324d3SSascha Wildner return ENA_COM_INVAL;
1361*394324d3SSascha Wildner }
1362*394324d3SSascha Wildner
1363*394324d3SSascha Wildner *io_sq = &ena_dev->io_sq_queues[qid];
1364*394324d3SSascha Wildner *io_cq = &ena_dev->io_cq_queues[qid];
1365*394324d3SSascha Wildner
1366*394324d3SSascha Wildner return 0;
1367*394324d3SSascha Wildner }
1368*394324d3SSascha Wildner
ena_com_abort_admin_commands(struct ena_com_dev * ena_dev)1369*394324d3SSascha Wildner void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1370*394324d3SSascha Wildner {
1371*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1372*394324d3SSascha Wildner struct ena_comp_ctx *comp_ctx;
1373*394324d3SSascha Wildner u16 i;
1374*394324d3SSascha Wildner
1375*394324d3SSascha Wildner if (!admin_queue->comp_ctx)
1376*394324d3SSascha Wildner return;
1377*394324d3SSascha Wildner
1378*394324d3SSascha Wildner for (i = 0; i < admin_queue->q_depth; i++) {
1379*394324d3SSascha Wildner comp_ctx = get_comp_ctxt(admin_queue, i, false);
1380*394324d3SSascha Wildner if (unlikely(!comp_ctx))
1381*394324d3SSascha Wildner break;
1382*394324d3SSascha Wildner
1383*394324d3SSascha Wildner comp_ctx->status = ENA_CMD_ABORTED;
1384*394324d3SSascha Wildner
1385*394324d3SSascha Wildner ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1386*394324d3SSascha Wildner }
1387*394324d3SSascha Wildner }
1388*394324d3SSascha Wildner
ena_com_wait_for_abort_completion(struct ena_com_dev * ena_dev)1389*394324d3SSascha Wildner void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1390*394324d3SSascha Wildner {
1391*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1392*394324d3SSascha Wildner unsigned long flags;
1393*394324d3SSascha Wildner
1394*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1395*394324d3SSascha Wildner while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1396*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1397*394324d3SSascha Wildner ENA_MSLEEP(20);
1398*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1399*394324d3SSascha Wildner }
1400*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1401*394324d3SSascha Wildner }
1402*394324d3SSascha Wildner
ena_com_destroy_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1403*394324d3SSascha Wildner int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1404*394324d3SSascha Wildner struct ena_com_io_cq *io_cq)
1405*394324d3SSascha Wildner {
1406*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1407*394324d3SSascha Wildner struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1408*394324d3SSascha Wildner struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1409*394324d3SSascha Wildner int ret;
1410*394324d3SSascha Wildner
1411*394324d3SSascha Wildner memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1412*394324d3SSascha Wildner
1413*394324d3SSascha Wildner destroy_cmd.cq_idx = io_cq->idx;
1414*394324d3SSascha Wildner destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1415*394324d3SSascha Wildner
1416*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
1417*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&destroy_cmd,
1418*394324d3SSascha Wildner sizeof(destroy_cmd),
1419*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&destroy_resp,
1420*394324d3SSascha Wildner sizeof(destroy_resp));
1421*394324d3SSascha Wildner
1422*394324d3SSascha Wildner if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1423*394324d3SSascha Wildner ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1424*394324d3SSascha Wildner
1425*394324d3SSascha Wildner return ret;
1426*394324d3SSascha Wildner }
1427*394324d3SSascha Wildner
ena_com_get_admin_running_state(struct ena_com_dev * ena_dev)1428*394324d3SSascha Wildner bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1429*394324d3SSascha Wildner {
1430*394324d3SSascha Wildner return ena_dev->admin_queue.running_state;
1431*394324d3SSascha Wildner }
1432*394324d3SSascha Wildner
ena_com_set_admin_running_state(struct ena_com_dev * ena_dev,bool state)1433*394324d3SSascha Wildner void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1434*394324d3SSascha Wildner {
1435*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1436*394324d3SSascha Wildner unsigned long flags;
1437*394324d3SSascha Wildner
1438*394324d3SSascha Wildner ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1439*394324d3SSascha Wildner ena_dev->admin_queue.running_state = state;
1440*394324d3SSascha Wildner ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1441*394324d3SSascha Wildner }
1442*394324d3SSascha Wildner
ena_com_admin_aenq_enable(struct ena_com_dev * ena_dev)1443*394324d3SSascha Wildner void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1444*394324d3SSascha Wildner {
1445*394324d3SSascha Wildner u16 depth = ena_dev->aenq.q_depth;
1446*394324d3SSascha Wildner
1447*394324d3SSascha Wildner ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1448*394324d3SSascha Wildner
1449*394324d3SSascha Wildner /* Init head_db to mark that all entries in the queue
1450*394324d3SSascha Wildner * are initially available
1451*394324d3SSascha Wildner */
1452*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1453*394324d3SSascha Wildner }
1454*394324d3SSascha Wildner
ena_com_set_aenq_config(struct ena_com_dev * ena_dev,u32 groups_flag)1455*394324d3SSascha Wildner int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1456*394324d3SSascha Wildner {
1457*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue;
1458*394324d3SSascha Wildner struct ena_admin_set_feat_cmd cmd;
1459*394324d3SSascha Wildner struct ena_admin_set_feat_resp resp;
1460*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
1461*394324d3SSascha Wildner int ret;
1462*394324d3SSascha Wildner
1463*394324d3SSascha Wildner ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1464*394324d3SSascha Wildner if (ret) {
1465*394324d3SSascha Wildner ena_trc_info("Can't get aenq configuration\n");
1466*394324d3SSascha Wildner return ret;
1467*394324d3SSascha Wildner }
1468*394324d3SSascha Wildner
1469*394324d3SSascha Wildner if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1470*394324d3SSascha Wildner ena_trc_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1471*394324d3SSascha Wildner get_resp.u.aenq.supported_groups,
1472*394324d3SSascha Wildner groups_flag);
1473*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
1474*394324d3SSascha Wildner }
1475*394324d3SSascha Wildner
1476*394324d3SSascha Wildner memset(&cmd, 0x0, sizeof(cmd));
1477*394324d3SSascha Wildner admin_queue = &ena_dev->admin_queue;
1478*394324d3SSascha Wildner
1479*394324d3SSascha Wildner cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1480*394324d3SSascha Wildner cmd.aq_common_descriptor.flags = 0;
1481*394324d3SSascha Wildner cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1482*394324d3SSascha Wildner cmd.u.aenq.enabled_groups = groups_flag;
1483*394324d3SSascha Wildner
1484*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
1485*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&cmd,
1486*394324d3SSascha Wildner sizeof(cmd),
1487*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&resp,
1488*394324d3SSascha Wildner sizeof(resp));
1489*394324d3SSascha Wildner
1490*394324d3SSascha Wildner if (unlikely(ret))
1491*394324d3SSascha Wildner ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1492*394324d3SSascha Wildner
1493*394324d3SSascha Wildner return ret;
1494*394324d3SSascha Wildner }
1495*394324d3SSascha Wildner
ena_com_get_dma_width(struct ena_com_dev * ena_dev)1496*394324d3SSascha Wildner int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1497*394324d3SSascha Wildner {
1498*394324d3SSascha Wildner u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1499*394324d3SSascha Wildner int width;
1500*394324d3SSascha Wildner
1501*394324d3SSascha Wildner if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1502*394324d3SSascha Wildner ena_trc_err("Reg read timeout occurred\n");
1503*394324d3SSascha Wildner return ENA_COM_TIMER_EXPIRED;
1504*394324d3SSascha Wildner }
1505*394324d3SSascha Wildner
1506*394324d3SSascha Wildner width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1507*394324d3SSascha Wildner ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1508*394324d3SSascha Wildner
1509*394324d3SSascha Wildner ena_trc_dbg("ENA dma width: %d\n", width);
1510*394324d3SSascha Wildner
1511*394324d3SSascha Wildner if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1512*394324d3SSascha Wildner ena_trc_err("DMA width illegal value: %d\n", width);
1513*394324d3SSascha Wildner return ENA_COM_INVAL;
1514*394324d3SSascha Wildner }
1515*394324d3SSascha Wildner
1516*394324d3SSascha Wildner ena_dev->dma_addr_bits = width;
1517*394324d3SSascha Wildner
1518*394324d3SSascha Wildner return width;
1519*394324d3SSascha Wildner }
1520*394324d3SSascha Wildner
ena_com_validate_version(struct ena_com_dev * ena_dev)1521*394324d3SSascha Wildner int ena_com_validate_version(struct ena_com_dev *ena_dev)
1522*394324d3SSascha Wildner {
1523*394324d3SSascha Wildner u32 ver;
1524*394324d3SSascha Wildner u32 ctrl_ver;
1525*394324d3SSascha Wildner u32 ctrl_ver_masked;
1526*394324d3SSascha Wildner
1527*394324d3SSascha Wildner /* Make sure the ENA version and the controller version are at least
1528*394324d3SSascha Wildner * as the driver expects
1529*394324d3SSascha Wildner */
1530*394324d3SSascha Wildner ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1531*394324d3SSascha Wildner ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1532*394324d3SSascha Wildner ENA_REGS_CONTROLLER_VERSION_OFF);
1533*394324d3SSascha Wildner
1534*394324d3SSascha Wildner if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1535*394324d3SSascha Wildner (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1536*394324d3SSascha Wildner ena_trc_err("Reg read timeout occurred\n");
1537*394324d3SSascha Wildner return ENA_COM_TIMER_EXPIRED;
1538*394324d3SSascha Wildner }
1539*394324d3SSascha Wildner
1540*394324d3SSascha Wildner ena_trc_info("ena device version: %d.%d\n",
1541*394324d3SSascha Wildner (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1542*394324d3SSascha Wildner ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1543*394324d3SSascha Wildner ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1544*394324d3SSascha Wildner
1545*394324d3SSascha Wildner if (ver < MIN_ENA_VER) {
1546*394324d3SSascha Wildner ena_trc_err("ENA version is lower than the minimal version the driver supports\n");
1547*394324d3SSascha Wildner return -1;
1548*394324d3SSascha Wildner }
1549*394324d3SSascha Wildner
1550*394324d3SSascha Wildner ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1551*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1552*394324d3SSascha Wildner >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1553*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1554*394324d3SSascha Wildner >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1555*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1556*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1557*394324d3SSascha Wildner ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1558*394324d3SSascha Wildner
1559*394324d3SSascha Wildner ctrl_ver_masked =
1560*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1561*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1562*394324d3SSascha Wildner (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1563*394324d3SSascha Wildner
1564*394324d3SSascha Wildner /* Validate the ctrl version without the implementation ID */
1565*394324d3SSascha Wildner if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1566*394324d3SSascha Wildner ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1567*394324d3SSascha Wildner return -1;
1568*394324d3SSascha Wildner }
1569*394324d3SSascha Wildner
1570*394324d3SSascha Wildner return 0;
1571*394324d3SSascha Wildner }
1572*394324d3SSascha Wildner
ena_com_admin_destroy(struct ena_com_dev * ena_dev)1573*394324d3SSascha Wildner void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1574*394324d3SSascha Wildner {
1575*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1576*394324d3SSascha Wildner struct ena_com_admin_cq *cq = &admin_queue->cq;
1577*394324d3SSascha Wildner struct ena_com_admin_sq *sq = &admin_queue->sq;
1578*394324d3SSascha Wildner struct ena_com_aenq *aenq = &ena_dev->aenq;
1579*394324d3SSascha Wildner u16 size;
1580*394324d3SSascha Wildner
1581*394324d3SSascha Wildner ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1582*394324d3SSascha Wildner
1583*394324d3SSascha Wildner ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1584*394324d3SSascha Wildner
1585*394324d3SSascha Wildner if (admin_queue->comp_ctx)
1586*394324d3SSascha Wildner ENA_MEM_FREE(ena_dev->dmadev, admin_queue->comp_ctx);
1587*394324d3SSascha Wildner admin_queue->comp_ctx = NULL;
1588*394324d3SSascha Wildner size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1589*394324d3SSascha Wildner if (sq->entries)
1590*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1591*394324d3SSascha Wildner sq->dma_addr, sq->mem_handle);
1592*394324d3SSascha Wildner sq->entries = NULL;
1593*394324d3SSascha Wildner
1594*394324d3SSascha Wildner size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1595*394324d3SSascha Wildner if (cq->entries)
1596*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1597*394324d3SSascha Wildner cq->dma_addr, cq->mem_handle);
1598*394324d3SSascha Wildner cq->entries = NULL;
1599*394324d3SSascha Wildner
1600*394324d3SSascha Wildner size = ADMIN_AENQ_SIZE(aenq->q_depth);
1601*394324d3SSascha Wildner if (ena_dev->aenq.entries)
1602*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1603*394324d3SSascha Wildner aenq->dma_addr, aenq->mem_handle);
1604*394324d3SSascha Wildner aenq->entries = NULL;
1605*394324d3SSascha Wildner }
1606*394324d3SSascha Wildner
ena_com_set_admin_polling_mode(struct ena_com_dev * ena_dev,bool polling)1607*394324d3SSascha Wildner void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1608*394324d3SSascha Wildner {
1609*394324d3SSascha Wildner u32 mask_value = 0;
1610*394324d3SSascha Wildner
1611*394324d3SSascha Wildner if (polling)
1612*394324d3SSascha Wildner mask_value = ENA_REGS_ADMIN_INTR_MASK;
1613*394324d3SSascha Wildner
1614*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1615*394324d3SSascha Wildner ena_dev->admin_queue.polling = polling;
1616*394324d3SSascha Wildner }
1617*394324d3SSascha Wildner
ena_com_mmio_reg_read_request_init(struct ena_com_dev * ena_dev)1618*394324d3SSascha Wildner int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1619*394324d3SSascha Wildner {
1620*394324d3SSascha Wildner struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1621*394324d3SSascha Wildner
1622*394324d3SSascha Wildner ENA_SPINLOCK_INIT(mmio_read->lock);
1623*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1624*394324d3SSascha Wildner sizeof(*mmio_read->read_resp),
1625*394324d3SSascha Wildner mmio_read->read_resp,
1626*394324d3SSascha Wildner mmio_read->read_resp_dma_addr,
1627*394324d3SSascha Wildner mmio_read->read_resp_mem_handle);
1628*394324d3SSascha Wildner if (unlikely(!mmio_read->read_resp))
1629*394324d3SSascha Wildner return ENA_COM_NO_MEM;
1630*394324d3SSascha Wildner
1631*394324d3SSascha Wildner ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1632*394324d3SSascha Wildner
1633*394324d3SSascha Wildner mmio_read->read_resp->req_id = 0x0;
1634*394324d3SSascha Wildner mmio_read->seq_num = 0x0;
1635*394324d3SSascha Wildner mmio_read->readless_supported = true;
1636*394324d3SSascha Wildner
1637*394324d3SSascha Wildner return 0;
1638*394324d3SSascha Wildner }
1639*394324d3SSascha Wildner
ena_com_set_mmio_read_mode(struct ena_com_dev * ena_dev,bool readless_supported)1640*394324d3SSascha Wildner void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1641*394324d3SSascha Wildner {
1642*394324d3SSascha Wildner struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1643*394324d3SSascha Wildner
1644*394324d3SSascha Wildner mmio_read->readless_supported = readless_supported;
1645*394324d3SSascha Wildner }
1646*394324d3SSascha Wildner
ena_com_mmio_reg_read_request_destroy(struct ena_com_dev * ena_dev)1647*394324d3SSascha Wildner void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1648*394324d3SSascha Wildner {
1649*394324d3SSascha Wildner struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1650*394324d3SSascha Wildner
1651*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1652*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1653*394324d3SSascha Wildner
1654*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1655*394324d3SSascha Wildner sizeof(*mmio_read->read_resp),
1656*394324d3SSascha Wildner mmio_read->read_resp,
1657*394324d3SSascha Wildner mmio_read->read_resp_dma_addr,
1658*394324d3SSascha Wildner mmio_read->read_resp_mem_handle);
1659*394324d3SSascha Wildner
1660*394324d3SSascha Wildner mmio_read->read_resp = NULL;
1661*394324d3SSascha Wildner
1662*394324d3SSascha Wildner ENA_SPINLOCK_DESTROY(mmio_read->lock);
1663*394324d3SSascha Wildner }
1664*394324d3SSascha Wildner
ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev * ena_dev)1665*394324d3SSascha Wildner void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1666*394324d3SSascha Wildner {
1667*394324d3SSascha Wildner struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1668*394324d3SSascha Wildner u32 addr_low, addr_high;
1669*394324d3SSascha Wildner
1670*394324d3SSascha Wildner addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1671*394324d3SSascha Wildner addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1672*394324d3SSascha Wildner
1673*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1674*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1675*394324d3SSascha Wildner }
1676*394324d3SSascha Wildner
ena_com_admin_init(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers,bool init_spinlock)1677*394324d3SSascha Wildner int ena_com_admin_init(struct ena_com_dev *ena_dev,
1678*394324d3SSascha Wildner struct ena_aenq_handlers *aenq_handlers,
1679*394324d3SSascha Wildner bool init_spinlock)
1680*394324d3SSascha Wildner {
1681*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1682*394324d3SSascha Wildner u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1683*394324d3SSascha Wildner int ret;
1684*394324d3SSascha Wildner
1685*394324d3SSascha Wildner #ifdef ENA_INTERNAL
1686*394324d3SSascha Wildner ena_trc_info("ena_defs : Version:[%s] Build date [%s]",
1687*394324d3SSascha Wildner ENA_GEN_COMMIT, ENA_GEN_DATE);
1688*394324d3SSascha Wildner #endif
1689*394324d3SSascha Wildner dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1690*394324d3SSascha Wildner
1691*394324d3SSascha Wildner if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1692*394324d3SSascha Wildner ena_trc_err("Reg read timeout occurred\n");
1693*394324d3SSascha Wildner return ENA_COM_TIMER_EXPIRED;
1694*394324d3SSascha Wildner }
1695*394324d3SSascha Wildner
1696*394324d3SSascha Wildner if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1697*394324d3SSascha Wildner ena_trc_err("Device isn't ready, abort com init\n");
1698*394324d3SSascha Wildner return ENA_COM_NO_DEVICE;
1699*394324d3SSascha Wildner }
1700*394324d3SSascha Wildner
1701*394324d3SSascha Wildner admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1702*394324d3SSascha Wildner
1703*394324d3SSascha Wildner admin_queue->bus = ena_dev->bus;
1704*394324d3SSascha Wildner admin_queue->q_dmadev = ena_dev->dmadev;
1705*394324d3SSascha Wildner admin_queue->polling = false;
1706*394324d3SSascha Wildner admin_queue->curr_cmd_id = 0;
1707*394324d3SSascha Wildner
1708*394324d3SSascha Wildner ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1709*394324d3SSascha Wildner
1710*394324d3SSascha Wildner if (init_spinlock)
1711*394324d3SSascha Wildner ENA_SPINLOCK_INIT(admin_queue->q_lock);
1712*394324d3SSascha Wildner
1713*394324d3SSascha Wildner ret = ena_com_init_comp_ctxt(admin_queue);
1714*394324d3SSascha Wildner if (ret)
1715*394324d3SSascha Wildner goto error;
1716*394324d3SSascha Wildner
1717*394324d3SSascha Wildner ret = ena_com_admin_init_sq(admin_queue);
1718*394324d3SSascha Wildner if (ret)
1719*394324d3SSascha Wildner goto error;
1720*394324d3SSascha Wildner
1721*394324d3SSascha Wildner ret = ena_com_admin_init_cq(admin_queue);
1722*394324d3SSascha Wildner if (ret)
1723*394324d3SSascha Wildner goto error;
1724*394324d3SSascha Wildner
1725*394324d3SSascha Wildner admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1726*394324d3SSascha Wildner ENA_REGS_AQ_DB_OFF);
1727*394324d3SSascha Wildner
1728*394324d3SSascha Wildner addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1729*394324d3SSascha Wildner addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1730*394324d3SSascha Wildner
1731*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1732*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1733*394324d3SSascha Wildner
1734*394324d3SSascha Wildner addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1735*394324d3SSascha Wildner addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1736*394324d3SSascha Wildner
1737*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1738*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1739*394324d3SSascha Wildner
1740*394324d3SSascha Wildner aq_caps = 0;
1741*394324d3SSascha Wildner aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1742*394324d3SSascha Wildner aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1743*394324d3SSascha Wildner ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1744*394324d3SSascha Wildner ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1745*394324d3SSascha Wildner
1746*394324d3SSascha Wildner acq_caps = 0;
1747*394324d3SSascha Wildner acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1748*394324d3SSascha Wildner acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1749*394324d3SSascha Wildner ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1750*394324d3SSascha Wildner ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1751*394324d3SSascha Wildner
1752*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1753*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1754*394324d3SSascha Wildner ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1755*394324d3SSascha Wildner if (ret)
1756*394324d3SSascha Wildner goto error;
1757*394324d3SSascha Wildner
1758*394324d3SSascha Wildner admin_queue->running_state = true;
1759*394324d3SSascha Wildner
1760*394324d3SSascha Wildner return 0;
1761*394324d3SSascha Wildner error:
1762*394324d3SSascha Wildner ena_com_admin_destroy(ena_dev);
1763*394324d3SSascha Wildner
1764*394324d3SSascha Wildner return ret;
1765*394324d3SSascha Wildner }
1766*394324d3SSascha Wildner
ena_com_create_io_queue(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx)1767*394324d3SSascha Wildner int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1768*394324d3SSascha Wildner struct ena_com_create_io_ctx *ctx)
1769*394324d3SSascha Wildner {
1770*394324d3SSascha Wildner struct ena_com_io_sq *io_sq;
1771*394324d3SSascha Wildner struct ena_com_io_cq *io_cq;
1772*394324d3SSascha Wildner int ret;
1773*394324d3SSascha Wildner
1774*394324d3SSascha Wildner if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1775*394324d3SSascha Wildner ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1776*394324d3SSascha Wildner ctx->qid, ENA_TOTAL_NUM_QUEUES);
1777*394324d3SSascha Wildner return ENA_COM_INVAL;
1778*394324d3SSascha Wildner }
1779*394324d3SSascha Wildner
1780*394324d3SSascha Wildner io_sq = &ena_dev->io_sq_queues[ctx->qid];
1781*394324d3SSascha Wildner io_cq = &ena_dev->io_cq_queues[ctx->qid];
1782*394324d3SSascha Wildner
1783*394324d3SSascha Wildner memset(io_sq, 0x0, sizeof(*io_sq));
1784*394324d3SSascha Wildner memset(io_cq, 0x0, sizeof(*io_cq));
1785*394324d3SSascha Wildner
1786*394324d3SSascha Wildner /* Init CQ */
1787*394324d3SSascha Wildner io_cq->q_depth = ctx->queue_size;
1788*394324d3SSascha Wildner io_cq->direction = ctx->direction;
1789*394324d3SSascha Wildner io_cq->qid = ctx->qid;
1790*394324d3SSascha Wildner
1791*394324d3SSascha Wildner io_cq->msix_vector = ctx->msix_vector;
1792*394324d3SSascha Wildner
1793*394324d3SSascha Wildner io_sq->q_depth = ctx->queue_size;
1794*394324d3SSascha Wildner io_sq->direction = ctx->direction;
1795*394324d3SSascha Wildner io_sq->qid = ctx->qid;
1796*394324d3SSascha Wildner
1797*394324d3SSascha Wildner io_sq->mem_queue_type = ctx->mem_queue_type;
1798*394324d3SSascha Wildner
1799*394324d3SSascha Wildner if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1800*394324d3SSascha Wildner /* header length is limited to 8 bits */
1801*394324d3SSascha Wildner io_sq->tx_max_header_size =
1802*394324d3SSascha Wildner ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1803*394324d3SSascha Wildner
1804*394324d3SSascha Wildner ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1805*394324d3SSascha Wildner if (ret)
1806*394324d3SSascha Wildner goto error;
1807*394324d3SSascha Wildner ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1808*394324d3SSascha Wildner if (ret)
1809*394324d3SSascha Wildner goto error;
1810*394324d3SSascha Wildner
1811*394324d3SSascha Wildner ret = ena_com_create_io_cq(ena_dev, io_cq);
1812*394324d3SSascha Wildner if (ret)
1813*394324d3SSascha Wildner goto error;
1814*394324d3SSascha Wildner
1815*394324d3SSascha Wildner ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1816*394324d3SSascha Wildner if (ret)
1817*394324d3SSascha Wildner goto destroy_io_cq;
1818*394324d3SSascha Wildner
1819*394324d3SSascha Wildner return 0;
1820*394324d3SSascha Wildner
1821*394324d3SSascha Wildner destroy_io_cq:
1822*394324d3SSascha Wildner ena_com_destroy_io_cq(ena_dev, io_cq);
1823*394324d3SSascha Wildner error:
1824*394324d3SSascha Wildner ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1825*394324d3SSascha Wildner return ret;
1826*394324d3SSascha Wildner }
1827*394324d3SSascha Wildner
ena_com_destroy_io_queue(struct ena_com_dev * ena_dev,u16 qid)1828*394324d3SSascha Wildner void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1829*394324d3SSascha Wildner {
1830*394324d3SSascha Wildner struct ena_com_io_sq *io_sq;
1831*394324d3SSascha Wildner struct ena_com_io_cq *io_cq;
1832*394324d3SSascha Wildner
1833*394324d3SSascha Wildner if (qid >= ENA_TOTAL_NUM_QUEUES) {
1834*394324d3SSascha Wildner ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1835*394324d3SSascha Wildner qid, ENA_TOTAL_NUM_QUEUES);
1836*394324d3SSascha Wildner return;
1837*394324d3SSascha Wildner }
1838*394324d3SSascha Wildner
1839*394324d3SSascha Wildner io_sq = &ena_dev->io_sq_queues[qid];
1840*394324d3SSascha Wildner io_cq = &ena_dev->io_cq_queues[qid];
1841*394324d3SSascha Wildner
1842*394324d3SSascha Wildner ena_com_destroy_io_sq(ena_dev, io_sq);
1843*394324d3SSascha Wildner ena_com_destroy_io_cq(ena_dev, io_cq);
1844*394324d3SSascha Wildner
1845*394324d3SSascha Wildner ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1846*394324d3SSascha Wildner }
1847*394324d3SSascha Wildner
ena_com_get_link_params(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * resp)1848*394324d3SSascha Wildner int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1849*394324d3SSascha Wildner struct ena_admin_get_feat_resp *resp)
1850*394324d3SSascha Wildner {
1851*394324d3SSascha Wildner return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1852*394324d3SSascha Wildner }
1853*394324d3SSascha Wildner
ena_com_get_dev_attr_feat(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)1854*394324d3SSascha Wildner int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1855*394324d3SSascha Wildner struct ena_com_dev_get_features_ctx *get_feat_ctx)
1856*394324d3SSascha Wildner {
1857*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
1858*394324d3SSascha Wildner int rc;
1859*394324d3SSascha Wildner
1860*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp,
1861*394324d3SSascha Wildner ENA_ADMIN_DEVICE_ATTRIBUTES);
1862*394324d3SSascha Wildner if (rc)
1863*394324d3SSascha Wildner return rc;
1864*394324d3SSascha Wildner
1865*394324d3SSascha Wildner memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1866*394324d3SSascha Wildner sizeof(get_resp.u.dev_attr));
1867*394324d3SSascha Wildner ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1868*394324d3SSascha Wildner
1869*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp,
1870*394324d3SSascha Wildner ENA_ADMIN_MAX_QUEUES_NUM);
1871*394324d3SSascha Wildner if (rc)
1872*394324d3SSascha Wildner return rc;
1873*394324d3SSascha Wildner
1874*394324d3SSascha Wildner memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1875*394324d3SSascha Wildner sizeof(get_resp.u.max_queue));
1876*394324d3SSascha Wildner ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1877*394324d3SSascha Wildner
1878*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp,
1879*394324d3SSascha Wildner ENA_ADMIN_AENQ_CONFIG);
1880*394324d3SSascha Wildner if (rc)
1881*394324d3SSascha Wildner return rc;
1882*394324d3SSascha Wildner
1883*394324d3SSascha Wildner memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1884*394324d3SSascha Wildner sizeof(get_resp.u.aenq));
1885*394324d3SSascha Wildner
1886*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp,
1887*394324d3SSascha Wildner ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1888*394324d3SSascha Wildner if (rc)
1889*394324d3SSascha Wildner return rc;
1890*394324d3SSascha Wildner
1891*394324d3SSascha Wildner memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1892*394324d3SSascha Wildner sizeof(get_resp.u.offload));
1893*394324d3SSascha Wildner
1894*394324d3SSascha Wildner /* Driver hints isn't mandatory admin command. So in case the
1895*394324d3SSascha Wildner * command isn't supported set driver hints to 0
1896*394324d3SSascha Wildner */
1897*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS);
1898*394324d3SSascha Wildner
1899*394324d3SSascha Wildner if (!rc)
1900*394324d3SSascha Wildner memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1901*394324d3SSascha Wildner sizeof(get_resp.u.hw_hints));
1902*394324d3SSascha Wildner else if (rc == ENA_COM_UNSUPPORTED)
1903*394324d3SSascha Wildner memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1904*394324d3SSascha Wildner else
1905*394324d3SSascha Wildner return rc;
1906*394324d3SSascha Wildner
1907*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ);
1908*394324d3SSascha Wildner if (!rc)
1909*394324d3SSascha Wildner memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
1910*394324d3SSascha Wildner sizeof(get_resp.u.llq));
1911*394324d3SSascha Wildner else if (rc == ENA_COM_UNSUPPORTED)
1912*394324d3SSascha Wildner memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
1913*394324d3SSascha Wildner else
1914*394324d3SSascha Wildner return rc;
1915*394324d3SSascha Wildner
1916*394324d3SSascha Wildner return 0;
1917*394324d3SSascha Wildner }
1918*394324d3SSascha Wildner
ena_com_admin_q_comp_intr_handler(struct ena_com_dev * ena_dev)1919*394324d3SSascha Wildner void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1920*394324d3SSascha Wildner {
1921*394324d3SSascha Wildner ena_com_handle_admin_completion(&ena_dev->admin_queue);
1922*394324d3SSascha Wildner }
1923*394324d3SSascha Wildner
1924*394324d3SSascha Wildner /* ena_handle_specific_aenq_event:
1925*394324d3SSascha Wildner * return the handler that is relevant to the specific event group
1926*394324d3SSascha Wildner */
ena_com_get_specific_aenq_cb(struct ena_com_dev * dev,u16 group)1927*394324d3SSascha Wildner static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1928*394324d3SSascha Wildner u16 group)
1929*394324d3SSascha Wildner {
1930*394324d3SSascha Wildner struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1931*394324d3SSascha Wildner
1932*394324d3SSascha Wildner if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1933*394324d3SSascha Wildner return aenq_handlers->handlers[group];
1934*394324d3SSascha Wildner
1935*394324d3SSascha Wildner return aenq_handlers->unimplemented_handler;
1936*394324d3SSascha Wildner }
1937*394324d3SSascha Wildner
1938*394324d3SSascha Wildner /* ena_aenq_intr_handler:
1939*394324d3SSascha Wildner * handles the aenq incoming events.
1940*394324d3SSascha Wildner * pop events from the queue and apply the specific handler
1941*394324d3SSascha Wildner */
ena_com_aenq_intr_handler(struct ena_com_dev * dev,void * data)1942*394324d3SSascha Wildner void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1943*394324d3SSascha Wildner {
1944*394324d3SSascha Wildner struct ena_admin_aenq_entry *aenq_e;
1945*394324d3SSascha Wildner struct ena_admin_aenq_common_desc *aenq_common;
1946*394324d3SSascha Wildner struct ena_com_aenq *aenq = &dev->aenq;
1947*394324d3SSascha Wildner ena_aenq_handler handler_cb;
1948*394324d3SSascha Wildner unsigned long long timestamp;
1949*394324d3SSascha Wildner u16 masked_head, processed = 0;
1950*394324d3SSascha Wildner u8 phase;
1951*394324d3SSascha Wildner
1952*394324d3SSascha Wildner masked_head = aenq->head & (aenq->q_depth - 1);
1953*394324d3SSascha Wildner phase = aenq->phase;
1954*394324d3SSascha Wildner aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1955*394324d3SSascha Wildner aenq_common = &aenq_e->aenq_common_desc;
1956*394324d3SSascha Wildner
1957*394324d3SSascha Wildner /* Go over all the events */
1958*394324d3SSascha Wildner while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) ==
1959*394324d3SSascha Wildner phase) {
1960*394324d3SSascha Wildner timestamp = (unsigned long long)aenq_common->timestamp_low |
1961*394324d3SSascha Wildner ((unsigned long long)aenq_common->timestamp_high << 32);
1962*394324d3SSascha Wildner ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1963*394324d3SSascha Wildner aenq_common->group,
1964*394324d3SSascha Wildner aenq_common->syndrom,
1965*394324d3SSascha Wildner timestamp);
1966*394324d3SSascha Wildner
1967*394324d3SSascha Wildner /* Handle specific event*/
1968*394324d3SSascha Wildner handler_cb = ena_com_get_specific_aenq_cb(dev,
1969*394324d3SSascha Wildner aenq_common->group);
1970*394324d3SSascha Wildner handler_cb(data, aenq_e); /* call the actual event handler*/
1971*394324d3SSascha Wildner
1972*394324d3SSascha Wildner /* Get next event entry */
1973*394324d3SSascha Wildner masked_head++;
1974*394324d3SSascha Wildner processed++;
1975*394324d3SSascha Wildner
1976*394324d3SSascha Wildner if (unlikely(masked_head == aenq->q_depth)) {
1977*394324d3SSascha Wildner masked_head = 0;
1978*394324d3SSascha Wildner phase = !phase;
1979*394324d3SSascha Wildner }
1980*394324d3SSascha Wildner aenq_e = &aenq->entries[masked_head];
1981*394324d3SSascha Wildner aenq_common = &aenq_e->aenq_common_desc;
1982*394324d3SSascha Wildner }
1983*394324d3SSascha Wildner
1984*394324d3SSascha Wildner aenq->head += processed;
1985*394324d3SSascha Wildner aenq->phase = phase;
1986*394324d3SSascha Wildner
1987*394324d3SSascha Wildner /* Don't update aenq doorbell if there weren't any processed events */
1988*394324d3SSascha Wildner if (!processed)
1989*394324d3SSascha Wildner return;
1990*394324d3SSascha Wildner
1991*394324d3SSascha Wildner /* write the aenq doorbell after all AENQ descriptors were read */
1992*394324d3SSascha Wildner mb();
1993*394324d3SSascha Wildner ENA_REG_WRITE32(dev->bus, (u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1994*394324d3SSascha Wildner }
1995*394324d3SSascha Wildner #ifdef ENA_EXTENDED_STATS
1996*394324d3SSascha Wildner /*
1997*394324d3SSascha Wildner * Sets the function Idx and Queue Idx to be used for
1998*394324d3SSascha Wildner * get full statistics feature
1999*394324d3SSascha Wildner *
2000*394324d3SSascha Wildner */
ena_com_extended_stats_set_func_queue(struct ena_com_dev * ena_dev,u32 func_queue)2001*394324d3SSascha Wildner int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
2002*394324d3SSascha Wildner u32 func_queue)
2003*394324d3SSascha Wildner {
2004*394324d3SSascha Wildner
2005*394324d3SSascha Wildner /* Function & Queue is acquired from user in the following format :
2006*394324d3SSascha Wildner * Bottom Half word: funct
2007*394324d3SSascha Wildner * Top Half Word: queue
2008*394324d3SSascha Wildner */
2009*394324d3SSascha Wildner ena_dev->stats_func = ENA_EXTENDED_STAT_GET_FUNCT(func_queue);
2010*394324d3SSascha Wildner ena_dev->stats_queue = ENA_EXTENDED_STAT_GET_QUEUE(func_queue);
2011*394324d3SSascha Wildner
2012*394324d3SSascha Wildner return 0;
2013*394324d3SSascha Wildner }
2014*394324d3SSascha Wildner
2015*394324d3SSascha Wildner #endif /* ENA_EXTENDED_STATS */
2016*394324d3SSascha Wildner
ena_com_dev_reset(struct ena_com_dev * ena_dev,enum ena_regs_reset_reason_types reset_reason)2017*394324d3SSascha Wildner int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2018*394324d3SSascha Wildner enum ena_regs_reset_reason_types reset_reason)
2019*394324d3SSascha Wildner {
2020*394324d3SSascha Wildner u32 stat, timeout, cap, reset_val;
2021*394324d3SSascha Wildner int rc;
2022*394324d3SSascha Wildner
2023*394324d3SSascha Wildner stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2024*394324d3SSascha Wildner cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2025*394324d3SSascha Wildner
2026*394324d3SSascha Wildner if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2027*394324d3SSascha Wildner (cap == ENA_MMIO_READ_TIMEOUT))) {
2028*394324d3SSascha Wildner ena_trc_err("Reg read32 timeout occurred\n");
2029*394324d3SSascha Wildner return ENA_COM_TIMER_EXPIRED;
2030*394324d3SSascha Wildner }
2031*394324d3SSascha Wildner
2032*394324d3SSascha Wildner if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2033*394324d3SSascha Wildner ena_trc_err("Device isn't ready, can't reset device\n");
2034*394324d3SSascha Wildner return ENA_COM_INVAL;
2035*394324d3SSascha Wildner }
2036*394324d3SSascha Wildner
2037*394324d3SSascha Wildner timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2038*394324d3SSascha Wildner ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2039*394324d3SSascha Wildner if (timeout == 0) {
2040*394324d3SSascha Wildner ena_trc_err("Invalid timeout value\n");
2041*394324d3SSascha Wildner return ENA_COM_INVAL;
2042*394324d3SSascha Wildner }
2043*394324d3SSascha Wildner
2044*394324d3SSascha Wildner /* start reset */
2045*394324d3SSascha Wildner reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2046*394324d3SSascha Wildner reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2047*394324d3SSascha Wildner ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2048*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2049*394324d3SSascha Wildner
2050*394324d3SSascha Wildner /* Write again the MMIO read request address */
2051*394324d3SSascha Wildner ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2052*394324d3SSascha Wildner
2053*394324d3SSascha Wildner rc = wait_for_reset_state(ena_dev, timeout,
2054*394324d3SSascha Wildner ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2055*394324d3SSascha Wildner if (rc != 0) {
2056*394324d3SSascha Wildner ena_trc_err("Reset indication didn't turn on\n");
2057*394324d3SSascha Wildner return rc;
2058*394324d3SSascha Wildner }
2059*394324d3SSascha Wildner
2060*394324d3SSascha Wildner /* reset done */
2061*394324d3SSascha Wildner ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2062*394324d3SSascha Wildner rc = wait_for_reset_state(ena_dev, timeout, 0);
2063*394324d3SSascha Wildner if (rc != 0) {
2064*394324d3SSascha Wildner ena_trc_err("Reset indication didn't turn off\n");
2065*394324d3SSascha Wildner return rc;
2066*394324d3SSascha Wildner }
2067*394324d3SSascha Wildner
2068*394324d3SSascha Wildner timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2069*394324d3SSascha Wildner ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2070*394324d3SSascha Wildner if (timeout)
2071*394324d3SSascha Wildner /* the resolution of timeout reg is 100ms */
2072*394324d3SSascha Wildner ena_dev->admin_queue.completion_timeout = timeout * 100000;
2073*394324d3SSascha Wildner else
2074*394324d3SSascha Wildner ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2075*394324d3SSascha Wildner
2076*394324d3SSascha Wildner return 0;
2077*394324d3SSascha Wildner }
2078*394324d3SSascha Wildner
ena_get_dev_stats(struct ena_com_dev * ena_dev,struct ena_com_stats_ctx * ctx,enum ena_admin_get_stats_type type)2079*394324d3SSascha Wildner static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2080*394324d3SSascha Wildner struct ena_com_stats_ctx *ctx,
2081*394324d3SSascha Wildner enum ena_admin_get_stats_type type)
2082*394324d3SSascha Wildner {
2083*394324d3SSascha Wildner struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2084*394324d3SSascha Wildner struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2085*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue;
2086*394324d3SSascha Wildner int ret;
2087*394324d3SSascha Wildner
2088*394324d3SSascha Wildner admin_queue = &ena_dev->admin_queue;
2089*394324d3SSascha Wildner
2090*394324d3SSascha Wildner get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2091*394324d3SSascha Wildner get_cmd->aq_common_descriptor.flags = 0;
2092*394324d3SSascha Wildner get_cmd->type = type;
2093*394324d3SSascha Wildner
2094*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
2095*394324d3SSascha Wildner (struct ena_admin_aq_entry *)get_cmd,
2096*394324d3SSascha Wildner sizeof(*get_cmd),
2097*394324d3SSascha Wildner (struct ena_admin_acq_entry *)get_resp,
2098*394324d3SSascha Wildner sizeof(*get_resp));
2099*394324d3SSascha Wildner
2100*394324d3SSascha Wildner if (unlikely(ret))
2101*394324d3SSascha Wildner ena_trc_err("Failed to get stats. error: %d\n", ret);
2102*394324d3SSascha Wildner
2103*394324d3SSascha Wildner return ret;
2104*394324d3SSascha Wildner }
2105*394324d3SSascha Wildner
ena_com_get_dev_basic_stats(struct ena_com_dev * ena_dev,struct ena_admin_basic_stats * stats)2106*394324d3SSascha Wildner int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2107*394324d3SSascha Wildner struct ena_admin_basic_stats *stats)
2108*394324d3SSascha Wildner {
2109*394324d3SSascha Wildner struct ena_com_stats_ctx ctx;
2110*394324d3SSascha Wildner int ret;
2111*394324d3SSascha Wildner
2112*394324d3SSascha Wildner memset(&ctx, 0x0, sizeof(ctx));
2113*394324d3SSascha Wildner ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2114*394324d3SSascha Wildner if (likely(ret == 0))
2115*394324d3SSascha Wildner memcpy(stats, &ctx.get_resp.basic_stats,
2116*394324d3SSascha Wildner sizeof(ctx.get_resp.basic_stats));
2117*394324d3SSascha Wildner
2118*394324d3SSascha Wildner return ret;
2119*394324d3SSascha Wildner }
2120*394324d3SSascha Wildner #ifdef ENA_EXTENDED_STATS
2121*394324d3SSascha Wildner
ena_com_get_dev_extended_stats(struct ena_com_dev * ena_dev,char * buff,u32 len)2122*394324d3SSascha Wildner int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
2123*394324d3SSascha Wildner u32 len)
2124*394324d3SSascha Wildner {
2125*394324d3SSascha Wildner struct ena_com_stats_ctx ctx;
2126*394324d3SSascha Wildner struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx.get_cmd;
2127*394324d3SSascha Wildner ena_mem_handle_t mem_handle;
2128*394324d3SSascha Wildner void *virt_addr;
2129*394324d3SSascha Wildner dma_addr_t phys_addr;
2130*394324d3SSascha Wildner int ret;
2131*394324d3SSascha Wildner
2132*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, len,
2133*394324d3SSascha Wildner virt_addr, phys_addr, mem_handle);
2134*394324d3SSascha Wildner if (!virt_addr) {
2135*394324d3SSascha Wildner ret = ENA_COM_NO_MEM;
2136*394324d3SSascha Wildner goto done;
2137*394324d3SSascha Wildner }
2138*394324d3SSascha Wildner memset(&ctx, 0x0, sizeof(ctx));
2139*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
2140*394324d3SSascha Wildner &get_cmd->u.control_buffer.address,
2141*394324d3SSascha Wildner phys_addr);
2142*394324d3SSascha Wildner if (unlikely(ret)) {
2143*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
2144*394324d3SSascha Wildner return ret;
2145*394324d3SSascha Wildner }
2146*394324d3SSascha Wildner get_cmd->u.control_buffer.length = len;
2147*394324d3SSascha Wildner
2148*394324d3SSascha Wildner get_cmd->device_id = ena_dev->stats_func;
2149*394324d3SSascha Wildner get_cmd->queue_idx = ena_dev->stats_queue;
2150*394324d3SSascha Wildner
2151*394324d3SSascha Wildner ret = ena_get_dev_stats(ena_dev, &ctx,
2152*394324d3SSascha Wildner ENA_ADMIN_GET_STATS_TYPE_EXTENDED);
2153*394324d3SSascha Wildner if (ret < 0)
2154*394324d3SSascha Wildner goto free_ext_stats_mem;
2155*394324d3SSascha Wildner
2156*394324d3SSascha Wildner ret = snprintf(buff, len, "%s", (char *)virt_addr);
2157*394324d3SSascha Wildner
2158*394324d3SSascha Wildner free_ext_stats_mem:
2159*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev, len, virt_addr, phys_addr,
2160*394324d3SSascha Wildner mem_handle);
2161*394324d3SSascha Wildner done:
2162*394324d3SSascha Wildner return ret;
2163*394324d3SSascha Wildner }
2164*394324d3SSascha Wildner #endif
2165*394324d3SSascha Wildner
ena_com_set_dev_mtu(struct ena_com_dev * ena_dev,int mtu)2166*394324d3SSascha Wildner int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2167*394324d3SSascha Wildner {
2168*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue;
2169*394324d3SSascha Wildner struct ena_admin_set_feat_cmd cmd;
2170*394324d3SSascha Wildner struct ena_admin_set_feat_resp resp;
2171*394324d3SSascha Wildner int ret;
2172*394324d3SSascha Wildner
2173*394324d3SSascha Wildner if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2174*394324d3SSascha Wildner ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2175*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2176*394324d3SSascha Wildner }
2177*394324d3SSascha Wildner
2178*394324d3SSascha Wildner memset(&cmd, 0x0, sizeof(cmd));
2179*394324d3SSascha Wildner admin_queue = &ena_dev->admin_queue;
2180*394324d3SSascha Wildner
2181*394324d3SSascha Wildner cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2182*394324d3SSascha Wildner cmd.aq_common_descriptor.flags = 0;
2183*394324d3SSascha Wildner cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2184*394324d3SSascha Wildner cmd.u.mtu.mtu = mtu;
2185*394324d3SSascha Wildner
2186*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
2187*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&cmd,
2188*394324d3SSascha Wildner sizeof(cmd),
2189*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&resp,
2190*394324d3SSascha Wildner sizeof(resp));
2191*394324d3SSascha Wildner
2192*394324d3SSascha Wildner if (unlikely(ret))
2193*394324d3SSascha Wildner ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2194*394324d3SSascha Wildner
2195*394324d3SSascha Wildner return ret;
2196*394324d3SSascha Wildner }
2197*394324d3SSascha Wildner
ena_com_get_offload_settings(struct ena_com_dev * ena_dev,struct ena_admin_feature_offload_desc * offload)2198*394324d3SSascha Wildner int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2199*394324d3SSascha Wildner struct ena_admin_feature_offload_desc *offload)
2200*394324d3SSascha Wildner {
2201*394324d3SSascha Wildner int ret;
2202*394324d3SSascha Wildner struct ena_admin_get_feat_resp resp;
2203*394324d3SSascha Wildner
2204*394324d3SSascha Wildner ret = ena_com_get_feature(ena_dev, &resp,
2205*394324d3SSascha Wildner ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
2206*394324d3SSascha Wildner if (unlikely(ret)) {
2207*394324d3SSascha Wildner ena_trc_err("Failed to get offload capabilities %d\n", ret);
2208*394324d3SSascha Wildner return ret;
2209*394324d3SSascha Wildner }
2210*394324d3SSascha Wildner
2211*394324d3SSascha Wildner memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2212*394324d3SSascha Wildner
2213*394324d3SSascha Wildner return 0;
2214*394324d3SSascha Wildner }
2215*394324d3SSascha Wildner
ena_com_set_hash_function(struct ena_com_dev * ena_dev)2216*394324d3SSascha Wildner int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2217*394324d3SSascha Wildner {
2218*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2219*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2220*394324d3SSascha Wildner struct ena_admin_set_feat_cmd cmd;
2221*394324d3SSascha Wildner struct ena_admin_set_feat_resp resp;
2222*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
2223*394324d3SSascha Wildner int ret;
2224*394324d3SSascha Wildner
2225*394324d3SSascha Wildner if (!ena_com_check_supported_feature_id(ena_dev,
2226*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_FUNCTION)) {
2227*394324d3SSascha Wildner ena_trc_dbg("Feature %d isn't supported\n",
2228*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_FUNCTION);
2229*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2230*394324d3SSascha Wildner }
2231*394324d3SSascha Wildner
2232*394324d3SSascha Wildner /* Validate hash function is supported */
2233*394324d3SSascha Wildner ret = ena_com_get_feature(ena_dev, &get_resp,
2234*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_FUNCTION);
2235*394324d3SSascha Wildner if (unlikely(ret))
2236*394324d3SSascha Wildner return ret;
2237*394324d3SSascha Wildner
2238*394324d3SSascha Wildner if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {
2239*394324d3SSascha Wildner ena_trc_err("Func hash %d isn't supported by device, abort\n",
2240*394324d3SSascha Wildner rss->hash_func);
2241*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2242*394324d3SSascha Wildner }
2243*394324d3SSascha Wildner
2244*394324d3SSascha Wildner memset(&cmd, 0x0, sizeof(cmd));
2245*394324d3SSascha Wildner
2246*394324d3SSascha Wildner cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2247*394324d3SSascha Wildner cmd.aq_common_descriptor.flags =
2248*394324d3SSascha Wildner ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2249*394324d3SSascha Wildner cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2250*394324d3SSascha Wildner cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2251*394324d3SSascha Wildner cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2252*394324d3SSascha Wildner
2253*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
2254*394324d3SSascha Wildner &cmd.control_buffer.address,
2255*394324d3SSascha Wildner rss->hash_key_dma_addr);
2256*394324d3SSascha Wildner if (unlikely(ret)) {
2257*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
2258*394324d3SSascha Wildner return ret;
2259*394324d3SSascha Wildner }
2260*394324d3SSascha Wildner
2261*394324d3SSascha Wildner cmd.control_buffer.length = sizeof(*rss->hash_key);
2262*394324d3SSascha Wildner
2263*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
2264*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&cmd,
2265*394324d3SSascha Wildner sizeof(cmd),
2266*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&resp,
2267*394324d3SSascha Wildner sizeof(resp));
2268*394324d3SSascha Wildner if (unlikely(ret)) {
2269*394324d3SSascha Wildner ena_trc_err("Failed to set hash function %d. error: %d\n",
2270*394324d3SSascha Wildner rss->hash_func, ret);
2271*394324d3SSascha Wildner return ENA_COM_INVAL;
2272*394324d3SSascha Wildner }
2273*394324d3SSascha Wildner
2274*394324d3SSascha Wildner return 0;
2275*394324d3SSascha Wildner }
2276*394324d3SSascha Wildner
ena_com_fill_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions func,const u8 * key,u16 key_len,u32 init_val)2277*394324d3SSascha Wildner int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2278*394324d3SSascha Wildner enum ena_admin_hash_functions func,
2279*394324d3SSascha Wildner const u8 *key, u16 key_len, u32 init_val)
2280*394324d3SSascha Wildner {
2281*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2282*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
2283*394324d3SSascha Wildner struct ena_admin_feature_rss_flow_hash_control *hash_key =
2284*394324d3SSascha Wildner rss->hash_key;
2285*394324d3SSascha Wildner int rc;
2286*394324d3SSascha Wildner
2287*394324d3SSascha Wildner /* Make sure size is a mult of DWs */
2288*394324d3SSascha Wildner if (unlikely(key_len & 0x3))
2289*394324d3SSascha Wildner return ENA_COM_INVAL;
2290*394324d3SSascha Wildner
2291*394324d3SSascha Wildner rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2292*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_FUNCTION,
2293*394324d3SSascha Wildner rss->hash_key_dma_addr,
2294*394324d3SSascha Wildner sizeof(*rss->hash_key));
2295*394324d3SSascha Wildner if (unlikely(rc))
2296*394324d3SSascha Wildner return rc;
2297*394324d3SSascha Wildner
2298*394324d3SSascha Wildner if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2299*394324d3SSascha Wildner ena_trc_err("Flow hash function %d isn't supported\n", func);
2300*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2301*394324d3SSascha Wildner }
2302*394324d3SSascha Wildner
2303*394324d3SSascha Wildner switch (func) {
2304*394324d3SSascha Wildner case ENA_ADMIN_TOEPLITZ:
2305*394324d3SSascha Wildner if (key_len > sizeof(hash_key->key)) {
2306*394324d3SSascha Wildner ena_trc_err("key len (%hu) is bigger than the max supported (%zu)\n",
2307*394324d3SSascha Wildner key_len, sizeof(hash_key->key));
2308*394324d3SSascha Wildner return ENA_COM_INVAL;
2309*394324d3SSascha Wildner }
2310*394324d3SSascha Wildner
2311*394324d3SSascha Wildner memcpy(hash_key->key, key, key_len);
2312*394324d3SSascha Wildner rss->hash_init_val = init_val;
2313*394324d3SSascha Wildner hash_key->keys_num = key_len >> 2;
2314*394324d3SSascha Wildner break;
2315*394324d3SSascha Wildner case ENA_ADMIN_CRC32:
2316*394324d3SSascha Wildner rss->hash_init_val = init_val;
2317*394324d3SSascha Wildner break;
2318*394324d3SSascha Wildner default:
2319*394324d3SSascha Wildner ena_trc_err("Invalid hash function (%d)\n", func);
2320*394324d3SSascha Wildner return ENA_COM_INVAL;
2321*394324d3SSascha Wildner }
2322*394324d3SSascha Wildner
2323*394324d3SSascha Wildner rc = ena_com_set_hash_function(ena_dev);
2324*394324d3SSascha Wildner
2325*394324d3SSascha Wildner /* Restore the old function */
2326*394324d3SSascha Wildner if (unlikely(rc))
2327*394324d3SSascha Wildner ena_com_get_hash_function(ena_dev, NULL, NULL);
2328*394324d3SSascha Wildner
2329*394324d3SSascha Wildner return rc;
2330*394324d3SSascha Wildner }
2331*394324d3SSascha Wildner
ena_com_get_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions * func,u8 * key)2332*394324d3SSascha Wildner int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2333*394324d3SSascha Wildner enum ena_admin_hash_functions *func,
2334*394324d3SSascha Wildner u8 *key)
2335*394324d3SSascha Wildner {
2336*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2337*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
2338*394324d3SSascha Wildner struct ena_admin_feature_rss_flow_hash_control *hash_key =
2339*394324d3SSascha Wildner rss->hash_key;
2340*394324d3SSascha Wildner int rc;
2341*394324d3SSascha Wildner
2342*394324d3SSascha Wildner rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2343*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_FUNCTION,
2344*394324d3SSascha Wildner rss->hash_key_dma_addr,
2345*394324d3SSascha Wildner sizeof(*rss->hash_key));
2346*394324d3SSascha Wildner if (unlikely(rc))
2347*394324d3SSascha Wildner return rc;
2348*394324d3SSascha Wildner
2349*394324d3SSascha Wildner rss->hash_func = get_resp.u.flow_hash_func.selected_func;
2350*394324d3SSascha Wildner if (func)
2351*394324d3SSascha Wildner *func = rss->hash_func;
2352*394324d3SSascha Wildner
2353*394324d3SSascha Wildner if (key)
2354*394324d3SSascha Wildner memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2355*394324d3SSascha Wildner
2356*394324d3SSascha Wildner return 0;
2357*394324d3SSascha Wildner }
2358*394324d3SSascha Wildner
ena_com_get_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 * fields)2359*394324d3SSascha Wildner int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2360*394324d3SSascha Wildner enum ena_admin_flow_hash_proto proto,
2361*394324d3SSascha Wildner u16 *fields)
2362*394324d3SSascha Wildner {
2363*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2364*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
2365*394324d3SSascha Wildner int rc;
2366*394324d3SSascha Wildner
2367*394324d3SSascha Wildner rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2368*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_INPUT,
2369*394324d3SSascha Wildner rss->hash_ctrl_dma_addr,
2370*394324d3SSascha Wildner sizeof(*rss->hash_ctrl));
2371*394324d3SSascha Wildner if (unlikely(rc))
2372*394324d3SSascha Wildner return rc;
2373*394324d3SSascha Wildner
2374*394324d3SSascha Wildner if (fields)
2375*394324d3SSascha Wildner *fields = rss->hash_ctrl->selected_fields[proto].fields;
2376*394324d3SSascha Wildner
2377*394324d3SSascha Wildner return 0;
2378*394324d3SSascha Wildner }
2379*394324d3SSascha Wildner
ena_com_set_hash_ctrl(struct ena_com_dev * ena_dev)2380*394324d3SSascha Wildner int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2381*394324d3SSascha Wildner {
2382*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2383*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2384*394324d3SSascha Wildner struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2385*394324d3SSascha Wildner struct ena_admin_set_feat_cmd cmd;
2386*394324d3SSascha Wildner struct ena_admin_set_feat_resp resp;
2387*394324d3SSascha Wildner int ret;
2388*394324d3SSascha Wildner
2389*394324d3SSascha Wildner if (!ena_com_check_supported_feature_id(ena_dev,
2390*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_INPUT)) {
2391*394324d3SSascha Wildner ena_trc_dbg("Feature %d isn't supported\n",
2392*394324d3SSascha Wildner ENA_ADMIN_RSS_HASH_INPUT);
2393*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2394*394324d3SSascha Wildner }
2395*394324d3SSascha Wildner
2396*394324d3SSascha Wildner memset(&cmd, 0x0, sizeof(cmd));
2397*394324d3SSascha Wildner
2398*394324d3SSascha Wildner cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2399*394324d3SSascha Wildner cmd.aq_common_descriptor.flags =
2400*394324d3SSascha Wildner ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2401*394324d3SSascha Wildner cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2402*394324d3SSascha Wildner cmd.u.flow_hash_input.enabled_input_sort =
2403*394324d3SSascha Wildner ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2404*394324d3SSascha Wildner ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2405*394324d3SSascha Wildner
2406*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
2407*394324d3SSascha Wildner &cmd.control_buffer.address,
2408*394324d3SSascha Wildner rss->hash_ctrl_dma_addr);
2409*394324d3SSascha Wildner if (unlikely(ret)) {
2410*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
2411*394324d3SSascha Wildner return ret;
2412*394324d3SSascha Wildner }
2413*394324d3SSascha Wildner cmd.control_buffer.length = sizeof(*hash_ctrl);
2414*394324d3SSascha Wildner
2415*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
2416*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&cmd,
2417*394324d3SSascha Wildner sizeof(cmd),
2418*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&resp,
2419*394324d3SSascha Wildner sizeof(resp));
2420*394324d3SSascha Wildner if (unlikely(ret))
2421*394324d3SSascha Wildner ena_trc_err("Failed to set hash input. error: %d\n", ret);
2422*394324d3SSascha Wildner
2423*394324d3SSascha Wildner return ret;
2424*394324d3SSascha Wildner }
2425*394324d3SSascha Wildner
ena_com_set_default_hash_ctrl(struct ena_com_dev * ena_dev)2426*394324d3SSascha Wildner int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2427*394324d3SSascha Wildner {
2428*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2429*394324d3SSascha Wildner struct ena_admin_feature_rss_hash_control *hash_ctrl =
2430*394324d3SSascha Wildner rss->hash_ctrl;
2431*394324d3SSascha Wildner u16 available_fields = 0;
2432*394324d3SSascha Wildner int rc, i;
2433*394324d3SSascha Wildner
2434*394324d3SSascha Wildner /* Get the supported hash input */
2435*394324d3SSascha Wildner rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2436*394324d3SSascha Wildner if (unlikely(rc))
2437*394324d3SSascha Wildner return rc;
2438*394324d3SSascha Wildner
2439*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2440*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2441*394324d3SSascha Wildner ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2442*394324d3SSascha Wildner
2443*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2444*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2445*394324d3SSascha Wildner ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2446*394324d3SSascha Wildner
2447*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2448*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2449*394324d3SSascha Wildner ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2450*394324d3SSascha Wildner
2451*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2452*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2453*394324d3SSascha Wildner ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2454*394324d3SSascha Wildner
2455*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2456*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2457*394324d3SSascha Wildner
2458*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2459*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2460*394324d3SSascha Wildner
2461*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2462*394324d3SSascha Wildner ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2463*394324d3SSascha Wildner
2464*394324d3SSascha Wildner hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2465*394324d3SSascha Wildner ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2466*394324d3SSascha Wildner
2467*394324d3SSascha Wildner for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2468*394324d3SSascha Wildner available_fields = hash_ctrl->selected_fields[i].fields &
2469*394324d3SSascha Wildner hash_ctrl->supported_fields[i].fields;
2470*394324d3SSascha Wildner if (available_fields != hash_ctrl->selected_fields[i].fields) {
2471*394324d3SSascha Wildner ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2472*394324d3SSascha Wildner i, hash_ctrl->supported_fields[i].fields,
2473*394324d3SSascha Wildner hash_ctrl->selected_fields[i].fields);
2474*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2475*394324d3SSascha Wildner }
2476*394324d3SSascha Wildner }
2477*394324d3SSascha Wildner
2478*394324d3SSascha Wildner rc = ena_com_set_hash_ctrl(ena_dev);
2479*394324d3SSascha Wildner
2480*394324d3SSascha Wildner /* In case of failure, restore the old hash ctrl */
2481*394324d3SSascha Wildner if (unlikely(rc))
2482*394324d3SSascha Wildner ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2483*394324d3SSascha Wildner
2484*394324d3SSascha Wildner return rc;
2485*394324d3SSascha Wildner }
2486*394324d3SSascha Wildner
ena_com_fill_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 hash_fields)2487*394324d3SSascha Wildner int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2488*394324d3SSascha Wildner enum ena_admin_flow_hash_proto proto,
2489*394324d3SSascha Wildner u16 hash_fields)
2490*394324d3SSascha Wildner {
2491*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2492*394324d3SSascha Wildner struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2493*394324d3SSascha Wildner u16 supported_fields;
2494*394324d3SSascha Wildner int rc;
2495*394324d3SSascha Wildner
2496*394324d3SSascha Wildner if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2497*394324d3SSascha Wildner ena_trc_err("Invalid proto num (%u)\n", proto);
2498*394324d3SSascha Wildner return ENA_COM_INVAL;
2499*394324d3SSascha Wildner }
2500*394324d3SSascha Wildner
2501*394324d3SSascha Wildner /* Get the ctrl table */
2502*394324d3SSascha Wildner rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2503*394324d3SSascha Wildner if (unlikely(rc))
2504*394324d3SSascha Wildner return rc;
2505*394324d3SSascha Wildner
2506*394324d3SSascha Wildner /* Make sure all the fields are supported */
2507*394324d3SSascha Wildner supported_fields = hash_ctrl->supported_fields[proto].fields;
2508*394324d3SSascha Wildner if ((hash_fields & supported_fields) != hash_fields) {
2509*394324d3SSascha Wildner ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2510*394324d3SSascha Wildner proto, hash_fields, supported_fields);
2511*394324d3SSascha Wildner }
2512*394324d3SSascha Wildner
2513*394324d3SSascha Wildner hash_ctrl->selected_fields[proto].fields = hash_fields;
2514*394324d3SSascha Wildner
2515*394324d3SSascha Wildner rc = ena_com_set_hash_ctrl(ena_dev);
2516*394324d3SSascha Wildner
2517*394324d3SSascha Wildner /* In case of failure, restore the old hash ctrl */
2518*394324d3SSascha Wildner if (unlikely(rc))
2519*394324d3SSascha Wildner ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2520*394324d3SSascha Wildner
2521*394324d3SSascha Wildner return 0;
2522*394324d3SSascha Wildner }
2523*394324d3SSascha Wildner
ena_com_indirect_table_fill_entry(struct ena_com_dev * ena_dev,u16 entry_idx,u16 entry_value)2524*394324d3SSascha Wildner int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2525*394324d3SSascha Wildner u16 entry_idx, u16 entry_value)
2526*394324d3SSascha Wildner {
2527*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2528*394324d3SSascha Wildner
2529*394324d3SSascha Wildner if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2530*394324d3SSascha Wildner return ENA_COM_INVAL;
2531*394324d3SSascha Wildner
2532*394324d3SSascha Wildner if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2533*394324d3SSascha Wildner return ENA_COM_INVAL;
2534*394324d3SSascha Wildner
2535*394324d3SSascha Wildner rss->host_rss_ind_tbl[entry_idx] = entry_value;
2536*394324d3SSascha Wildner
2537*394324d3SSascha Wildner return 0;
2538*394324d3SSascha Wildner }
2539*394324d3SSascha Wildner
ena_com_indirect_table_set(struct ena_com_dev * ena_dev)2540*394324d3SSascha Wildner int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2541*394324d3SSascha Wildner {
2542*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2543*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2544*394324d3SSascha Wildner struct ena_admin_set_feat_cmd cmd;
2545*394324d3SSascha Wildner struct ena_admin_set_feat_resp resp;
2546*394324d3SSascha Wildner int ret;
2547*394324d3SSascha Wildner
2548*394324d3SSascha Wildner if (!ena_com_check_supported_feature_id(ena_dev,
2549*394324d3SSascha Wildner ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2550*394324d3SSascha Wildner ena_trc_dbg("Feature %d isn't supported\n",
2551*394324d3SSascha Wildner ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2552*394324d3SSascha Wildner return ENA_COM_UNSUPPORTED;
2553*394324d3SSascha Wildner }
2554*394324d3SSascha Wildner
2555*394324d3SSascha Wildner ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2556*394324d3SSascha Wildner if (ret) {
2557*394324d3SSascha Wildner ena_trc_err("Failed to convert host indirection table to device table\n");
2558*394324d3SSascha Wildner return ret;
2559*394324d3SSascha Wildner }
2560*394324d3SSascha Wildner
2561*394324d3SSascha Wildner memset(&cmd, 0x0, sizeof(cmd));
2562*394324d3SSascha Wildner
2563*394324d3SSascha Wildner cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2564*394324d3SSascha Wildner cmd.aq_common_descriptor.flags =
2565*394324d3SSascha Wildner ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2566*394324d3SSascha Wildner cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2567*394324d3SSascha Wildner cmd.u.ind_table.size = rss->tbl_log_size;
2568*394324d3SSascha Wildner cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2569*394324d3SSascha Wildner
2570*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
2571*394324d3SSascha Wildner &cmd.control_buffer.address,
2572*394324d3SSascha Wildner rss->rss_ind_tbl_dma_addr);
2573*394324d3SSascha Wildner if (unlikely(ret)) {
2574*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
2575*394324d3SSascha Wildner return ret;
2576*394324d3SSascha Wildner }
2577*394324d3SSascha Wildner
2578*394324d3SSascha Wildner cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2579*394324d3SSascha Wildner sizeof(struct ena_admin_rss_ind_table_entry);
2580*394324d3SSascha Wildner
2581*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
2582*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&cmd,
2583*394324d3SSascha Wildner sizeof(cmd),
2584*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&resp,
2585*394324d3SSascha Wildner sizeof(resp));
2586*394324d3SSascha Wildner
2587*394324d3SSascha Wildner if (unlikely(ret))
2588*394324d3SSascha Wildner ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2589*394324d3SSascha Wildner
2590*394324d3SSascha Wildner return ret;
2591*394324d3SSascha Wildner }
2592*394324d3SSascha Wildner
ena_com_indirect_table_get(struct ena_com_dev * ena_dev,u32 * ind_tbl)2593*394324d3SSascha Wildner int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2594*394324d3SSascha Wildner {
2595*394324d3SSascha Wildner struct ena_rss *rss = &ena_dev->rss;
2596*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
2597*394324d3SSascha Wildner u32 tbl_size;
2598*394324d3SSascha Wildner int i, rc;
2599*394324d3SSascha Wildner
2600*394324d3SSascha Wildner tbl_size = (1ULL << rss->tbl_log_size) *
2601*394324d3SSascha Wildner sizeof(struct ena_admin_rss_ind_table_entry);
2602*394324d3SSascha Wildner
2603*394324d3SSascha Wildner rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2604*394324d3SSascha Wildner ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2605*394324d3SSascha Wildner rss->rss_ind_tbl_dma_addr,
2606*394324d3SSascha Wildner tbl_size);
2607*394324d3SSascha Wildner if (unlikely(rc))
2608*394324d3SSascha Wildner return rc;
2609*394324d3SSascha Wildner
2610*394324d3SSascha Wildner if (!ind_tbl)
2611*394324d3SSascha Wildner return 0;
2612*394324d3SSascha Wildner
2613*394324d3SSascha Wildner rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2614*394324d3SSascha Wildner if (unlikely(rc))
2615*394324d3SSascha Wildner return rc;
2616*394324d3SSascha Wildner
2617*394324d3SSascha Wildner for (i = 0; i < (1 << rss->tbl_log_size); i++)
2618*394324d3SSascha Wildner ind_tbl[i] = rss->host_rss_ind_tbl[i];
2619*394324d3SSascha Wildner
2620*394324d3SSascha Wildner return 0;
2621*394324d3SSascha Wildner }
2622*394324d3SSascha Wildner
ena_com_rss_init(struct ena_com_dev * ena_dev,u16 indr_tbl_log_size)2623*394324d3SSascha Wildner int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2624*394324d3SSascha Wildner {
2625*394324d3SSascha Wildner int rc;
2626*394324d3SSascha Wildner
2627*394324d3SSascha Wildner memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2628*394324d3SSascha Wildner
2629*394324d3SSascha Wildner rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2630*394324d3SSascha Wildner if (unlikely(rc))
2631*394324d3SSascha Wildner goto err_indr_tbl;
2632*394324d3SSascha Wildner
2633*394324d3SSascha Wildner rc = ena_com_hash_key_allocate(ena_dev);
2634*394324d3SSascha Wildner if (unlikely(rc))
2635*394324d3SSascha Wildner goto err_hash_key;
2636*394324d3SSascha Wildner
2637*394324d3SSascha Wildner rc = ena_com_hash_ctrl_init(ena_dev);
2638*394324d3SSascha Wildner if (unlikely(rc))
2639*394324d3SSascha Wildner goto err_hash_ctrl;
2640*394324d3SSascha Wildner
2641*394324d3SSascha Wildner return 0;
2642*394324d3SSascha Wildner
2643*394324d3SSascha Wildner err_hash_ctrl:
2644*394324d3SSascha Wildner ena_com_hash_key_destroy(ena_dev);
2645*394324d3SSascha Wildner err_hash_key:
2646*394324d3SSascha Wildner ena_com_indirect_table_destroy(ena_dev);
2647*394324d3SSascha Wildner err_indr_tbl:
2648*394324d3SSascha Wildner
2649*394324d3SSascha Wildner return rc;
2650*394324d3SSascha Wildner }
2651*394324d3SSascha Wildner
ena_com_rss_destroy(struct ena_com_dev * ena_dev)2652*394324d3SSascha Wildner void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2653*394324d3SSascha Wildner {
2654*394324d3SSascha Wildner ena_com_indirect_table_destroy(ena_dev);
2655*394324d3SSascha Wildner ena_com_hash_key_destroy(ena_dev);
2656*394324d3SSascha Wildner ena_com_hash_ctrl_destroy(ena_dev);
2657*394324d3SSascha Wildner
2658*394324d3SSascha Wildner memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2659*394324d3SSascha Wildner }
2660*394324d3SSascha Wildner
ena_com_allocate_host_info(struct ena_com_dev * ena_dev)2661*394324d3SSascha Wildner int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2662*394324d3SSascha Wildner {
2663*394324d3SSascha Wildner struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2664*394324d3SSascha Wildner
2665*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2666*394324d3SSascha Wildner SZ_4K,
2667*394324d3SSascha Wildner host_attr->host_info,
2668*394324d3SSascha Wildner host_attr->host_info_dma_addr,
2669*394324d3SSascha Wildner host_attr->host_info_dma_handle);
2670*394324d3SSascha Wildner if (unlikely(!host_attr->host_info))
2671*394324d3SSascha Wildner return ENA_COM_NO_MEM;
2672*394324d3SSascha Wildner
2673*394324d3SSascha Wildner return 0;
2674*394324d3SSascha Wildner }
2675*394324d3SSascha Wildner
ena_com_allocate_debug_area(struct ena_com_dev * ena_dev,u32 debug_area_size)2676*394324d3SSascha Wildner int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2677*394324d3SSascha Wildner u32 debug_area_size)
2678*394324d3SSascha Wildner {
2679*394324d3SSascha Wildner struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2680*394324d3SSascha Wildner
2681*394324d3SSascha Wildner ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2682*394324d3SSascha Wildner debug_area_size,
2683*394324d3SSascha Wildner host_attr->debug_area_virt_addr,
2684*394324d3SSascha Wildner host_attr->debug_area_dma_addr,
2685*394324d3SSascha Wildner host_attr->debug_area_dma_handle);
2686*394324d3SSascha Wildner if (unlikely(!host_attr->debug_area_virt_addr)) {
2687*394324d3SSascha Wildner host_attr->debug_area_size = 0;
2688*394324d3SSascha Wildner return ENA_COM_NO_MEM;
2689*394324d3SSascha Wildner }
2690*394324d3SSascha Wildner
2691*394324d3SSascha Wildner host_attr->debug_area_size = debug_area_size;
2692*394324d3SSascha Wildner
2693*394324d3SSascha Wildner return 0;
2694*394324d3SSascha Wildner }
2695*394324d3SSascha Wildner
ena_com_delete_host_info(struct ena_com_dev * ena_dev)2696*394324d3SSascha Wildner void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2697*394324d3SSascha Wildner {
2698*394324d3SSascha Wildner struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2699*394324d3SSascha Wildner
2700*394324d3SSascha Wildner if (host_attr->host_info) {
2701*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2702*394324d3SSascha Wildner SZ_4K,
2703*394324d3SSascha Wildner host_attr->host_info,
2704*394324d3SSascha Wildner host_attr->host_info_dma_addr,
2705*394324d3SSascha Wildner host_attr->host_info_dma_handle);
2706*394324d3SSascha Wildner host_attr->host_info = NULL;
2707*394324d3SSascha Wildner }
2708*394324d3SSascha Wildner }
2709*394324d3SSascha Wildner
ena_com_delete_debug_area(struct ena_com_dev * ena_dev)2710*394324d3SSascha Wildner void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2711*394324d3SSascha Wildner {
2712*394324d3SSascha Wildner struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2713*394324d3SSascha Wildner
2714*394324d3SSascha Wildner if (host_attr->debug_area_virt_addr) {
2715*394324d3SSascha Wildner ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2716*394324d3SSascha Wildner host_attr->debug_area_size,
2717*394324d3SSascha Wildner host_attr->debug_area_virt_addr,
2718*394324d3SSascha Wildner host_attr->debug_area_dma_addr,
2719*394324d3SSascha Wildner host_attr->debug_area_dma_handle);
2720*394324d3SSascha Wildner host_attr->debug_area_virt_addr = NULL;
2721*394324d3SSascha Wildner }
2722*394324d3SSascha Wildner }
2723*394324d3SSascha Wildner
ena_com_set_host_attributes(struct ena_com_dev * ena_dev)2724*394324d3SSascha Wildner int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2725*394324d3SSascha Wildner {
2726*394324d3SSascha Wildner struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2727*394324d3SSascha Wildner struct ena_com_admin_queue *admin_queue;
2728*394324d3SSascha Wildner struct ena_admin_set_feat_cmd cmd;
2729*394324d3SSascha Wildner struct ena_admin_set_feat_resp resp;
2730*394324d3SSascha Wildner
2731*394324d3SSascha Wildner int ret;
2732*394324d3SSascha Wildner
2733*394324d3SSascha Wildner /* Host attribute config is called before ena_com_get_dev_attr_feat
2734*394324d3SSascha Wildner * so ena_com can't check if the feature is supported.
2735*394324d3SSascha Wildner */
2736*394324d3SSascha Wildner
2737*394324d3SSascha Wildner memset(&cmd, 0x0, sizeof(cmd));
2738*394324d3SSascha Wildner admin_queue = &ena_dev->admin_queue;
2739*394324d3SSascha Wildner
2740*394324d3SSascha Wildner cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2741*394324d3SSascha Wildner cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2742*394324d3SSascha Wildner
2743*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
2744*394324d3SSascha Wildner &cmd.u.host_attr.debug_ba,
2745*394324d3SSascha Wildner host_attr->debug_area_dma_addr);
2746*394324d3SSascha Wildner if (unlikely(ret)) {
2747*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
2748*394324d3SSascha Wildner return ret;
2749*394324d3SSascha Wildner }
2750*394324d3SSascha Wildner
2751*394324d3SSascha Wildner ret = ena_com_mem_addr_set(ena_dev,
2752*394324d3SSascha Wildner &cmd.u.host_attr.os_info_ba,
2753*394324d3SSascha Wildner host_attr->host_info_dma_addr);
2754*394324d3SSascha Wildner if (unlikely(ret)) {
2755*394324d3SSascha Wildner ena_trc_err("memory address set failed\n");
2756*394324d3SSascha Wildner return ret;
2757*394324d3SSascha Wildner }
2758*394324d3SSascha Wildner
2759*394324d3SSascha Wildner cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2760*394324d3SSascha Wildner
2761*394324d3SSascha Wildner ret = ena_com_execute_admin_command(admin_queue,
2762*394324d3SSascha Wildner (struct ena_admin_aq_entry *)&cmd,
2763*394324d3SSascha Wildner sizeof(cmd),
2764*394324d3SSascha Wildner (struct ena_admin_acq_entry *)&resp,
2765*394324d3SSascha Wildner sizeof(resp));
2766*394324d3SSascha Wildner
2767*394324d3SSascha Wildner if (unlikely(ret))
2768*394324d3SSascha Wildner ena_trc_err("Failed to set host attributes: %d\n", ret);
2769*394324d3SSascha Wildner
2770*394324d3SSascha Wildner return ret;
2771*394324d3SSascha Wildner }
2772*394324d3SSascha Wildner
2773*394324d3SSascha Wildner /* Interrupt moderation */
ena_com_interrupt_moderation_supported(struct ena_com_dev * ena_dev)2774*394324d3SSascha Wildner bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2775*394324d3SSascha Wildner {
2776*394324d3SSascha Wildner return ena_com_check_supported_feature_id(ena_dev,
2777*394324d3SSascha Wildner ENA_ADMIN_INTERRUPT_MODERATION);
2778*394324d3SSascha Wildner }
2779*394324d3SSascha Wildner
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev,u32 tx_coalesce_usecs)2780*394324d3SSascha Wildner int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2781*394324d3SSascha Wildner u32 tx_coalesce_usecs)
2782*394324d3SSascha Wildner {
2783*394324d3SSascha Wildner if (!ena_dev->intr_delay_resolution) {
2784*394324d3SSascha Wildner ena_trc_err("Illegal interrupt delay granularity value\n");
2785*394324d3SSascha Wildner return ENA_COM_FAULT;
2786*394324d3SSascha Wildner }
2787*394324d3SSascha Wildner
2788*394324d3SSascha Wildner ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2789*394324d3SSascha Wildner ena_dev->intr_delay_resolution;
2790*394324d3SSascha Wildner
2791*394324d3SSascha Wildner return 0;
2792*394324d3SSascha Wildner }
2793*394324d3SSascha Wildner
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev,u32 rx_coalesce_usecs)2794*394324d3SSascha Wildner int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2795*394324d3SSascha Wildner u32 rx_coalesce_usecs)
2796*394324d3SSascha Wildner {
2797*394324d3SSascha Wildner if (!ena_dev->intr_delay_resolution) {
2798*394324d3SSascha Wildner ena_trc_err("Illegal interrupt delay granularity value\n");
2799*394324d3SSascha Wildner return ENA_COM_FAULT;
2800*394324d3SSascha Wildner }
2801*394324d3SSascha Wildner
2802*394324d3SSascha Wildner /* We use LOWEST entry of moderation table for storing
2803*394324d3SSascha Wildner * nonadaptive interrupt coalescing values
2804*394324d3SSascha Wildner */
2805*394324d3SSascha Wildner ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2806*394324d3SSascha Wildner rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2807*394324d3SSascha Wildner
2808*394324d3SSascha Wildner return 0;
2809*394324d3SSascha Wildner }
2810*394324d3SSascha Wildner
ena_com_destroy_interrupt_moderation(struct ena_com_dev * ena_dev)2811*394324d3SSascha Wildner void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2812*394324d3SSascha Wildner {
2813*394324d3SSascha Wildner if (ena_dev->intr_moder_tbl)
2814*394324d3SSascha Wildner ENA_MEM_FREE(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2815*394324d3SSascha Wildner ena_dev->intr_moder_tbl = NULL;
2816*394324d3SSascha Wildner }
2817*394324d3SSascha Wildner
ena_com_init_interrupt_moderation(struct ena_com_dev * ena_dev)2818*394324d3SSascha Wildner int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2819*394324d3SSascha Wildner {
2820*394324d3SSascha Wildner struct ena_admin_get_feat_resp get_resp;
2821*394324d3SSascha Wildner u16 delay_resolution;
2822*394324d3SSascha Wildner int rc;
2823*394324d3SSascha Wildner
2824*394324d3SSascha Wildner rc = ena_com_get_feature(ena_dev, &get_resp,
2825*394324d3SSascha Wildner ENA_ADMIN_INTERRUPT_MODERATION);
2826*394324d3SSascha Wildner
2827*394324d3SSascha Wildner if (rc) {
2828*394324d3SSascha Wildner if (rc == ENA_COM_UNSUPPORTED) {
2829*394324d3SSascha Wildner ena_trc_dbg("Feature %d isn't supported\n",
2830*394324d3SSascha Wildner ENA_ADMIN_INTERRUPT_MODERATION);
2831*394324d3SSascha Wildner rc = 0;
2832*394324d3SSascha Wildner } else {
2833*394324d3SSascha Wildner ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2834*394324d3SSascha Wildner rc);
2835*394324d3SSascha Wildner }
2836*394324d3SSascha Wildner
2837*394324d3SSascha Wildner /* no moderation supported, disable adaptive support */
2838*394324d3SSascha Wildner ena_com_disable_adaptive_moderation(ena_dev);
2839*394324d3SSascha Wildner return rc;
2840*394324d3SSascha Wildner }
2841*394324d3SSascha Wildner
2842*394324d3SSascha Wildner rc = ena_com_init_interrupt_moderation_table(ena_dev);
2843*394324d3SSascha Wildner if (rc)
2844*394324d3SSascha Wildner goto err;
2845*394324d3SSascha Wildner
2846*394324d3SSascha Wildner /* if moderation is supported by device we set adaptive moderation */
2847*394324d3SSascha Wildner delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2848*394324d3SSascha Wildner ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2849*394324d3SSascha Wildner ena_com_enable_adaptive_moderation(ena_dev);
2850*394324d3SSascha Wildner
2851*394324d3SSascha Wildner return 0;
2852*394324d3SSascha Wildner err:
2853*394324d3SSascha Wildner ena_com_destroy_interrupt_moderation(ena_dev);
2854*394324d3SSascha Wildner return rc;
2855*394324d3SSascha Wildner }
2856*394324d3SSascha Wildner
ena_com_config_default_interrupt_moderation_table(struct ena_com_dev * ena_dev)2857*394324d3SSascha Wildner void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2858*394324d3SSascha Wildner {
2859*394324d3SSascha Wildner struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2860*394324d3SSascha Wildner
2861*394324d3SSascha Wildner if (!intr_moder_tbl)
2862*394324d3SSascha Wildner return;
2863*394324d3SSascha Wildner
2864*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2865*394324d3SSascha Wildner ENA_INTR_LOWEST_USECS;
2866*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2867*394324d3SSascha Wildner ENA_INTR_LOWEST_PKTS;
2868*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2869*394324d3SSascha Wildner ENA_INTR_LOWEST_BYTES;
2870*394324d3SSascha Wildner
2871*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2872*394324d3SSascha Wildner ENA_INTR_LOW_USECS;
2873*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2874*394324d3SSascha Wildner ENA_INTR_LOW_PKTS;
2875*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2876*394324d3SSascha Wildner ENA_INTR_LOW_BYTES;
2877*394324d3SSascha Wildner
2878*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2879*394324d3SSascha Wildner ENA_INTR_MID_USECS;
2880*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2881*394324d3SSascha Wildner ENA_INTR_MID_PKTS;
2882*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2883*394324d3SSascha Wildner ENA_INTR_MID_BYTES;
2884*394324d3SSascha Wildner
2885*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2886*394324d3SSascha Wildner ENA_INTR_HIGH_USECS;
2887*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2888*394324d3SSascha Wildner ENA_INTR_HIGH_PKTS;
2889*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2890*394324d3SSascha Wildner ENA_INTR_HIGH_BYTES;
2891*394324d3SSascha Wildner
2892*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2893*394324d3SSascha Wildner ENA_INTR_HIGHEST_USECS;
2894*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2895*394324d3SSascha Wildner ENA_INTR_HIGHEST_PKTS;
2896*394324d3SSascha Wildner intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2897*394324d3SSascha Wildner ENA_INTR_HIGHEST_BYTES;
2898*394324d3SSascha Wildner }
2899*394324d3SSascha Wildner
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev)2900*394324d3SSascha Wildner unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2901*394324d3SSascha Wildner {
2902*394324d3SSascha Wildner return ena_dev->intr_moder_tx_interval;
2903*394324d3SSascha Wildner }
2904*394324d3SSascha Wildner
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev)2905*394324d3SSascha Wildner unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2906*394324d3SSascha Wildner {
2907*394324d3SSascha Wildner struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2908*394324d3SSascha Wildner
2909*394324d3SSascha Wildner if (intr_moder_tbl)
2910*394324d3SSascha Wildner return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2911*394324d3SSascha Wildner
2912*394324d3SSascha Wildner return 0;
2913*394324d3SSascha Wildner }
2914*394324d3SSascha Wildner
ena_com_init_intr_moderation_entry(struct ena_com_dev * ena_dev,enum ena_intr_moder_level level,struct ena_intr_moder_entry * entry)2915*394324d3SSascha Wildner void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2916*394324d3SSascha Wildner enum ena_intr_moder_level level,
2917*394324d3SSascha Wildner struct ena_intr_moder_entry *entry)
2918*394324d3SSascha Wildner {
2919*394324d3SSascha Wildner struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2920*394324d3SSascha Wildner
2921*394324d3SSascha Wildner if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2922*394324d3SSascha Wildner return;
2923*394324d3SSascha Wildner
2924*394324d3SSascha Wildner intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2925*394324d3SSascha Wildner if (ena_dev->intr_delay_resolution)
2926*394324d3SSascha Wildner intr_moder_tbl[level].intr_moder_interval /=
2927*394324d3SSascha Wildner ena_dev->intr_delay_resolution;
2928*394324d3SSascha Wildner intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2929*394324d3SSascha Wildner
2930*394324d3SSascha Wildner /* use hardcoded value until ethtool supports bytecount parameter */
2931*394324d3SSascha Wildner if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
2932*394324d3SSascha Wildner intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2933*394324d3SSascha Wildner }
2934*394324d3SSascha Wildner
ena_com_get_intr_moderation_entry(struct ena_com_dev * ena_dev,enum ena_intr_moder_level level,struct ena_intr_moder_entry * entry)2935*394324d3SSascha Wildner void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2936*394324d3SSascha Wildner enum ena_intr_moder_level level,
2937*394324d3SSascha Wildner struct ena_intr_moder_entry *entry)
2938*394324d3SSascha Wildner {
2939*394324d3SSascha Wildner struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2940*394324d3SSascha Wildner
2941*394324d3SSascha Wildner if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2942*394324d3SSascha Wildner return;
2943*394324d3SSascha Wildner
2944*394324d3SSascha Wildner entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2945*394324d3SSascha Wildner if (ena_dev->intr_delay_resolution)
2946*394324d3SSascha Wildner entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2947*394324d3SSascha Wildner entry->pkts_per_interval =
2948*394324d3SSascha Wildner intr_moder_tbl[level].pkts_per_interval;
2949*394324d3SSascha Wildner entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2950*394324d3SSascha Wildner }
2951*394324d3SSascha Wildner
ena_com_config_dev_mode(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq)2952*394324d3SSascha Wildner int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2953*394324d3SSascha Wildner struct ena_admin_feature_llq_desc *llq)
2954*394324d3SSascha Wildner {
2955*394324d3SSascha Wildner int rc;
2956*394324d3SSascha Wildner int size;
2957*394324d3SSascha Wildner
2958*394324d3SSascha Wildner if (llq->max_llq_num == 0) {
2959*394324d3SSascha Wildner ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2960*394324d3SSascha Wildner return 0;
2961*394324d3SSascha Wildner }
2962*394324d3SSascha Wildner
2963*394324d3SSascha Wildner rc = ena_com_config_llq_info(ena_dev, llq);
2964*394324d3SSascha Wildner if (rc)
2965*394324d3SSascha Wildner return rc;
2966*394324d3SSascha Wildner
2967*394324d3SSascha Wildner /* Validate the descriptor is not too big */
2968*394324d3SSascha Wildner size = ena_dev->tx_max_header_size;
2969*394324d3SSascha Wildner size += ena_dev->llq_info.descs_num_before_header *
2970*394324d3SSascha Wildner sizeof(struct ena_eth_io_tx_desc);
2971*394324d3SSascha Wildner
2972*394324d3SSascha Wildner if (unlikely(ena_dev->llq_info.desc_list_entry_size < size)) {
2973*394324d3SSascha Wildner ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2974*394324d3SSascha Wildner return ENA_COM_INVAL;
2975*394324d3SSascha Wildner }
2976*394324d3SSascha Wildner
2977*394324d3SSascha Wildner ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2978*394324d3SSascha Wildner
2979*394324d3SSascha Wildner return 0;
2980*394324d3SSascha Wildner }
2981