1*394324d3SSascha Wildner /*-
2*394324d3SSascha Wildner * BSD LICENSE
3*394324d3SSascha Wildner *
4*394324d3SSascha Wildner * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5*394324d3SSascha Wildner * All rights reserved.
6*394324d3SSascha Wildner *
7*394324d3SSascha Wildner * Redistribution and use in source and binary forms, with or without
8*394324d3SSascha Wildner * modification, are permitted provided that the following conditions
9*394324d3SSascha Wildner * are met:
10*394324d3SSascha Wildner *
11*394324d3SSascha Wildner * * Redistributions of source code must retain the above copyright
12*394324d3SSascha Wildner * notice, this list of conditions and the following disclaimer.
13*394324d3SSascha Wildner * * Redistributions in binary form must reproduce the above copyright
14*394324d3SSascha Wildner * notice, this list of conditions and the following disclaimer in
15*394324d3SSascha Wildner * the documentation and/or other materials provided with the
16*394324d3SSascha Wildner * distribution.
17*394324d3SSascha Wildner * * Neither the name of copyright holder nor the names of its
18*394324d3SSascha Wildner * contributors may be used to endorse or promote products derived
19*394324d3SSascha Wildner * from this software without specific prior written permission.
20*394324d3SSascha Wildner *
21*394324d3SSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22*394324d3SSascha Wildner * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23*394324d3SSascha Wildner * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24*394324d3SSascha Wildner * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25*394324d3SSascha Wildner * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26*394324d3SSascha Wildner * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27*394324d3SSascha Wildner * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28*394324d3SSascha Wildner * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29*394324d3SSascha Wildner * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30*394324d3SSascha Wildner * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31*394324d3SSascha Wildner * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*394324d3SSascha Wildner */
33*394324d3SSascha Wildner
34*394324d3SSascha Wildner #include "ena_eth_com.h"
35*394324d3SSascha Wildner
ena_com_get_next_rx_cdesc(struct ena_com_io_cq * io_cq)36*394324d3SSascha Wildner static inline struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(
37*394324d3SSascha Wildner struct ena_com_io_cq *io_cq)
38*394324d3SSascha Wildner {
39*394324d3SSascha Wildner struct ena_eth_io_rx_cdesc_base *cdesc;
40*394324d3SSascha Wildner u16 expected_phase, head_masked;
41*394324d3SSascha Wildner u16 desc_phase;
42*394324d3SSascha Wildner
43*394324d3SSascha Wildner head_masked = io_cq->head & (io_cq->q_depth - 1);
44*394324d3SSascha Wildner expected_phase = io_cq->phase;
45*394324d3SSascha Wildner
46*394324d3SSascha Wildner cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr
47*394324d3SSascha Wildner + (head_masked * io_cq->cdesc_entry_size_in_bytes));
48*394324d3SSascha Wildner
49*394324d3SSascha Wildner desc_phase = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>
50*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
51*394324d3SSascha Wildner
52*394324d3SSascha Wildner if (desc_phase != expected_phase)
53*394324d3SSascha Wildner return NULL;
54*394324d3SSascha Wildner
55*394324d3SSascha Wildner return cdesc;
56*394324d3SSascha Wildner }
57*394324d3SSascha Wildner
ena_com_cq_inc_head(struct ena_com_io_cq * io_cq)58*394324d3SSascha Wildner static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)
59*394324d3SSascha Wildner {
60*394324d3SSascha Wildner io_cq->head++;
61*394324d3SSascha Wildner
62*394324d3SSascha Wildner /* Switch phase bit in case of wrap around */
63*394324d3SSascha Wildner if (unlikely((io_cq->head & (io_cq->q_depth - 1)) == 0))
64*394324d3SSascha Wildner io_cq->phase ^= 1;
65*394324d3SSascha Wildner }
66*394324d3SSascha Wildner
get_sq_desc_regular_queue(struct ena_com_io_sq * io_sq)67*394324d3SSascha Wildner static inline void *get_sq_desc_regular_queue(struct ena_com_io_sq *io_sq)
68*394324d3SSascha Wildner {
69*394324d3SSascha Wildner u16 tail_masked;
70*394324d3SSascha Wildner u32 offset;
71*394324d3SSascha Wildner
72*394324d3SSascha Wildner tail_masked = io_sq->tail & (io_sq->q_depth - 1);
73*394324d3SSascha Wildner
74*394324d3SSascha Wildner offset = tail_masked * io_sq->desc_entry_size;
75*394324d3SSascha Wildner
76*394324d3SSascha Wildner return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset);
77*394324d3SSascha Wildner }
78*394324d3SSascha Wildner
ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq * io_sq,u8 * bounce_buffer)79*394324d3SSascha Wildner static inline void ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,
80*394324d3SSascha Wildner u8 *bounce_buffer)
81*394324d3SSascha Wildner {
82*394324d3SSascha Wildner struct ena_com_llq_info *llq_info = &io_sq->llq_info;
83*394324d3SSascha Wildner
84*394324d3SSascha Wildner u16 dst_tail_mask;
85*394324d3SSascha Wildner u32 dst_offset;
86*394324d3SSascha Wildner
87*394324d3SSascha Wildner dst_tail_mask = io_sq->tail & (io_sq->q_depth - 1);
88*394324d3SSascha Wildner dst_offset = dst_tail_mask * llq_info->desc_list_entry_size;
89*394324d3SSascha Wildner
90*394324d3SSascha Wildner /* Make sure everything was written into the bounce buffer before
91*394324d3SSascha Wildner * writing the bounce buffer to the device
92*394324d3SSascha Wildner */
93*394324d3SSascha Wildner wmb();
94*394324d3SSascha Wildner
95*394324d3SSascha Wildner /* The line is completed. Copy it to dev */
96*394324d3SSascha Wildner ENA_MEMCPY_TO_DEVICE_64(io_sq->desc_addr.pbuf_dev_addr + dst_offset,
97*394324d3SSascha Wildner bounce_buffer,
98*394324d3SSascha Wildner llq_info->desc_list_entry_size);
99*394324d3SSascha Wildner
100*394324d3SSascha Wildner io_sq->tail++;
101*394324d3SSascha Wildner
102*394324d3SSascha Wildner /* Switch phase bit in case of wrap around */
103*394324d3SSascha Wildner if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
104*394324d3SSascha Wildner io_sq->phase ^= 1;
105*394324d3SSascha Wildner }
106*394324d3SSascha Wildner
ena_com_write_header_to_bounce(struct ena_com_io_sq * io_sq,u8 * header_src,u16 header_len)107*394324d3SSascha Wildner static inline int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq,
108*394324d3SSascha Wildner u8 *header_src,
109*394324d3SSascha Wildner u16 header_len)
110*394324d3SSascha Wildner {
111*394324d3SSascha Wildner struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
112*394324d3SSascha Wildner struct ena_com_llq_info *llq_info = &io_sq->llq_info;
113*394324d3SSascha Wildner u8 *bounce_buffer = pkt_ctrl->curr_bounce_buf;
114*394324d3SSascha Wildner u16 header_offset;
115*394324d3SSascha Wildner
116*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
117*394324d3SSascha Wildner return 0;
118*394324d3SSascha Wildner
119*394324d3SSascha Wildner header_offset =
120*394324d3SSascha Wildner llq_info->descs_num_before_header * io_sq->desc_entry_size;
121*394324d3SSascha Wildner
122*394324d3SSascha Wildner if (unlikely((header_offset + header_len) > llq_info->desc_list_entry_size)) {
123*394324d3SSascha Wildner ena_trc_err("trying to write header larger than llq entry can accommodate\n");
124*394324d3SSascha Wildner return ENA_COM_FAULT;
125*394324d3SSascha Wildner }
126*394324d3SSascha Wildner
127*394324d3SSascha Wildner if (unlikely(!bounce_buffer)) {
128*394324d3SSascha Wildner ena_trc_err("bounce buffer is NULL\n");
129*394324d3SSascha Wildner return ENA_COM_FAULT;
130*394324d3SSascha Wildner }
131*394324d3SSascha Wildner
132*394324d3SSascha Wildner memcpy(bounce_buffer + header_offset, header_src, header_len);
133*394324d3SSascha Wildner
134*394324d3SSascha Wildner return 0;
135*394324d3SSascha Wildner }
136*394324d3SSascha Wildner
get_sq_desc_llq(struct ena_com_io_sq * io_sq)137*394324d3SSascha Wildner static inline void *get_sq_desc_llq(struct ena_com_io_sq *io_sq)
138*394324d3SSascha Wildner {
139*394324d3SSascha Wildner struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
140*394324d3SSascha Wildner u8 *bounce_buffer;
141*394324d3SSascha Wildner void *sq_desc;
142*394324d3SSascha Wildner
143*394324d3SSascha Wildner bounce_buffer = pkt_ctrl->curr_bounce_buf;
144*394324d3SSascha Wildner
145*394324d3SSascha Wildner if (unlikely(!bounce_buffer)) {
146*394324d3SSascha Wildner ena_trc_err("bounce buffer is NULL\n");
147*394324d3SSascha Wildner return NULL;
148*394324d3SSascha Wildner }
149*394324d3SSascha Wildner
150*394324d3SSascha Wildner sq_desc = bounce_buffer + pkt_ctrl->idx * io_sq->desc_entry_size;
151*394324d3SSascha Wildner pkt_ctrl->idx++;
152*394324d3SSascha Wildner pkt_ctrl->descs_left_in_line--;
153*394324d3SSascha Wildner
154*394324d3SSascha Wildner return sq_desc;
155*394324d3SSascha Wildner }
156*394324d3SSascha Wildner
ena_com_close_bounce_buffer(struct ena_com_io_sq * io_sq)157*394324d3SSascha Wildner static inline void ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)
158*394324d3SSascha Wildner {
159*394324d3SSascha Wildner struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
160*394324d3SSascha Wildner struct ena_com_llq_info *llq_info = &io_sq->llq_info;
161*394324d3SSascha Wildner
162*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
163*394324d3SSascha Wildner return;
164*394324d3SSascha Wildner
165*394324d3SSascha Wildner /* bounce buffer was used, so write it and get a new one */
166*394324d3SSascha Wildner if (pkt_ctrl->idx) {
167*394324d3SSascha Wildner ena_com_write_bounce_buffer_to_dev(io_sq,
168*394324d3SSascha Wildner pkt_ctrl->curr_bounce_buf);
169*394324d3SSascha Wildner pkt_ctrl->curr_bounce_buf =
170*394324d3SSascha Wildner ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
171*394324d3SSascha Wildner memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
172*394324d3SSascha Wildner 0x0, llq_info->desc_list_entry_size);
173*394324d3SSascha Wildner }
174*394324d3SSascha Wildner
175*394324d3SSascha Wildner pkt_ctrl->idx = 0;
176*394324d3SSascha Wildner pkt_ctrl->descs_left_in_line = llq_info->descs_num_before_header;
177*394324d3SSascha Wildner }
178*394324d3SSascha Wildner
get_sq_desc(struct ena_com_io_sq * io_sq)179*394324d3SSascha Wildner static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
180*394324d3SSascha Wildner {
181*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
182*394324d3SSascha Wildner return get_sq_desc_llq(io_sq);
183*394324d3SSascha Wildner
184*394324d3SSascha Wildner return get_sq_desc_regular_queue(io_sq);
185*394324d3SSascha Wildner }
186*394324d3SSascha Wildner
ena_com_sq_update_llq_tail(struct ena_com_io_sq * io_sq)187*394324d3SSascha Wildner static inline void ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)
188*394324d3SSascha Wildner {
189*394324d3SSascha Wildner struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
190*394324d3SSascha Wildner struct ena_com_llq_info *llq_info = &io_sq->llq_info;
191*394324d3SSascha Wildner
192*394324d3SSascha Wildner if (!pkt_ctrl->descs_left_in_line) {
193*394324d3SSascha Wildner ena_com_write_bounce_buffer_to_dev(io_sq,
194*394324d3SSascha Wildner pkt_ctrl->curr_bounce_buf);
195*394324d3SSascha Wildner
196*394324d3SSascha Wildner pkt_ctrl->curr_bounce_buf =
197*394324d3SSascha Wildner ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
198*394324d3SSascha Wildner memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
199*394324d3SSascha Wildner 0x0, llq_info->desc_list_entry_size);
200*394324d3SSascha Wildner
201*394324d3SSascha Wildner pkt_ctrl->idx = 0;
202*394324d3SSascha Wildner if (llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY)
203*394324d3SSascha Wildner pkt_ctrl->descs_left_in_line = 1;
204*394324d3SSascha Wildner else
205*394324d3SSascha Wildner pkt_ctrl->descs_left_in_line =
206*394324d3SSascha Wildner llq_info->desc_list_entry_size / io_sq->desc_entry_size;
207*394324d3SSascha Wildner }
208*394324d3SSascha Wildner }
209*394324d3SSascha Wildner
ena_com_sq_update_tail(struct ena_com_io_sq * io_sq)210*394324d3SSascha Wildner static inline void ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)
211*394324d3SSascha Wildner {
212*394324d3SSascha Wildner
213*394324d3SSascha Wildner if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
214*394324d3SSascha Wildner ena_com_sq_update_llq_tail(io_sq);
215*394324d3SSascha Wildner return;
216*394324d3SSascha Wildner }
217*394324d3SSascha Wildner
218*394324d3SSascha Wildner io_sq->tail++;
219*394324d3SSascha Wildner
220*394324d3SSascha Wildner /* Switch phase bit in case of wrap around */
221*394324d3SSascha Wildner if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
222*394324d3SSascha Wildner io_sq->phase ^= 1;
223*394324d3SSascha Wildner }
224*394324d3SSascha Wildner
225*394324d3SSascha Wildner static inline struct ena_eth_io_rx_cdesc_base *
ena_com_rx_cdesc_idx_to_ptr(struct ena_com_io_cq * io_cq,u16 idx)226*394324d3SSascha Wildner ena_com_rx_cdesc_idx_to_ptr(struct ena_com_io_cq *io_cq, u16 idx)
227*394324d3SSascha Wildner {
228*394324d3SSascha Wildner idx &= (io_cq->q_depth - 1);
229*394324d3SSascha Wildner return (struct ena_eth_io_rx_cdesc_base *)
230*394324d3SSascha Wildner ((uintptr_t)io_cq->cdesc_addr.virt_addr +
231*394324d3SSascha Wildner idx * io_cq->cdesc_entry_size_in_bytes);
232*394324d3SSascha Wildner }
233*394324d3SSascha Wildner
ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq * io_cq,u16 * first_cdesc_idx)234*394324d3SSascha Wildner static inline u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
235*394324d3SSascha Wildner u16 *first_cdesc_idx)
236*394324d3SSascha Wildner {
237*394324d3SSascha Wildner struct ena_eth_io_rx_cdesc_base *cdesc;
238*394324d3SSascha Wildner u16 count = 0, head_masked;
239*394324d3SSascha Wildner u32 last = 0;
240*394324d3SSascha Wildner
241*394324d3SSascha Wildner do {
242*394324d3SSascha Wildner cdesc = ena_com_get_next_rx_cdesc(io_cq);
243*394324d3SSascha Wildner if (!cdesc)
244*394324d3SSascha Wildner break;
245*394324d3SSascha Wildner
246*394324d3SSascha Wildner ena_com_cq_inc_head(io_cq);
247*394324d3SSascha Wildner count++;
248*394324d3SSascha Wildner last = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>
249*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
250*394324d3SSascha Wildner } while (!last);
251*394324d3SSascha Wildner
252*394324d3SSascha Wildner if (last) {
253*394324d3SSascha Wildner *first_cdesc_idx = io_cq->cur_rx_pkt_cdesc_start_idx;
254*394324d3SSascha Wildner count += io_cq->cur_rx_pkt_cdesc_count;
255*394324d3SSascha Wildner
256*394324d3SSascha Wildner head_masked = io_cq->head & (io_cq->q_depth - 1);
257*394324d3SSascha Wildner
258*394324d3SSascha Wildner io_cq->cur_rx_pkt_cdesc_count = 0;
259*394324d3SSascha Wildner io_cq->cur_rx_pkt_cdesc_start_idx = head_masked;
260*394324d3SSascha Wildner
261*394324d3SSascha Wildner ena_trc_dbg("ena q_id: %d packets were completed. first desc idx %u descs# %d\n",
262*394324d3SSascha Wildner io_cq->qid, *first_cdesc_idx, count);
263*394324d3SSascha Wildner } else {
264*394324d3SSascha Wildner io_cq->cur_rx_pkt_cdesc_count += count;
265*394324d3SSascha Wildner count = 0;
266*394324d3SSascha Wildner }
267*394324d3SSascha Wildner
268*394324d3SSascha Wildner return count;
269*394324d3SSascha Wildner }
270*394324d3SSascha Wildner
ena_com_meta_desc_changed(struct ena_com_io_sq * io_sq,struct ena_com_tx_ctx * ena_tx_ctx)271*394324d3SSascha Wildner static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,
272*394324d3SSascha Wildner struct ena_com_tx_ctx *ena_tx_ctx)
273*394324d3SSascha Wildner {
274*394324d3SSascha Wildner int rc;
275*394324d3SSascha Wildner
276*394324d3SSascha Wildner if (ena_tx_ctx->meta_valid) {
277*394324d3SSascha Wildner rc = memcmp(&io_sq->cached_tx_meta,
278*394324d3SSascha Wildner &ena_tx_ctx->ena_meta,
279*394324d3SSascha Wildner sizeof(struct ena_com_tx_meta));
280*394324d3SSascha Wildner
281*394324d3SSascha Wildner if (unlikely(rc != 0))
282*394324d3SSascha Wildner return true;
283*394324d3SSascha Wildner }
284*394324d3SSascha Wildner
285*394324d3SSascha Wildner return false;
286*394324d3SSascha Wildner }
287*394324d3SSascha Wildner
ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq * io_sq,struct ena_com_tx_ctx * ena_tx_ctx)288*394324d3SSascha Wildner static inline void ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
289*394324d3SSascha Wildner struct ena_com_tx_ctx *ena_tx_ctx)
290*394324d3SSascha Wildner {
291*394324d3SSascha Wildner struct ena_eth_io_tx_meta_desc *meta_desc = NULL;
292*394324d3SSascha Wildner struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
293*394324d3SSascha Wildner
294*394324d3SSascha Wildner meta_desc = get_sq_desc(io_sq);
295*394324d3SSascha Wildner memset(meta_desc, 0x0, sizeof(struct ena_eth_io_tx_meta_desc));
296*394324d3SSascha Wildner
297*394324d3SSascha Wildner meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
298*394324d3SSascha Wildner
299*394324d3SSascha Wildner meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
300*394324d3SSascha Wildner
301*394324d3SSascha Wildner /* bits 0-9 of the mss */
302*394324d3SSascha Wildner meta_desc->word2 |= (ena_meta->mss <<
303*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) &
304*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
305*394324d3SSascha Wildner /* bits 10-13 of the mss */
306*394324d3SSascha Wildner meta_desc->len_ctrl |= ((ena_meta->mss >> 10) <<
307*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) &
308*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
309*394324d3SSascha Wildner
310*394324d3SSascha Wildner /* Extended meta desc */
311*394324d3SSascha Wildner meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
312*394324d3SSascha Wildner meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
313*394324d3SSascha Wildner meta_desc->len_ctrl |= (io_sq->phase <<
314*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) &
315*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
316*394324d3SSascha Wildner
317*394324d3SSascha Wildner meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
318*394324d3SSascha Wildner meta_desc->word2 |= ena_meta->l3_hdr_len &
319*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
320*394324d3SSascha Wildner meta_desc->word2 |= (ena_meta->l3_hdr_offset <<
321*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) &
322*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
323*394324d3SSascha Wildner
324*394324d3SSascha Wildner meta_desc->word2 |= (ena_meta->l4_hdr_len <<
325*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) &
326*394324d3SSascha Wildner ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
327*394324d3SSascha Wildner
328*394324d3SSascha Wildner meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
329*394324d3SSascha Wildner
330*394324d3SSascha Wildner /* Cached the meta desc */
331*394324d3SSascha Wildner memcpy(&io_sq->cached_tx_meta, ena_meta,
332*394324d3SSascha Wildner sizeof(struct ena_com_tx_meta));
333*394324d3SSascha Wildner
334*394324d3SSascha Wildner ena_com_sq_update_tail(io_sq);
335*394324d3SSascha Wildner }
336*394324d3SSascha Wildner
ena_com_rx_set_flags(struct ena_com_rx_ctx * ena_rx_ctx,struct ena_eth_io_rx_cdesc_base * cdesc)337*394324d3SSascha Wildner static inline void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
338*394324d3SSascha Wildner struct ena_eth_io_rx_cdesc_base *cdesc)
339*394324d3SSascha Wildner {
340*394324d3SSascha Wildner ena_rx_ctx->l3_proto = cdesc->status &
341*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
342*394324d3SSascha Wildner ena_rx_ctx->l4_proto =
343*394324d3SSascha Wildner (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>
344*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
345*394324d3SSascha Wildner ena_rx_ctx->l3_csum_err =
346*394324d3SSascha Wildner (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >>
347*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
348*394324d3SSascha Wildner ena_rx_ctx->l4_csum_err =
349*394324d3SSascha Wildner (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >>
350*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;
351*394324d3SSascha Wildner ena_rx_ctx->hash = cdesc->hash;
352*394324d3SSascha Wildner ena_rx_ctx->frag =
353*394324d3SSascha Wildner (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >>
354*394324d3SSascha Wildner ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
355*394324d3SSascha Wildner
356*394324d3SSascha Wildner ena_trc_dbg("ena_rx_ctx->l3_proto %d ena_rx_ctx->l4_proto %d\nena_rx_ctx->l3_csum_err %d ena_rx_ctx->l4_csum_err %d\nhash frag %d frag: %d cdesc_status: %x\n",
357*394324d3SSascha Wildner ena_rx_ctx->l3_proto,
358*394324d3SSascha Wildner ena_rx_ctx->l4_proto,
359*394324d3SSascha Wildner ena_rx_ctx->l3_csum_err,
360*394324d3SSascha Wildner ena_rx_ctx->l4_csum_err,
361*394324d3SSascha Wildner ena_rx_ctx->hash,
362*394324d3SSascha Wildner ena_rx_ctx->frag,
363*394324d3SSascha Wildner cdesc->status);
364*394324d3SSascha Wildner }
365*394324d3SSascha Wildner
366*394324d3SSascha Wildner /*****************************************************************************/
367*394324d3SSascha Wildner /***************************** API **********************************/
368*394324d3SSascha Wildner /*****************************************************************************/
369*394324d3SSascha Wildner
ena_com_prepare_tx(struct ena_com_io_sq * io_sq,struct ena_com_tx_ctx * ena_tx_ctx,int * nb_hw_desc)370*394324d3SSascha Wildner int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
371*394324d3SSascha Wildner struct ena_com_tx_ctx *ena_tx_ctx,
372*394324d3SSascha Wildner int *nb_hw_desc)
373*394324d3SSascha Wildner {
374*394324d3SSascha Wildner struct ena_eth_io_tx_desc *desc = NULL;
375*394324d3SSascha Wildner struct ena_com_buf *ena_bufs = ena_tx_ctx->ena_bufs;
376*394324d3SSascha Wildner void *buffer_to_push = ena_tx_ctx->push_header;
377*394324d3SSascha Wildner u16 header_len = ena_tx_ctx->header_len;
378*394324d3SSascha Wildner u16 num_bufs = ena_tx_ctx->num_bufs;
379*394324d3SSascha Wildner u16 start_tail = io_sq->tail;
380*394324d3SSascha Wildner int i, rc;
381*394324d3SSascha Wildner bool have_meta;
382*394324d3SSascha Wildner u64 addr_hi;
383*394324d3SSascha Wildner
384*394324d3SSascha Wildner ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX,
385*394324d3SSascha Wildner "wrong Q type");
386*394324d3SSascha Wildner
387*394324d3SSascha Wildner /* num_bufs +1 for potential meta desc */
388*394324d3SSascha Wildner if (!ena_com_sq_have_enough_space(io_sq, num_bufs + 1)) {
389*394324d3SSascha Wildner ena_trc_err("Not enough space in the tx queue\n");
390*394324d3SSascha Wildner return ENA_COM_NO_MEM;
391*394324d3SSascha Wildner }
392*394324d3SSascha Wildner
393*394324d3SSascha Wildner if (unlikely(header_len > io_sq->tx_max_header_size)) {
394*394324d3SSascha Wildner ena_trc_err("header size is too large %d max header: %d\n",
395*394324d3SSascha Wildner header_len, io_sq->tx_max_header_size);
396*394324d3SSascha Wildner return ENA_COM_INVAL;
397*394324d3SSascha Wildner }
398*394324d3SSascha Wildner
399*394324d3SSascha Wildner if (unlikely((io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) && !buffer_to_push))
400*394324d3SSascha Wildner return ENA_COM_INVAL;
401*394324d3SSascha Wildner
402*394324d3SSascha Wildner rc = ena_com_write_header_to_bounce(io_sq, buffer_to_push, header_len);
403*394324d3SSascha Wildner if (unlikely(rc))
404*394324d3SSascha Wildner return rc;
405*394324d3SSascha Wildner
406*394324d3SSascha Wildner have_meta = ena_tx_ctx->meta_valid && ena_com_meta_desc_changed(io_sq,
407*394324d3SSascha Wildner ena_tx_ctx);
408*394324d3SSascha Wildner if (have_meta)
409*394324d3SSascha Wildner ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx);
410*394324d3SSascha Wildner
411*394324d3SSascha Wildner /* If the caller doesn't want send packets */
412*394324d3SSascha Wildner if (unlikely(!num_bufs && !header_len)) {
413*394324d3SSascha Wildner ena_com_close_bounce_buffer(io_sq);
414*394324d3SSascha Wildner *nb_hw_desc = io_sq->tail - start_tail;
415*394324d3SSascha Wildner return 0;
416*394324d3SSascha Wildner }
417*394324d3SSascha Wildner
418*394324d3SSascha Wildner desc = get_sq_desc(io_sq);
419*394324d3SSascha Wildner if (unlikely(!desc))
420*394324d3SSascha Wildner return ENA_COM_FAULT;
421*394324d3SSascha Wildner memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
422*394324d3SSascha Wildner
423*394324d3SSascha Wildner /* Set first desc when we don't have meta descriptor */
424*394324d3SSascha Wildner if (!have_meta)
425*394324d3SSascha Wildner desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK;
426*394324d3SSascha Wildner
427*394324d3SSascha Wildner desc->buff_addr_hi_hdr_sz |= (header_len <<
428*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) &
429*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
430*394324d3SSascha Wildner desc->len_ctrl |= (io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
431*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_PHASE_MASK;
432*394324d3SSascha Wildner
433*394324d3SSascha Wildner desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
434*394324d3SSascha Wildner
435*394324d3SSascha Wildner /* Bits 0-9 */
436*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->req_id <<
437*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) &
438*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
439*394324d3SSascha Wildner
440*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->df <<
441*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_DF_SHIFT) &
442*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_DF_MASK;
443*394324d3SSascha Wildner
444*394324d3SSascha Wildner /* Bits 10-15 */
445*394324d3SSascha Wildner desc->len_ctrl |= ((ena_tx_ctx->req_id >> 10) <<
446*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) &
447*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
448*394324d3SSascha Wildner
449*394324d3SSascha Wildner if (ena_tx_ctx->meta_valid) {
450*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->tso_enable <<
451*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) &
452*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
453*394324d3SSascha Wildner desc->meta_ctrl |= ena_tx_ctx->l3_proto &
454*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
455*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->l4_proto <<
456*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) &
457*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
458*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->l3_csum_enable <<
459*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) &
460*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
461*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->l4_csum_enable <<
462*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) &
463*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
464*394324d3SSascha Wildner desc->meta_ctrl |= (ena_tx_ctx->l4_csum_partial <<
465*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) &
466*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
467*394324d3SSascha Wildner }
468*394324d3SSascha Wildner
469*394324d3SSascha Wildner for (i = 0; i < num_bufs; i++) {
470*394324d3SSascha Wildner /* The first desc share the same desc as the header */
471*394324d3SSascha Wildner if (likely(i != 0)) {
472*394324d3SSascha Wildner ena_com_sq_update_tail(io_sq);
473*394324d3SSascha Wildner
474*394324d3SSascha Wildner desc = get_sq_desc(io_sq);
475*394324d3SSascha Wildner if (unlikely(!desc))
476*394324d3SSascha Wildner return ENA_COM_FAULT;
477*394324d3SSascha Wildner
478*394324d3SSascha Wildner memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
479*394324d3SSascha Wildner
480*394324d3SSascha Wildner desc->len_ctrl |= (io_sq->phase <<
481*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
482*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_PHASE_MASK;
483*394324d3SSascha Wildner }
484*394324d3SSascha Wildner
485*394324d3SSascha Wildner desc->len_ctrl |= ena_bufs->len &
486*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_LENGTH_MASK;
487*394324d3SSascha Wildner
488*394324d3SSascha Wildner addr_hi = ((ena_bufs->paddr &
489*394324d3SSascha Wildner GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
490*394324d3SSascha Wildner
491*394324d3SSascha Wildner desc->buff_addr_lo = (u32)ena_bufs->paddr;
492*394324d3SSascha Wildner desc->buff_addr_hi_hdr_sz |= addr_hi &
493*394324d3SSascha Wildner ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
494*394324d3SSascha Wildner ena_bufs++;
495*394324d3SSascha Wildner }
496*394324d3SSascha Wildner
497*394324d3SSascha Wildner /* set the last desc indicator */
498*394324d3SSascha Wildner desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK;
499*394324d3SSascha Wildner
500*394324d3SSascha Wildner ena_com_sq_update_tail(io_sq);
501*394324d3SSascha Wildner
502*394324d3SSascha Wildner ena_com_close_bounce_buffer(io_sq);
503*394324d3SSascha Wildner
504*394324d3SSascha Wildner *nb_hw_desc = io_sq->tail - start_tail;
505*394324d3SSascha Wildner return 0;
506*394324d3SSascha Wildner }
507*394324d3SSascha Wildner
ena_com_rx_pkt(struct ena_com_io_cq * io_cq,struct ena_com_io_sq * io_sq,struct ena_com_rx_ctx * ena_rx_ctx)508*394324d3SSascha Wildner int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
509*394324d3SSascha Wildner struct ena_com_io_sq *io_sq,
510*394324d3SSascha Wildner struct ena_com_rx_ctx *ena_rx_ctx)
511*394324d3SSascha Wildner {
512*394324d3SSascha Wildner struct ena_com_rx_buf_info *ena_buf = &ena_rx_ctx->ena_bufs[0];
513*394324d3SSascha Wildner struct ena_eth_io_rx_cdesc_base *cdesc = NULL;
514*394324d3SSascha Wildner u16 cdesc_idx = 0;
515*394324d3SSascha Wildner u16 nb_hw_desc;
516*394324d3SSascha Wildner u16 i;
517*394324d3SSascha Wildner
518*394324d3SSascha Wildner ENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
519*394324d3SSascha Wildner "wrong Q type");
520*394324d3SSascha Wildner
521*394324d3SSascha Wildner nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);
522*394324d3SSascha Wildner if (nb_hw_desc == 0) {
523*394324d3SSascha Wildner ena_rx_ctx->descs = nb_hw_desc;
524*394324d3SSascha Wildner return 0;
525*394324d3SSascha Wildner }
526*394324d3SSascha Wildner
527*394324d3SSascha Wildner ena_trc_dbg("fetch rx packet: queue %d completed desc: %d\n",
528*394324d3SSascha Wildner io_cq->qid, nb_hw_desc);
529*394324d3SSascha Wildner
530*394324d3SSascha Wildner if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) {
531*394324d3SSascha Wildner ena_trc_err("Too many RX cdescs (%d) > MAX(%d)\n",
532*394324d3SSascha Wildner nb_hw_desc, ena_rx_ctx->max_bufs);
533*394324d3SSascha Wildner return ENA_COM_NO_SPACE;
534*394324d3SSascha Wildner }
535*394324d3SSascha Wildner
536*394324d3SSascha Wildner for (i = 0; i < nb_hw_desc; i++) {
537*394324d3SSascha Wildner cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);
538*394324d3SSascha Wildner
539*394324d3SSascha Wildner ena_buf->len = cdesc->length;
540*394324d3SSascha Wildner ena_buf->req_id = cdesc->req_id;
541*394324d3SSascha Wildner ena_buf++;
542*394324d3SSascha Wildner }
543*394324d3SSascha Wildner
544*394324d3SSascha Wildner /* Update SQ head ptr */
545*394324d3SSascha Wildner io_sq->next_to_comp += nb_hw_desc;
546*394324d3SSascha Wildner
547*394324d3SSascha Wildner ena_trc_dbg("[%s][QID#%d] Updating SQ head to: %d\n", __func__,
548*394324d3SSascha Wildner io_sq->qid, io_sq->next_to_comp);
549*394324d3SSascha Wildner
550*394324d3SSascha Wildner /* Get rx flags from the last pkt */
551*394324d3SSascha Wildner ena_com_rx_set_flags(ena_rx_ctx, cdesc);
552*394324d3SSascha Wildner
553*394324d3SSascha Wildner ena_rx_ctx->descs = nb_hw_desc;
554*394324d3SSascha Wildner return 0;
555*394324d3SSascha Wildner }
556*394324d3SSascha Wildner
ena_com_add_single_rx_desc(struct ena_com_io_sq * io_sq,struct ena_com_buf * ena_buf,u16 req_id)557*394324d3SSascha Wildner int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
558*394324d3SSascha Wildner struct ena_com_buf *ena_buf,
559*394324d3SSascha Wildner u16 req_id)
560*394324d3SSascha Wildner {
561*394324d3SSascha Wildner struct ena_eth_io_rx_desc *desc;
562*394324d3SSascha Wildner
563*394324d3SSascha Wildner ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
564*394324d3SSascha Wildner "wrong Q type");
565*394324d3SSascha Wildner
566*394324d3SSascha Wildner if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1)))
567*394324d3SSascha Wildner return ENA_COM_NO_SPACE;
568*394324d3SSascha Wildner
569*394324d3SSascha Wildner desc = get_sq_desc(io_sq);
570*394324d3SSascha Wildner if (unlikely(!desc))
571*394324d3SSascha Wildner return ENA_COM_FAULT;
572*394324d3SSascha Wildner
573*394324d3SSascha Wildner memset(desc, 0x0, sizeof(struct ena_eth_io_rx_desc));
574*394324d3SSascha Wildner
575*394324d3SSascha Wildner desc->length = ena_buf->len;
576*394324d3SSascha Wildner
577*394324d3SSascha Wildner desc->ctrl |= ENA_ETH_IO_RX_DESC_FIRST_MASK;
578*394324d3SSascha Wildner desc->ctrl |= ENA_ETH_IO_RX_DESC_LAST_MASK;
579*394324d3SSascha Wildner desc->ctrl |= io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK;
580*394324d3SSascha Wildner desc->ctrl |= ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
581*394324d3SSascha Wildner
582*394324d3SSascha Wildner desc->req_id = req_id;
583*394324d3SSascha Wildner
584*394324d3SSascha Wildner desc->buff_addr_lo = (u32)ena_buf->paddr;
585*394324d3SSascha Wildner desc->buff_addr_hi =
586*394324d3SSascha Wildner ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
587*394324d3SSascha Wildner
588*394324d3SSascha Wildner ena_com_sq_update_tail(io_sq);
589*394324d3SSascha Wildner
590*394324d3SSascha Wildner return 0;
591*394324d3SSascha Wildner }
592*394324d3SSascha Wildner
ena_com_tx_comp_req_id_get(struct ena_com_io_cq * io_cq,u16 * req_id)593*394324d3SSascha Wildner int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id)
594*394324d3SSascha Wildner {
595*394324d3SSascha Wildner u8 expected_phase, cdesc_phase;
596*394324d3SSascha Wildner struct ena_eth_io_tx_cdesc *cdesc;
597*394324d3SSascha Wildner u16 masked_head;
598*394324d3SSascha Wildner
599*394324d3SSascha Wildner masked_head = io_cq->head & (io_cq->q_depth - 1);
600*394324d3SSascha Wildner expected_phase = io_cq->phase;
601*394324d3SSascha Wildner
602*394324d3SSascha Wildner cdesc = (struct ena_eth_io_tx_cdesc *)
603*394324d3SSascha Wildner ((uintptr_t)io_cq->cdesc_addr.virt_addr +
604*394324d3SSascha Wildner (masked_head * io_cq->cdesc_entry_size_in_bytes));
605*394324d3SSascha Wildner
606*394324d3SSascha Wildner /* When the current completion descriptor phase isn't the same as the
607*394324d3SSascha Wildner * expected, it mean that the device still didn't update
608*394324d3SSascha Wildner * this completion.
609*394324d3SSascha Wildner */
610*394324d3SSascha Wildner cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
611*394324d3SSascha Wildner if (cdesc_phase != expected_phase)
612*394324d3SSascha Wildner return ENA_COM_TRY_AGAIN;
613*394324d3SSascha Wildner
614*394324d3SSascha Wildner if (unlikely(cdesc->req_id >= io_cq->q_depth)) {
615*394324d3SSascha Wildner ena_trc_err("Invalid req id %d\n", cdesc->req_id);
616*394324d3SSascha Wildner return ENA_COM_INVAL;
617*394324d3SSascha Wildner }
618*394324d3SSascha Wildner
619*394324d3SSascha Wildner ena_com_cq_inc_head(io_cq);
620*394324d3SSascha Wildner
621*394324d3SSascha Wildner *req_id = READ_ONCE(cdesc->req_id);
622*394324d3SSascha Wildner
623*394324d3SSascha Wildner return 0;
624*394324d3SSascha Wildner }
625