1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/contrib/ena-com/ena_plat.h 325589 2017-11-09 13:30:39Z mw $ 34 */ 35 36 #ifndef ENA_PLAT_H_ 37 #define ENA_PLAT_H_ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 42 #include <sys/bus.h> 43 #include <sys/condvar.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/module.h> 50 #include <sys/rman.h> 51 #include <sys/proc.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/spinlock.h> 55 #include <sys/spinlock2.h> 56 #include <sys/sysctl.h> 57 #include <sys/taskqueue.h> 58 #include <sys/eventhandler.h> 59 #include <sys/types.h> 60 #include <sys/cdefs.h> 61 62 #include <machine/atomic.h> 63 64 #include <net/bpf.h> 65 #include <net/ethernet.h> 66 #include <net/if.h> 67 #include <net/if_var.h> 68 #include <net/if_arp.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 72 #include <net/if_types.h> 73 74 #include <netinet/in_systm.h> 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #include <netinet/ip.h> 78 #include <netinet/ip6.h> 79 #include <netinet/tcp.h> 80 #include <netinet/udp.h> 81 82 #include <dev/misc/led/led.h> 83 #include <bus/pci/pcivar.h> 84 #include <bus/pci/pcireg.h> 85 86 extern struct ena_bus_space ebs; 87 88 /* Levels */ 89 #define ENA_ALERT (1 << 0) /* Alerts are providing more error info. */ 90 #define ENA_WARNING (1 << 1) /* Driver output is more error sensitive. */ 91 #define ENA_INFO (1 << 2) /* Provides additional driver info. */ 92 #define ENA_DBG (1 << 3) /* Driver output for debugging. */ 93 /* Detailed info that will be printed with ENA_INFO or ENA_DEBUG flag. */ 94 #define ENA_TXPTH (1 << 4) /* Allows TX path tracing. */ 95 #define ENA_RXPTH (1 << 5) /* Allows RX path tracing. */ 96 #define ENA_RSC (1 << 6) /* Goes with TXPTH or RXPTH, free/alloc res. */ 97 #define ENA_IOQ (1 << 7) /* Detailed info about IO queues. */ 98 #define ENA_ADMQ (1 << 8) /* Detailed info about admin queue. */ 99 100 extern int ena_log_level; 101 102 #define ena_trace_raw(level, fmt, args...) \ 103 do { \ 104 if (((level) & ena_log_level) != (level)) \ 105 break; \ 106 kprintf(fmt, ##args); \ 107 } while (0) 108 109 #define ena_trace(level, fmt, args...) \ 110 ena_trace_raw(level, "%s() [TID:%p]: " \ 111 fmt " \n", __func__, curthread, ##args) 112 113 114 #define ena_trc_dbg(format, arg...) ena_trace(ENA_DBG, format, ##arg) 115 #define ena_trc_info(format, arg...) ena_trace(ENA_INFO, format, ##arg) 116 #define ena_trc_warn(format, arg...) ena_trace(ENA_WARNING, format, ##arg) 117 #define ena_trc_err(format, arg...) ena_trace(ENA_ALERT, format, ##arg) 118 119 #define unlikely(x) __predict_false(x) 120 #define likely(x) __predict_true(x) 121 122 #define __iomem 123 #define ____cacheline_aligned __cachealign 124 125 #define MAX_ERRNO 4095 126 #define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO) 127 128 #define ENA_ASSERT(cond, format, arg...) \ 129 do { \ 130 if (unlikely(!(cond))) { \ 131 ena_trc_err( \ 132 "Assert failed on %s:%s:%d:" format, \ 133 __FILE__, __func__, __LINE__, ##arg); \ 134 } \ 135 } while (0) 136 137 #define ENA_WARN(cond, format, arg...) \ 138 do { \ 139 if (unlikely((cond))) { \ 140 ena_trc_warn(format, ##arg); \ 141 } \ 142 } while (0) 143 144 static inline long IS_ERR(const void *ptr) 145 { 146 return IS_ERR_VALUE((unsigned long)ptr); 147 } 148 149 static inline void *ERR_PTR(long error) 150 { 151 return (void *)error; 152 } 153 154 static inline long PTR_ERR(const void *ptr) 155 { 156 return (long) ptr; 157 } 158 159 #define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l)) 160 #define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) 161 #define BIT(x) (1 << (x)) 162 163 #define ENA_ABORT() BUG() 164 #define BUG() panic("ENA BUG") 165 166 #define SZ_256 (256) 167 #define SZ_4K (4096) 168 169 #define ENA_COM_OK 0 170 #define ENA_COM_FAULT EFAULT 171 #define ENA_COM_INVAL EINVAL 172 #define ENA_COM_NO_MEM ENOMEM 173 #define ENA_COM_NO_SPACE ENOSPC 174 #define ENA_COM_TRY_AGAIN -1 175 #define ENA_COM_UNSUPPORTED EOPNOTSUPP 176 #define ENA_COM_NO_DEVICE ENODEV 177 #define ENA_COM_PERMISSION EPERM 178 #define ENA_COM_TIMER_EXPIRED ETIMEDOUT 179 180 #define cputick2usec(t) (1000000*(t) / hz) 181 #define ENA_MSLEEP(x) do { \ 182 int dummy; \ 183 int wait_ticks = 1; \ 184 \ 185 tsleep(&dummy, 0, "ena", wait_ticks); \ 186 } while (0) 187 #define ENA_UDELAY(x) DELAY(x) 188 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ 189 ((long)cputick2usec(ticks) + (timeout_us)) 190 #define ENA_TIME_EXPIRE(timeout) ((timeout) < (long)cputick2usec(ticks)) 191 #define ENA_MIGHT_SLEEP() 192 193 #define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y)) 194 #define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y)) 195 196 #define ENA_MIN32(x,y) MIN(x, y) 197 #define ENA_MIN16(x,y) MIN(x, y) 198 #define ENA_MIN8(x,y) MIN(x, y) 199 200 #define ENA_MAX32(x,y) MAX(x, y) 201 #define ENA_MAX16(x,y) MAX(x, y) 202 #define ENA_MAX8(x,y) MAX(x, y) 203 204 /* Spinlock related methods */ 205 #define ena_spinlock_t struct spinlock 206 #define ENA_SPINLOCK_INIT(spinlock) \ 207 spin_init(&(spinlock), "ena_spin") 208 #define ENA_SPINLOCK_DESTROY(spinlock) \ 209 do { \ 210 spin_uninit(&(spinlock)); \ 211 } while (0) 212 #define ENA_SPINLOCK_LOCK(spinlock, flags) \ 213 do { \ 214 (void)(flags); \ 215 spin_lock(&(spinlock)); \ 216 } while (0) 217 #define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ 218 do { \ 219 (void)(flags); \ 220 spin_unlock(&(spinlock)); \ 221 } while (0) 222 223 224 /* Wait queue related methods */ 225 #define ena_wait_event_t struct { struct cv wq; struct lock lock; } 226 #define ENA_WAIT_EVENT_INIT(waitqueue) \ 227 do { \ 228 cv_init(&((waitqueue).wq), "cv"); \ 229 lockinit(&((waitqueue).lock), "wq", 0, LK_CANRECURSE); \ 230 } while (0) 231 #define ENA_WAIT_EVENT_DESTROY(waitqueue) \ 232 do { \ 233 cv_destroy(&((waitqueue).wq)); \ 234 lockuninit(&((waitqueue).lock)); \ 235 } while (0) 236 #define ENA_WAIT_EVENT_CLEAR(waitqueue) \ 237 cv_init(&((waitqueue).wq), (waitqueue).wq.cv_desc) 238 #define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us) \ 239 do { \ 240 lockmgr(&((waitqueue).lock), LK_EXCLUSIVE); \ 241 cv_timedwait(&((waitqueue).wq), &((waitqueue).lock), \ 242 timeout_us * hz / 1000 / 1000 ); \ 243 lockmgr(&((waitqueue).lock), LK_RELEASE); \ 244 } while (0) 245 #define ENA_WAIT_EVENT_SIGNAL(waitqueue) cv_broadcast(&((waitqueue).wq)) 246 247 #define dma_addr_t bus_addr_t 248 #define u8 uint8_t 249 #define u16 uint16_t 250 #define u32 uint32_t 251 #define u64 uint64_t 252 253 #ifdef __x86_64__ 254 #define mb() __asm volatile("mfence" ::: "memory") 255 #define wmb() __asm volatile("sfence" ::: "memory") 256 #define rmb() __asm volatile("lfence" ::: "memory") 257 #else 258 #define mb() 259 #define rmb() 260 #define wmb() 261 #endif 262 263 typedef struct { 264 bus_addr_t paddr; 265 caddr_t vaddr; 266 bus_dma_tag_t tag; 267 bus_dmamap_t map; 268 bus_dma_segment_t seg; 269 int nseg; 270 } ena_mem_handle_t; 271 272 struct ena_bus { 273 bus_space_handle_t reg_bar_h; 274 bus_space_tag_t reg_bar_t; 275 bus_space_handle_t mem_bar_h; 276 bus_space_tag_t mem_bar_t; 277 }; 278 279 typedef uint32_t ena_atomic32_t; 280 281 void ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg, 282 int error); 283 int ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma, 284 int mapflags); 285 286 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ 287 do { \ 288 int count, i; \ 289 volatile uint64_t *to = (volatile uint64_t *)(dst); \ 290 const uint64_t *from = (const uint64_t *)(src); \ 291 count = (size) / 8; \ 292 \ 293 for (i = 0; i < count; i++, from++, to++) \ 294 *to = *from; \ 295 } while (0) 296 297 #define ENA_MEM_ALLOC(dmadev, size) kmalloc(size, M_DEVBUF, M_NOWAIT | M_ZERO) 298 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL) 299 #define ENA_MEM_FREE(dmadev, ptr) kfree(ptr, M_DEVBUF) 300 #define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, node, \ 301 dev_node) \ 302 do { \ 303 ((virt) = NULL); \ 304 (void)(dev_node); \ 305 } while (0) 306 307 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma) \ 308 do { \ 309 ena_dma_alloc((dmadev), (size), &(dma), 0); \ 310 (virt) = (void *)(dma).vaddr; \ 311 (phys) = (dma).paddr; \ 312 } while (0) 313 314 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma) \ 315 do { \ 316 (void)size; \ 317 bus_dmamap_unload((dma).tag, (dma).map); \ 318 bus_dmamem_free((dma).tag, (virt), (dma).map); \ 319 bus_dma_tag_destroy((dma).tag); \ 320 (dma).tag = NULL; \ 321 (virt) = NULL; \ 322 } while (0) 323 324 /* Register R/W methods */ 325 #define ENA_REG_WRITE32(bus, value, offset) \ 326 bus_space_write_4( \ 327 ((struct ena_bus*)bus)->reg_bar_t, \ 328 ((struct ena_bus*)bus)->reg_bar_h, \ 329 (bus_size_t)(offset), (value)) 330 331 #define ENA_REG_READ32(bus, offset) \ 332 bus_space_read_4( \ 333 ((struct ena_bus*)bus)->reg_bar_t, \ 334 ((struct ena_bus*)bus)->reg_bar_h, \ 335 (bus_size_t)(offset)) 336 337 #define ENA_DB_SYNC(mem_handle) bus_dmamap_sync((mem_handle)->tag, \ 338 (mem_handle)->map, BUS_DMASYNC_PREREAD) 339 340 #define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0) 341 342 #define VLAN_HLEN sizeof(struct ether_vlan_header) 343 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 344 345 #if defined(__i386__) || defined(__amd64__) 346 static __inline 347 void prefetch(void *x) 348 { 349 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 350 } 351 #else 352 #define prefetch(x) 353 #endif 354 355 /* DMA buffers access */ 356 #define dma_unmap_addr(p, name) ((p)->dma->name) 357 #define dma_unmap_addr_set(p, name, v) (((p)->dma->name) = (v)) 358 #define dma_unmap_len(p, name) ((p)->name) 359 #define dma_unmap_len_set(p, name, v) (((p)->name) = (v)) 360 361 #define memcpy_toio memcpy 362 363 #define ATOMIC32_INC(I32_PTR) atomic_add_int(I32_PTR, 1) 364 #define ATOMIC32_DEC(I32_PTR) atomic_add_int(I32_PTR, -1) 365 #define ATOMIC32_READ(I32_PTR) atomic_load_acq_int(I32_PTR) 366 #define ATOMIC32_SET(I32_PTR, VAL) atomic_store_rel_int(I32_PTR, VAL) 367 368 #define barrier() __asm__ __volatile__("": : :"memory") 369 #define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x)) 370 #define READ_ONCE(x) ({ \ 371 __typeof(x) __var; \ 372 barrier(); \ 373 __var = ACCESS_ONCE(x); \ 374 barrier(); \ 375 __var; \ 376 }) 377 378 #include "ena_defs/ena_includes.h" 379 380 #endif /* ENA_PLAT_H_ */ 381