1 /* 2 * Copyright (c) 2018-2021 Maxime Villard, m00nbsd.net 3 * All rights reserved. 4 * 5 * This code is part of the NVMM hypervisor. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _NVMM_IOCTL_H_ 30 #define _NVMM_IOCTL_H_ 31 32 #include <sys/ioccom.h> 33 34 #if defined(__NetBSD__) 35 #include <dev/nvmm/nvmm.h> 36 #elif defined(__DragonFly__) 37 #include <dev/virtual/nvmm/nvmm.h> 38 #else 39 #error "Unsupported OS." 40 #endif 41 42 struct nvmm_ioc_capability { 43 struct nvmm_capability cap; 44 }; 45 46 struct nvmm_ioc_machine_create { 47 nvmm_machid_t machid; 48 }; 49 50 struct nvmm_ioc_machine_destroy { 51 nvmm_machid_t machid; 52 }; 53 54 struct nvmm_ioc_machine_configure { 55 nvmm_machid_t machid; 56 uint64_t op; 57 void *conf; 58 }; 59 60 struct nvmm_ioc_vcpu_create { 61 nvmm_machid_t machid; 62 nvmm_cpuid_t cpuid; 63 struct nvmm_comm_page *comm; 64 }; 65 66 struct nvmm_ioc_vcpu_destroy { 67 nvmm_machid_t machid; 68 nvmm_cpuid_t cpuid; 69 }; 70 71 struct nvmm_ioc_vcpu_configure { 72 nvmm_machid_t machid; 73 nvmm_cpuid_t cpuid; 74 uint64_t op; 75 void *conf; 76 }; 77 78 struct nvmm_ioc_vcpu_setstate { 79 nvmm_machid_t machid; 80 nvmm_cpuid_t cpuid; 81 }; 82 83 struct nvmm_ioc_vcpu_getstate { 84 nvmm_machid_t machid; 85 nvmm_cpuid_t cpuid; 86 }; 87 88 struct nvmm_ioc_vcpu_inject { 89 nvmm_machid_t machid; 90 nvmm_cpuid_t cpuid; 91 }; 92 93 struct nvmm_ioc_vcpu_run { 94 /* input */ 95 nvmm_machid_t machid; 96 nvmm_cpuid_t cpuid; 97 /* output */ 98 struct nvmm_vcpu_exit exit; 99 }; 100 101 struct nvmm_ioc_hva_map { 102 nvmm_machid_t machid; 103 uintptr_t hva; 104 size_t size; 105 int flags; 106 }; 107 108 struct nvmm_ioc_hva_unmap { 109 nvmm_machid_t machid; 110 uintptr_t hva; 111 size_t size; 112 int flags; 113 }; 114 115 struct nvmm_ioc_gpa_map { 116 nvmm_machid_t machid; 117 uintptr_t hva; 118 gpaddr_t gpa; 119 size_t size; 120 int prot; 121 }; 122 123 struct nvmm_ioc_gpa_unmap { 124 nvmm_machid_t machid; 125 gpaddr_t gpa; 126 size_t size; 127 }; 128 129 struct nvmm_ctl_mach_info { 130 /* input */ 131 nvmm_machid_t machid; 132 /* output */ 133 uint32_t nvcpus; 134 uint64_t nram; 135 pid_t pid; 136 time_t time; 137 }; 138 139 struct nvmm_ioc_ctl { 140 int op; 141 #define NVMM_CTL_MACH_INFO 0 142 143 void *data; 144 size_t size; 145 }; 146 147 #define NVMM_IOC_CAPABILITY _IOR ('N', 0, struct nvmm_ioc_capability) 148 #define NVMM_IOC_MACHINE_CREATE _IOWR('N', 1, struct nvmm_ioc_machine_create) 149 #define NVMM_IOC_MACHINE_DESTROY _IOW ('N', 2, struct nvmm_ioc_machine_destroy) 150 #define NVMM_IOC_MACHINE_CONFIGURE _IOW ('N', 3, struct nvmm_ioc_machine_configure) 151 #define NVMM_IOC_VCPU_CREATE _IOWR('N', 4, struct nvmm_ioc_vcpu_create) 152 #define NVMM_IOC_VCPU_DESTROY _IOW ('N', 5, struct nvmm_ioc_vcpu_destroy) 153 #define NVMM_IOC_VCPU_CONFIGURE _IOW ('N', 6, struct nvmm_ioc_vcpu_configure) 154 #define NVMM_IOC_VCPU_SETSTATE _IOW ('N', 7, struct nvmm_ioc_vcpu_setstate) 155 #define NVMM_IOC_VCPU_GETSTATE _IOW ('N', 8, struct nvmm_ioc_vcpu_getstate) 156 #define NVMM_IOC_VCPU_INJECT _IOW ('N', 9, struct nvmm_ioc_vcpu_inject) 157 #define NVMM_IOC_VCPU_RUN _IOWR('N', 10, struct nvmm_ioc_vcpu_run) 158 #define NVMM_IOC_GPA_MAP _IOW ('N', 11, struct nvmm_ioc_gpa_map) 159 #define NVMM_IOC_GPA_UNMAP _IOW ('N', 12, struct nvmm_ioc_gpa_unmap) 160 #define NVMM_IOC_HVA_MAP _IOW ('N', 13, struct nvmm_ioc_hva_map) 161 #define NVMM_IOC_HVA_UNMAP _IOW ('N', 14, struct nvmm_ioc_hva_unmap) 162 #define NVMM_IOC_CTL _IOW ('N', 20, struct nvmm_ioc_ctl) 163 164 #endif /* _NVMM_IOCTL_H_ */ 165