1 /* $NetBSD: nvmm_x86.c,v 1.7.4.6 2020/09/13 11:54:10 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.6 2020/09/13 11:54:10 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/cpu.h> 39 40 #include <uvm/uvm.h> 41 #include <uvm/uvm_page.h> 42 43 #include <x86/cputypes.h> 44 #include <x86/specialreg.h> 45 #include <x86/pmap.h> 46 47 #include <dev/nvmm/nvmm.h> 48 #include <dev/nvmm/nvmm_internal.h> 49 #include <dev/nvmm/x86/nvmm_x86.h> 50 51 /* 52 * Code shared between x86-SVM and x86-VMX. 53 */ 54 55 const struct nvmm_x64_state nvmm_x86_reset_state = { 56 .segs = { 57 [NVMM_X64_SEG_ES] = { 58 .selector = 0x0000, 59 .base = 0x00000000, 60 .limit = 0xFFFF, 61 .attrib = { 62 .type = 3, 63 .s = 1, 64 .p = 1, 65 } 66 }, 67 [NVMM_X64_SEG_CS] = { 68 .selector = 0xF000, 69 .base = 0xFFFF0000, 70 .limit = 0xFFFF, 71 .attrib = { 72 .type = 3, 73 .s = 1, 74 .p = 1, 75 } 76 }, 77 [NVMM_X64_SEG_SS] = { 78 .selector = 0x0000, 79 .base = 0x00000000, 80 .limit = 0xFFFF, 81 .attrib = { 82 .type = 3, 83 .s = 1, 84 .p = 1, 85 } 86 }, 87 [NVMM_X64_SEG_DS] = { 88 .selector = 0x0000, 89 .base = 0x00000000, 90 .limit = 0xFFFF, 91 .attrib = { 92 .type = 3, 93 .s = 1, 94 .p = 1, 95 } 96 }, 97 [NVMM_X64_SEG_FS] = { 98 .selector = 0x0000, 99 .base = 0x00000000, 100 .limit = 0xFFFF, 101 .attrib = { 102 .type = 3, 103 .s = 1, 104 .p = 1, 105 } 106 }, 107 [NVMM_X64_SEG_GS] = { 108 .selector = 0x0000, 109 .base = 0x00000000, 110 .limit = 0xFFFF, 111 .attrib = { 112 .type = 3, 113 .s = 1, 114 .p = 1, 115 } 116 }, 117 [NVMM_X64_SEG_GDT] = { 118 .selector = 0x0000, 119 .base = 0x00000000, 120 .limit = 0xFFFF, 121 .attrib = { 122 .type = 2, 123 .s = 1, 124 .p = 1, 125 } 126 }, 127 [NVMM_X64_SEG_IDT] = { 128 .selector = 0x0000, 129 .base = 0x00000000, 130 .limit = 0xFFFF, 131 .attrib = { 132 .type = 2, 133 .s = 1, 134 .p = 1, 135 } 136 }, 137 [NVMM_X64_SEG_LDT] = { 138 .selector = 0x0000, 139 .base = 0x00000000, 140 .limit = 0xFFFF, 141 .attrib = { 142 .type = SDT_SYSLDT, 143 .s = 0, 144 .p = 1, 145 } 146 }, 147 [NVMM_X64_SEG_TR] = { 148 .selector = 0x0000, 149 .base = 0x00000000, 150 .limit = 0xFFFF, 151 .attrib = { 152 .type = SDT_SYS286BSY, 153 .s = 0, 154 .p = 1, 155 } 156 }, 157 }, 158 159 .gprs = { 160 [NVMM_X64_GPR_RAX] = 0x00000000, 161 [NVMM_X64_GPR_RCX] = 0x00000000, 162 [NVMM_X64_GPR_RDX] = 0x00000600, 163 [NVMM_X64_GPR_RBX] = 0x00000000, 164 [NVMM_X64_GPR_RSP] = 0x00000000, 165 [NVMM_X64_GPR_RBP] = 0x00000000, 166 [NVMM_X64_GPR_RSI] = 0x00000000, 167 [NVMM_X64_GPR_RDI] = 0x00000000, 168 [NVMM_X64_GPR_R8] = 0x00000000, 169 [NVMM_X64_GPR_R9] = 0x00000000, 170 [NVMM_X64_GPR_R10] = 0x00000000, 171 [NVMM_X64_GPR_R11] = 0x00000000, 172 [NVMM_X64_GPR_R12] = 0x00000000, 173 [NVMM_X64_GPR_R13] = 0x00000000, 174 [NVMM_X64_GPR_R14] = 0x00000000, 175 [NVMM_X64_GPR_R15] = 0x00000000, 176 [NVMM_X64_GPR_RIP] = 0x0000FFF0, 177 [NVMM_X64_GPR_RFLAGS] = 0x00000002, 178 }, 179 180 .crs = { 181 [NVMM_X64_CR_CR0] = 0x60000010, 182 [NVMM_X64_CR_CR2] = 0x00000000, 183 [NVMM_X64_CR_CR3] = 0x00000000, 184 [NVMM_X64_CR_CR4] = 0x00000000, 185 [NVMM_X64_CR_CR8] = 0x00000000, 186 [NVMM_X64_CR_XCR0] = 0x00000001, 187 }, 188 189 .drs = { 190 [NVMM_X64_DR_DR0] = 0x00000000, 191 [NVMM_X64_DR_DR1] = 0x00000000, 192 [NVMM_X64_DR_DR2] = 0x00000000, 193 [NVMM_X64_DR_DR3] = 0x00000000, 194 [NVMM_X64_DR_DR6] = 0xFFFF0FF0, 195 [NVMM_X64_DR_DR7] = 0x00000400, 196 }, 197 198 .msrs = { 199 [NVMM_X64_MSR_EFER] = 0x00000000, 200 [NVMM_X64_MSR_STAR] = 0x00000000, 201 [NVMM_X64_MSR_LSTAR] = 0x00000000, 202 [NVMM_X64_MSR_CSTAR] = 0x00000000, 203 [NVMM_X64_MSR_SFMASK] = 0x00000000, 204 [NVMM_X64_MSR_KERNELGSBASE] = 0x00000000, 205 [NVMM_X64_MSR_SYSENTER_CS] = 0x00000000, 206 [NVMM_X64_MSR_SYSENTER_ESP] = 0x00000000, 207 [NVMM_X64_MSR_SYSENTER_EIP] = 0x00000000, 208 [NVMM_X64_MSR_PAT] = 209 PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WT) | 210 PATENTRY(2, PAT_UCMINUS) | PATENTRY(3, PAT_UC) | 211 PATENTRY(4, PAT_WB) | PATENTRY(5, PAT_WT) | 212 PATENTRY(6, PAT_UCMINUS) | PATENTRY(7, PAT_UC), 213 [NVMM_X64_MSR_TSC] = 0, 214 }, 215 216 .intr = { 217 .int_shadow = 0, 218 .int_window_exiting = 0, 219 .nmi_window_exiting = 0, 220 .evt_pending = 0, 221 }, 222 223 .fpu = { 224 .fx_cw = 0x0040, 225 .fx_sw = 0x0000, 226 .fx_tw = 0x55, 227 .fx_zero = 0x55, 228 .fx_mxcsr = 0x1F80, 229 } 230 }; 231 232 const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001 = { 233 .eax = ~0, 234 .ebx = ~0, 235 .ecx = 236 CPUID2_SSE3 | 237 CPUID2_PCLMUL | 238 /* CPUID2_DTES64 excluded */ 239 /* CPUID2_MONITOR excluded */ 240 /* CPUID2_DS_CPL excluded */ 241 /* CPUID2_VMX excluded */ 242 /* CPUID2_SMX excluded */ 243 /* CPUID2_EST excluded */ 244 /* CPUID2_TM2 excluded */ 245 CPUID2_SSSE3 | 246 /* CPUID2_CID excluded */ 247 /* CPUID2_SDBG excluded */ 248 CPUID2_FMA | 249 CPUID2_CX16 | 250 /* CPUID2_xTPR excluded */ 251 /* CPUID2_PDCM excluded */ 252 /* CPUID2_PCID excluded, but re-included in VMX */ 253 /* CPUID2_DCA excluded */ 254 CPUID2_SSE41 | 255 CPUID2_SSE42 | 256 /* CPUID2_X2APIC excluded */ 257 CPUID2_MOVBE | 258 CPUID2_POPCNT | 259 /* CPUID2_DEADLINE excluded */ 260 CPUID2_AES | 261 CPUID2_XSAVE | 262 CPUID2_OSXSAVE | 263 /* CPUID2_AVX excluded */ 264 CPUID2_F16C | 265 CPUID2_RDRAND, 266 /* CPUID2_RAZ excluded */ 267 .edx = 268 CPUID_FPU | 269 CPUID_VME | 270 CPUID_DE | 271 CPUID_PSE | 272 CPUID_TSC | 273 CPUID_MSR | 274 CPUID_PAE | 275 /* CPUID_MCE excluded */ 276 CPUID_CX8 | 277 CPUID_APIC | 278 CPUID_SEP | 279 /* CPUID_MTRR excluded */ 280 CPUID_PGE | 281 /* CPUID_MCA excluded */ 282 CPUID_CMOV | 283 CPUID_PAT | 284 CPUID_PSE36 | 285 /* CPUID_PN excluded */ 286 CPUID_CFLUSH | 287 /* CPUID_DS excluded */ 288 /* CPUID_ACPI excluded */ 289 CPUID_MMX | 290 CPUID_FXSR | 291 CPUID_SSE | 292 CPUID_SSE2 | 293 CPUID_SS | 294 CPUID_HTT | 295 /* CPUID_TM excluded */ 296 CPUID_SBF 297 }; 298 299 const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007 = { 300 .eax = ~0, 301 .ebx = 302 CPUID_SEF_FSGSBASE | 303 /* CPUID_SEF_TSC_ADJUST excluded */ 304 /* CPUID_SEF_SGX excluded */ 305 CPUID_SEF_BMI1 | 306 /* CPUID_SEF_HLE excluded */ 307 /* CPUID_SEF_AVX2 excluded */ 308 CPUID_SEF_FDPEXONLY | 309 CPUID_SEF_SMEP | 310 CPUID_SEF_BMI2 | 311 CPUID_SEF_ERMS | 312 /* CPUID_SEF_INVPCID excluded, but re-included in VMX */ 313 /* CPUID_SEF_RTM excluded */ 314 /* CPUID_SEF_QM excluded */ 315 CPUID_SEF_FPUCSDS | 316 /* CPUID_SEF_MPX excluded */ 317 CPUID_SEF_PQE | 318 /* CPUID_SEF_AVX512F excluded */ 319 /* CPUID_SEF_AVX512DQ excluded */ 320 CPUID_SEF_RDSEED | 321 CPUID_SEF_ADX | 322 CPUID_SEF_SMAP | 323 /* CPUID_SEF_AVX512_IFMA excluded */ 324 CPUID_SEF_CLFLUSHOPT | 325 CPUID_SEF_CLWB, 326 /* CPUID_SEF_PT excluded */ 327 /* CPUID_SEF_AVX512PF excluded */ 328 /* CPUID_SEF_AVX512ER excluded */ 329 /* CPUID_SEF_AVX512CD excluded */ 330 /* CPUID_SEF_SHA excluded */ 331 /* CPUID_SEF_AVX512BW excluded */ 332 /* CPUID_SEF_AVX512VL excluded */ 333 .ecx = 334 CPUID_SEF_PREFETCHWT1 | 335 /* CPUID_SEF_AVX512_VBMI excluded */ 336 CPUID_SEF_UMIP | 337 /* CPUID_SEF_PKU excluded */ 338 /* CPUID_SEF_OSPKE excluded */ 339 /* CPUID_SEF_WAITPKG excluded */ 340 /* CPUID_SEF_AVX512_VBMI2 excluded */ 341 /* CPUID_SEF_CET_SS excluded */ 342 CPUID_SEF_GFNI | 343 CPUID_SEF_VAES | 344 CPUID_SEF_VPCLMULQDQ | 345 /* CPUID_SEF_AVX512_VNNI excluded */ 346 /* CPUID_SEF_AVX512_BITALG excluded */ 347 /* CPUID_SEF_AVX512_VPOPCNTDQ excluded */ 348 /* CPUID_SEF_MAWAU excluded */ 349 /* CPUID_SEF_RDPID excluded */ 350 CPUID_SEF_CLDEMOTE | 351 CPUID_SEF_MOVDIRI | 352 CPUID_SEF_MOVDIR64B, 353 /* CPUID_SEF_SGXLC excluded */ 354 /* CPUID_SEF_PKS excluded */ 355 .edx = 356 /* CPUID_SEF_AVX512_4VNNIW excluded */ 357 /* CPUID_SEF_AVX512_4FMAPS excluded */ 358 CPUID_SEF_FSREP_MOV | 359 /* CPUID_SEF_AVX512_VP2INTERSECT excluded */ 360 /* CPUID_SEF_SRBDS_CTRL excluded */ 361 CPUID_SEF_MD_CLEAR | 362 /* CPUID_SEF_TSX_FORCE_ABORT excluded */ 363 CPUID_SEF_SERIALIZE | 364 /* CPUID_SEF_HYBRID excluded */ 365 /* CPUID_SEF_TSXLDTRK excluded */ 366 /* CPUID_SEF_CET_IBT excluded */ 367 /* CPUID_SEF_IBRS excluded */ 368 /* CPUID_SEF_STIBP excluded */ 369 /* CPUID_SEF_L1D_FLUSH excluded */ 370 CPUID_SEF_ARCH_CAP 371 /* CPUID_SEF_CORE_CAP excluded */ 372 /* CPUID_SEF_SSBD excluded */ 373 }; 374 375 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001 = { 376 .eax = ~0, 377 .ebx = ~0, 378 .ecx = 379 CPUID_LAHF | 380 CPUID_CMPLEGACY | 381 /* CPUID_SVM excluded */ 382 /* CPUID_EAPIC excluded */ 383 CPUID_ALTMOVCR0 | 384 CPUID_LZCNT | 385 CPUID_SSE4A | 386 CPUID_MISALIGNSSE | 387 CPUID_3DNOWPF | 388 /* CPUID_OSVW excluded */ 389 /* CPUID_IBS excluded */ 390 CPUID_XOP | 391 /* CPUID_SKINIT excluded */ 392 /* CPUID_WDT excluded */ 393 /* CPUID_LWP excluded */ 394 CPUID_FMA4 | 395 CPUID_TCE | 396 /* CPUID_NODEID excluded */ 397 CPUID_TBM | 398 CPUID_TOPOEXT, 399 /* CPUID_PCEC excluded */ 400 /* CPUID_PCENB excluded */ 401 /* CPUID_SPM excluded */ 402 /* CPUID_DBE excluded */ 403 /* CPUID_PTSC excluded */ 404 /* CPUID_L2IPERFC excluded */ 405 /* CPUID_MWAITX excluded */ 406 .edx = 407 CPUID_SYSCALL | 408 CPUID_MPC | 409 CPUID_XD | 410 CPUID_MMXX | 411 CPUID_MMX | 412 CPUID_FXSR | 413 CPUID_FFXSR | 414 CPUID_P1GB | 415 /* CPUID_RDTSCP excluded */ 416 CPUID_EM64T | 417 CPUID_3DNOW2 | 418 CPUID_3DNOW 419 }; 420 421 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000007 = { 422 .eax = 0, 423 .ebx = 0, 424 .ecx = 0, 425 .edx = CPUID_APM_ITSC 426 }; 427 428 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000008 = { 429 .eax = ~0, 430 .ebx = 431 CPUID_CAPEX_CLZERO | 432 /* CPUID_CAPEX_IRPERF excluded */ 433 CPUID_CAPEX_XSAVEERPTR | 434 /* CPUID_CAPEX_RDPRU excluded */ 435 /* CPUID_CAPEX_MCOMMIT excluded */ 436 CPUID_CAPEX_WBNOINVD, 437 .ecx = ~0, /* TODO? */ 438 .edx = 0 439 }; 440 441 bool 442 nvmm_x86_pat_validate(uint64_t val) 443 { 444 uint8_t *pat = (uint8_t *)&val; 445 size_t i; 446 447 for (i = 0; i < 8; i++) { 448 if (__predict_false(pat[i] & ~__BITS(2,0))) 449 return false; 450 if (__predict_false(pat[i] == 2 || pat[i] == 3)) 451 return false; 452 } 453 454 return true; 455 } 456