16d65b43dSAaron LI /*
2bfc69df0SAaron LI * Copyright (c) 2018-2021 Maxime Villard, m00nbsd.net
36d65b43dSAaron LI * All rights reserved.
46d65b43dSAaron LI *
57f0e1ce2SAaron LI * This code is part of the NVMM hypervisor.
66d65b43dSAaron LI *
76d65b43dSAaron LI * Redistribution and use in source and binary forms, with or without
86d65b43dSAaron LI * modification, are permitted provided that the following conditions
96d65b43dSAaron LI * are met:
106d65b43dSAaron LI * 1. Redistributions of source code must retain the above copyright
116d65b43dSAaron LI * notice, this list of conditions and the following disclaimer.
126d65b43dSAaron LI * 2. Redistributions in binary form must reproduce the above copyright
136d65b43dSAaron LI * notice, this list of conditions and the following disclaimer in the
146d65b43dSAaron LI * documentation and/or other materials provided with the distribution.
156d65b43dSAaron LI *
167f0e1ce2SAaron LI * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
177f0e1ce2SAaron LI * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
187f0e1ce2SAaron LI * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
197f0e1ce2SAaron LI * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
207f0e1ce2SAaron LI * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
217f0e1ce2SAaron LI * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
227f0e1ce2SAaron LI * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
237f0e1ce2SAaron LI * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
247f0e1ce2SAaron LI * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
257f0e1ce2SAaron LI * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
267f0e1ce2SAaron LI * SUCH DAMAGE.
276d65b43dSAaron LI */
286d65b43dSAaron LI
296d65b43dSAaron LI #ifndef _NVMM_X86_H_
306d65b43dSAaron LI #define _NVMM_X86_H_
316d65b43dSAaron LI
3242862644SAaron LI #if defined(__NetBSD__)
3342862644SAaron LI #include <x86/specialreg.h>
3442862644SAaron LI #elif defined(__DragonFly__)
3542862644SAaron LI #include <machine/specialreg.h>
3642862644SAaron LI #endif
3742862644SAaron LI
386d65b43dSAaron LI /* -------------------------------------------------------------------------- */
396d65b43dSAaron LI
406d65b43dSAaron LI #ifndef ASM_NVMM
416d65b43dSAaron LI
426d65b43dSAaron LI struct nvmm_x86_exit_memory {
436d65b43dSAaron LI int prot;
446d65b43dSAaron LI gpaddr_t gpa;
456d65b43dSAaron LI uint8_t inst_len;
466d65b43dSAaron LI uint8_t inst_bytes[15];
476d65b43dSAaron LI };
486d65b43dSAaron LI
496d65b43dSAaron LI struct nvmm_x86_exit_io {
506d65b43dSAaron LI bool in;
516d65b43dSAaron LI uint16_t port;
526d65b43dSAaron LI int8_t seg;
536d65b43dSAaron LI uint8_t address_size;
546d65b43dSAaron LI uint8_t operand_size;
556d65b43dSAaron LI bool rep;
566d65b43dSAaron LI bool str;
576d65b43dSAaron LI uint64_t npc;
586d65b43dSAaron LI };
596d65b43dSAaron LI
606d65b43dSAaron LI struct nvmm_x86_exit_rdmsr {
616d65b43dSAaron LI uint32_t msr;
626d65b43dSAaron LI uint64_t npc;
636d65b43dSAaron LI };
646d65b43dSAaron LI
656d65b43dSAaron LI struct nvmm_x86_exit_wrmsr {
666d65b43dSAaron LI uint32_t msr;
676d65b43dSAaron LI uint64_t val;
686d65b43dSAaron LI uint64_t npc;
696d65b43dSAaron LI };
706d65b43dSAaron LI
716d65b43dSAaron LI struct nvmm_x86_exit_insn {
726d65b43dSAaron LI uint64_t npc;
736d65b43dSAaron LI };
746d65b43dSAaron LI
756d65b43dSAaron LI struct nvmm_x86_exit_invalid {
766d65b43dSAaron LI uint64_t hwcode;
776d65b43dSAaron LI };
786d65b43dSAaron LI
796d65b43dSAaron LI /* Generic. */
806d65b43dSAaron LI #define NVMM_VCPU_EXIT_NONE 0x0000000000000000ULL
816d65b43dSAaron LI #define NVMM_VCPU_EXIT_INVALID 0xFFFFFFFFFFFFFFFFULL
826d65b43dSAaron LI /* x86: operations. */
836d65b43dSAaron LI #define NVMM_VCPU_EXIT_MEMORY 0x0000000000000001ULL
846d65b43dSAaron LI #define NVMM_VCPU_EXIT_IO 0x0000000000000002ULL
856d65b43dSAaron LI /* x86: changes in VCPU state. */
866d65b43dSAaron LI #define NVMM_VCPU_EXIT_SHUTDOWN 0x0000000000001000ULL
876d65b43dSAaron LI #define NVMM_VCPU_EXIT_INT_READY 0x0000000000001001ULL
886d65b43dSAaron LI #define NVMM_VCPU_EXIT_NMI_READY 0x0000000000001002ULL
896d65b43dSAaron LI #define NVMM_VCPU_EXIT_HALTED 0x0000000000001003ULL
906d65b43dSAaron LI #define NVMM_VCPU_EXIT_TPR_CHANGED 0x0000000000001004ULL
916d65b43dSAaron LI /* x86: instructions. */
926d65b43dSAaron LI #define NVMM_VCPU_EXIT_RDMSR 0x0000000000002000ULL
936d65b43dSAaron LI #define NVMM_VCPU_EXIT_WRMSR 0x0000000000002001ULL
946d65b43dSAaron LI #define NVMM_VCPU_EXIT_MONITOR 0x0000000000002002ULL
956d65b43dSAaron LI #define NVMM_VCPU_EXIT_MWAIT 0x0000000000002003ULL
966d65b43dSAaron LI #define NVMM_VCPU_EXIT_CPUID 0x0000000000002004ULL
976d65b43dSAaron LI
986d65b43dSAaron LI struct nvmm_x86_exit {
996d65b43dSAaron LI uint64_t reason;
1006d65b43dSAaron LI union {
1016d65b43dSAaron LI struct nvmm_x86_exit_memory mem;
1026d65b43dSAaron LI struct nvmm_x86_exit_io io;
1036d65b43dSAaron LI struct nvmm_x86_exit_rdmsr rdmsr;
1046d65b43dSAaron LI struct nvmm_x86_exit_wrmsr wrmsr;
1056d65b43dSAaron LI struct nvmm_x86_exit_insn insn;
1066d65b43dSAaron LI struct nvmm_x86_exit_invalid inv;
1076d65b43dSAaron LI } u;
1086d65b43dSAaron LI struct {
1096d65b43dSAaron LI uint64_t rflags;
1106d65b43dSAaron LI uint64_t cr8;
1116d65b43dSAaron LI uint64_t int_shadow:1;
1126d65b43dSAaron LI uint64_t int_window_exiting:1;
1136d65b43dSAaron LI uint64_t nmi_window_exiting:1;
1146d65b43dSAaron LI uint64_t evt_pending:1;
1156d65b43dSAaron LI uint64_t rsvd:60;
1166d65b43dSAaron LI } exitstate;
1176d65b43dSAaron LI };
118bfc69df0SAaron LI #define nvmm_vcpu_exit nvmm_x86_exit
1196d65b43dSAaron LI
1206d65b43dSAaron LI #define NVMM_VCPU_EVENT_EXCP 0
1216d65b43dSAaron LI #define NVMM_VCPU_EVENT_INTR 1
1226d65b43dSAaron LI
1236d65b43dSAaron LI struct nvmm_x86_event {
1246d65b43dSAaron LI u_int type;
1256d65b43dSAaron LI uint8_t vector;
1266d65b43dSAaron LI union {
1276d65b43dSAaron LI struct {
1286d65b43dSAaron LI uint64_t error;
1296d65b43dSAaron LI } excp;
1306d65b43dSAaron LI } u;
1316d65b43dSAaron LI };
132bfc69df0SAaron LI #define nvmm_vcpu_event nvmm_x86_event
1336d65b43dSAaron LI
1346d65b43dSAaron LI struct nvmm_cap_md {
1356d65b43dSAaron LI uint64_t mach_conf_support;
1366d65b43dSAaron LI
1376d65b43dSAaron LI uint64_t vcpu_conf_support;
1386d65b43dSAaron LI #define NVMM_CAP_ARCH_VCPU_CONF_CPUID __BIT(0)
1396d65b43dSAaron LI #define NVMM_CAP_ARCH_VCPU_CONF_TPR __BIT(1)
1406d65b43dSAaron LI
1416d65b43dSAaron LI uint64_t xcr0_mask;
1426d65b43dSAaron LI uint32_t mxcsr_mask;
1436d65b43dSAaron LI uint32_t conf_cpuid_maxops;
1446d65b43dSAaron LI uint64_t rsvd[6];
1456d65b43dSAaron LI };
1466d65b43dSAaron LI
147bfc69df0SAaron LI #endif /* ASM_NVMM */
1486d65b43dSAaron LI
1496d65b43dSAaron LI /* -------------------------------------------------------------------------- */
1506d65b43dSAaron LI
1516d65b43dSAaron LI /*
15223b2397dSAaron LI * State indexes. We use X64 as naming convention, not to confuse with X86
15323b2397dSAaron LI * which originally implied 32bit.
1546d65b43dSAaron LI */
1556d65b43dSAaron LI
1566d65b43dSAaron LI /* Segments. */
1576d65b43dSAaron LI #define NVMM_X64_SEG_ES 0
1586d65b43dSAaron LI #define NVMM_X64_SEG_CS 1
1596d65b43dSAaron LI #define NVMM_X64_SEG_SS 2
1606d65b43dSAaron LI #define NVMM_X64_SEG_DS 3
1616d65b43dSAaron LI #define NVMM_X64_SEG_FS 4
1626d65b43dSAaron LI #define NVMM_X64_SEG_GS 5
1636d65b43dSAaron LI #define NVMM_X64_SEG_GDT 6
1646d65b43dSAaron LI #define NVMM_X64_SEG_IDT 7
1656d65b43dSAaron LI #define NVMM_X64_SEG_LDT 8
1666d65b43dSAaron LI #define NVMM_X64_SEG_TR 9
1676d65b43dSAaron LI #define NVMM_X64_NSEG 10
1686d65b43dSAaron LI
1696d65b43dSAaron LI /* General Purpose Registers. */
1706d65b43dSAaron LI #define NVMM_X64_GPR_RAX 0
1716d65b43dSAaron LI #define NVMM_X64_GPR_RCX 1
1726d65b43dSAaron LI #define NVMM_X64_GPR_RDX 2
1736d65b43dSAaron LI #define NVMM_X64_GPR_RBX 3
1746d65b43dSAaron LI #define NVMM_X64_GPR_RSP 4
1756d65b43dSAaron LI #define NVMM_X64_GPR_RBP 5
1766d65b43dSAaron LI #define NVMM_X64_GPR_RSI 6
1776d65b43dSAaron LI #define NVMM_X64_GPR_RDI 7
1786d65b43dSAaron LI #define NVMM_X64_GPR_R8 8
1796d65b43dSAaron LI #define NVMM_X64_GPR_R9 9
1806d65b43dSAaron LI #define NVMM_X64_GPR_R10 10
1816d65b43dSAaron LI #define NVMM_X64_GPR_R11 11
1826d65b43dSAaron LI #define NVMM_X64_GPR_R12 12
1836d65b43dSAaron LI #define NVMM_X64_GPR_R13 13
1846d65b43dSAaron LI #define NVMM_X64_GPR_R14 14
1856d65b43dSAaron LI #define NVMM_X64_GPR_R15 15
1866d65b43dSAaron LI #define NVMM_X64_GPR_RIP 16
1876d65b43dSAaron LI #define NVMM_X64_GPR_RFLAGS 17
1886d65b43dSAaron LI #define NVMM_X64_NGPR 18
1896d65b43dSAaron LI
1906d65b43dSAaron LI /* Control Registers. */
1916d65b43dSAaron LI #define NVMM_X64_CR_CR0 0
1926d65b43dSAaron LI #define NVMM_X64_CR_CR2 1
1936d65b43dSAaron LI #define NVMM_X64_CR_CR3 2
1946d65b43dSAaron LI #define NVMM_X64_CR_CR4 3
1956d65b43dSAaron LI #define NVMM_X64_CR_CR8 4
1966d65b43dSAaron LI #define NVMM_X64_CR_XCR0 5
1976d65b43dSAaron LI #define NVMM_X64_NCR 6
1986d65b43dSAaron LI
1996d65b43dSAaron LI /* Debug Registers. */
2006d65b43dSAaron LI #define NVMM_X64_DR_DR0 0
2016d65b43dSAaron LI #define NVMM_X64_DR_DR1 1
2026d65b43dSAaron LI #define NVMM_X64_DR_DR2 2
2036d65b43dSAaron LI #define NVMM_X64_DR_DR3 3
2046d65b43dSAaron LI #define NVMM_X64_DR_DR6 4
2056d65b43dSAaron LI #define NVMM_X64_DR_DR7 5
2066d65b43dSAaron LI #define NVMM_X64_NDR 6
2076d65b43dSAaron LI
2086d65b43dSAaron LI /* MSRs. */
2096d65b43dSAaron LI #define NVMM_X64_MSR_EFER 0
2106d65b43dSAaron LI #define NVMM_X64_MSR_STAR 1
2116d65b43dSAaron LI #define NVMM_X64_MSR_LSTAR 2
2126d65b43dSAaron LI #define NVMM_X64_MSR_CSTAR 3
2136d65b43dSAaron LI #define NVMM_X64_MSR_SFMASK 4
2146d65b43dSAaron LI #define NVMM_X64_MSR_KERNELGSBASE 5
2156d65b43dSAaron LI #define NVMM_X64_MSR_SYSENTER_CS 6
2166d65b43dSAaron LI #define NVMM_X64_MSR_SYSENTER_ESP 7
2176d65b43dSAaron LI #define NVMM_X64_MSR_SYSENTER_EIP 8
2186d65b43dSAaron LI #define NVMM_X64_MSR_PAT 9
2196d65b43dSAaron LI #define NVMM_X64_MSR_TSC 10
2206d65b43dSAaron LI #define NVMM_X64_NMSR 11
2216d65b43dSAaron LI
2226d65b43dSAaron LI #ifndef ASM_NVMM
2236d65b43dSAaron LI
2246d65b43dSAaron LI #include <sys/types.h>
22542862644SAaron LI #include <sys/bitops.h>
22642862644SAaron LI #if defined(__DragonFly__)
22742862644SAaron LI #ifdef __x86_64__
22842862644SAaron LI #undef __BIT
22942862644SAaron LI #define __BIT(__n) __BIT64(__n)
23042862644SAaron LI #undef __BITS
23142862644SAaron LI #define __BITS(__m, __n) __BITS64(__m, __n)
23242862644SAaron LI #endif /* __x86_64__ */
23342862644SAaron LI #endif
2346d65b43dSAaron LI
23523b2397dSAaron LI /* Segment state. */
2366d65b43dSAaron LI struct nvmm_x64_state_seg {
2376d65b43dSAaron LI uint16_t selector;
2386d65b43dSAaron LI struct { /* hidden */
2396d65b43dSAaron LI uint16_t type:4;
2406d65b43dSAaron LI uint16_t s:1;
2416d65b43dSAaron LI uint16_t dpl:2;
2426d65b43dSAaron LI uint16_t p:1;
2436d65b43dSAaron LI uint16_t avl:1;
2446d65b43dSAaron LI uint16_t l:1;
2456d65b43dSAaron LI uint16_t def:1;
2466d65b43dSAaron LI uint16_t g:1;
2476d65b43dSAaron LI uint16_t rsvd:4;
2486d65b43dSAaron LI } attrib;
2496d65b43dSAaron LI uint32_t limit; /* hidden */
2506d65b43dSAaron LI uint64_t base; /* hidden */
2516d65b43dSAaron LI };
2526d65b43dSAaron LI
25323b2397dSAaron LI /* Interrupt state. */
2546d65b43dSAaron LI struct nvmm_x64_state_intr {
2556d65b43dSAaron LI uint64_t int_shadow:1;
2566d65b43dSAaron LI uint64_t int_window_exiting:1;
2576d65b43dSAaron LI uint64_t nmi_window_exiting:1;
2586d65b43dSAaron LI uint64_t evt_pending:1;
2596d65b43dSAaron LI uint64_t rsvd:60;
2606d65b43dSAaron LI };
2616d65b43dSAaron LI
26223b2397dSAaron LI /* FPU state structures. */
26323b2397dSAaron LI union nvmm_x64_state_fpu_addr {
26423b2397dSAaron LI uint64_t fa_64;
26523b2397dSAaron LI struct {
26623b2397dSAaron LI uint32_t fa_off;
26723b2397dSAaron LI uint16_t fa_seg;
26823b2397dSAaron LI uint16_t fa_opcode;
26923b2397dSAaron LI } fa_32;
27023b2397dSAaron LI };
27123b2397dSAaron LI CTASSERT(sizeof(union nvmm_x64_state_fpu_addr) == 8);
27223b2397dSAaron LI struct nvmm_x64_state_fpu_mmreg {
27323b2397dSAaron LI uint64_t mm_significand;
27423b2397dSAaron LI uint16_t mm_exp_sign;
27523b2397dSAaron LI uint8_t mm_rsvd[6];
27623b2397dSAaron LI };
27723b2397dSAaron LI CTASSERT(sizeof(struct nvmm_x64_state_fpu_mmreg) == 16);
27823b2397dSAaron LI struct nvmm_x64_state_fpu_xmmreg {
27923b2397dSAaron LI uint8_t xmm_bytes[16];
28023b2397dSAaron LI };
28123b2397dSAaron LI CTASSERT(sizeof(struct nvmm_x64_state_fpu_xmmreg) == 16);
28223b2397dSAaron LI
28323b2397dSAaron LI /* FPU state (x87 + SSE). */
28423b2397dSAaron LI struct nvmm_x64_state_fpu {
28523b2397dSAaron LI uint16_t fx_cw; /* Control Word */
28623b2397dSAaron LI uint16_t fx_sw; /* Status Word */
28723b2397dSAaron LI uint8_t fx_tw; /* Tag Word */
28823b2397dSAaron LI uint8_t fx_zero;
28923b2397dSAaron LI uint16_t fx_opcode;
29023b2397dSAaron LI union nvmm_x64_state_fpu_addr fx_ip; /* Instruction Pointer */
29123b2397dSAaron LI union nvmm_x64_state_fpu_addr fx_dp; /* Data pointer */
29223b2397dSAaron LI uint32_t fx_mxcsr;
29323b2397dSAaron LI uint32_t fx_mxcsr_mask;
29423b2397dSAaron LI struct nvmm_x64_state_fpu_mmreg fx_87_ac[8]; /* x87 registers */
29523b2397dSAaron LI struct nvmm_x64_state_fpu_xmmreg fx_xmm[16]; /* XMM registers */
29623b2397dSAaron LI uint8_t fx_rsvd[96];
29723b2397dSAaron LI } __aligned(16);
29823b2397dSAaron LI CTASSERT(sizeof(struct nvmm_x64_state_fpu) == 512);
29923b2397dSAaron LI
3006d65b43dSAaron LI /* Flags. */
3016d65b43dSAaron LI #define NVMM_X64_STATE_SEGS 0x01
3026d65b43dSAaron LI #define NVMM_X64_STATE_GPRS 0x02
3036d65b43dSAaron LI #define NVMM_X64_STATE_CRS 0x04
3046d65b43dSAaron LI #define NVMM_X64_STATE_DRS 0x08
3056d65b43dSAaron LI #define NVMM_X64_STATE_MSRS 0x10
3066d65b43dSAaron LI #define NVMM_X64_STATE_INTR 0x20
3076d65b43dSAaron LI #define NVMM_X64_STATE_FPU 0x40
3086d65b43dSAaron LI #define NVMM_X64_STATE_ALL \
3096d65b43dSAaron LI (NVMM_X64_STATE_SEGS | NVMM_X64_STATE_GPRS | NVMM_X64_STATE_CRS | \
3106d65b43dSAaron LI NVMM_X64_STATE_DRS | NVMM_X64_STATE_MSRS | NVMM_X64_STATE_INTR | \
3116d65b43dSAaron LI NVMM_X64_STATE_FPU)
3126d65b43dSAaron LI
3136d65b43dSAaron LI struct nvmm_x64_state {
3146d65b43dSAaron LI struct nvmm_x64_state_seg segs[NVMM_X64_NSEG];
3156d65b43dSAaron LI uint64_t gprs[NVMM_X64_NGPR];
3166d65b43dSAaron LI uint64_t crs[NVMM_X64_NCR];
3176d65b43dSAaron LI uint64_t drs[NVMM_X64_NDR];
3186d65b43dSAaron LI uint64_t msrs[NVMM_X64_NMSR];
3196d65b43dSAaron LI struct nvmm_x64_state_intr intr;
32023b2397dSAaron LI struct nvmm_x64_state_fpu fpu;
3216d65b43dSAaron LI };
322bfc69df0SAaron LI #define nvmm_vcpu_state nvmm_x64_state
3236d65b43dSAaron LI
32423b2397dSAaron LI /* -------------------------------------------------------------------------- */
32523b2397dSAaron LI
3266d65b43dSAaron LI #define NVMM_VCPU_CONF_CPUID NVMM_VCPU_CONF_MD_BEGIN
3276d65b43dSAaron LI #define NVMM_VCPU_CONF_TPR (NVMM_VCPU_CONF_MD_BEGIN + 1)
3286d65b43dSAaron LI
3296d65b43dSAaron LI struct nvmm_vcpu_conf_cpuid {
3306d65b43dSAaron LI /* The options. */
3316d65b43dSAaron LI uint32_t mask:1;
3326d65b43dSAaron LI uint32_t exit:1;
3336d65b43dSAaron LI uint32_t rsvd:30;
3346d65b43dSAaron LI
3356d65b43dSAaron LI /* The leaf. */
3366d65b43dSAaron LI uint32_t leaf;
3376d65b43dSAaron LI
3386d65b43dSAaron LI /* The params. */
3396d65b43dSAaron LI union {
3406d65b43dSAaron LI struct {
3416d65b43dSAaron LI struct {
3426d65b43dSAaron LI uint32_t eax;
3436d65b43dSAaron LI uint32_t ebx;
3446d65b43dSAaron LI uint32_t ecx;
3456d65b43dSAaron LI uint32_t edx;
3466d65b43dSAaron LI } set;
3476d65b43dSAaron LI struct {
3486d65b43dSAaron LI uint32_t eax;
3496d65b43dSAaron LI uint32_t ebx;
3506d65b43dSAaron LI uint32_t ecx;
3516d65b43dSAaron LI uint32_t edx;
3526d65b43dSAaron LI } del;
3536d65b43dSAaron LI } mask;
3546d65b43dSAaron LI } u;
3556d65b43dSAaron LI };
3566d65b43dSAaron LI
3576d65b43dSAaron LI struct nvmm_vcpu_conf_tpr {
3586d65b43dSAaron LI uint32_t exit_changed:1;
3596d65b43dSAaron LI uint32_t rsvd:31;
3606d65b43dSAaron LI };
3616d65b43dSAaron LI
362c1d369d5SAaron LI /* -------------------------------------------------------------------------- */
363c1d369d5SAaron LI
364c1d369d5SAaron LI /*
365c1d369d5SAaron LI * CPUID defines.
366c1d369d5SAaron LI */
367c1d369d5SAaron LI
368c1d369d5SAaron LI /* Fn0000_0001:EBX */
369c1d369d5SAaron LI #define CPUID_0_01_EBX_BRAND_INDEX __BITS(7,0)
370c1d369d5SAaron LI #define CPUID_0_01_EBX_CLFLUSH_SIZE __BITS(15,8)
371c1d369d5SAaron LI #define CPUID_0_01_EBX_HTT_CORES __BITS(23,16)
372c1d369d5SAaron LI #define CPUID_0_01_EBX_LOCAL_APIC_ID __BITS(31,24)
373c1d369d5SAaron LI /* Fn0000_0001:ECX */
374c1d369d5SAaron LI #define CPUID_0_01_ECX_SSE3 __BIT(0)
375c1d369d5SAaron LI #define CPUID_0_01_ECX_PCLMULQDQ __BIT(1)
376c1d369d5SAaron LI #define CPUID_0_01_ECX_DTES64 __BIT(2)
377c1d369d5SAaron LI #define CPUID_0_01_ECX_MONITOR __BIT(3)
378c1d369d5SAaron LI #define CPUID_0_01_ECX_DS_CPL __BIT(4)
379c1d369d5SAaron LI #define CPUID_0_01_ECX_VMX __BIT(5)
380c1d369d5SAaron LI #define CPUID_0_01_ECX_SMX __BIT(6)
381c1d369d5SAaron LI #define CPUID_0_01_ECX_EIST __BIT(7)
382c1d369d5SAaron LI #define CPUID_0_01_ECX_TM2 __BIT(8)
383c1d369d5SAaron LI #define CPUID_0_01_ECX_SSSE3 __BIT(9)
384c1d369d5SAaron LI #define CPUID_0_01_ECX_CNXTID __BIT(10)
385c1d369d5SAaron LI #define CPUID_0_01_ECX_SDBG __BIT(11)
386c1d369d5SAaron LI #define CPUID_0_01_ECX_FMA __BIT(12)
387c1d369d5SAaron LI #define CPUID_0_01_ECX_CX16 __BIT(13)
388c1d369d5SAaron LI #define CPUID_0_01_ECX_XTPR __BIT(14)
389c1d369d5SAaron LI #define CPUID_0_01_ECX_PDCM __BIT(15)
390c1d369d5SAaron LI #define CPUID_0_01_ECX_PCID __BIT(17)
391c1d369d5SAaron LI #define CPUID_0_01_ECX_DCA __BIT(18)
392c1d369d5SAaron LI #define CPUID_0_01_ECX_SSE41 __BIT(19)
393c1d369d5SAaron LI #define CPUID_0_01_ECX_SSE42 __BIT(20)
394c1d369d5SAaron LI #define CPUID_0_01_ECX_X2APIC __BIT(21)
395c1d369d5SAaron LI #define CPUID_0_01_ECX_MOVBE __BIT(22)
396c1d369d5SAaron LI #define CPUID_0_01_ECX_POPCNT __BIT(23)
397c1d369d5SAaron LI #define CPUID_0_01_ECX_TSC_DEADLINE __BIT(24)
398c1d369d5SAaron LI #define CPUID_0_01_ECX_AESNI __BIT(25)
399c1d369d5SAaron LI #define CPUID_0_01_ECX_XSAVE __BIT(26)
400c1d369d5SAaron LI #define CPUID_0_01_ECX_OSXSAVE __BIT(27)
401c1d369d5SAaron LI #define CPUID_0_01_ECX_AVX __BIT(28)
402c1d369d5SAaron LI #define CPUID_0_01_ECX_F16C __BIT(29)
403c1d369d5SAaron LI #define CPUID_0_01_ECX_RDRAND __BIT(30)
404c1d369d5SAaron LI #define CPUID_0_01_ECX_RAZ __BIT(31)
405c1d369d5SAaron LI /* Fn0000_0001:EDX */
406c1d369d5SAaron LI #define CPUID_0_01_EDX_FPU __BIT(0)
407c1d369d5SAaron LI #define CPUID_0_01_EDX_VME __BIT(1)
408c1d369d5SAaron LI #define CPUID_0_01_EDX_DE __BIT(2)
409c1d369d5SAaron LI #define CPUID_0_01_EDX_PSE __BIT(3)
410c1d369d5SAaron LI #define CPUID_0_01_EDX_TSC __BIT(4)
411c1d369d5SAaron LI #define CPUID_0_01_EDX_MSR __BIT(5)
412c1d369d5SAaron LI #define CPUID_0_01_EDX_PAE __BIT(6)
413c1d369d5SAaron LI #define CPUID_0_01_EDX_MCE __BIT(7)
414c1d369d5SAaron LI #define CPUID_0_01_EDX_CX8 __BIT(8)
415c1d369d5SAaron LI #define CPUID_0_01_EDX_APIC __BIT(9)
416c1d369d5SAaron LI #define CPUID_0_01_EDX_SEP __BIT(11)
417c1d369d5SAaron LI #define CPUID_0_01_EDX_MTRR __BIT(12)
418c1d369d5SAaron LI #define CPUID_0_01_EDX_PGE __BIT(13)
419c1d369d5SAaron LI #define CPUID_0_01_EDX_MCA __BIT(14)
420c1d369d5SAaron LI #define CPUID_0_01_EDX_CMOV __BIT(15)
421c1d369d5SAaron LI #define CPUID_0_01_EDX_PAT __BIT(16)
422c1d369d5SAaron LI #define CPUID_0_01_EDX_PSE36 __BIT(17)
423c1d369d5SAaron LI #define CPUID_0_01_EDX_PSN __BIT(18)
424c1d369d5SAaron LI #define CPUID_0_01_EDX_CLFSH __BIT(19)
425c1d369d5SAaron LI #define CPUID_0_01_EDX_DS __BIT(21)
426c1d369d5SAaron LI #define CPUID_0_01_EDX_ACPI __BIT(22)
427c1d369d5SAaron LI #define CPUID_0_01_EDX_MMX __BIT(23)
428c1d369d5SAaron LI #define CPUID_0_01_EDX_FXSR __BIT(24)
429c1d369d5SAaron LI #define CPUID_0_01_EDX_SSE __BIT(25)
430c1d369d5SAaron LI #define CPUID_0_01_EDX_SSE2 __BIT(26)
431c1d369d5SAaron LI #define CPUID_0_01_EDX_SS __BIT(27)
432c1d369d5SAaron LI #define CPUID_0_01_EDX_HTT __BIT(28)
433c1d369d5SAaron LI #define CPUID_0_01_EDX_TM __BIT(29)
434c1d369d5SAaron LI #define CPUID_0_01_EDX_PBE __BIT(31)
435c1d369d5SAaron LI
436c1d369d5SAaron LI /* Fn0000_0004:EAX (Intel Deterministic Cache Parameter Leaf) */
437c1d369d5SAaron LI #define CPUID_0_04_EAX_CACHETYPE __BITS(4, 0)
438c1d369d5SAaron LI #define CPUID_0_04_EAX_CACHETYPE_NULL 0
439c1d369d5SAaron LI #define CPUID_0_04_EAX_CACHETYPE_DATA 1
440c1d369d5SAaron LI #define CPUID_0_04_EAX_CACHETYPE_INSN 2
441c1d369d5SAaron LI #define CPUID_0_04_EAX_CACHETYPE_UNIFIED 3
442c1d369d5SAaron LI #define CPUID_0_04_EAX_CACHELEVEL __BITS(7, 5)
443c1d369d5SAaron LI #define CPUID_0_04_EAX_SELFINITCL __BIT(8)
444c1d369d5SAaron LI #define CPUID_0_04_EAX_FULLASSOC __BIT(9)
445c1d369d5SAaron LI #define CPUID_0_04_EAX_SHARING __BITS(25, 14)
446c1d369d5SAaron LI #define CPUID_0_04_EAX_CORE_P_PKG __BITS(31, 26)
447c1d369d5SAaron LI
448c1d369d5SAaron LI /* [ECX=0] Fn0000_0007:EBX (Structured Extended Features) */
449c1d369d5SAaron LI #define CPUID_0_07_EBX_FSGSBASE __BIT(0)
450c1d369d5SAaron LI #define CPUID_0_07_EBX_TSC_ADJUST __BIT(1)
451c1d369d5SAaron LI #define CPUID_0_07_EBX_SGX __BIT(2)
452c1d369d5SAaron LI #define CPUID_0_07_EBX_BMI1 __BIT(3)
453c1d369d5SAaron LI #define CPUID_0_07_EBX_HLE __BIT(4)
454c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX2 __BIT(5)
455c1d369d5SAaron LI #define CPUID_0_07_EBX_FDPEXONLY __BIT(6)
456c1d369d5SAaron LI #define CPUID_0_07_EBX_SMEP __BIT(7)
457c1d369d5SAaron LI #define CPUID_0_07_EBX_BMI2 __BIT(8)
458c1d369d5SAaron LI #define CPUID_0_07_EBX_ERMS __BIT(9)
459c1d369d5SAaron LI #define CPUID_0_07_EBX_INVPCID __BIT(10)
460c1d369d5SAaron LI #define CPUID_0_07_EBX_RTM __BIT(11)
461c1d369d5SAaron LI #define CPUID_0_07_EBX_QM __BIT(12)
462c1d369d5SAaron LI #define CPUID_0_07_EBX_FPUCSDS __BIT(13)
463c1d369d5SAaron LI #define CPUID_0_07_EBX_MPX __BIT(14)
464c1d369d5SAaron LI #define CPUID_0_07_EBX_PQE __BIT(15)
465c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512F __BIT(16)
466c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512DQ __BIT(17)
467c1d369d5SAaron LI #define CPUID_0_07_EBX_RDSEED __BIT(18)
468c1d369d5SAaron LI #define CPUID_0_07_EBX_ADX __BIT(19)
469c1d369d5SAaron LI #define CPUID_0_07_EBX_SMAP __BIT(20)
470c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512_IFMA __BIT(21)
471c1d369d5SAaron LI #define CPUID_0_07_EBX_CLFLUSHOPT __BIT(23)
472c1d369d5SAaron LI #define CPUID_0_07_EBX_CLWB __BIT(24)
473c1d369d5SAaron LI #define CPUID_0_07_EBX_PT __BIT(25)
474c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512PF __BIT(26)
475c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512ER __BIT(27)
476c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512CD __BIT(28)
477c1d369d5SAaron LI #define CPUID_0_07_EBX_SHA __BIT(29)
478c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512BW __BIT(30)
479c1d369d5SAaron LI #define CPUID_0_07_EBX_AVX512VL __BIT(31)
480c1d369d5SAaron LI /* [ECX=0] Fn0000_0007:ECX (Structured Extended Features) */
481c1d369d5SAaron LI #define CPUID_0_07_ECX_PREFETCHWT1 __BIT(0)
482c1d369d5SAaron LI #define CPUID_0_07_ECX_AVX512_VBMI __BIT(1)
483c1d369d5SAaron LI #define CPUID_0_07_ECX_UMIP __BIT(2)
484c1d369d5SAaron LI #define CPUID_0_07_ECX_PKU __BIT(3)
485c1d369d5SAaron LI #define CPUID_0_07_ECX_OSPKE __BIT(4)
486c1d369d5SAaron LI #define CPUID_0_07_ECX_WAITPKG __BIT(5)
487c1d369d5SAaron LI #define CPUID_0_07_ECX_AVX512_VBMI2 __BIT(6)
488c1d369d5SAaron LI #define CPUID_0_07_ECX_CET_SS __BIT(7)
489c1d369d5SAaron LI #define CPUID_0_07_ECX_GFNI __BIT(8)
490c1d369d5SAaron LI #define CPUID_0_07_ECX_VAES __BIT(9)
491c1d369d5SAaron LI #define CPUID_0_07_ECX_VPCLMULQDQ __BIT(10)
492c1d369d5SAaron LI #define CPUID_0_07_ECX_AVX512_VNNI __BIT(11)
493c1d369d5SAaron LI #define CPUID_0_07_ECX_AVX512_BITALG __BIT(12)
494c1d369d5SAaron LI #define CPUID_0_07_ECX_AVX512_VPOPCNTDQ __BIT(14)
495c1d369d5SAaron LI #define CPUID_0_07_ECX_LA57 __BIT(16)
496c1d369d5SAaron LI #define CPUID_0_07_ECX_MAWAU __BITS(21, 17)
497c1d369d5SAaron LI #define CPUID_0_07_ECX_RDPID __BIT(22)
498c1d369d5SAaron LI #define CPUID_0_07_ECX_KL __BIT(23)
499c1d369d5SAaron LI #define CPUID_0_07_ECX_CLDEMOTE __BIT(25)
500c1d369d5SAaron LI #define CPUID_0_07_ECX_MOVDIRI __BIT(27)
501c1d369d5SAaron LI #define CPUID_0_07_ECX_MOVDIR64B __BIT(28)
502c1d369d5SAaron LI #define CPUID_0_07_ECX_SGXLC __BIT(30)
503c1d369d5SAaron LI #define CPUID_0_07_ECX_PKS __BIT(31)
504c1d369d5SAaron LI /* [ECX=0] Fn0000_0007:EDX (Structured Extended Features) */
505c1d369d5SAaron LI #define CPUID_0_07_EDX_AVX512_4VNNIW __BIT(2)
506c1d369d5SAaron LI #define CPUID_0_07_EDX_AVX512_4FMAPS __BIT(3)
507c1d369d5SAaron LI #define CPUID_0_07_EDX_FSREP_MOV __BIT(4)
508c1d369d5SAaron LI #define CPUID_0_07_EDX_AVX512_VP2INTERSECT __BIT(8)
509c1d369d5SAaron LI #define CPUID_0_07_EDX_SRBDS_CTRL __BIT(9)
510c1d369d5SAaron LI #define CPUID_0_07_EDX_MD_CLEAR __BIT(10)
511c1d369d5SAaron LI #define CPUID_0_07_EDX_TSX_FORCE_ABORT __BIT(13)
512c1d369d5SAaron LI #define CPUID_0_07_EDX_SERIALIZE __BIT(14)
513c1d369d5SAaron LI #define CPUID_0_07_EDX_HYBRID __BIT(15)
514c1d369d5SAaron LI #define CPUID_0_07_EDX_TSXLDTRK __BIT(16)
515c1d369d5SAaron LI #define CPUID_0_07_EDX_CET_IBT __BIT(20)
516c1d369d5SAaron LI #define CPUID_0_07_EDX_IBRS __BIT(26)
517c1d369d5SAaron LI #define CPUID_0_07_EDX_STIBP __BIT(27)
518c1d369d5SAaron LI #define CPUID_0_07_EDX_L1D_FLUSH __BIT(28)
519c1d369d5SAaron LI #define CPUID_0_07_EDX_ARCH_CAP __BIT(29)
520c1d369d5SAaron LI #define CPUID_0_07_EDX_CORE_CAP __BIT(30)
521c1d369d5SAaron LI #define CPUID_0_07_EDX_SSBD __BIT(31)
522c1d369d5SAaron LI
523c1d369d5SAaron LI /* Fn0000_000B:EAX (Extended Topology Enumeration) */
524c1d369d5SAaron LI #define CPUID_0_0B_EAX_SHIFTNUM __BITS(4, 0)
525c1d369d5SAaron LI /* Fn0000_000B:ECX (Extended Topology Enumeration) */
526c1d369d5SAaron LI #define CPUID_0_0B_ECX_LVLNUM __BITS(7, 0)
527c1d369d5SAaron LI #define CPUID_0_0B_ECX_LVLTYPE __BITS(15, 8)
528c1d369d5SAaron LI #define CPUID_0_0B_ECX_LVLTYPE_INVAL 0
529c1d369d5SAaron LI #define CPUID_0_0B_ECX_LVLTYPE_SMT 1
530c1d369d5SAaron LI #define CPUID_0_0B_ECX_LVLTYPE_CORE 2
531c1d369d5SAaron LI
532c1d369d5SAaron LI /* [ECX=1] Fn0000_000D:EAX (Processor Extended State Enumeration) */
533c1d369d5SAaron LI #define CPUID_0_0D_ECX1_EAX_XSAVEOPT __BIT(0)
534c1d369d5SAaron LI #define CPUID_0_0D_ECX1_EAX_XSAVEC __BIT(1)
535c1d369d5SAaron LI #define CPUID_0_0D_ECX1_EAX_XGETBV __BIT(2)
536c1d369d5SAaron LI #define CPUID_0_0D_ECX1_EAX_XSAVES __BIT(3)
537c1d369d5SAaron LI
538c1d369d5SAaron LI /* Fn8000_0001:ECX */
539c1d369d5SAaron LI #define CPUID_8_01_ECX_LAHF __BIT(0)
540c1d369d5SAaron LI #define CPUID_8_01_ECX_CMPLEGACY __BIT(1)
541c1d369d5SAaron LI #define CPUID_8_01_ECX_SVM __BIT(2)
542c1d369d5SAaron LI #define CPUID_8_01_ECX_EAPIC __BIT(3)
543c1d369d5SAaron LI #define CPUID_8_01_ECX_ALTMOVCR8 __BIT(4)
544c1d369d5SAaron LI #define CPUID_8_01_ECX_ABM __BIT(5)
545c1d369d5SAaron LI #define CPUID_8_01_ECX_SSE4A __BIT(6)
546c1d369d5SAaron LI #define CPUID_8_01_ECX_MISALIGNSSE __BIT(7)
547c1d369d5SAaron LI #define CPUID_8_01_ECX_3DNOWPF __BIT(8)
548c1d369d5SAaron LI #define CPUID_8_01_ECX_OSVW __BIT(9)
549c1d369d5SAaron LI #define CPUID_8_01_ECX_IBS __BIT(10)
550c1d369d5SAaron LI #define CPUID_8_01_ECX_XOP __BIT(11)
551c1d369d5SAaron LI #define CPUID_8_01_ECX_SKINIT __BIT(12)
552c1d369d5SAaron LI #define CPUID_8_01_ECX_WDT __BIT(13)
553c1d369d5SAaron LI #define CPUID_8_01_ECX_LWP __BIT(15)
554c1d369d5SAaron LI #define CPUID_8_01_ECX_FMA4 __BIT(16)
555c1d369d5SAaron LI #define CPUID_8_01_ECX_TCE __BIT(17)
556c1d369d5SAaron LI #define CPUID_8_01_ECX_NODEID __BIT(19)
557c1d369d5SAaron LI #define CPUID_8_01_ECX_TBM __BIT(21)
558c1d369d5SAaron LI #define CPUID_8_01_ECX_TOPOEXT __BIT(22)
559c1d369d5SAaron LI #define CPUID_8_01_ECX_PCEC __BIT(23)
560c1d369d5SAaron LI #define CPUID_8_01_ECX_PCENB __BIT(24)
561c1d369d5SAaron LI #define CPUID_8_01_ECX_DBE __BIT(26)
562c1d369d5SAaron LI #define CPUID_8_01_ECX_PERFTSC __BIT(27)
563c1d369d5SAaron LI #define CPUID_8_01_ECX_PERFEXTLLC __BIT(28)
564c1d369d5SAaron LI #define CPUID_8_01_ECX_MWAITX __BIT(29)
565c1d369d5SAaron LI /* Fn8000_0001:EDX */
566c1d369d5SAaron LI #define CPUID_8_01_EDX_FPU __BIT(0)
567c1d369d5SAaron LI #define CPUID_8_01_EDX_VME __BIT(1)
568c1d369d5SAaron LI #define CPUID_8_01_EDX_DE __BIT(2)
569c1d369d5SAaron LI #define CPUID_8_01_EDX_PSE __BIT(3)
570c1d369d5SAaron LI #define CPUID_8_01_EDX_TSC __BIT(4)
571c1d369d5SAaron LI #define CPUID_8_01_EDX_MSR __BIT(5)
572c1d369d5SAaron LI #define CPUID_8_01_EDX_PAE __BIT(6)
573c1d369d5SAaron LI #define CPUID_8_01_EDX_MCE __BIT(7)
574c1d369d5SAaron LI #define CPUID_8_01_EDX_CX8 __BIT(8)
575c1d369d5SAaron LI #define CPUID_8_01_EDX_APIC __BIT(9)
576c1d369d5SAaron LI #define CPUID_8_01_EDX_SYSCALL __BIT(11)
577c1d369d5SAaron LI #define CPUID_8_01_EDX_MTRR __BIT(12)
578c1d369d5SAaron LI #define CPUID_8_01_EDX_PGE __BIT(13)
579c1d369d5SAaron LI #define CPUID_8_01_EDX_MCA __BIT(14)
580c1d369d5SAaron LI #define CPUID_8_01_EDX_CMOV __BIT(15)
581c1d369d5SAaron LI #define CPUID_8_01_EDX_PAT __BIT(16)
582c1d369d5SAaron LI #define CPUID_8_01_EDX_PSE36 __BIT(17)
583c1d369d5SAaron LI #define CPUID_8_01_EDX_XD __BIT(20)
584c1d369d5SAaron LI #define CPUID_8_01_EDX_MMXEXT __BIT(22)
585c1d369d5SAaron LI #define CPUID_8_01_EDX_MMX __BIT(23)
586c1d369d5SAaron LI #define CPUID_8_01_EDX_FXSR __BIT(24)
587c1d369d5SAaron LI #define CPUID_8_01_EDX_FFXSR __BIT(25)
588c1d369d5SAaron LI #define CPUID_8_01_EDX_PAGE1GB __BIT(26)
589c1d369d5SAaron LI #define CPUID_8_01_EDX_RDTSCP __BIT(27)
590c1d369d5SAaron LI #define CPUID_8_01_EDX_LM __BIT(29)
591c1d369d5SAaron LI #define CPUID_8_01_EDX_3DNOWEXT __BIT(30)
592c1d369d5SAaron LI #define CPUID_8_01_EDX_3DNOW __BIT(31)
593c1d369d5SAaron LI
594c1d369d5SAaron LI /* Fn8000_0007:EDX (Advanced Power Management) */
595c1d369d5SAaron LI #define CPUID_8_07_EDX_TS __BIT(0)
596c1d369d5SAaron LI #define CPUID_8_07_EDX_FID __BIT(1)
597c1d369d5SAaron LI #define CPUID_8_07_EDX_VID __BIT(2)
598c1d369d5SAaron LI #define CPUID_8_07_EDX_TTP __BIT(3)
599c1d369d5SAaron LI #define CPUID_8_07_EDX_TM __BIT(4)
600c1d369d5SAaron LI #define CPUID_8_07_EDX_100MHzSteps __BIT(6)
601c1d369d5SAaron LI #define CPUID_8_07_EDX_HwPstate __BIT(7)
602c1d369d5SAaron LI #define CPUID_8_07_EDX_TscInvariant __BIT(8)
603c1d369d5SAaron LI #define CPUID_8_07_EDX_CPB __BIT(9)
604c1d369d5SAaron LI #define CPUID_8_07_EDX_EffFreqRO __BIT(10)
605c1d369d5SAaron LI #define CPUID_8_07_EDX_ProcFeedbackIntf __BIT(11)
606c1d369d5SAaron LI #define CPUID_8_07_EDX_ProcPowerReport __BIT(12)
607c1d369d5SAaron LI
608c1d369d5SAaron LI /* Fn8000_0008:EBX */
609c1d369d5SAaron LI #define CPUID_8_08_EBX_CLZERO __BIT(0)
610c1d369d5SAaron LI #define CPUID_8_08_EBX_InstRetCntMsr __BIT(1)
611c1d369d5SAaron LI #define CPUID_8_08_EBX_RstrFpErrPtrs __BIT(2)
612c1d369d5SAaron LI #define CPUID_8_08_EBX_INVLPGB __BIT(3)
613c1d369d5SAaron LI #define CPUID_8_08_EBX_RDPRU __BIT(4)
614c1d369d5SAaron LI #define CPUID_8_08_EBX_MCOMMIT __BIT(8)
615c1d369d5SAaron LI #define CPUID_8_08_EBX_WBNOINVD __BIT(9)
616c1d369d5SAaron LI #define CPUID_8_08_EBX_IBPB __BIT(12)
617c1d369d5SAaron LI #define CPUID_8_08_EBX_INT_WBINVD __BIT(13)
618c1d369d5SAaron LI #define CPUID_8_08_EBX_IBRS __BIT(14)
619c1d369d5SAaron LI #define CPUID_8_08_EBX_STIBP __BIT(15)
620c1d369d5SAaron LI #define CPUID_8_08_EBX_IBRS_ALWAYSON __BIT(16)
621c1d369d5SAaron LI #define CPUID_8_08_EBX_STIBP_ALWAYSON __BIT(17)
622c1d369d5SAaron LI #define CPUID_8_08_EBX_PREFER_IBRS __BIT(18)
623c1d369d5SAaron LI #define CPUID_8_08_EBX_EferLmsleUnsupp __BIT(20)
624c1d369d5SAaron LI #define CPUID_8_08_EBX_INVLPGBnestedPg __BIT(21)
625c1d369d5SAaron LI #define CPUID_8_08_EBX_SSBD __BIT(24)
626c1d369d5SAaron LI #define CPUID_8_08_EBX_VIRT_SSBD __BIT(25)
627c1d369d5SAaron LI #define CPUID_8_08_EBX_SSB_NO __BIT(26)
628c1d369d5SAaron LI /* Fn8000_0008:ECX */
629c1d369d5SAaron LI #define CPUID_8_08_ECX_NC __BITS(7,0)
630c1d369d5SAaron LI #define CPUID_8_08_ECX_ApicIdSize __BITS(15,12)
631c1d369d5SAaron LI #define CPUID_8_08_ECX_PerfTscSize __BITS(17,16)
632c1d369d5SAaron LI
633c1d369d5SAaron LI /* Fn8000_000A:EAX (SVM features) */
634c1d369d5SAaron LI #define CPUID_8_0A_EAX_SvmRev __BITS(7,0)
635c1d369d5SAaron LI /* Fn8000_000A:EDX (SVM features) */
636c1d369d5SAaron LI #define CPUID_8_0A_EDX_NP __BIT(0)
637c1d369d5SAaron LI #define CPUID_8_0A_EDX_LbrVirt __BIT(1)
638c1d369d5SAaron LI #define CPUID_8_0A_EDX_SVML __BIT(2)
639c1d369d5SAaron LI #define CPUID_8_0A_EDX_NRIPS __BIT(3)
640c1d369d5SAaron LI #define CPUID_8_0A_EDX_TscRateMsr __BIT(4)
641c1d369d5SAaron LI #define CPUID_8_0A_EDX_VmcbClean __BIT(5)
642c1d369d5SAaron LI #define CPUID_8_0A_EDX_FlushByASID __BIT(6)
643c1d369d5SAaron LI #define CPUID_8_0A_EDX_DecodeAssists __BIT(7)
644c1d369d5SAaron LI #define CPUID_8_0A_EDX_PauseFilter __BIT(10)
645c1d369d5SAaron LI #define CPUID_8_0A_EDX_PFThreshold __BIT(12)
646c1d369d5SAaron LI #define CPUID_8_0A_EDX_AVIC __BIT(13)
647c1d369d5SAaron LI #define CPUID_8_0A_EDX_VMSAVEvirt __BIT(15)
648c1d369d5SAaron LI #define CPUID_8_0A_EDX_VGIF __BIT(16)
649c1d369d5SAaron LI #define CPUID_8_0A_EDX_GMET __BIT(17)
650c1d369d5SAaron LI #define CPUID_8_0A_EDX_SSSCheck __BIT(19)
651c1d369d5SAaron LI #define CPUID_8_0A_EDX_SpecCtrl __BIT(20)
652c1d369d5SAaron LI #define CPUID_8_0A_EDX_TlbiCtl __BIT(24)
653c1d369d5SAaron LI
654c1d369d5SAaron LI /* -------------------------------------------------------------------------- */
655c1d369d5SAaron LI
65642862644SAaron LI /*
65742862644SAaron LI * Register defines. We mainly rely on the already-existing OS definitions.
65842862644SAaron LI */
65942862644SAaron LI
66042862644SAaron LI #if defined(__DragonFly__)
66142862644SAaron LI
66242862644SAaron LI #define XCR0_X87 CPU_XFEATURE_X87 /* 0x00000001 */
66342862644SAaron LI #define XCR0_SSE CPU_XFEATURE_SSE /* 0x00000002 */
66442862644SAaron LI
66542862644SAaron LI #define MSR_MISC_ENABLE MSR_IA32_MISC_ENABLE /* 0x1a0 */
66642862644SAaron LI #define MSR_CR_PAT MSR_PAT /* 0x277 */
66742862644SAaron LI #define MSR_SFMASK MSR_SF_MASK /* 0xc0000084 */
66842862644SAaron LI #define MSR_KERNELGSBASE MSR_KGSBASE /* 0xc0000102 */
66942862644SAaron LI #define MSR_NB_CFG MSR_AMD_NB_CFG /* 0xc001001f */
67042862644SAaron LI #define MSR_IC_CFG MSR_AMD_IC_CFG /* 0xc0011021 */
67142862644SAaron LI #define MSR_DE_CFG MSR_AMD_DE_CFG /* 0xc0011029 */
67242862644SAaron LI #define MSR_UCODE_AMD_PATCHLEVEL MSR_AMD_PATCH_LEVEL /* 0x0000008b */
67342862644SAaron LI
67442862644SAaron LI /* MSR_IA32_ARCH_CAPABILITIES (0x10a) */
67542862644SAaron LI #define IA32_ARCH_RDCL_NO IA32_ARCH_CAP_RDCL_NO
67642862644SAaron LI #define IA32_ARCH_IBRS_ALL IA32_ARCH_CAP_IBRS_ALL
67742862644SAaron LI #define IA32_ARCH_RSBA IA32_ARCH_CAP_RSBA
67842862644SAaron LI #define IA32_ARCH_SKIP_L1DFL_VMENTRY IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY
67942862644SAaron LI #define IA32_ARCH_SSB_NO IA32_ARCH_CAP_SSB_NO
68042862644SAaron LI #define IA32_ARCH_MDS_NO IA32_ARCH_CAP_MDS_NO
68142862644SAaron LI #define IA32_ARCH_IF_PSCHANGE_MC_NO IA32_ARCH_CAP_IF_PSCHANGE_MC_NO
68242862644SAaron LI #define IA32_ARCH_TSX_CTRL IA32_ARCH_CAP_TSX_CTRL
68342862644SAaron LI #define IA32_ARCH_TAA_NO IA32_ARCH_CAP_TAA_NO
68442862644SAaron LI
68542862644SAaron LI /* MSR_IA32_FLUSH_CMD (0x10b) */
68642862644SAaron LI #define IA32_FLUSH_CMD_L1D_FLUSH IA32_FLUSH_CMD_L1D
68742862644SAaron LI
68842862644SAaron LI #endif /* __DragonFly__ */
68942862644SAaron LI
69042862644SAaron LI /* -------------------------------------------------------------------------- */
69142862644SAaron LI
6926d65b43dSAaron LI #ifdef _KERNEL
6936d65b43dSAaron LI #define NVMM_X86_MACH_NCONF 0
6946d65b43dSAaron LI #define NVMM_X86_VCPU_NCONF 2
69523b2397dSAaron LI
6966d65b43dSAaron LI struct nvmm_x86_cpuid_mask {
6976d65b43dSAaron LI uint32_t eax;
6986d65b43dSAaron LI uint32_t ebx;
6996d65b43dSAaron LI uint32_t ecx;
7006d65b43dSAaron LI uint32_t edx;
7016d65b43dSAaron LI };
70223b2397dSAaron LI
70323b2397dSAaron LI /* FPU area + XSAVE header. */
70423b2397dSAaron LI struct nvmm_x86_xsave {
70523b2397dSAaron LI struct nvmm_x64_state_fpu fpu;
70623b2397dSAaron LI uint64_t xstate_bv;
70723b2397dSAaron LI uint64_t xcomp_bv;
70823b2397dSAaron LI uint8_t rsvd0[8];
70923b2397dSAaron LI uint8_t rsvd[40];
71023b2397dSAaron LI };
71123b2397dSAaron LI CTASSERT(sizeof(struct nvmm_x86_xsave) == 512 + 64);
71223b2397dSAaron LI
7136d65b43dSAaron LI extern const struct nvmm_x64_state nvmm_x86_reset_state;
7146d65b43dSAaron LI extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001;
7156d65b43dSAaron LI extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007;
7166d65b43dSAaron LI extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001;
7176d65b43dSAaron LI extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000007;
7186d65b43dSAaron LI extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000008;
71923b2397dSAaron LI
7206d65b43dSAaron LI bool nvmm_x86_pat_validate(uint64_t);
72123b2397dSAaron LI uint32_t nvmm_x86_xsave_size(uint64_t);
72242862644SAaron LI
72342862644SAaron LI /* -------------------------------------------------------------------------- */
72442862644SAaron LI
72542862644SAaron LI /*
72642862644SAaron LI * ASM defines. We mainly rely on the already-existing OS definitions.
72742862644SAaron LI */
72842862644SAaron LI
72942862644SAaron LI #if defined(__NetBSD__)
73042862644SAaron LI #include <x86/cpufunc.h>
73142862644SAaron LI #include <x86/fpu.h>
73242862644SAaron LI #elif defined(__DragonFly__)
73342862644SAaron LI #include <machine/cpufunc.h>
73442862644SAaron LI #include <machine/npx.h>
73542862644SAaron LI #endif
73642862644SAaron LI
73742862644SAaron LI /* CPUID. */
73842862644SAaron LI typedef struct {
73942862644SAaron LI uint32_t eax, ebx, ecx, edx;
74042862644SAaron LI } cpuid_desc_t;
74142862644SAaron LI
74242862644SAaron LI #if defined(__NetBSD__)
74342862644SAaron LI #define x86_get_cpuid(l, d) x86_cpuid(l, (uint32_t *)d)
74442862644SAaron LI #define x86_get_cpuid2(l, c, d) x86_cpuid2(l, c, (uint32_t *)d)
74542862644SAaron LI #elif defined(__DragonFly__)
74642862644SAaron LI #define x86_get_cpuid(l, d) do_cpuid(l, (uint32_t *)d)
74742862644SAaron LI #define x86_get_cpuid2(l, c, d) cpuid_count(l, c, (uint32_t *)d)
74842862644SAaron LI #endif
74942862644SAaron LI
75042862644SAaron LI /* Control registers. */
75142862644SAaron LI #if defined(__NetBSD__)
75242862644SAaron LI #define x86_get_cr0() rcr0()
75342862644SAaron LI #define x86_get_cr2() rcr2()
75442862644SAaron LI #define x86_get_cr3() rcr3()
75542862644SAaron LI #define x86_get_cr4() rcr4()
75642862644SAaron LI #define x86_set_cr0(v) lcr0(v)
75742862644SAaron LI #define x86_set_cr2(v) lcr2(v)
75842862644SAaron LI #define x86_set_cr4(v) lcr4(v)
75942862644SAaron LI #elif defined(__DragonFly__)
76042862644SAaron LI #define x86_get_cr0() rcr0()
76142862644SAaron LI #define x86_get_cr2() rcr2()
76242862644SAaron LI #define x86_get_cr3() rcr3()
76342862644SAaron LI #define x86_get_cr4() rcr4()
76442862644SAaron LI #define x86_set_cr0(v) load_cr0(v)
76542862644SAaron LI #define x86_set_cr2(v) load_cr2(v)
76642862644SAaron LI #define x86_set_cr4(v) load_cr4(v)
76742862644SAaron LI #endif
76842862644SAaron LI
76942862644SAaron LI /* Debug registers. */
77042862644SAaron LI #if defined(__NetBSD__)
771*b3f7271cSAaron LI #include <x86/dbregs.h>
772*b3f7271cSAaron LI static inline void
x86_curthread_save_dbregs(uint64_t * drs __unused)773*b3f7271cSAaron LI x86_curthread_save_dbregs(uint64_t *drs __unused)
774*b3f7271cSAaron LI {
775*b3f7271cSAaron LI x86_dbregs_save(curlwp);
776*b3f7271cSAaron LI }
777*b3f7271cSAaron LI static inline void
x86_curthread_restore_dbregs(uint64_t * drs __unused)778*b3f7271cSAaron LI x86_curthread_restore_dbregs(uint64_t *drs __unused)
779*b3f7271cSAaron LI {
780*b3f7271cSAaron LI x86_dbregs_restore(curlwp);
781*b3f7271cSAaron LI }
78242862644SAaron LI #define x86_get_dr0() rdr0()
78342862644SAaron LI #define x86_get_dr1() rdr1()
78442862644SAaron LI #define x86_get_dr2() rdr2()
78542862644SAaron LI #define x86_get_dr3() rdr3()
78642862644SAaron LI #define x86_get_dr6() rdr6()
78742862644SAaron LI #define x86_get_dr7() rdr7()
78842862644SAaron LI #define x86_set_dr0(v) ldr0(v)
78942862644SAaron LI #define x86_set_dr1(v) ldr1(v)
79042862644SAaron LI #define x86_set_dr2(v) ldr2(v)
79142862644SAaron LI #define x86_set_dr3(v) ldr3(v)
79242862644SAaron LI #define x86_set_dr6(v) ldr6(v)
79342862644SAaron LI #define x86_set_dr7(v) ldr7(v)
79442862644SAaron LI #elif defined(__DragonFly__)
795*b3f7271cSAaron LI #include <sys/proc.h> /* struct lwp */
796*b3f7271cSAaron LI static inline void
x86_curthread_save_dbregs(uint64_t * drs)797*b3f7271cSAaron LI x86_curthread_save_dbregs(uint64_t *drs)
798*b3f7271cSAaron LI {
799*b3f7271cSAaron LI struct pcb *pcb = curthread->td_lwp->lwp_thread->td_pcb;
800*b3f7271cSAaron LI
801*b3f7271cSAaron LI if (__predict_true(!(pcb->pcb_flags & PCB_DBREGS)))
802*b3f7271cSAaron LI return;
803*b3f7271cSAaron LI
804*b3f7271cSAaron LI drs[NVMM_X64_DR_DR0] = rdr0();
805*b3f7271cSAaron LI drs[NVMM_X64_DR_DR1] = rdr1();
806*b3f7271cSAaron LI drs[NVMM_X64_DR_DR2] = rdr2();
807*b3f7271cSAaron LI drs[NVMM_X64_DR_DR3] = rdr3();
808*b3f7271cSAaron LI drs[NVMM_X64_DR_DR6] = rdr6();
809*b3f7271cSAaron LI drs[NVMM_X64_DR_DR7] = rdr7();
810*b3f7271cSAaron LI }
811*b3f7271cSAaron LI static inline void
x86_curthread_restore_dbregs(uint64_t * drs)812*b3f7271cSAaron LI x86_curthread_restore_dbregs(uint64_t *drs)
813*b3f7271cSAaron LI {
814*b3f7271cSAaron LI struct pcb *pcb = curthread->td_lwp->lwp_thread->td_pcb;
815*b3f7271cSAaron LI
816*b3f7271cSAaron LI if (__predict_true(!(pcb->pcb_flags & PCB_DBREGS)))
817*b3f7271cSAaron LI return;
818*b3f7271cSAaron LI
819*b3f7271cSAaron LI load_dr0(drs[NVMM_X64_DR_DR0]);
820*b3f7271cSAaron LI load_dr1(drs[NVMM_X64_DR_DR1]);
821*b3f7271cSAaron LI load_dr2(drs[NVMM_X64_DR_DR2]);
822*b3f7271cSAaron LI load_dr3(drs[NVMM_X64_DR_DR3]);
823*b3f7271cSAaron LI load_dr6(drs[NVMM_X64_DR_DR6]);
824*b3f7271cSAaron LI load_dr7(drs[NVMM_X64_DR_DR7]);
825*b3f7271cSAaron LI }
82642862644SAaron LI #define x86_get_dr0() rdr0()
82742862644SAaron LI #define x86_get_dr1() rdr1()
82842862644SAaron LI #define x86_get_dr2() rdr2()
82942862644SAaron LI #define x86_get_dr3() rdr3()
83042862644SAaron LI #define x86_get_dr6() rdr6()
83142862644SAaron LI #define x86_get_dr7() rdr7()
83242862644SAaron LI #define x86_set_dr0(v) load_dr0(v)
83342862644SAaron LI #define x86_set_dr1(v) load_dr1(v)
83442862644SAaron LI #define x86_set_dr2(v) load_dr2(v)
83542862644SAaron LI #define x86_set_dr3(v) load_dr3(v)
83642862644SAaron LI #define x86_set_dr6(v) load_dr6(v)
83742862644SAaron LI #define x86_set_dr7(v) load_dr7(v)
8381467e875SAaron LI #endif
83942862644SAaron LI
84042862644SAaron LI /* FPU. */
84142862644SAaron LI #if defined(__NetBSD__)
84242862644SAaron LI #define x86_curthread_save_fpu() fpu_kern_enter()
84342862644SAaron LI #define x86_curthread_restore_fpu() fpu_kern_leave()
84442862644SAaron LI #define x86_save_fpu(a, m) fpu_area_save(a, m, true)
84542862644SAaron LI #define x86_restore_fpu(a, m) fpu_area_restore(a, m, true)
84642862644SAaron LI #elif defined(__DragonFly__)
84742862644SAaron LI #define x86_curthread_save_fpu() /* TODO */
84842862644SAaron LI #define x86_curthread_restore_fpu() /* TODO */
84942862644SAaron LI #define x86_save_fpu(a, m) \
85042862644SAaron LI ({ \
85142862644SAaron LI fpusave((union savefpu *)(a), m); \
85242862644SAaron LI load_cr0(rcr0() | CR0_TS); \
85342862644SAaron LI })
85442862644SAaron LI #define x86_restore_fpu(a, m) \
85542862644SAaron LI ({ \
856e0cf4209SAaron LI __asm volatile("clts" ::: "memory"); \
85742862644SAaron LI fpurstor((union savefpu *)(a), m); \
85842862644SAaron LI })
8591467e875SAaron LI #endif
86042862644SAaron LI
86142862644SAaron LI /* XCRs. */
86242862644SAaron LI static inline uint64_t
x86_get_xcr(uint32_t xcr)86342862644SAaron LI x86_get_xcr(uint32_t xcr)
86442862644SAaron LI {
86542862644SAaron LI uint32_t low, high;
86642862644SAaron LI
86742862644SAaron LI __asm volatile (
86842862644SAaron LI "xgetbv"
86942862644SAaron LI : "=a" (low), "=d" (high)
87042862644SAaron LI : "c" (xcr)
87142862644SAaron LI );
87242862644SAaron LI
87342862644SAaron LI return (low | ((uint64_t)high << 32));
87442862644SAaron LI }
87542862644SAaron LI
87642862644SAaron LI static inline void
x86_set_xcr(uint32_t xcr,uint64_t val)87742862644SAaron LI x86_set_xcr(uint32_t xcr, uint64_t val)
87842862644SAaron LI {
87942862644SAaron LI uint32_t low, high;
88042862644SAaron LI
88142862644SAaron LI low = val;
88242862644SAaron LI high = val >> 32;
88342862644SAaron LI __asm volatile (
88442862644SAaron LI "xsetbv"
88542862644SAaron LI :
88642862644SAaron LI : "a" (low), "d" (high), "c" (xcr)
88742862644SAaron LI : "memory"
88842862644SAaron LI );
88942862644SAaron LI }
89042862644SAaron LI
89142862644SAaron LI #if defined(__DragonFly__)
89242862644SAaron LI #define x86_xsave_features npx_xcr0_mask
89342862644SAaron LI #define x86_fpu_mxcsr_mask npx_mxcsr_mask
89442862644SAaron LI #endif
89542862644SAaron LI
89623b2397dSAaron LI #endif /* _KERNEL */
8976d65b43dSAaron LI
8986d65b43dSAaron LI #endif /* ASM_NVMM */
8996d65b43dSAaron LI
9006d65b43dSAaron LI #endif /* _NVMM_X86_H_ */
901