132176cfdSRui Paulo /*- 232176cfdSRui Paulo * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 332176cfdSRui Paulo * Copyright (c) 2007-2009 Intel Corporation 432176cfdSRui Paulo * All rights reserved. 532176cfdSRui Paulo * 632176cfdSRui Paulo * Redistribution and use in source and binary forms, with or without 732176cfdSRui Paulo * modification, are permitted provided that the following conditions 832176cfdSRui Paulo * are met: 932176cfdSRui Paulo * 1. Redistributions of source code must retain the above copyright 1032176cfdSRui Paulo * notice, this list of conditions and the following disclaimer. 1132176cfdSRui Paulo * 2. Redistributions in binary form must reproduce the above copyright 1232176cfdSRui Paulo * notice, this list of conditions and the following disclaimer in the 1332176cfdSRui Paulo * documentation and/or other materials provided with the distribution. 1432176cfdSRui Paulo * 1532176cfdSRui Paulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1632176cfdSRui Paulo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1732176cfdSRui Paulo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1832176cfdSRui Paulo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1932176cfdSRui Paulo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2032176cfdSRui Paulo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2132176cfdSRui Paulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2232176cfdSRui Paulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2332176cfdSRui Paulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2432176cfdSRui Paulo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2532176cfdSRui Paulo * 26085ff963SMatthew Dillon * $FreeBSD$ 2732176cfdSRui Paulo */ 2832176cfdSRui Paulo #ifndef _NET80211_IEEE80211_TDMA_H_ 2932176cfdSRui Paulo #define _NET80211_IEEE80211_TDMA_H_ 3032176cfdSRui Paulo 3132176cfdSRui Paulo /* 3232176cfdSRui Paulo * TDMA-mode implementation definitions. 3332176cfdSRui Paulo */ 3432176cfdSRui Paulo 3532176cfdSRui Paulo #define TDMA_SUBTYPE_PARAM 0x01 3632176cfdSRui Paulo #define TDMA_VERSION_V2 2 3732176cfdSRui Paulo #define TDMA_VERSION TDMA_VERSION_V2 3832176cfdSRui Paulo 3932176cfdSRui Paulo /* NB: we only support 2 right now but protocol handles up to 8 */ 4032176cfdSRui Paulo #define TDMA_MAXSLOTS 2 /* max slots/sta's */ 4132176cfdSRui Paulo 4232176cfdSRui Paulo #define TDMA_PARAM_LEN_V2 sizeof(struct ieee80211_tdma_param) 4332176cfdSRui Paulo 4432176cfdSRui Paulo /* 4532176cfdSRui Paulo * TDMA information element. 4632176cfdSRui Paulo */ 4732176cfdSRui Paulo struct ieee80211_tdma_param { 4832176cfdSRui Paulo u_int8_t tdma_id; /* IEEE80211_ELEMID_VENDOR */ 4932176cfdSRui Paulo u_int8_t tdma_len; 5032176cfdSRui Paulo u_int8_t tdma_oui[3]; /* TDMA_OUI */ 5132176cfdSRui Paulo u_int8_t tdma_type; /* TDMA_OUI_TYPE */ 5232176cfdSRui Paulo u_int8_t tdma_subtype; /* TDMA_SUBTYPE_PARAM */ 5332176cfdSRui Paulo u_int8_t tdma_version; /* spec revision */ 5432176cfdSRui Paulo u_int8_t tdma_slot; /* station slot # [0..7] */ 5532176cfdSRui Paulo u_int8_t tdma_slotcnt; /* bss slot count [1..8] */ 5632176cfdSRui Paulo u_int16_t tdma_slotlen; /* bss slot len (100us) */ 5732176cfdSRui Paulo u_int8_t tdma_bintval; /* beacon interval (superframes) */ 5832176cfdSRui Paulo u_int8_t tdma_inuse[1]; /* slot occupancy map */ 5932176cfdSRui Paulo u_int8_t tdma_pad[2]; 6032176cfdSRui Paulo u_int8_t tdma_tstamp[8]; /* timestamp from last beacon */ 6132176cfdSRui Paulo } __packed; 6232176cfdSRui Paulo 6332176cfdSRui Paulo #ifdef _KERNEL 6432176cfdSRui Paulo /* 6532176cfdSRui Paulo * Implementation state. 6632176cfdSRui Paulo */ 6732176cfdSRui Paulo struct ieee80211_tdma_state { 6832176cfdSRui Paulo u_int tdma_slotlen; /* bss slot length (us) */ 6932176cfdSRui Paulo uint8_t tdma_version; /* protocol version to use */ 7032176cfdSRui Paulo uint8_t tdma_slotcnt; /* bss slot count */ 7132176cfdSRui Paulo uint8_t tdma_bintval; /* beacon interval (slots) */ 7232176cfdSRui Paulo uint8_t tdma_slot; /* station slot # */ 7332176cfdSRui Paulo uint8_t tdma_inuse[1]; /* mask of slots in use */ 7432176cfdSRui Paulo uint8_t tdma_active[1]; /* mask of active slots */ 7532176cfdSRui Paulo int tdma_count; /* active/inuse countdown */ 7632176cfdSRui Paulo void *tdma_peer; /* peer station cookie */ 7732176cfdSRui Paulo struct timeval tdma_lastprint; /* time of last rate-limited printf */ 7832176cfdSRui Paulo int tdma_fails; /* fail count for rate-limiting */ 7932176cfdSRui Paulo 8032176cfdSRui Paulo /* parent method pointers */ 8132176cfdSRui Paulo int (*tdma_newstate)(struct ieee80211vap *, enum ieee80211_state, 8232176cfdSRui Paulo int arg); 8332176cfdSRui Paulo void (*tdma_recv_mgmt)(struct ieee80211_node *, 84*4f898719SImre Vadász struct mbuf *, int, 85*4f898719SImre Vadász const struct ieee80211_rx_stats *rxs, int, int); 8632176cfdSRui Paulo void (*tdma_opdetach)(struct ieee80211vap *); 8732176cfdSRui Paulo }; 8832176cfdSRui Paulo 8932176cfdSRui Paulo #define TDMA_UPDATE_SLOT 0x0001 /* tdma_slot changed */ 9032176cfdSRui Paulo #define TDMA_UPDATE_SLOTCNT 0x0002 /* tdma_slotcnt changed */ 9132176cfdSRui Paulo #define TDMA_UPDATE_SLOTLEN 0x0004 /* tdma_slotlen changed */ 9232176cfdSRui Paulo #define TDMA_UPDATE_BINTVAL 0x0008 /* tdma_bintval changed */ 9332176cfdSRui Paulo 9432176cfdSRui Paulo void ieee80211_tdma_vattach(struct ieee80211vap *); 9532176cfdSRui Paulo 9632176cfdSRui Paulo int ieee80211_tdma_getslot(struct ieee80211vap *vap); 9732176cfdSRui Paulo void ieee80211_parse_tdma(struct ieee80211_node *ni, const uint8_t *ie); 9832176cfdSRui Paulo uint8_t *ieee80211_add_tdma(uint8_t *frm, struct ieee80211vap *vap); 9932176cfdSRui Paulo struct ieee80211_beacon_offsets; 10032176cfdSRui Paulo void ieee80211_tdma_update_beacon(struct ieee80211vap *vap, 10132176cfdSRui Paulo struct ieee80211_beacon_offsets *bo); 10232176cfdSRui Paulo #endif /* _KERNEL */ 10332176cfdSRui Paulo #endif /* !_NET80211_IEEE80211_TDMA_H_ */ 104