1/* 2 * from: vector.s, 386BSD 0.1 unknown origin 3 * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $ 4 */ 5 6#if 0 7#include "opt_auto_eoi.h" 8#endif 9 10#include <machine/asmacros.h> 11#include <machine/lock.h> 12#include <machine/psl.h> 13#include <machine/trap.h> 14#include <machine/segments.h> 15 16#include <machine_base/icu/icu.h> 17#include <bus/isa/isa.h> 18 19#include "assym.s" 20 21#include "apicreg.h" 22#include <machine_base/apic/ioapic_ipl.h> 23#include <machine/intr_machdep.h> 24 25#ifdef foo 26/* convert an absolute IRQ# into bitmask */ 27#define IRQ_LBIT(irq_num) (1UL << (irq_num & 0x3f)) 28#endif 29 30#define IRQ_SBITS(irq_num) ((irq_num) & 0x3f) 31 32/* convert an absolute IRQ# into gd_ipending index */ 33#define IRQ_LIDX(irq_num) ((irq_num) >> 6) 34 35#define MPLOCKED lock ; 36 37#define APIC_PUSH_FRAME \ 38 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \ 39 movq $0,TF_XFLAGS(%rsp) ; \ 40 movq $0,TF_TRAPNO(%rsp) ; \ 41 movq $0,TF_ADDR(%rsp) ; \ 42 movq $0,TF_FLAGS(%rsp) ; \ 43 movq $0,TF_ERR(%rsp) ; \ 44 cld ; \ 45 46/* 47 * JG stale? Warning: POP_FRAME can only be used if there is no chance of a 48 * segment register being changed (e.g. by procfs), which is why syscalls 49 * have to use doreti. 50 */ 51#define APIC_POP_FRAME \ 52 POP_FRAME ; \ 53 54#define IOAPICADDR(irq_num) \ 55 CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_ADDR 56#define REDIRIDX(irq_num) \ 57 CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_IDX 58#define IOAPICFLAGS(irq_num) \ 59 CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_FLAGS 60 61#define MASK_IRQ(irq_num) \ 62 IOAPIC_IMASK_LOCK ; /* into critical reg */ \ 63 testl $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 64 jne 7f ; /* masked, don't mask */ \ 65 orl $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 66 /* set the mask bit */ \ 67 movq IOAPICADDR(irq_num), %rcx ; /* ioapic addr */ \ 68 movl REDIRIDX(irq_num), %eax ; /* get the index */ \ 69 movl %eax, (%rcx) ; /* write the index */ \ 70 orl $IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* set the mask */ \ 717: ; /* already masked */ \ 72 IOAPIC_IMASK_UNLOCK ; \ 73 74/* 75 * Test to see whether we are handling an edge or level triggered INT. 76 * Level-triggered INTs must still be masked as we don't clear the source, 77 * and the EOI cycle would cause redundant INTs to occur. 78 */ 79#define MASK_LEVEL_IRQ(irq_num) \ 80 testl $IOAPIC_IRQI_FLAG_LEVEL, IOAPICFLAGS(irq_num) ; \ 81 jz 9f ; /* edge, don't mask */ \ 82 MASK_IRQ(irq_num) ; \ 839: ; \ 84 85/* 86 * Test to see if the source is currntly masked, clear if so. 87 */ 88#define UNMASK_IRQ(irq_num) \ 89 cmpl $0,%eax ; \ 90 jnz 8f ; \ 91 IOAPIC_IMASK_LOCK ; /* into critical reg */ \ 92 testl $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 93 je 7f ; /* bit clear, not masked */ \ 94 andl $~IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 95 /* clear mask bit */ \ 96 movq IOAPICADDR(irq_num),%rcx ; /* ioapic addr */ \ 97 movl REDIRIDX(irq_num), %eax ; /* get the index */ \ 98 movl %eax,(%rcx) ; /* write the index */ \ 99 andl $~IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* clear the mask */ \ 1007: ; \ 101 IOAPIC_IMASK_UNLOCK ; \ 1028: ; \ 103 104/* 105 * Interrupt call handlers run in the following sequence: 106 * 107 * - Push the trap frame required by doreti 108 * - Mask the interrupt and reenable its source 109 * - If we cannot take the interrupt set its ipending bit and 110 * doreti. 111 * - If we can take the interrupt clear its ipending bit, 112 * call the handler, then unmask and doreti. 113 * 114 * YYY can cache gd base opitner instead of using hidden %fs prefixes. 115 */ 116 117#define INTR_HANDLER(irq_num) \ 118 .text ; \ 119 SUPERALIGN_TEXT ; \ 120IDTVEC(ioapic_intr##irq_num) ; \ 121 APIC_PUSH_FRAME ; \ 122 FAKE_MCOUNT(TF_RIP(%rsp)) ; \ 123 MASK_LEVEL_IRQ(irq_num) ; \ 124 movq lapic, %rax ; \ 125 movl $0, LA_EOI(%rax) ; \ 126 movq PCPU(curthread),%rbx ; \ 127 testl $-1,TD_NEST_COUNT(%rbx) ; \ 128 jne 1f ; \ 129 testl $-1,TD_CRITCOUNT(%rbx) ; \ 130 je 2f ; \ 1311: ; \ 132 /* in critical section, make interrupt pending */ \ 133 /* set the pending bit and return, leave interrupt masked */ \ 134 movq $1,%rcx ; \ 135 shlq $IRQ_SBITS(irq_num),%rcx ; \ 136 movq $IRQ_LIDX(irq_num),%rdx ; \ 137 orq %rcx,PCPU_E8(ipending,%rdx) ; \ 138 orl $RQF_INTPEND,PCPU(reqflags) ; \ 139 jmp 5f ; \ 1402: ; \ 141 /* clear pending bit, run handler */ \ 142 movq $1,%rcx ; \ 143 shlq $IRQ_SBITS(irq_num),%rcx ; \ 144 notq %rcx ; \ 145 movq $IRQ_LIDX(irq_num),%rdx ; \ 146 andq %rcx,PCPU_E8(ipending,%rdx) ; \ 147 pushq $irq_num ; /* trapframe -> intrframe */ \ 148 movq %rsp, %rdi ; /* pass frame by reference */ \ 149 incl TD_CRITCOUNT(%rbx) ; \ 150 sti ; \ 151 call ithread_fast_handler ; /* returns 0 to unmask */ \ 152 cli ; /* interlock avoid stacking */ \ 153 decl TD_CRITCOUNT(%rbx) ; \ 154 addq $8, %rsp ; /* intrframe -> trapframe */ \ 155 UNMASK_IRQ(irq_num) ; \ 1565: ; \ 157 MEXITCOUNT ; \ 158 jmp doreti ; \ 159 160/* 161 * Handle "spurious INTerrupts". 162 * 163 * NOTE: This is different than the "spurious INTerrupt" generated by an 164 * 8259 PIC for missing INTs. See the APIC documentation for details. 165 * This routine should NOT do an 'EOI' cycle. 166 * 167 * NOTE: Even though we don't do anything here we must still swapgs if 168 * coming from a user frame in case the iretq faults... just use 169 * the nominal APIC_PUSH_FRAME sequence to get it done. 170 */ 171 .text 172 SUPERALIGN_TEXT 173 .globl Xspuriousint 174Xspuriousint: 175 APIC_PUSH_FRAME 176 /* No EOI cycle used here */ 177 FAKE_MCOUNT(TF_RIP(%rsp)) 178 MEXITCOUNT 179 APIC_POP_FRAME 180 jmp doreti_iret 181 182/* 183 * Handle TLB shootdowns. 184 * 185 * NOTE: interrupts are left disabled. 186 */ 187 .text 188 SUPERALIGN_TEXT 189 .globl Xinvltlb 190Xinvltlb: 191 APIC_PUSH_FRAME 192 movq lapic, %rax 193 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 194 FAKE_MCOUNT(TF_RIP(%rsp)) 195 incl PCPU(cnt) + V_IPI 196 movq PCPU(curthread),%rbx 197 incl PCPU(intr_nesting_level) 198 incl TD_CRITCOUNT(%rbx) 199 subq $8,%rsp /* make same as interrupt frame */ 200 movq %rsp,%rdi /* pass frame by reference */ 201 call smp_inval_intr /* called w/interrupts disabled */ 202 addq $8,%rsp /* turn into trapframe */ 203 decl TD_CRITCOUNT(%rbx) 204 decl PCPU(intr_nesting_level) 205 MEXITCOUNT 206 /*APIC_POP_FRAME*/ 207 jmp doreti /* doreti b/c intrs enabled */ 208 209/* 210 * Handle sniffs - sniff %rip and %rsp. 211 */ 212 .text 213 SUPERALIGN_TEXT 214 .globl Xsniff 215Xsniff: 216 APIC_PUSH_FRAME 217 movq lapic, %rax 218 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 219 FAKE_MCOUNT(TF_RIP(%rsp)) 220 incl PCPU(cnt) + V_IPI 221 movq TF_RIP(%rsp),%rax 222 movq %rax,PCPU(sample_pc) 223 movq TF_RSP(%rsp),%rax 224 movq %rax,PCPU(sample_sp) 225 MEXITCOUNT 226 APIC_POP_FRAME 227 jmp doreti_iret 228 229/* 230 * Executed by a CPU when it receives an Xcpustop IPI from another CPU, 231 * 232 * - We cannot call doreti 233 * - Signals its receipt. 234 * - Waits for permission to restart. 235 * - Processing pending IPIQ events while waiting. 236 * - Signals its restart. 237 */ 238 239 .text 240 SUPERALIGN_TEXT 241 .globl Xcpustop 242Xcpustop: 243 APIC_PUSH_FRAME 244 movq lapic, %rax 245 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 246 247 movl PCPU(cpuid), %eax 248 imull $PCB_SIZE, %eax 249 leaq CNAME(stoppcbs), %rdi 250 addq %rax, %rdi 251 call CNAME(savectx) /* Save process context */ 252 253 /* 254 * Indicate that we have stopped and loop waiting for permission 255 * to start again. We must still process IPI events while in a 256 * stopped state. 257 * 258 * Interrupts must remain enabled for non-IPI'd per-cpu interrupts 259 * (e.g. Xtimer, Xinvltlb). 260 */ 261#if CPUMASK_ELEMENTS != 4 262#error "assembly incompatible with cpumask_t" 263#endif 264 movq PCPU(cpumask)+0,%rax /* stopped_cpus |= 1 << cpuid */ 265 MPLOCKED orq %rax, stopped_cpus+0 266 movq PCPU(cpumask)+8,%rax 267 MPLOCKED orq %rax, stopped_cpus+8 268 movq PCPU(cpumask)+16,%rax 269 MPLOCKED orq %rax, stopped_cpus+16 270 movq PCPU(cpumask)+24,%rax 271 MPLOCKED orq %rax, stopped_cpus+24 272 273 movq PCPU(curthread),%rbx 274 incl PCPU(intr_nesting_level) 275 incl TD_CRITCOUNT(%rbx) 276 sti 2771: 278 andl $~RQF_IPIQ,PCPU(reqflags) 279 call lwkt_smp_stopped 280 pause 281 282 subq %rdi,%rdi 283 movq started_cpus+0,%rax /* while (!(started_cpus & (1<<id))) */ 284 andq PCPU(cpumask)+0,%rax 285 orq %rax,%rdi 286 movq started_cpus+8,%rax 287 andq PCPU(cpumask)+8,%rax 288 orq %rax,%rdi 289 movq started_cpus+16,%rax 290 andq PCPU(cpumask)+16,%rax 291 orq %rax,%rdi 292 movq started_cpus+24,%rax 293 andq PCPU(cpumask)+24,%rax 294 orq %rax,%rdi 295 testq %rdi,%rdi 296 jz 1b 297 298 movq PCPU(other_cpus)+0,%rax /* started_cpus &= ~(1 << cpuid) */ 299 MPLOCKED andq %rax, started_cpus+0 300 movq PCPU(other_cpus)+8,%rax 301 MPLOCKED andq %rax, started_cpus+8 302 movq PCPU(other_cpus)+16,%rax 303 MPLOCKED andq %rax, started_cpus+16 304 movq PCPU(other_cpus)+24,%rax 305 MPLOCKED andq %rax, started_cpus+24 306 307 movq PCPU(other_cpus)+0,%rax /* stopped_cpus &= ~(1 << cpuid) */ 308 MPLOCKED andq %rax, stopped_cpus+0 309 movq PCPU(other_cpus)+8,%rax 310 MPLOCKED andq %rax, stopped_cpus+8 311 movq PCPU(other_cpus)+16,%rax 312 MPLOCKED andq %rax, stopped_cpus+16 313 movq PCPU(other_cpus)+24,%rax 314 MPLOCKED andq %rax, stopped_cpus+24 315 316 cmpl $0,PCPU(cpuid) 317 jnz 2f 318 319 movq CNAME(cpustop_restartfunc), %rax 320 testq %rax, %rax 321 jz 2f 322 movq $0, CNAME(cpustop_restartfunc) /* One-shot */ 323 324 call *%rax 3252: 326 decl TD_CRITCOUNT(%rbx) 327 decl PCPU(intr_nesting_level) 328 MEXITCOUNT 329 /*APIC_POP_FRAME*/ 330 jmp doreti 331 332 /* 333 * For now just have one ipiq IPI, but what we really want is 334 * to have one for each source cpu to the APICs don't get stalled 335 * backlogging the requests. 336 */ 337 .text 338 SUPERALIGN_TEXT 339 .globl Xipiq 340Xipiq: 341 APIC_PUSH_FRAME 342 movq lapic, %rax 343 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 344 FAKE_MCOUNT(TF_RIP(%rsp)) 345 346 incl PCPU(cnt) + V_IPI 347 movq PCPU(curthread),%rbx 348 testl $-1,TD_CRITCOUNT(%rbx) 349 jne 1f 350 subq $8,%rsp /* make same as interrupt frame */ 351 movq %rsp,%rdi /* pass frame by reference */ 352 incl PCPU(intr_nesting_level) 353 incl TD_CRITCOUNT(%rbx) 354 subq %rax,%rax 355 sti 356 xchgl %eax,PCPU(npoll) /* (atomic op) allow another Xipi */ 357 call lwkt_process_ipiq_frame 358 cli /* interlock avoid stacking */ 359 decl TD_CRITCOUNT(%rbx) 360 decl PCPU(intr_nesting_level) 361 addq $8,%rsp /* turn into trapframe */ 362 MEXITCOUNT 363 jmp doreti 3641: 365 orl $RQF_IPIQ,PCPU(reqflags) 366 MEXITCOUNT 367 APIC_POP_FRAME 368 jmp doreti_iret 369 370 .text 371 SUPERALIGN_TEXT 372 .globl Xtimer 373Xtimer: 374 APIC_PUSH_FRAME 375 movq lapic, %rax 376 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 377 FAKE_MCOUNT(TF_RIP(%rsp)) 378 379 subq $8,%rsp /* make same as interrupt frame */ 380 movq %rsp,%rdi /* pass frame by reference */ 381 call pcpu_timer_always 382 addq $8,%rsp /* turn into trapframe */ 383 384 incl PCPU(cnt) + V_TIMER 385 movq TF_RIP(%rsp),%rbx /* sample addr before checking crit */ 386 movq %rbx,PCPU(sample_pc) 387 movq PCPU(curthread),%rbx 388 testl $-1,TD_CRITCOUNT(%rbx) 389 jne 1f 390 testl $-1,TD_NEST_COUNT(%rbx) 391 jne 1f 392 subq $8,%rsp /* make same as interrupt frame */ 393 movq %rsp,%rdi /* pass frame by reference */ 394 incl PCPU(intr_nesting_level) 395 incl TD_CRITCOUNT(%rbx) 396 sti 397 call pcpu_timer_process_frame 398 cli /* interlock avoid stacking */ 399 decl TD_CRITCOUNT(%rbx) 400 decl PCPU(intr_nesting_level) 401 addq $8,%rsp /* turn into trapframe */ 402 MEXITCOUNT 403 jmp doreti 4041: 405 orl $RQF_TIMER,PCPU(reqflags) 406 MEXITCOUNT 407 APIC_POP_FRAME 408 jmp doreti_iret 409 410MCOUNT_LABEL(bintr) 411 INTR_HANDLER(0) 412 INTR_HANDLER(1) 413 INTR_HANDLER(2) 414 INTR_HANDLER(3) 415 INTR_HANDLER(4) 416 INTR_HANDLER(5) 417 INTR_HANDLER(6) 418 INTR_HANDLER(7) 419 INTR_HANDLER(8) 420 INTR_HANDLER(9) 421 INTR_HANDLER(10) 422 INTR_HANDLER(11) 423 INTR_HANDLER(12) 424 INTR_HANDLER(13) 425 INTR_HANDLER(14) 426 INTR_HANDLER(15) 427 INTR_HANDLER(16) 428 INTR_HANDLER(17) 429 INTR_HANDLER(18) 430 INTR_HANDLER(19) 431 INTR_HANDLER(20) 432 INTR_HANDLER(21) 433 INTR_HANDLER(22) 434 INTR_HANDLER(23) 435 INTR_HANDLER(24) 436 INTR_HANDLER(25) 437 INTR_HANDLER(26) 438 INTR_HANDLER(27) 439 INTR_HANDLER(28) 440 INTR_HANDLER(29) 441 INTR_HANDLER(30) 442 INTR_HANDLER(31) 443 INTR_HANDLER(32) 444 INTR_HANDLER(33) 445 INTR_HANDLER(34) 446 INTR_HANDLER(35) 447 INTR_HANDLER(36) 448 INTR_HANDLER(37) 449 INTR_HANDLER(38) 450 INTR_HANDLER(39) 451 INTR_HANDLER(40) 452 INTR_HANDLER(41) 453 INTR_HANDLER(42) 454 INTR_HANDLER(43) 455 INTR_HANDLER(44) 456 INTR_HANDLER(45) 457 INTR_HANDLER(46) 458 INTR_HANDLER(47) 459 INTR_HANDLER(48) 460 INTR_HANDLER(49) 461 INTR_HANDLER(50) 462 INTR_HANDLER(51) 463 INTR_HANDLER(52) 464 INTR_HANDLER(53) 465 INTR_HANDLER(54) 466 INTR_HANDLER(55) 467 INTR_HANDLER(56) 468 INTR_HANDLER(57) 469 INTR_HANDLER(58) 470 INTR_HANDLER(59) 471 INTR_HANDLER(60) 472 INTR_HANDLER(61) 473 INTR_HANDLER(62) 474 INTR_HANDLER(63) 475 INTR_HANDLER(64) 476 INTR_HANDLER(65) 477 INTR_HANDLER(66) 478 INTR_HANDLER(67) 479 INTR_HANDLER(68) 480 INTR_HANDLER(69) 481 INTR_HANDLER(70) 482 INTR_HANDLER(71) 483 INTR_HANDLER(72) 484 INTR_HANDLER(73) 485 INTR_HANDLER(74) 486 INTR_HANDLER(75) 487 INTR_HANDLER(76) 488 INTR_HANDLER(77) 489 INTR_HANDLER(78) 490 INTR_HANDLER(79) 491 INTR_HANDLER(80) 492 INTR_HANDLER(81) 493 INTR_HANDLER(82) 494 INTR_HANDLER(83) 495 INTR_HANDLER(84) 496 INTR_HANDLER(85) 497 INTR_HANDLER(86) 498 INTR_HANDLER(87) 499 INTR_HANDLER(88) 500 INTR_HANDLER(89) 501 INTR_HANDLER(90) 502 INTR_HANDLER(91) 503 INTR_HANDLER(92) 504 INTR_HANDLER(93) 505 INTR_HANDLER(94) 506 INTR_HANDLER(95) 507 INTR_HANDLER(96) 508 INTR_HANDLER(97) 509 INTR_HANDLER(98) 510 INTR_HANDLER(99) 511 INTR_HANDLER(100) 512 INTR_HANDLER(101) 513 INTR_HANDLER(102) 514 INTR_HANDLER(103) 515 INTR_HANDLER(104) 516 INTR_HANDLER(105) 517 INTR_HANDLER(106) 518 INTR_HANDLER(107) 519 INTR_HANDLER(108) 520 INTR_HANDLER(109) 521 INTR_HANDLER(110) 522 INTR_HANDLER(111) 523 INTR_HANDLER(112) 524 INTR_HANDLER(113) 525 INTR_HANDLER(114) 526 INTR_HANDLER(115) 527 INTR_HANDLER(116) 528 INTR_HANDLER(117) 529 INTR_HANDLER(118) 530 INTR_HANDLER(119) 531 INTR_HANDLER(120) 532 INTR_HANDLER(121) 533 INTR_HANDLER(122) 534 INTR_HANDLER(123) 535 INTR_HANDLER(124) 536 INTR_HANDLER(125) 537 INTR_HANDLER(126) 538 INTR_HANDLER(127) 539 INTR_HANDLER(128) 540 INTR_HANDLER(129) 541 INTR_HANDLER(130) 542 INTR_HANDLER(131) 543 INTR_HANDLER(132) 544 INTR_HANDLER(133) 545 INTR_HANDLER(134) 546 INTR_HANDLER(135) 547 INTR_HANDLER(136) 548 INTR_HANDLER(137) 549 INTR_HANDLER(138) 550 INTR_HANDLER(139) 551 INTR_HANDLER(140) 552 INTR_HANDLER(141) 553 INTR_HANDLER(142) 554 INTR_HANDLER(143) 555 INTR_HANDLER(144) 556 INTR_HANDLER(145) 557 INTR_HANDLER(146) 558 INTR_HANDLER(147) 559 INTR_HANDLER(148) 560 INTR_HANDLER(149) 561 INTR_HANDLER(150) 562 INTR_HANDLER(151) 563 INTR_HANDLER(152) 564 INTR_HANDLER(153) 565 INTR_HANDLER(154) 566 INTR_HANDLER(155) 567 INTR_HANDLER(156) 568 INTR_HANDLER(157) 569 INTR_HANDLER(158) 570 INTR_HANDLER(159) 571 INTR_HANDLER(160) 572 INTR_HANDLER(161) 573 INTR_HANDLER(162) 574 INTR_HANDLER(163) 575 INTR_HANDLER(164) 576 INTR_HANDLER(165) 577 INTR_HANDLER(166) 578 INTR_HANDLER(167) 579 INTR_HANDLER(168) 580 INTR_HANDLER(169) 581 INTR_HANDLER(170) 582 INTR_HANDLER(171) 583 INTR_HANDLER(172) 584 INTR_HANDLER(173) 585 INTR_HANDLER(174) 586 INTR_HANDLER(175) 587 INTR_HANDLER(176) 588 INTR_HANDLER(177) 589 INTR_HANDLER(178) 590 INTR_HANDLER(179) 591 INTR_HANDLER(180) 592 INTR_HANDLER(181) 593 INTR_HANDLER(182) 594 INTR_HANDLER(183) 595 INTR_HANDLER(184) 596 INTR_HANDLER(185) 597 INTR_HANDLER(186) 598 INTR_HANDLER(187) 599 INTR_HANDLER(188) 600 INTR_HANDLER(189) 601 INTR_HANDLER(190) 602 INTR_HANDLER(191) 603MCOUNT_LABEL(eintr) 604 605 .data 606 607#if CPUMASK_ELEMENTS != 4 608#error "assembly incompatible with cpumask_t" 609#endif 610/* variables used by stop_cpus()/restart_cpus()/Xcpustop */ 611 .globl stopped_cpus, started_cpus 612stopped_cpus: 613 .quad 0 614 .quad 0 615 .quad 0 616 .quad 0 617started_cpus: 618 .quad 0 619 .quad 0 620 .quad 0 621 .quad 0 622 623 .globl CNAME(cpustop_restartfunc) 624CNAME(cpustop_restartfunc): 625 .quad 0 626 627 .text 628 629