1/* 2 * from: vector.s, 386BSD 0.1 unknown origin 3 * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $ 4 */ 5 6#if 0 7#include "opt_auto_eoi.h" 8#endif 9 10#include <machine/asmacros.h> 11#include <machine/lock.h> 12#include <machine/psl.h> 13#include <machine/trap.h> 14#include <machine/segments.h> 15 16#include <machine_base/icu/icu.h> 17#include <bus/isa/isa.h> 18 19#include "assym.s" 20 21#include "apicreg.h" 22#include <machine_base/apic/ioapic_ipl.h> 23#include <machine/intr_machdep.h> 24 25#ifdef foo 26/* convert an absolute IRQ# into bitmask */ 27#define IRQ_LBIT(irq_num) (1UL << (irq_num & 0x3f)) 28#endif 29 30#define IRQ_SBITS(irq_num) ((irq_num) & 0x3f) 31 32/* convert an absolute IRQ# into gd_ipending index */ 33#define IRQ_LIDX(irq_num) ((irq_num) >> 6) 34 35#define MPLOCKED lock ; 36 37#define APIC_PUSH_FRAME \ 38 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \ 39 movq $0,TF_XFLAGS(%rsp) ; \ 40 movq $0,TF_TRAPNO(%rsp) ; \ 41 movq $0,TF_ADDR(%rsp) ; \ 42 movq $0,TF_FLAGS(%rsp) ; \ 43 movq $0,TF_ERR(%rsp) ; \ 44 cld ; \ 45 46/* 47 * JG stale? Warning: POP_FRAME can only be used if there is no chance of a 48 * segment register being changed (e.g. by procfs), which is why syscalls 49 * have to use doreti. 50 */ 51#define APIC_POP_FRAME \ 52 POP_FRAME ; \ 53 54#define IOAPICADDR(irq_num) \ 55 CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_ADDR 56#define REDIRIDX(irq_num) \ 57 CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_IDX 58#define IOAPICFLAGS(irq_num) \ 59 CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_FLAGS 60 61#define MASK_IRQ(irq_num) \ 62 IOAPIC_IMASK_LOCK ; /* into critical reg */ \ 63 testl $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 64 jne 7f ; /* masked, don't mask */ \ 65 orl $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 66 /* set the mask bit */ \ 67 movq IOAPICADDR(irq_num), %rcx ; /* ioapic addr */ \ 68 movl REDIRIDX(irq_num), %eax ; /* get the index */ \ 69 movl %eax, (%rcx) ; /* write the index */ \ 70 orl $IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* set the mask */ \ 717: ; /* already masked */ \ 72 IOAPIC_IMASK_UNLOCK ; \ 73 74/* 75 * Test to see whether we are handling an edge or level triggered INT. 76 * Level-triggered INTs must still be masked as we don't clear the source, 77 * and the EOI cycle would cause redundant INTs to occur. 78 */ 79#define MASK_LEVEL_IRQ(irq_num) \ 80 testl $IOAPIC_IRQI_FLAG_LEVEL, IOAPICFLAGS(irq_num) ; \ 81 jz 9f ; /* edge, don't mask */ \ 82 MASK_IRQ(irq_num) ; \ 839: ; \ 84 85/* 86 * Test to see if the source is currntly masked, clear if so. 87 */ 88#define UNMASK_IRQ(irq_num) \ 89 cmpl $0,%eax ; \ 90 jnz 8f ; \ 91 IOAPIC_IMASK_LOCK ; /* into critical reg */ \ 92 testl $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 93 je 7f ; /* bit clear, not masked */ \ 94 andl $~IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \ 95 /* clear mask bit */ \ 96 movq IOAPICADDR(irq_num),%rcx ; /* ioapic addr */ \ 97 movl REDIRIDX(irq_num), %eax ; /* get the index */ \ 98 movl %eax,(%rcx) ; /* write the index */ \ 99 andl $~IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* clear the mask */ \ 1007: ; \ 101 IOAPIC_IMASK_UNLOCK ; \ 1028: ; \ 103 104/* 105 * Interrupt call handlers run in the following sequence: 106 * 107 * - Push the trap frame required by doreti 108 * - Mask the interrupt and reenable its source 109 * - If we cannot take the interrupt set its ipending bit and 110 * doreti. 111 * - If we can take the interrupt clear its ipending bit, 112 * call the handler, then unmask and doreti. 113 * 114 * YYY can cache gd base opitner instead of using hidden %fs prefixes. 115 */ 116 117#define INTR_HANDLER(irq_num) \ 118 .text ; \ 119 SUPERALIGN_TEXT ; \ 120IDTVEC(ioapic_intr##irq_num) ; \ 121 APIC_PUSH_FRAME ; \ 122 FAKE_MCOUNT(TF_RIP(%rsp)) ; \ 123 MASK_LEVEL_IRQ(irq_num) ; \ 124 movq lapic, %rax ; \ 125 movl $0, LA_EOI(%rax) ; \ 126 movq PCPU(curthread),%rbx ; \ 127 testl $-1,TD_NEST_COUNT(%rbx) ; \ 128 jne 1f ; \ 129 testl $-1,TD_CRITCOUNT(%rbx) ; \ 130 je 2f ; \ 1311: ; \ 132 /* in critical section, make interrupt pending */ \ 133 /* set the pending bit and return, leave interrupt masked */ \ 134 movq $1,%rcx ; \ 135 shlq $IRQ_SBITS(irq_num),%rcx ; \ 136 movq $IRQ_LIDX(irq_num),%rdx ; \ 137 orq %rcx,PCPU_E8(ipending,%rdx) ; \ 138 orl $RQF_INTPEND,PCPU(reqflags) ; \ 139 jmp 5f ; \ 1402: ; \ 141 /* clear pending bit, run handler */ \ 142 movq $1,%rcx ; \ 143 shlq $IRQ_SBITS(irq_num),%rcx ; \ 144 notq %rcx ; \ 145 movq $IRQ_LIDX(irq_num),%rdx ; \ 146 andq %rcx,PCPU_E8(ipending,%rdx) ; \ 147 pushq $irq_num ; /* trapframe -> intrframe */ \ 148 movq %rsp, %rdi ; /* pass frame by reference */ \ 149 incl TD_CRITCOUNT(%rbx) ; \ 150 sti ; \ 151 call ithread_fast_handler ; /* returns 0 to unmask */ \ 152 decl TD_CRITCOUNT(%rbx) ; \ 153 addq $8, %rsp ; /* intrframe -> trapframe */ \ 154 UNMASK_IRQ(irq_num) ; \ 1555: ; \ 156 MEXITCOUNT ; \ 157 jmp doreti ; \ 158 159/* 160 * Handle "spurious INTerrupts". 161 * 162 * NOTE: This is different than the "spurious INTerrupt" generated by an 163 * 8259 PIC for missing INTs. See the APIC documentation for details. 164 * This routine should NOT do an 'EOI' cycle. 165 * 166 * NOTE: Even though we don't do anything here we must still swapgs if 167 * coming from a user frame in case the iretq faults... just use 168 * the nominal APIC_PUSH_FRAME sequence to get it done. 169 */ 170 .text 171 SUPERALIGN_TEXT 172 .globl Xspuriousint 173Xspuriousint: 174 APIC_PUSH_FRAME 175 /* No EOI cycle used here */ 176 FAKE_MCOUNT(TF_RIP(%rsp)) 177 MEXITCOUNT 178 APIC_POP_FRAME 179 jmp doreti_iret 180 181/* 182 * Handle TLB shootdowns. 183 * 184 * NOTE: interrupts are left disabled. 185 */ 186 .text 187 SUPERALIGN_TEXT 188 .globl Xinvltlb 189Xinvltlb: 190 APIC_PUSH_FRAME 191 movq lapic, %rax 192 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 193 FAKE_MCOUNT(TF_RIP(%rsp)) 194 subq $8,%rsp /* make same as interrupt frame */ 195 movq %rsp,%rdi /* pass frame by reference */ 196 call smp_invltlb_intr 197 addq $8,%rsp /* turn into trapframe */ 198 MEXITCOUNT 199 APIC_POP_FRAME 200 jmp doreti_iret 201 202/* 203 * Executed by a CPU when it receives an Xcpustop IPI from another CPU, 204 * 205 * - We cannot call doreti 206 * - Signals its receipt. 207 * - Waits for permission to restart. 208 * - Processing pending IPIQ events while waiting. 209 * - Signals its restart. 210 */ 211 212 .text 213 SUPERALIGN_TEXT 214 .globl Xcpustop 215Xcpustop: 216 APIC_PUSH_FRAME 217 movq lapic, %rax 218 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 219 220 movl PCPU(cpuid), %eax 221 imull $PCB_SIZE, %eax 222 leaq CNAME(stoppcbs), %rdi 223 addq %rax, %rdi 224 call CNAME(savectx) /* Save process context */ 225 226 /* 227 * Indicate that we have stopped and loop waiting for permission 228 * to start again. We must still process IPI events while in a 229 * stopped state. 230 * 231 * Interrupts must remain enabled for non-IPI'd per-cpu interrupts 232 * (e.g. Xtimer, Xinvltlb). 233 */ 234#if CPUMASK_ELEMENTS != 4 235#error "assembly incompatible with cpumask_t" 236#endif 237 movq PCPU(cpumask)+0,%rax /* stopped_cpus |= 1 << cpuid */ 238 MPLOCKED orq %rax, stopped_cpus+0 239 movq PCPU(cpumask)+8,%rax 240 MPLOCKED orq %rax, stopped_cpus+8 241 movq PCPU(cpumask)+16,%rax 242 MPLOCKED orq %rax, stopped_cpus+16 243 movq PCPU(cpumask)+24,%rax 244 MPLOCKED orq %rax, stopped_cpus+24 245 246 movq PCPU(curthread),%rbx 247 incl PCPU(intr_nesting_level) 248 incl TD_CRITCOUNT(%rbx) 249 sti 2501: 251 andl $~RQF_IPIQ,PCPU(reqflags) 252 call lwkt_smp_stopped 253 pause 254 255 subq %rdi,%rdi 256 movq started_cpus+0,%rax /* while (!(started_cpus & (1<<id))) */ 257 andq PCPU(cpumask)+0,%rax 258 orq %rax,%rdi 259 movq started_cpus+8,%rax 260 andq PCPU(cpumask)+8,%rax 261 orq %rax,%rdi 262 movq started_cpus+16,%rax 263 andq PCPU(cpumask)+16,%rax 264 orq %rax,%rdi 265 movq started_cpus+24,%rax 266 andq PCPU(cpumask)+24,%rax 267 orq %rax,%rdi 268 testq %rdi,%rdi 269 jz 1b 270 271 movq PCPU(other_cpus)+0,%rax /* started_cpus &= ~(1 << cpuid) */ 272 MPLOCKED andq %rax, started_cpus+0 273 movq PCPU(other_cpus)+8,%rax 274 MPLOCKED andq %rax, started_cpus+8 275 movq PCPU(other_cpus)+16,%rax 276 MPLOCKED andq %rax, started_cpus+16 277 movq PCPU(other_cpus)+24,%rax 278 MPLOCKED andq %rax, started_cpus+24 279 280 movq PCPU(other_cpus)+0,%rax /* stopped_cpus &= ~(1 << cpuid) */ 281 MPLOCKED andq %rax, stopped_cpus+0 282 movq PCPU(other_cpus)+8,%rax 283 MPLOCKED andq %rax, stopped_cpus+8 284 movq PCPU(other_cpus)+16,%rax 285 MPLOCKED andq %rax, stopped_cpus+16 286 movq PCPU(other_cpus)+24,%rax 287 MPLOCKED andq %rax, stopped_cpus+24 288 289 cmpl $0,PCPU(cpuid) 290 jnz 2f 291 292 movq CNAME(cpustop_restartfunc), %rax 293 testq %rax, %rax 294 jz 2f 295 movq $0, CNAME(cpustop_restartfunc) /* One-shot */ 296 297 call *%rax 2982: 299 decl TD_CRITCOUNT(%rbx) 300 decl PCPU(intr_nesting_level) 301 MEXITCOUNT 302 /*APIC_POP_FRAME*/ 303 jmp doreti 304 305 /* 306 * For now just have one ipiq IPI, but what we really want is 307 * to have one for each source cpu to the APICs don't get stalled 308 * backlogging the requests. 309 */ 310 .text 311 SUPERALIGN_TEXT 312 .globl Xipiq 313Xipiq: 314 APIC_PUSH_FRAME 315 movq lapic, %rax 316 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 317 FAKE_MCOUNT(TF_RIP(%rsp)) 318 319 incl PCPU(cnt) + V_IPI 320 movq PCPU(curthread),%rbx 321 testl $-1,TD_CRITCOUNT(%rbx) 322 jne 1f 323 subq $8,%rsp /* make same as interrupt frame */ 324 movq %rsp,%rdi /* pass frame by reference */ 325 incl PCPU(intr_nesting_level) 326 incl TD_CRITCOUNT(%rbx) 327 sti 328 call lwkt_process_ipiq_frame 329 decl TD_CRITCOUNT(%rbx) 330 decl PCPU(intr_nesting_level) 331 addq $8,%rsp /* turn into trapframe */ 332 MEXITCOUNT 333 jmp doreti 3341: 335 orl $RQF_IPIQ,PCPU(reqflags) 336 MEXITCOUNT 337 APIC_POP_FRAME 338 jmp doreti_iret 339 340 .text 341 SUPERALIGN_TEXT 342 .globl Xtimer 343Xtimer: 344 APIC_PUSH_FRAME 345 movq lapic, %rax 346 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 347 FAKE_MCOUNT(TF_RIP(%rsp)) 348 349 subq $8,%rsp /* make same as interrupt frame */ 350 movq %rsp,%rdi /* pass frame by reference */ 351 call lapic_timer_always 352 addq $8,%rsp /* turn into trapframe */ 353 354 incl PCPU(cnt) + V_TIMER 355 movq TF_RIP(%rsp),%rbx /* sample addr before checking crit */ 356 movq %rbx,PCPU(sample_pc) 357 movq PCPU(curthread),%rbx 358 testl $-1,TD_CRITCOUNT(%rbx) 359 jne 1f 360 testl $-1,TD_NEST_COUNT(%rbx) 361 jne 1f 362 subq $8,%rsp /* make same as interrupt frame */ 363 movq %rsp,%rdi /* pass frame by reference */ 364 incl PCPU(intr_nesting_level) 365 incl TD_CRITCOUNT(%rbx) 366 sti 367 call lapic_timer_process_frame 368 decl TD_CRITCOUNT(%rbx) 369 decl PCPU(intr_nesting_level) 370 addq $8,%rsp /* turn into trapframe */ 371 MEXITCOUNT 372 jmp doreti 3731: 374 orl $RQF_TIMER,PCPU(reqflags) 375 MEXITCOUNT 376 APIC_POP_FRAME 377 jmp doreti_iret 378 379MCOUNT_LABEL(bintr) 380 INTR_HANDLER(0) 381 INTR_HANDLER(1) 382 INTR_HANDLER(2) 383 INTR_HANDLER(3) 384 INTR_HANDLER(4) 385 INTR_HANDLER(5) 386 INTR_HANDLER(6) 387 INTR_HANDLER(7) 388 INTR_HANDLER(8) 389 INTR_HANDLER(9) 390 INTR_HANDLER(10) 391 INTR_HANDLER(11) 392 INTR_HANDLER(12) 393 INTR_HANDLER(13) 394 INTR_HANDLER(14) 395 INTR_HANDLER(15) 396 INTR_HANDLER(16) 397 INTR_HANDLER(17) 398 INTR_HANDLER(18) 399 INTR_HANDLER(19) 400 INTR_HANDLER(20) 401 INTR_HANDLER(21) 402 INTR_HANDLER(22) 403 INTR_HANDLER(23) 404 INTR_HANDLER(24) 405 INTR_HANDLER(25) 406 INTR_HANDLER(26) 407 INTR_HANDLER(27) 408 INTR_HANDLER(28) 409 INTR_HANDLER(29) 410 INTR_HANDLER(30) 411 INTR_HANDLER(31) 412 INTR_HANDLER(32) 413 INTR_HANDLER(33) 414 INTR_HANDLER(34) 415 INTR_HANDLER(35) 416 INTR_HANDLER(36) 417 INTR_HANDLER(37) 418 INTR_HANDLER(38) 419 INTR_HANDLER(39) 420 INTR_HANDLER(40) 421 INTR_HANDLER(41) 422 INTR_HANDLER(42) 423 INTR_HANDLER(43) 424 INTR_HANDLER(44) 425 INTR_HANDLER(45) 426 INTR_HANDLER(46) 427 INTR_HANDLER(47) 428 INTR_HANDLER(48) 429 INTR_HANDLER(49) 430 INTR_HANDLER(50) 431 INTR_HANDLER(51) 432 INTR_HANDLER(52) 433 INTR_HANDLER(53) 434 INTR_HANDLER(54) 435 INTR_HANDLER(55) 436 INTR_HANDLER(56) 437 INTR_HANDLER(57) 438 INTR_HANDLER(58) 439 INTR_HANDLER(59) 440 INTR_HANDLER(60) 441 INTR_HANDLER(61) 442 INTR_HANDLER(62) 443 INTR_HANDLER(63) 444 INTR_HANDLER(64) 445 INTR_HANDLER(65) 446 INTR_HANDLER(66) 447 INTR_HANDLER(67) 448 INTR_HANDLER(68) 449 INTR_HANDLER(69) 450 INTR_HANDLER(70) 451 INTR_HANDLER(71) 452 INTR_HANDLER(72) 453 INTR_HANDLER(73) 454 INTR_HANDLER(74) 455 INTR_HANDLER(75) 456 INTR_HANDLER(76) 457 INTR_HANDLER(77) 458 INTR_HANDLER(78) 459 INTR_HANDLER(79) 460 INTR_HANDLER(80) 461 INTR_HANDLER(81) 462 INTR_HANDLER(82) 463 INTR_HANDLER(83) 464 INTR_HANDLER(84) 465 INTR_HANDLER(85) 466 INTR_HANDLER(86) 467 INTR_HANDLER(87) 468 INTR_HANDLER(88) 469 INTR_HANDLER(89) 470 INTR_HANDLER(90) 471 INTR_HANDLER(91) 472 INTR_HANDLER(92) 473 INTR_HANDLER(93) 474 INTR_HANDLER(94) 475 INTR_HANDLER(95) 476 INTR_HANDLER(96) 477 INTR_HANDLER(97) 478 INTR_HANDLER(98) 479 INTR_HANDLER(99) 480 INTR_HANDLER(100) 481 INTR_HANDLER(101) 482 INTR_HANDLER(102) 483 INTR_HANDLER(103) 484 INTR_HANDLER(104) 485 INTR_HANDLER(105) 486 INTR_HANDLER(106) 487 INTR_HANDLER(107) 488 INTR_HANDLER(108) 489 INTR_HANDLER(109) 490 INTR_HANDLER(110) 491 INTR_HANDLER(111) 492 INTR_HANDLER(112) 493 INTR_HANDLER(113) 494 INTR_HANDLER(114) 495 INTR_HANDLER(115) 496 INTR_HANDLER(116) 497 INTR_HANDLER(117) 498 INTR_HANDLER(118) 499 INTR_HANDLER(119) 500 INTR_HANDLER(120) 501 INTR_HANDLER(121) 502 INTR_HANDLER(122) 503 INTR_HANDLER(123) 504 INTR_HANDLER(124) 505 INTR_HANDLER(125) 506 INTR_HANDLER(126) 507 INTR_HANDLER(127) 508 INTR_HANDLER(128) 509 INTR_HANDLER(129) 510 INTR_HANDLER(130) 511 INTR_HANDLER(131) 512 INTR_HANDLER(132) 513 INTR_HANDLER(133) 514 INTR_HANDLER(134) 515 INTR_HANDLER(135) 516 INTR_HANDLER(136) 517 INTR_HANDLER(137) 518 INTR_HANDLER(138) 519 INTR_HANDLER(139) 520 INTR_HANDLER(140) 521 INTR_HANDLER(141) 522 INTR_HANDLER(142) 523 INTR_HANDLER(143) 524 INTR_HANDLER(144) 525 INTR_HANDLER(145) 526 INTR_HANDLER(146) 527 INTR_HANDLER(147) 528 INTR_HANDLER(148) 529 INTR_HANDLER(149) 530 INTR_HANDLER(150) 531 INTR_HANDLER(151) 532 INTR_HANDLER(152) 533 INTR_HANDLER(153) 534 INTR_HANDLER(154) 535 INTR_HANDLER(155) 536 INTR_HANDLER(156) 537 INTR_HANDLER(157) 538 INTR_HANDLER(158) 539 INTR_HANDLER(159) 540 INTR_HANDLER(160) 541 INTR_HANDLER(161) 542 INTR_HANDLER(162) 543 INTR_HANDLER(163) 544 INTR_HANDLER(164) 545 INTR_HANDLER(165) 546 INTR_HANDLER(166) 547 INTR_HANDLER(167) 548 INTR_HANDLER(168) 549 INTR_HANDLER(169) 550 INTR_HANDLER(170) 551 INTR_HANDLER(171) 552 INTR_HANDLER(172) 553 INTR_HANDLER(173) 554 INTR_HANDLER(174) 555 INTR_HANDLER(175) 556 INTR_HANDLER(176) 557 INTR_HANDLER(177) 558 INTR_HANDLER(178) 559 INTR_HANDLER(179) 560 INTR_HANDLER(180) 561 INTR_HANDLER(181) 562 INTR_HANDLER(182) 563 INTR_HANDLER(183) 564 INTR_HANDLER(184) 565 INTR_HANDLER(185) 566 INTR_HANDLER(186) 567 INTR_HANDLER(187) 568 INTR_HANDLER(188) 569 INTR_HANDLER(189) 570 INTR_HANDLER(190) 571 INTR_HANDLER(191) 572MCOUNT_LABEL(eintr) 573 574 .data 575 576#if CPUMASK_ELEMENTS != 4 577#error "assembly incompatible with cpumask_t" 578#endif 579/* variables used by stop_cpus()/restart_cpus()/Xcpustop */ 580 .globl stopped_cpus, started_cpus 581stopped_cpus: 582 .quad 0 583 .quad 0 584 .quad 0 585 .quad 0 586started_cpus: 587 .quad 0 588 .quad 0 589 .quad 0 590 .quad 0 591 592 .globl CNAME(cpustop_restartfunc) 593CNAME(cpustop_restartfunc): 594 .quad 0 595 596 .text 597 598