1 /* 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 1996, by Steve Passe. All rights reserved. 4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * This code is derived from software contributed to Berkeley by 11 * William Jolitz. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 3. Neither the name of The DragonFly Project nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific, prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/machintr.h> 45 #include <sys/interrupt.h> 46 #include <sys/bus.h> 47 #include <sys/rman.h> 48 #include <sys/thread2.h> 49 50 #include <machine/smp.h> 51 #include <machine/segments.h> 52 #include <machine/md_var.h> 53 #include <machine/intr_machdep.h> 54 #include <machine/globaldata.h> 55 #include <machine/msi_var.h> 56 57 #include <machine_base/isa/isa_intr.h> 58 #include <machine_base/icu/icu.h> 59 #include <machine_base/icu/icu_var.h> 60 #include <machine_base/apic/ioapic.h> 61 #include <machine_base/apic/ioapic_abi.h> 62 #include <machine_base/apic/ioapic_ipl.h> 63 #include <machine_base/apic/apicreg.h> 64 65 #include <dev/acpica/acpi_sci_var.h> 66 67 #define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS 68 69 extern inthand_t 70 IDTVEC(ioapic_intr0), 71 IDTVEC(ioapic_intr1), 72 IDTVEC(ioapic_intr2), 73 IDTVEC(ioapic_intr3), 74 IDTVEC(ioapic_intr4), 75 IDTVEC(ioapic_intr5), 76 IDTVEC(ioapic_intr6), 77 IDTVEC(ioapic_intr7), 78 IDTVEC(ioapic_intr8), 79 IDTVEC(ioapic_intr9), 80 IDTVEC(ioapic_intr10), 81 IDTVEC(ioapic_intr11), 82 IDTVEC(ioapic_intr12), 83 IDTVEC(ioapic_intr13), 84 IDTVEC(ioapic_intr14), 85 IDTVEC(ioapic_intr15), 86 IDTVEC(ioapic_intr16), 87 IDTVEC(ioapic_intr17), 88 IDTVEC(ioapic_intr18), 89 IDTVEC(ioapic_intr19), 90 IDTVEC(ioapic_intr20), 91 IDTVEC(ioapic_intr21), 92 IDTVEC(ioapic_intr22), 93 IDTVEC(ioapic_intr23), 94 IDTVEC(ioapic_intr24), 95 IDTVEC(ioapic_intr25), 96 IDTVEC(ioapic_intr26), 97 IDTVEC(ioapic_intr27), 98 IDTVEC(ioapic_intr28), 99 IDTVEC(ioapic_intr29), 100 IDTVEC(ioapic_intr30), 101 IDTVEC(ioapic_intr31), 102 IDTVEC(ioapic_intr32), 103 IDTVEC(ioapic_intr33), 104 IDTVEC(ioapic_intr34), 105 IDTVEC(ioapic_intr35), 106 IDTVEC(ioapic_intr36), 107 IDTVEC(ioapic_intr37), 108 IDTVEC(ioapic_intr38), 109 IDTVEC(ioapic_intr39), 110 IDTVEC(ioapic_intr40), 111 IDTVEC(ioapic_intr41), 112 IDTVEC(ioapic_intr42), 113 IDTVEC(ioapic_intr43), 114 IDTVEC(ioapic_intr44), 115 IDTVEC(ioapic_intr45), 116 IDTVEC(ioapic_intr46), 117 IDTVEC(ioapic_intr47), 118 IDTVEC(ioapic_intr48), 119 IDTVEC(ioapic_intr49), 120 IDTVEC(ioapic_intr50), 121 IDTVEC(ioapic_intr51), 122 IDTVEC(ioapic_intr52), 123 IDTVEC(ioapic_intr53), 124 IDTVEC(ioapic_intr54), 125 IDTVEC(ioapic_intr55), 126 IDTVEC(ioapic_intr56), 127 IDTVEC(ioapic_intr57), 128 IDTVEC(ioapic_intr58), 129 IDTVEC(ioapic_intr59), 130 IDTVEC(ioapic_intr60), 131 IDTVEC(ioapic_intr61), 132 IDTVEC(ioapic_intr62), 133 IDTVEC(ioapic_intr63), 134 IDTVEC(ioapic_intr64), 135 IDTVEC(ioapic_intr65), 136 IDTVEC(ioapic_intr66), 137 IDTVEC(ioapic_intr67), 138 IDTVEC(ioapic_intr68), 139 IDTVEC(ioapic_intr69), 140 IDTVEC(ioapic_intr70), 141 IDTVEC(ioapic_intr71), 142 IDTVEC(ioapic_intr72), 143 IDTVEC(ioapic_intr73), 144 IDTVEC(ioapic_intr74), 145 IDTVEC(ioapic_intr75), 146 IDTVEC(ioapic_intr76), 147 IDTVEC(ioapic_intr77), 148 IDTVEC(ioapic_intr78), 149 IDTVEC(ioapic_intr79), 150 IDTVEC(ioapic_intr80), 151 IDTVEC(ioapic_intr81), 152 IDTVEC(ioapic_intr82), 153 IDTVEC(ioapic_intr83), 154 IDTVEC(ioapic_intr84), 155 IDTVEC(ioapic_intr85), 156 IDTVEC(ioapic_intr86), 157 IDTVEC(ioapic_intr87), 158 IDTVEC(ioapic_intr88), 159 IDTVEC(ioapic_intr89), 160 IDTVEC(ioapic_intr90), 161 IDTVEC(ioapic_intr91), 162 IDTVEC(ioapic_intr92), 163 IDTVEC(ioapic_intr93), 164 IDTVEC(ioapic_intr94), 165 IDTVEC(ioapic_intr95), 166 IDTVEC(ioapic_intr96), 167 IDTVEC(ioapic_intr97), 168 IDTVEC(ioapic_intr98), 169 IDTVEC(ioapic_intr99), 170 IDTVEC(ioapic_intr100), 171 IDTVEC(ioapic_intr101), 172 IDTVEC(ioapic_intr102), 173 IDTVEC(ioapic_intr103), 174 IDTVEC(ioapic_intr104), 175 IDTVEC(ioapic_intr105), 176 IDTVEC(ioapic_intr106), 177 IDTVEC(ioapic_intr107), 178 IDTVEC(ioapic_intr108), 179 IDTVEC(ioapic_intr109), 180 IDTVEC(ioapic_intr110), 181 IDTVEC(ioapic_intr111), 182 IDTVEC(ioapic_intr112), 183 IDTVEC(ioapic_intr113), 184 IDTVEC(ioapic_intr114), 185 IDTVEC(ioapic_intr115), 186 IDTVEC(ioapic_intr116), 187 IDTVEC(ioapic_intr117), 188 IDTVEC(ioapic_intr118), 189 IDTVEC(ioapic_intr119), 190 IDTVEC(ioapic_intr120), 191 IDTVEC(ioapic_intr121), 192 IDTVEC(ioapic_intr122), 193 IDTVEC(ioapic_intr123), 194 IDTVEC(ioapic_intr124), 195 IDTVEC(ioapic_intr125), 196 IDTVEC(ioapic_intr126), 197 IDTVEC(ioapic_intr127), 198 IDTVEC(ioapic_intr128), 199 IDTVEC(ioapic_intr129), 200 IDTVEC(ioapic_intr130), 201 IDTVEC(ioapic_intr131), 202 IDTVEC(ioapic_intr132), 203 IDTVEC(ioapic_intr133), 204 IDTVEC(ioapic_intr134), 205 IDTVEC(ioapic_intr135), 206 IDTVEC(ioapic_intr136), 207 IDTVEC(ioapic_intr137), 208 IDTVEC(ioapic_intr138), 209 IDTVEC(ioapic_intr139), 210 IDTVEC(ioapic_intr140), 211 IDTVEC(ioapic_intr141), 212 IDTVEC(ioapic_intr142), 213 IDTVEC(ioapic_intr143), 214 IDTVEC(ioapic_intr144), 215 IDTVEC(ioapic_intr145), 216 IDTVEC(ioapic_intr146), 217 IDTVEC(ioapic_intr147), 218 IDTVEC(ioapic_intr148), 219 IDTVEC(ioapic_intr149), 220 IDTVEC(ioapic_intr150), 221 IDTVEC(ioapic_intr151), 222 IDTVEC(ioapic_intr152), 223 IDTVEC(ioapic_intr153), 224 IDTVEC(ioapic_intr154), 225 IDTVEC(ioapic_intr155), 226 IDTVEC(ioapic_intr156), 227 IDTVEC(ioapic_intr157), 228 IDTVEC(ioapic_intr158), 229 IDTVEC(ioapic_intr159), 230 IDTVEC(ioapic_intr160), 231 IDTVEC(ioapic_intr161), 232 IDTVEC(ioapic_intr162), 233 IDTVEC(ioapic_intr163), 234 IDTVEC(ioapic_intr164), 235 IDTVEC(ioapic_intr165), 236 IDTVEC(ioapic_intr166), 237 IDTVEC(ioapic_intr167), 238 IDTVEC(ioapic_intr168), 239 IDTVEC(ioapic_intr169), 240 IDTVEC(ioapic_intr170), 241 IDTVEC(ioapic_intr171), 242 IDTVEC(ioapic_intr172), 243 IDTVEC(ioapic_intr173), 244 IDTVEC(ioapic_intr174), 245 IDTVEC(ioapic_intr175), 246 IDTVEC(ioapic_intr176), 247 IDTVEC(ioapic_intr177), 248 IDTVEC(ioapic_intr178), 249 IDTVEC(ioapic_intr179), 250 IDTVEC(ioapic_intr180), 251 IDTVEC(ioapic_intr181), 252 IDTVEC(ioapic_intr182), 253 IDTVEC(ioapic_intr183), 254 IDTVEC(ioapic_intr184), 255 IDTVEC(ioapic_intr185), 256 IDTVEC(ioapic_intr186), 257 IDTVEC(ioapic_intr187), 258 IDTVEC(ioapic_intr188), 259 IDTVEC(ioapic_intr189), 260 IDTVEC(ioapic_intr190), 261 IDTVEC(ioapic_intr191); 262 263 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = { 264 &IDTVEC(ioapic_intr0), 265 &IDTVEC(ioapic_intr1), 266 &IDTVEC(ioapic_intr2), 267 &IDTVEC(ioapic_intr3), 268 &IDTVEC(ioapic_intr4), 269 &IDTVEC(ioapic_intr5), 270 &IDTVEC(ioapic_intr6), 271 &IDTVEC(ioapic_intr7), 272 &IDTVEC(ioapic_intr8), 273 &IDTVEC(ioapic_intr9), 274 &IDTVEC(ioapic_intr10), 275 &IDTVEC(ioapic_intr11), 276 &IDTVEC(ioapic_intr12), 277 &IDTVEC(ioapic_intr13), 278 &IDTVEC(ioapic_intr14), 279 &IDTVEC(ioapic_intr15), 280 &IDTVEC(ioapic_intr16), 281 &IDTVEC(ioapic_intr17), 282 &IDTVEC(ioapic_intr18), 283 &IDTVEC(ioapic_intr19), 284 &IDTVEC(ioapic_intr20), 285 &IDTVEC(ioapic_intr21), 286 &IDTVEC(ioapic_intr22), 287 &IDTVEC(ioapic_intr23), 288 &IDTVEC(ioapic_intr24), 289 &IDTVEC(ioapic_intr25), 290 &IDTVEC(ioapic_intr26), 291 &IDTVEC(ioapic_intr27), 292 &IDTVEC(ioapic_intr28), 293 &IDTVEC(ioapic_intr29), 294 &IDTVEC(ioapic_intr30), 295 &IDTVEC(ioapic_intr31), 296 &IDTVEC(ioapic_intr32), 297 &IDTVEC(ioapic_intr33), 298 &IDTVEC(ioapic_intr34), 299 &IDTVEC(ioapic_intr35), 300 &IDTVEC(ioapic_intr36), 301 &IDTVEC(ioapic_intr37), 302 &IDTVEC(ioapic_intr38), 303 &IDTVEC(ioapic_intr39), 304 &IDTVEC(ioapic_intr40), 305 &IDTVEC(ioapic_intr41), 306 &IDTVEC(ioapic_intr42), 307 &IDTVEC(ioapic_intr43), 308 &IDTVEC(ioapic_intr44), 309 &IDTVEC(ioapic_intr45), 310 &IDTVEC(ioapic_intr46), 311 &IDTVEC(ioapic_intr47), 312 &IDTVEC(ioapic_intr48), 313 &IDTVEC(ioapic_intr49), 314 &IDTVEC(ioapic_intr50), 315 &IDTVEC(ioapic_intr51), 316 &IDTVEC(ioapic_intr52), 317 &IDTVEC(ioapic_intr53), 318 &IDTVEC(ioapic_intr54), 319 &IDTVEC(ioapic_intr55), 320 &IDTVEC(ioapic_intr56), 321 &IDTVEC(ioapic_intr57), 322 &IDTVEC(ioapic_intr58), 323 &IDTVEC(ioapic_intr59), 324 &IDTVEC(ioapic_intr60), 325 &IDTVEC(ioapic_intr61), 326 &IDTVEC(ioapic_intr62), 327 &IDTVEC(ioapic_intr63), 328 &IDTVEC(ioapic_intr64), 329 &IDTVEC(ioapic_intr65), 330 &IDTVEC(ioapic_intr66), 331 &IDTVEC(ioapic_intr67), 332 &IDTVEC(ioapic_intr68), 333 &IDTVEC(ioapic_intr69), 334 &IDTVEC(ioapic_intr70), 335 &IDTVEC(ioapic_intr71), 336 &IDTVEC(ioapic_intr72), 337 &IDTVEC(ioapic_intr73), 338 &IDTVEC(ioapic_intr74), 339 &IDTVEC(ioapic_intr75), 340 &IDTVEC(ioapic_intr76), 341 &IDTVEC(ioapic_intr77), 342 &IDTVEC(ioapic_intr78), 343 &IDTVEC(ioapic_intr79), 344 &IDTVEC(ioapic_intr80), 345 &IDTVEC(ioapic_intr81), 346 &IDTVEC(ioapic_intr82), 347 &IDTVEC(ioapic_intr83), 348 &IDTVEC(ioapic_intr84), 349 &IDTVEC(ioapic_intr85), 350 &IDTVEC(ioapic_intr86), 351 &IDTVEC(ioapic_intr87), 352 &IDTVEC(ioapic_intr88), 353 &IDTVEC(ioapic_intr89), 354 &IDTVEC(ioapic_intr90), 355 &IDTVEC(ioapic_intr91), 356 &IDTVEC(ioapic_intr92), 357 &IDTVEC(ioapic_intr93), 358 &IDTVEC(ioapic_intr94), 359 &IDTVEC(ioapic_intr95), 360 &IDTVEC(ioapic_intr96), 361 &IDTVEC(ioapic_intr97), 362 &IDTVEC(ioapic_intr98), 363 &IDTVEC(ioapic_intr99), 364 &IDTVEC(ioapic_intr100), 365 &IDTVEC(ioapic_intr101), 366 &IDTVEC(ioapic_intr102), 367 &IDTVEC(ioapic_intr103), 368 &IDTVEC(ioapic_intr104), 369 &IDTVEC(ioapic_intr105), 370 &IDTVEC(ioapic_intr106), 371 &IDTVEC(ioapic_intr107), 372 &IDTVEC(ioapic_intr108), 373 &IDTVEC(ioapic_intr109), 374 &IDTVEC(ioapic_intr110), 375 &IDTVEC(ioapic_intr111), 376 &IDTVEC(ioapic_intr112), 377 &IDTVEC(ioapic_intr113), 378 &IDTVEC(ioapic_intr114), 379 &IDTVEC(ioapic_intr115), 380 &IDTVEC(ioapic_intr116), 381 &IDTVEC(ioapic_intr117), 382 &IDTVEC(ioapic_intr118), 383 &IDTVEC(ioapic_intr119), 384 &IDTVEC(ioapic_intr120), 385 &IDTVEC(ioapic_intr121), 386 &IDTVEC(ioapic_intr122), 387 &IDTVEC(ioapic_intr123), 388 &IDTVEC(ioapic_intr124), 389 &IDTVEC(ioapic_intr125), 390 &IDTVEC(ioapic_intr126), 391 &IDTVEC(ioapic_intr127), 392 &IDTVEC(ioapic_intr128), 393 &IDTVEC(ioapic_intr129), 394 &IDTVEC(ioapic_intr130), 395 &IDTVEC(ioapic_intr131), 396 &IDTVEC(ioapic_intr132), 397 &IDTVEC(ioapic_intr133), 398 &IDTVEC(ioapic_intr134), 399 &IDTVEC(ioapic_intr135), 400 &IDTVEC(ioapic_intr136), 401 &IDTVEC(ioapic_intr137), 402 &IDTVEC(ioapic_intr138), 403 &IDTVEC(ioapic_intr139), 404 &IDTVEC(ioapic_intr140), 405 &IDTVEC(ioapic_intr141), 406 &IDTVEC(ioapic_intr142), 407 &IDTVEC(ioapic_intr143), 408 &IDTVEC(ioapic_intr144), 409 &IDTVEC(ioapic_intr145), 410 &IDTVEC(ioapic_intr146), 411 &IDTVEC(ioapic_intr147), 412 &IDTVEC(ioapic_intr148), 413 &IDTVEC(ioapic_intr149), 414 &IDTVEC(ioapic_intr150), 415 &IDTVEC(ioapic_intr151), 416 &IDTVEC(ioapic_intr152), 417 &IDTVEC(ioapic_intr153), 418 &IDTVEC(ioapic_intr154), 419 &IDTVEC(ioapic_intr155), 420 &IDTVEC(ioapic_intr156), 421 &IDTVEC(ioapic_intr157), 422 &IDTVEC(ioapic_intr158), 423 &IDTVEC(ioapic_intr159), 424 &IDTVEC(ioapic_intr160), 425 &IDTVEC(ioapic_intr161), 426 &IDTVEC(ioapic_intr162), 427 &IDTVEC(ioapic_intr163), 428 &IDTVEC(ioapic_intr164), 429 &IDTVEC(ioapic_intr165), 430 &IDTVEC(ioapic_intr166), 431 &IDTVEC(ioapic_intr167), 432 &IDTVEC(ioapic_intr168), 433 &IDTVEC(ioapic_intr169), 434 &IDTVEC(ioapic_intr170), 435 &IDTVEC(ioapic_intr171), 436 &IDTVEC(ioapic_intr172), 437 &IDTVEC(ioapic_intr173), 438 &IDTVEC(ioapic_intr174), 439 &IDTVEC(ioapic_intr175), 440 &IDTVEC(ioapic_intr176), 441 &IDTVEC(ioapic_intr177), 442 &IDTVEC(ioapic_intr178), 443 &IDTVEC(ioapic_intr179), 444 &IDTVEC(ioapic_intr180), 445 &IDTVEC(ioapic_intr181), 446 &IDTVEC(ioapic_intr182), 447 &IDTVEC(ioapic_intr183), 448 &IDTVEC(ioapic_intr184), 449 &IDTVEC(ioapic_intr185), 450 &IDTVEC(ioapic_intr186), 451 &IDTVEC(ioapic_intr187), 452 &IDTVEC(ioapic_intr188), 453 &IDTVEC(ioapic_intr189), 454 &IDTVEC(ioapic_intr190), 455 &IDTVEC(ioapic_intr191) 456 }; 457 458 #define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET) 459 460 /* 461 * NOTE: Initialized before VM so cannot use kmalloc() for this array. 462 */ 463 static struct ioapic_irqmap { 464 int im_type; /* IOAPIC_IMT_ */ 465 enum intr_trigger im_trig; 466 enum intr_polarity im_pola; 467 int im_gsi; 468 int im_msi_base; 469 uint32_t im_flags; /* IOAPIC_IMF_ */ 470 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS]; 471 472 static struct lwkt_token ioapic_irqmap_tok = 473 LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token); 474 475 #define IOAPIC_IMT_UNUSED 0 476 #define IOAPIC_IMT_RESERVED 1 477 #define IOAPIC_IMT_LEGACY 2 478 #define IOAPIC_IMT_SYSCALL 3 479 #define IOAPIC_IMT_MSI 4 480 #define IOAPIC_IMT_MSIX 5 481 482 #define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \ 483 (map)->im_type != IOAPIC_IMT_SYSCALL) 484 485 #define IOAPIC_IMF_CONF 0x1 486 487 extern void IOAPIC_INTREN(int); 488 extern void IOAPIC_INTRDIS(int); 489 490 extern int imcr_present; 491 492 static void ioapic_abi_intr_enable(int); 493 static void ioapic_abi_intr_disable(int); 494 static void ioapic_abi_intr_setup(int, int); 495 static void ioapic_abi_intr_teardown(int); 496 497 static void ioapic_abi_legacy_intr_config(int, 498 enum intr_trigger, enum intr_polarity); 499 static int ioapic_abi_legacy_intr_cpuid(int); 500 static int ioapic_abi_legacy_intr_find(int, 501 enum intr_trigger, enum intr_polarity); 502 static int ioapic_abi_legacy_intr_find_bygsi(int, 503 enum intr_trigger, enum intr_polarity); 504 505 static int ioapic_abi_msi_alloc(int [], int, int); 506 static void ioapic_abi_msi_release(const int [], int, int); 507 static void ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int); 508 static int ioapic_abi_msix_alloc(int *, int); 509 static void ioapic_abi_msix_release(int, int); 510 511 static int ioapic_abi_msi_alloc_intern(int, const char *, 512 int [], int, int); 513 static void ioapic_abi_msi_release_intern(int, const char *, 514 const int [], int, int); 515 516 static void ioapic_abi_finalize(void); 517 static void ioapic_abi_cleanup(void); 518 static void ioapic_abi_setdefault(void); 519 static void ioapic_abi_stabilize(void); 520 static void ioapic_abi_initmap(void); 521 static void ioapic_abi_rman_setup(struct rman *); 522 523 static int ioapic_abi_gsi_cpuid(int, int); 524 static int ioapic_find_unused_irqmap(int); 525 526 struct machintr_abi MachIntrABI_IOAPIC = { 527 MACHINTR_IOAPIC, 528 .intr_disable = ioapic_abi_intr_disable, 529 .intr_enable = ioapic_abi_intr_enable, 530 .intr_setup = ioapic_abi_intr_setup, 531 .intr_teardown = ioapic_abi_intr_teardown, 532 533 .legacy_intr_config = ioapic_abi_legacy_intr_config, 534 .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid, 535 .legacy_intr_find = ioapic_abi_legacy_intr_find, 536 .legacy_intr_find_bygsi = ioapic_abi_legacy_intr_find_bygsi, 537 538 .msi_alloc = ioapic_abi_msi_alloc, 539 .msi_release = ioapic_abi_msi_release, 540 .msi_map = ioapic_abi_msi_map, 541 .msix_alloc = ioapic_abi_msix_alloc, 542 .msix_release = ioapic_abi_msix_release, 543 544 .finalize = ioapic_abi_finalize, 545 .cleanup = ioapic_abi_cleanup, 546 .setdefault = ioapic_abi_setdefault, 547 .stabilize = ioapic_abi_stabilize, 548 .initmap = ioapic_abi_initmap, 549 .rman_setup = ioapic_abi_rman_setup 550 }; 551 552 static int ioapic_abi_extint_irq = -1; 553 static int ioapic_abi_legacy_irq_max; 554 static int ioapic_abi_gsi_balance = 1; 555 static int ioapic_abi_msi_start; /* NOTE: for testing only */ 556 557 struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS]; 558 559 static void 560 ioapic_abi_intr_enable(int irq) 561 { 562 const struct ioapic_irqmap *map; 563 564 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS, 565 ("ioapic enable, invalid irq %d", irq)); 566 567 map = &ioapic_irqmaps[mycpuid][irq]; 568 KASSERT(IOAPIC_IMT_ISHWI(map), 569 ("ioapic enable, not hwi irq %d, type %d, cpu%d", 570 irq, map->im_type, mycpuid)); 571 if (map->im_type != IOAPIC_IMT_LEGACY) 572 return; 573 574 IOAPIC_INTREN(irq); 575 } 576 577 static void 578 ioapic_abi_intr_disable(int irq) 579 { 580 const struct ioapic_irqmap *map; 581 582 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS, 583 ("ioapic disable, invalid irq %d", irq)); 584 585 map = &ioapic_irqmaps[mycpuid][irq]; 586 KASSERT(IOAPIC_IMT_ISHWI(map), 587 ("ioapic disable, not hwi irq %d, type %d, cpu%d", 588 irq, map->im_type, mycpuid)); 589 if (map->im_type != IOAPIC_IMT_LEGACY) 590 return; 591 592 IOAPIC_INTRDIS(irq); 593 } 594 595 static void 596 ioapic_abi_finalize(void) 597 { 598 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC); 599 KKASSERT(ioapic_enable); 600 601 /* 602 * If an IMCR is present, program bit 0 to disconnect the 8259 603 * from the BSP. 604 */ 605 if (imcr_present) { 606 outb(0x22, 0x70); /* select IMCR */ 607 outb(0x23, 0x01); /* disconnect 8259 */ 608 } 609 } 610 611 /* 612 * This routine is called after physical interrupts are enabled but before 613 * the critical section is released. We need to clean out any interrupts 614 * that had already been posted to the cpu. 615 */ 616 static void 617 ioapic_abi_cleanup(void) 618 { 619 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 620 } 621 622 /* Must never be called */ 623 static void 624 ioapic_abi_stabilize(void) 625 { 626 panic("ioapic_stabilize is called"); 627 } 628 629 static void 630 ioapic_abi_intr_setup(int intr, int flags) 631 { 632 const struct ioapic_irqmap *map; 633 int vector, select; 634 uint32_t value; 635 register_t ef; 636 637 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 638 ("ioapic setup, invalid irq %d", intr)); 639 640 map = &ioapic_irqmaps[mycpuid][intr]; 641 KASSERT(IOAPIC_IMT_ISHWI(map), 642 ("ioapic setup, not hwi irq %d, type %d, cpu%d", 643 intr, map->im_type, mycpuid)); 644 if (map->im_type != IOAPIC_IMT_LEGACY) 645 return; 646 647 KASSERT(ioapic_irqs[intr].io_addr != NULL, 648 ("ioapic setup, no GSI information, irq %d", intr)); 649 650 ef = read_rflags(); 651 cpu_disable_intr(); 652 653 vector = IDT_OFFSET + intr; 654 655 /* 656 * Now reprogram the vector in the IO APIC. In order to avoid 657 * losing an EOI for a level interrupt, which is vector based, 658 * make sure that the IO APIC is programmed for edge-triggering 659 * first, then reprogrammed with the new vector. This should 660 * clear the IRR bit. 661 */ 662 imen_lock(); 663 664 select = ioapic_irqs[intr].io_idx; 665 value = ioapic_read(ioapic_irqs[intr].io_addr, select); 666 value |= IOART_INTMSET; 667 668 ioapic_write(ioapic_irqs[intr].io_addr, select, 669 (value & ~APIC_TRIGMOD_MASK)); 670 ioapic_write(ioapic_irqs[intr].io_addr, select, 671 (value & ~IOART_INTVEC) | vector); 672 673 imen_unlock(); 674 675 IOAPIC_INTREN(intr); 676 677 write_rflags(ef); 678 } 679 680 static void 681 ioapic_abi_intr_teardown(int intr) 682 { 683 const struct ioapic_irqmap *map; 684 int vector, select; 685 uint32_t value; 686 register_t ef; 687 688 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 689 ("ioapic teardown, invalid irq %d", intr)); 690 691 map = &ioapic_irqmaps[mycpuid][intr]; 692 KASSERT(IOAPIC_IMT_ISHWI(map), 693 ("ioapic teardown, not hwi irq %d, type %d, cpu%d", 694 intr, map->im_type, mycpuid)); 695 if (map->im_type != IOAPIC_IMT_LEGACY) 696 return; 697 698 KASSERT(ioapic_irqs[intr].io_addr != NULL, 699 ("ioapic teardown, no GSI information, irq %d", intr)); 700 701 ef = read_rflags(); 702 cpu_disable_intr(); 703 704 /* 705 * Teardown an interrupt vector. The vector should already be 706 * installed in the cpu's IDT, but make sure. 707 */ 708 IOAPIC_INTRDIS(intr); 709 710 vector = IDT_OFFSET + intr; 711 712 /* 713 * In order to avoid losing an EOI for a level interrupt, which 714 * is vector based, make sure that the IO APIC is programmed for 715 * edge-triggering first, then reprogrammed with the new vector. 716 * This should clear the IRR bit. 717 */ 718 imen_lock(); 719 720 select = ioapic_irqs[intr].io_idx; 721 value = ioapic_read(ioapic_irqs[intr].io_addr, select); 722 723 ioapic_write(ioapic_irqs[intr].io_addr, select, 724 (value & ~APIC_TRIGMOD_MASK)); 725 ioapic_write(ioapic_irqs[intr].io_addr, select, 726 (value & ~IOART_INTVEC) | vector); 727 728 imen_unlock(); 729 730 write_rflags(ef); 731 } 732 733 static void 734 ioapic_abi_setdefault(void) 735 { 736 int intr; 737 738 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) { 739 if (intr == IOAPIC_HWI_SYSCALL) 740 continue; 741 setidt_global(IDT_OFFSET + intr, ioapic_intr[intr], 742 SDT_SYSIGT, SEL_KPL, 0); 743 } 744 } 745 746 static void 747 ioapic_abi_initmap(void) 748 { 749 int cpu; 750 751 kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance); 752 753 kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start); 754 ioapic_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ 755 756 /* 757 * NOTE: ncpus is not ready yet 758 */ 759 for (cpu = 0; cpu < MAXCPU; ++cpu) { 760 int i; 761 762 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) { 763 ioapic_irqmaps[cpu][i].im_gsi = -1; 764 ioapic_irqmaps[cpu][i].im_msi_base = -1; 765 } 766 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type = 767 IOAPIC_IMT_SYSCALL; 768 } 769 } 770 771 static int 772 ioapic_find_unused_irqmap(int gsi) 773 { 774 int cpuid, i; 775 776 cpuid = ioapic_abi_gsi_cpuid(-1, gsi); 777 778 for (i = ISA_IRQ_CNT; i < IOAPIC_HWI_VECTORS; ++i) { 779 if (i == acpi_sci_irqno()) 780 continue; 781 if (ioapic_irqmaps[cpuid][i].im_type == IOAPIC_IMT_UNUSED) 782 return i; 783 } 784 return -1; 785 } 786 787 void 788 ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig, 789 enum intr_polarity pola) 790 { 791 struct ioapic_irqinfo *info; 792 struct ioapic_irqmap *map; 793 void *ioaddr; 794 int pin, cpuid; 795 796 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 797 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW); 798 799 KKASSERT(irq >= 0); 800 if (irq >= IOAPIC_HWI_VECTORS) { 801 /* 802 * Some BIOSes seem to assume that all 256 IDT vectors 803 * could be used, while we limit the available IDT 804 * vectors to 192; find an unused IRQ for this GSI. 805 */ 806 irq = ioapic_find_unused_irqmap(gsi); 807 if (irq < 0) { 808 kprintf("failed to find unused irq for gsi %d, " 809 "overflow\n", gsi); 810 return; 811 } 812 } 813 KKASSERT(irq < IOAPIC_HWI_VECTORS); 814 815 cpuid = ioapic_abi_gsi_cpuid(irq, gsi); 816 map = &ioapic_irqmaps[cpuid][irq]; 817 818 if (map->im_type != IOAPIC_IMT_UNUSED) { 819 /* 820 * There are so many IOAPICs, that 1:1 mapping 821 * of GSI and IRQ hits SYSCALL entry. 822 */ 823 irq = ioapic_find_unused_irqmap(gsi); 824 if (irq < 0) { 825 kprintf("failed to find unused irq for gsi %d, " 826 "conflict\n", gsi); 827 return; 828 } 829 KKASSERT(irq < IOAPIC_HWI_VECTORS); 830 831 cpuid = ioapic_abi_gsi_cpuid(irq, gsi); 832 map = &ioapic_irqmaps[cpuid][irq]; 833 } 834 835 if (irq > ioapic_abi_legacy_irq_max) 836 ioapic_abi_legacy_irq_max = irq; 837 838 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED); 839 map->im_type = IOAPIC_IMT_LEGACY; 840 841 map->im_gsi = gsi; 842 map->im_trig = trig; 843 map->im_pola = pola; 844 845 if (bootverbose) { 846 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n", 847 irq, map->im_gsi, 848 intr_str_trigger(map->im_trig), 849 intr_str_polarity(map->im_pola)); 850 } 851 852 pin = ioapic_gsi_pin(map->im_gsi); 853 ioaddr = ioapic_gsi_ioaddr(map->im_gsi); 854 855 info = &ioapic_irqs[irq]; 856 857 imen_lock(); 858 859 info->io_addr = ioaddr; 860 info->io_idx = IOAPIC_REDTBL + (2 * pin); 861 info->io_flags = IOAPIC_IRQI_FLAG_MASKED; 862 if (map->im_trig == INTR_TRIGGER_LEVEL) 863 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL; 864 865 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq, 866 map->im_trig, map->im_pola, cpuid); 867 868 imen_unlock(); 869 } 870 871 void 872 ioapic_fixup_legacy_irqmaps(void) 873 { 874 int cpu; 875 876 for (cpu = 0; cpu < ncpus; ++cpu) { 877 int i; 878 879 for (i = 0; i < ISA_IRQ_CNT; ++i) { 880 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i]; 881 882 if (map->im_type == IOAPIC_IMT_UNUSED) { 883 map->im_type = IOAPIC_IMT_RESERVED; 884 if (bootverbose) { 885 kprintf("IOAPIC: " 886 "cpu%d irq %d reserved\n", cpu, i); 887 } 888 } 889 } 890 } 891 892 ioapic_abi_legacy_irq_max += 1; 893 if (bootverbose) { 894 kprintf("IOAPIC: legacy irq max %d\n", 895 ioapic_abi_legacy_irq_max); 896 } 897 } 898 899 static int 900 ioapic_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig, 901 enum intr_polarity pola) 902 { 903 int cpu; 904 905 #ifdef INVARIANTS 906 if (trig == INTR_TRIGGER_CONFORM) { 907 KKASSERT(pola == INTR_POLARITY_CONFORM); 908 } else { 909 KKASSERT(trig == INTR_TRIGGER_EDGE || 910 trig == INTR_TRIGGER_LEVEL); 911 KKASSERT(pola == INTR_POLARITY_HIGH || 912 pola == INTR_POLARITY_LOW); 913 } 914 #endif 915 916 for (cpu = 0; cpu < ncpus; ++cpu) { 917 int irq; 918 919 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) { 920 const struct ioapic_irqmap *map = 921 &ioapic_irqmaps[cpu][irq]; 922 923 if (map->im_gsi == gsi) { 924 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY); 925 926 if ((map->im_flags & IOAPIC_IMF_CONF) && 927 trig != INTR_TRIGGER_CONFORM && 928 pola != INTR_POLARITY_CONFORM) { 929 if (map->im_trig != trig || 930 map->im_pola != pola) 931 return -1; 932 } 933 return irq; 934 } 935 } 936 } 937 return -1; 938 } 939 940 static int 941 ioapic_abi_legacy_intr_find(int irq, enum intr_trigger trig, 942 enum intr_polarity pola) 943 { 944 int cpu; 945 946 #ifdef INVARIANTS 947 if (trig == INTR_TRIGGER_CONFORM) { 948 KKASSERT(pola == INTR_POLARITY_CONFORM); 949 } else { 950 KKASSERT(trig == INTR_TRIGGER_EDGE || 951 trig == INTR_TRIGGER_LEVEL); 952 KKASSERT(pola == INTR_POLARITY_HIGH || 953 pola == INTR_POLARITY_LOW); 954 } 955 #endif 956 957 if (irq < 0 || irq >= ioapic_abi_legacy_irq_max) 958 return -1; 959 960 for (cpu = 0; cpu < ncpus; ++cpu) { 961 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq]; 962 963 if (map->im_type == IOAPIC_IMT_LEGACY) { 964 if ((map->im_flags & IOAPIC_IMF_CONF) && 965 trig != INTR_TRIGGER_CONFORM && 966 pola != INTR_POLARITY_CONFORM) { 967 if (map->im_trig != trig || 968 map->im_pola != pola) 969 return -1; 970 } 971 return irq; 972 } 973 } 974 return -1; 975 } 976 977 static void 978 ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig, 979 enum intr_polarity pola) 980 { 981 struct ioapic_irqinfo *info; 982 struct ioapic_irqmap *map = NULL; 983 void *ioaddr; 984 int pin, cpuid; 985 986 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 987 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW); 988 989 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max); 990 for (cpuid = 0; cpuid < ncpus; ++cpuid) { 991 map = &ioapic_irqmaps[cpuid][irq]; 992 if (map->im_type == IOAPIC_IMT_LEGACY) 993 break; 994 } 995 KKASSERT(cpuid < ncpus); 996 997 #ifdef notyet 998 if (map->im_flags & IOAPIC_IMF_CONF) { 999 if (trig != map->im_trig) { 1000 panic("ioapic_intr_config: trig %s -> %s", 1001 intr_str_trigger(map->im_trig), 1002 intr_str_trigger(trig)); 1003 } 1004 if (pola != map->im_pola) { 1005 panic("ioapic_intr_config: pola %s -> %s", 1006 intr_str_polarity(map->im_pola), 1007 intr_str_polarity(pola)); 1008 } 1009 return; 1010 } 1011 #endif 1012 map->im_flags |= IOAPIC_IMF_CONF; 1013 1014 if (trig == map->im_trig && pola == map->im_pola) 1015 return; 1016 1017 if (bootverbose) { 1018 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n", 1019 irq, map->im_gsi, 1020 intr_str_trigger(map->im_trig), 1021 intr_str_polarity(map->im_pola), 1022 intr_str_trigger(trig), 1023 intr_str_polarity(pola)); 1024 } 1025 map->im_trig = trig; 1026 map->im_pola = pola; 1027 1028 pin = ioapic_gsi_pin(map->im_gsi); 1029 ioaddr = ioapic_gsi_ioaddr(map->im_gsi); 1030 1031 info = &ioapic_irqs[irq]; 1032 1033 imen_lock(); 1034 1035 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL; 1036 if (map->im_trig == INTR_TRIGGER_LEVEL) 1037 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL; 1038 1039 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq, 1040 map->im_trig, map->im_pola, cpuid); 1041 1042 imen_unlock(); 1043 } 1044 1045 int 1046 ioapic_conf_legacy_extint(int irq) 1047 { 1048 struct ioapic_irqinfo *info; 1049 struct ioapic_irqmap *map; 1050 void *ioaddr; 1051 int pin, error, vec; 1052 1053 /* XXX only irq0 is allowed */ 1054 KKASSERT(irq == 0); 1055 1056 vec = IDT_OFFSET + irq; 1057 1058 if (ioapic_abi_extint_irq == irq) 1059 return 0; 1060 else if (ioapic_abi_extint_irq >= 0) 1061 return EEXIST; 1062 1063 error = icu_ioapic_extint(irq, vec); 1064 if (error) 1065 return error; 1066 1067 /* ExtINT is always targeted to cpu0 */ 1068 map = &ioapic_irqmaps[0][irq]; 1069 1070 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED || 1071 map->im_type == IOAPIC_IMT_LEGACY); 1072 if (map->im_type == IOAPIC_IMT_LEGACY) { 1073 if (map->im_flags & IOAPIC_IMF_CONF) 1074 return EEXIST; 1075 } 1076 ioapic_abi_extint_irq = irq; 1077 1078 map->im_type = IOAPIC_IMT_LEGACY; 1079 map->im_trig = INTR_TRIGGER_EDGE; 1080 map->im_pola = INTR_POLARITY_HIGH; 1081 map->im_flags = IOAPIC_IMF_CONF; 1082 1083 map->im_gsi = ioapic_extpin_gsi(); 1084 KKASSERT(map->im_gsi >= 0); 1085 1086 if (bootverbose) { 1087 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n", 1088 irq, map->im_gsi, 1089 intr_str_trigger(map->im_trig), 1090 intr_str_polarity(map->im_pola)); 1091 } 1092 1093 pin = ioapic_gsi_pin(map->im_gsi); 1094 ioaddr = ioapic_gsi_ioaddr(map->im_gsi); 1095 1096 info = &ioapic_irqs[irq]; 1097 1098 imen_lock(); 1099 1100 info->io_addr = ioaddr; 1101 info->io_idx = IOAPIC_REDTBL + (2 * pin); 1102 info->io_flags = IOAPIC_IRQI_FLAG_MASKED; 1103 1104 ioapic_extpin_setup(ioaddr, pin, vec); 1105 1106 imen_unlock(); 1107 1108 return 0; 1109 } 1110 1111 static int 1112 ioapic_abi_legacy_intr_cpuid(int irq) 1113 { 1114 const struct ioapic_irqmap *map = NULL; 1115 int cpuid; 1116 1117 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max); 1118 1119 for (cpuid = 0; cpuid < ncpus; ++cpuid) { 1120 map = &ioapic_irqmaps[cpuid][irq]; 1121 if (map->im_type == IOAPIC_IMT_LEGACY) 1122 return cpuid; 1123 } 1124 1125 /* XXX some drivers tries to peek at reserved IRQs */ 1126 for (cpuid = 0; cpuid < ncpus; ++cpuid) { 1127 map = &ioapic_irqmaps[cpuid][irq]; 1128 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED); 1129 } 1130 return 0; 1131 } 1132 1133 static int 1134 ioapic_abi_gsi_cpuid(int irq, int gsi) 1135 { 1136 char envpath[32]; 1137 int cpuid = -1; 1138 1139 KKASSERT(gsi >= 0); 1140 1141 if (irq == 0 || gsi == 0) { 1142 KKASSERT(irq >= 0); 1143 if (bootverbose) { 1144 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n", 1145 irq, gsi); 1146 } 1147 return 0; 1148 } 1149 1150 if (irq >= 0 && irq == acpi_sci_irqno()) { 1151 if (bootverbose) { 1152 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n", 1153 irq, gsi); 1154 } 1155 return 0; 1156 } 1157 1158 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi); 1159 kgetenv_int(envpath, &cpuid); 1160 1161 if (cpuid < 0) { 1162 if (!ioapic_abi_gsi_balance) { 1163 if (irq >= 0 && bootverbose) { 1164 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 " 1165 "(fixed)\n", irq, gsi); 1166 } 1167 return 0; 1168 } 1169 1170 cpuid = gsi % ncpus; 1171 if (irq >= 0 && bootverbose) { 1172 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n", 1173 irq, gsi, cpuid); 1174 } 1175 } else if (cpuid >= ncpus) { 1176 cpuid = ncpus - 1; 1177 if (irq >= 0 && bootverbose) { 1178 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n", 1179 irq, gsi, cpuid); 1180 } 1181 } else { 1182 if (irq >= 0 && bootverbose) { 1183 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n", 1184 irq, gsi, cpuid); 1185 } 1186 } 1187 return cpuid; 1188 } 1189 1190 static void 1191 ioapic_abi_rman_setup(struct rman *rm) 1192 { 1193 int start, end, i; 1194 1195 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, 1196 ("invalid rman cpuid %d", rm->rm_cpuid)); 1197 1198 start = end = -1; 1199 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) { 1200 const struct ioapic_irqmap *map = 1201 &ioapic_irqmaps[rm->rm_cpuid][i]; 1202 1203 if (start < 0) { 1204 if (IOAPIC_IMT_ISHWI(map)) 1205 start = end = i; 1206 } else { 1207 if (IOAPIC_IMT_ISHWI(map)) { 1208 end = i; 1209 } else { 1210 KKASSERT(end >= 0); 1211 if (bootverbose) { 1212 kprintf("IOAPIC: rman cpu%d %d - %d\n", 1213 rm->rm_cpuid, start, end); 1214 } 1215 if (rman_manage_region(rm, start, end)) { 1216 panic("rman_manage_region" 1217 "(cpu%d %d - %d)", rm->rm_cpuid, 1218 start, end); 1219 } 1220 start = end = -1; 1221 } 1222 } 1223 } 1224 if (start >= 0) { 1225 KKASSERT(end >= 0); 1226 if (bootverbose) { 1227 kprintf("IOAPIC: rman cpu%d %d - %d\n", 1228 rm->rm_cpuid, start, end); 1229 } 1230 if (rman_manage_region(rm, start, end)) { 1231 panic("rman_manage_region(cpu%d %d - %d)", 1232 rm->rm_cpuid, start, end); 1233 } 1234 } 1235 } 1236 1237 static int 1238 ioapic_abi_msi_alloc_intern(int type, const char *desc, 1239 int intrs[], int count, int cpuid) 1240 { 1241 int i, error; 1242 1243 KASSERT(cpuid >= 0 && cpuid < ncpus, 1244 ("invalid cpuid %d", cpuid)); 1245 1246 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 1247 KASSERT((count & (count - 1)) == 0, 1248 ("count %d is not power of 2", count)); 1249 1250 lwkt_gettoken(&ioapic_irqmap_tok); 1251 1252 /* 1253 * NOTE: 1254 * Since IDT_OFFSET is 32, which is the maximum valid 'count', 1255 * we do not need to find out the first properly aligned 1256 * interrupt vector. 1257 */ 1258 1259 error = EMSGSIZE; 1260 for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) { 1261 int j; 1262 1263 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED) 1264 continue; 1265 1266 for (j = 1; j < count; ++j) { 1267 if (ioapic_irqmaps[cpuid][i + j].im_type != 1268 IOAPIC_IMT_UNUSED) 1269 break; 1270 } 1271 if (j != count) 1272 continue; 1273 1274 for (j = 0; j < count; ++j) { 1275 struct ioapic_irqmap *map; 1276 int intr = i + j; 1277 1278 map = &ioapic_irqmaps[cpuid][intr]; 1279 KASSERT(map->im_msi_base < 0, 1280 ("intr %d, stale %s-base %d", 1281 intr, desc, map->im_msi_base)); 1282 1283 map->im_type = type; 1284 map->im_msi_base = i; 1285 1286 intrs[j] = intr; 1287 msi_setup(intr, cpuid); 1288 1289 if (bootverbose) { 1290 kprintf("alloc %s intr %d on cpu%d\n", 1291 desc, intr, cpuid); 1292 } 1293 } 1294 error = 0; 1295 break; 1296 } 1297 1298 lwkt_reltoken(&ioapic_irqmap_tok); 1299 1300 return error; 1301 } 1302 1303 static void 1304 ioapic_abi_msi_release_intern(int type, const char *desc, 1305 const int intrs[], int count, int cpuid) 1306 { 1307 int i, msi_base = -1, intr_next = -1, mask; 1308 1309 KASSERT(cpuid >= 0 && cpuid < ncpus, 1310 ("invalid cpuid %d", cpuid)); 1311 1312 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 1313 1314 mask = count - 1; 1315 KASSERT((count & mask) == 0, ("count %d is not power of 2", count)); 1316 1317 lwkt_gettoken(&ioapic_irqmap_tok); 1318 1319 for (i = 0; i < count; ++i) { 1320 struct ioapic_irqmap *map; 1321 int intr = intrs[i]; 1322 1323 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 1324 ("invalid intr %d", intr)); 1325 1326 map = &ioapic_irqmaps[cpuid][intr]; 1327 KASSERT(map->im_type == type, 1328 ("trying to release non-%s intr %d, type %d", desc, 1329 intr, map->im_type)); 1330 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 1331 ("intr %d, invalid %s-base %d", intr, desc, 1332 map->im_msi_base)); 1333 KASSERT((map->im_msi_base & mask) == 0, 1334 ("intr %d, %s-base %d is not properly aligned %d", 1335 intr, desc, map->im_msi_base, count)); 1336 1337 if (msi_base < 0) { 1338 msi_base = map->im_msi_base; 1339 } else { 1340 KASSERT(map->im_msi_base == msi_base, 1341 ("intr %d, inconsistent %s-base, " 1342 "was %d, now %d", 1343 intr, desc, msi_base, map->im_msi_base)); 1344 } 1345 1346 if (intr_next < intr) 1347 intr_next = intr; 1348 1349 map->im_type = IOAPIC_IMT_UNUSED; 1350 map->im_msi_base = -1; 1351 1352 if (bootverbose) { 1353 kprintf("release %s intr %d on cpu%d\n", 1354 desc, intr, cpuid); 1355 } 1356 } 1357 1358 KKASSERT(intr_next > 0); 1359 KKASSERT(msi_base >= 0); 1360 1361 ++intr_next; 1362 if (intr_next < IOAPIC_HWI_VECTORS) { 1363 const struct ioapic_irqmap *map = 1364 &ioapic_irqmaps[cpuid][intr_next]; 1365 1366 if (map->im_type == type) { 1367 KASSERT(map->im_msi_base != msi_base, 1368 ("more than %d %s was allocated", count, desc)); 1369 } 1370 } 1371 1372 lwkt_reltoken(&ioapic_irqmap_tok); 1373 } 1374 1375 static int 1376 ioapic_abi_msi_alloc(int intrs[], int count, int cpuid) 1377 { 1378 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSI, "MSI", 1379 intrs, count, cpuid); 1380 } 1381 1382 static void 1383 ioapic_abi_msi_release(const int intrs[], int count, int cpuid) 1384 { 1385 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSI, "MSI", 1386 intrs, count, cpuid); 1387 } 1388 1389 static int 1390 ioapic_abi_msix_alloc(int *intr, int cpuid) 1391 { 1392 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSIX, "MSI-X", 1393 intr, 1, cpuid); 1394 } 1395 1396 static void 1397 ioapic_abi_msix_release(int intr, int cpuid) 1398 { 1399 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSIX, "MSI-X", 1400 &intr, 1, cpuid); 1401 } 1402 1403 static void 1404 ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) 1405 { 1406 const struct ioapic_irqmap *map; 1407 1408 KASSERT(cpuid >= 0 && cpuid < ncpus, 1409 ("invalid cpuid %d", cpuid)); 1410 1411 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 1412 ("invalid intr %d", intr)); 1413 1414 lwkt_gettoken(&ioapic_irqmap_tok); 1415 1416 map = &ioapic_irqmaps[cpuid][intr]; 1417 KASSERT(map->im_type == IOAPIC_IMT_MSI || 1418 map->im_type == IOAPIC_IMT_MSIX, 1419 ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type)); 1420 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 1421 ("intr %d, invalid %s-base %d", intr, 1422 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X", 1423 map->im_msi_base)); 1424 1425 msi_map(map->im_msi_base, addr, data, cpuid); 1426 1427 if (bootverbose) { 1428 kprintf("map %s intr %d on cpu%d\n", 1429 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X", 1430 intr, cpuid); 1431 } 1432 1433 lwkt_reltoken(&ioapic_irqmap_tok); 1434 } 1435