1 /* 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 1996, by Steve Passe. All rights reserved. 4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * This code is derived from software contributed to Berkeley by 11 * William Jolitz. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 3. Neither the name of The DragonFly Project nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific, prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/machintr.h> 45 #include <sys/interrupt.h> 46 #include <sys/bus.h> 47 #include <sys/rman.h> 48 #include <sys/thread2.h> 49 50 #include <machine/smp.h> 51 #include <machine/segments.h> 52 #include <machine/md_var.h> 53 #include <machine/intr_machdep.h> 54 #include <machine/globaldata.h> 55 #include <machine/msi_var.h> 56 57 #include <machine_base/isa/isa_intr.h> 58 #include <machine_base/icu/icu.h> 59 #include <machine_base/icu/icu_var.h> 60 #include <machine_base/apic/ioapic.h> 61 #include <machine_base/apic/ioapic_abi.h> 62 #include <machine_base/apic/ioapic_ipl.h> 63 #include <machine_base/apic/apicreg.h> 64 65 #include <dev/acpica/acpi_sci_var.h> 66 67 #define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS 68 69 extern inthand_t 70 IDTVEC(ioapic_intr0), 71 IDTVEC(ioapic_intr1), 72 IDTVEC(ioapic_intr2), 73 IDTVEC(ioapic_intr3), 74 IDTVEC(ioapic_intr4), 75 IDTVEC(ioapic_intr5), 76 IDTVEC(ioapic_intr6), 77 IDTVEC(ioapic_intr7), 78 IDTVEC(ioapic_intr8), 79 IDTVEC(ioapic_intr9), 80 IDTVEC(ioapic_intr10), 81 IDTVEC(ioapic_intr11), 82 IDTVEC(ioapic_intr12), 83 IDTVEC(ioapic_intr13), 84 IDTVEC(ioapic_intr14), 85 IDTVEC(ioapic_intr15), 86 IDTVEC(ioapic_intr16), 87 IDTVEC(ioapic_intr17), 88 IDTVEC(ioapic_intr18), 89 IDTVEC(ioapic_intr19), 90 IDTVEC(ioapic_intr20), 91 IDTVEC(ioapic_intr21), 92 IDTVEC(ioapic_intr22), 93 IDTVEC(ioapic_intr23), 94 IDTVEC(ioapic_intr24), 95 IDTVEC(ioapic_intr25), 96 IDTVEC(ioapic_intr26), 97 IDTVEC(ioapic_intr27), 98 IDTVEC(ioapic_intr28), 99 IDTVEC(ioapic_intr29), 100 IDTVEC(ioapic_intr30), 101 IDTVEC(ioapic_intr31), 102 IDTVEC(ioapic_intr32), 103 IDTVEC(ioapic_intr33), 104 IDTVEC(ioapic_intr34), 105 IDTVEC(ioapic_intr35), 106 IDTVEC(ioapic_intr36), 107 IDTVEC(ioapic_intr37), 108 IDTVEC(ioapic_intr38), 109 IDTVEC(ioapic_intr39), 110 IDTVEC(ioapic_intr40), 111 IDTVEC(ioapic_intr41), 112 IDTVEC(ioapic_intr42), 113 IDTVEC(ioapic_intr43), 114 IDTVEC(ioapic_intr44), 115 IDTVEC(ioapic_intr45), 116 IDTVEC(ioapic_intr46), 117 IDTVEC(ioapic_intr47), 118 IDTVEC(ioapic_intr48), 119 IDTVEC(ioapic_intr49), 120 IDTVEC(ioapic_intr50), 121 IDTVEC(ioapic_intr51), 122 IDTVEC(ioapic_intr52), 123 IDTVEC(ioapic_intr53), 124 IDTVEC(ioapic_intr54), 125 IDTVEC(ioapic_intr55), 126 IDTVEC(ioapic_intr56), 127 IDTVEC(ioapic_intr57), 128 IDTVEC(ioapic_intr58), 129 IDTVEC(ioapic_intr59), 130 IDTVEC(ioapic_intr60), 131 IDTVEC(ioapic_intr61), 132 IDTVEC(ioapic_intr62), 133 IDTVEC(ioapic_intr63), 134 IDTVEC(ioapic_intr64), 135 IDTVEC(ioapic_intr65), 136 IDTVEC(ioapic_intr66), 137 IDTVEC(ioapic_intr67), 138 IDTVEC(ioapic_intr68), 139 IDTVEC(ioapic_intr69), 140 IDTVEC(ioapic_intr70), 141 IDTVEC(ioapic_intr71), 142 IDTVEC(ioapic_intr72), 143 IDTVEC(ioapic_intr73), 144 IDTVEC(ioapic_intr74), 145 IDTVEC(ioapic_intr75), 146 IDTVEC(ioapic_intr76), 147 IDTVEC(ioapic_intr77), 148 IDTVEC(ioapic_intr78), 149 IDTVEC(ioapic_intr79), 150 IDTVEC(ioapic_intr80), 151 IDTVEC(ioapic_intr81), 152 IDTVEC(ioapic_intr82), 153 IDTVEC(ioapic_intr83), 154 IDTVEC(ioapic_intr84), 155 IDTVEC(ioapic_intr85), 156 IDTVEC(ioapic_intr86), 157 IDTVEC(ioapic_intr87), 158 IDTVEC(ioapic_intr88), 159 IDTVEC(ioapic_intr89), 160 IDTVEC(ioapic_intr90), 161 IDTVEC(ioapic_intr91), 162 IDTVEC(ioapic_intr92), 163 IDTVEC(ioapic_intr93), 164 IDTVEC(ioapic_intr94), 165 IDTVEC(ioapic_intr95), 166 IDTVEC(ioapic_intr96), 167 IDTVEC(ioapic_intr97), 168 IDTVEC(ioapic_intr98), 169 IDTVEC(ioapic_intr99), 170 IDTVEC(ioapic_intr100), 171 IDTVEC(ioapic_intr101), 172 IDTVEC(ioapic_intr102), 173 IDTVEC(ioapic_intr103), 174 IDTVEC(ioapic_intr104), 175 IDTVEC(ioapic_intr105), 176 IDTVEC(ioapic_intr106), 177 IDTVEC(ioapic_intr107), 178 IDTVEC(ioapic_intr108), 179 IDTVEC(ioapic_intr109), 180 IDTVEC(ioapic_intr110), 181 IDTVEC(ioapic_intr111), 182 IDTVEC(ioapic_intr112), 183 IDTVEC(ioapic_intr113), 184 IDTVEC(ioapic_intr114), 185 IDTVEC(ioapic_intr115), 186 IDTVEC(ioapic_intr116), 187 IDTVEC(ioapic_intr117), 188 IDTVEC(ioapic_intr118), 189 IDTVEC(ioapic_intr119), 190 IDTVEC(ioapic_intr120), 191 IDTVEC(ioapic_intr121), 192 IDTVEC(ioapic_intr122), 193 IDTVEC(ioapic_intr123), 194 IDTVEC(ioapic_intr124), 195 IDTVEC(ioapic_intr125), 196 IDTVEC(ioapic_intr126), 197 IDTVEC(ioapic_intr127), 198 IDTVEC(ioapic_intr128), 199 IDTVEC(ioapic_intr129), 200 IDTVEC(ioapic_intr130), 201 IDTVEC(ioapic_intr131), 202 IDTVEC(ioapic_intr132), 203 IDTVEC(ioapic_intr133), 204 IDTVEC(ioapic_intr134), 205 IDTVEC(ioapic_intr135), 206 IDTVEC(ioapic_intr136), 207 IDTVEC(ioapic_intr137), 208 IDTVEC(ioapic_intr138), 209 IDTVEC(ioapic_intr139), 210 IDTVEC(ioapic_intr140), 211 IDTVEC(ioapic_intr141), 212 IDTVEC(ioapic_intr142), 213 IDTVEC(ioapic_intr143), 214 IDTVEC(ioapic_intr144), 215 IDTVEC(ioapic_intr145), 216 IDTVEC(ioapic_intr146), 217 IDTVEC(ioapic_intr147), 218 IDTVEC(ioapic_intr148), 219 IDTVEC(ioapic_intr149), 220 IDTVEC(ioapic_intr150), 221 IDTVEC(ioapic_intr151), 222 IDTVEC(ioapic_intr152), 223 IDTVEC(ioapic_intr153), 224 IDTVEC(ioapic_intr154), 225 IDTVEC(ioapic_intr155), 226 IDTVEC(ioapic_intr156), 227 IDTVEC(ioapic_intr157), 228 IDTVEC(ioapic_intr158), 229 IDTVEC(ioapic_intr159), 230 IDTVEC(ioapic_intr160), 231 IDTVEC(ioapic_intr161), 232 IDTVEC(ioapic_intr162), 233 IDTVEC(ioapic_intr163), 234 IDTVEC(ioapic_intr164), 235 IDTVEC(ioapic_intr165), 236 IDTVEC(ioapic_intr166), 237 IDTVEC(ioapic_intr167), 238 IDTVEC(ioapic_intr168), 239 IDTVEC(ioapic_intr169), 240 IDTVEC(ioapic_intr170), 241 IDTVEC(ioapic_intr171), 242 IDTVEC(ioapic_intr172), 243 IDTVEC(ioapic_intr173), 244 IDTVEC(ioapic_intr174), 245 IDTVEC(ioapic_intr175), 246 IDTVEC(ioapic_intr176), 247 IDTVEC(ioapic_intr177), 248 IDTVEC(ioapic_intr178), 249 IDTVEC(ioapic_intr179), 250 IDTVEC(ioapic_intr180), 251 IDTVEC(ioapic_intr181), 252 IDTVEC(ioapic_intr182), 253 IDTVEC(ioapic_intr183), 254 IDTVEC(ioapic_intr184), 255 IDTVEC(ioapic_intr185), 256 IDTVEC(ioapic_intr186), 257 IDTVEC(ioapic_intr187), 258 IDTVEC(ioapic_intr188), 259 IDTVEC(ioapic_intr189), 260 IDTVEC(ioapic_intr190), 261 IDTVEC(ioapic_intr191); 262 263 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = { 264 &IDTVEC(ioapic_intr0), 265 &IDTVEC(ioapic_intr1), 266 &IDTVEC(ioapic_intr2), 267 &IDTVEC(ioapic_intr3), 268 &IDTVEC(ioapic_intr4), 269 &IDTVEC(ioapic_intr5), 270 &IDTVEC(ioapic_intr6), 271 &IDTVEC(ioapic_intr7), 272 &IDTVEC(ioapic_intr8), 273 &IDTVEC(ioapic_intr9), 274 &IDTVEC(ioapic_intr10), 275 &IDTVEC(ioapic_intr11), 276 &IDTVEC(ioapic_intr12), 277 &IDTVEC(ioapic_intr13), 278 &IDTVEC(ioapic_intr14), 279 &IDTVEC(ioapic_intr15), 280 &IDTVEC(ioapic_intr16), 281 &IDTVEC(ioapic_intr17), 282 &IDTVEC(ioapic_intr18), 283 &IDTVEC(ioapic_intr19), 284 &IDTVEC(ioapic_intr20), 285 &IDTVEC(ioapic_intr21), 286 &IDTVEC(ioapic_intr22), 287 &IDTVEC(ioapic_intr23), 288 &IDTVEC(ioapic_intr24), 289 &IDTVEC(ioapic_intr25), 290 &IDTVEC(ioapic_intr26), 291 &IDTVEC(ioapic_intr27), 292 &IDTVEC(ioapic_intr28), 293 &IDTVEC(ioapic_intr29), 294 &IDTVEC(ioapic_intr30), 295 &IDTVEC(ioapic_intr31), 296 &IDTVEC(ioapic_intr32), 297 &IDTVEC(ioapic_intr33), 298 &IDTVEC(ioapic_intr34), 299 &IDTVEC(ioapic_intr35), 300 &IDTVEC(ioapic_intr36), 301 &IDTVEC(ioapic_intr37), 302 &IDTVEC(ioapic_intr38), 303 &IDTVEC(ioapic_intr39), 304 &IDTVEC(ioapic_intr40), 305 &IDTVEC(ioapic_intr41), 306 &IDTVEC(ioapic_intr42), 307 &IDTVEC(ioapic_intr43), 308 &IDTVEC(ioapic_intr44), 309 &IDTVEC(ioapic_intr45), 310 &IDTVEC(ioapic_intr46), 311 &IDTVEC(ioapic_intr47), 312 &IDTVEC(ioapic_intr48), 313 &IDTVEC(ioapic_intr49), 314 &IDTVEC(ioapic_intr50), 315 &IDTVEC(ioapic_intr51), 316 &IDTVEC(ioapic_intr52), 317 &IDTVEC(ioapic_intr53), 318 &IDTVEC(ioapic_intr54), 319 &IDTVEC(ioapic_intr55), 320 &IDTVEC(ioapic_intr56), 321 &IDTVEC(ioapic_intr57), 322 &IDTVEC(ioapic_intr58), 323 &IDTVEC(ioapic_intr59), 324 &IDTVEC(ioapic_intr60), 325 &IDTVEC(ioapic_intr61), 326 &IDTVEC(ioapic_intr62), 327 &IDTVEC(ioapic_intr63), 328 &IDTVEC(ioapic_intr64), 329 &IDTVEC(ioapic_intr65), 330 &IDTVEC(ioapic_intr66), 331 &IDTVEC(ioapic_intr67), 332 &IDTVEC(ioapic_intr68), 333 &IDTVEC(ioapic_intr69), 334 &IDTVEC(ioapic_intr70), 335 &IDTVEC(ioapic_intr71), 336 &IDTVEC(ioapic_intr72), 337 &IDTVEC(ioapic_intr73), 338 &IDTVEC(ioapic_intr74), 339 &IDTVEC(ioapic_intr75), 340 &IDTVEC(ioapic_intr76), 341 &IDTVEC(ioapic_intr77), 342 &IDTVEC(ioapic_intr78), 343 &IDTVEC(ioapic_intr79), 344 &IDTVEC(ioapic_intr80), 345 &IDTVEC(ioapic_intr81), 346 &IDTVEC(ioapic_intr82), 347 &IDTVEC(ioapic_intr83), 348 &IDTVEC(ioapic_intr84), 349 &IDTVEC(ioapic_intr85), 350 &IDTVEC(ioapic_intr86), 351 &IDTVEC(ioapic_intr87), 352 &IDTVEC(ioapic_intr88), 353 &IDTVEC(ioapic_intr89), 354 &IDTVEC(ioapic_intr90), 355 &IDTVEC(ioapic_intr91), 356 &IDTVEC(ioapic_intr92), 357 &IDTVEC(ioapic_intr93), 358 &IDTVEC(ioapic_intr94), 359 &IDTVEC(ioapic_intr95), 360 &IDTVEC(ioapic_intr96), 361 &IDTVEC(ioapic_intr97), 362 &IDTVEC(ioapic_intr98), 363 &IDTVEC(ioapic_intr99), 364 &IDTVEC(ioapic_intr100), 365 &IDTVEC(ioapic_intr101), 366 &IDTVEC(ioapic_intr102), 367 &IDTVEC(ioapic_intr103), 368 &IDTVEC(ioapic_intr104), 369 &IDTVEC(ioapic_intr105), 370 &IDTVEC(ioapic_intr106), 371 &IDTVEC(ioapic_intr107), 372 &IDTVEC(ioapic_intr108), 373 &IDTVEC(ioapic_intr109), 374 &IDTVEC(ioapic_intr110), 375 &IDTVEC(ioapic_intr111), 376 &IDTVEC(ioapic_intr112), 377 &IDTVEC(ioapic_intr113), 378 &IDTVEC(ioapic_intr114), 379 &IDTVEC(ioapic_intr115), 380 &IDTVEC(ioapic_intr116), 381 &IDTVEC(ioapic_intr117), 382 &IDTVEC(ioapic_intr118), 383 &IDTVEC(ioapic_intr119), 384 &IDTVEC(ioapic_intr120), 385 &IDTVEC(ioapic_intr121), 386 &IDTVEC(ioapic_intr122), 387 &IDTVEC(ioapic_intr123), 388 &IDTVEC(ioapic_intr124), 389 &IDTVEC(ioapic_intr125), 390 &IDTVEC(ioapic_intr126), 391 &IDTVEC(ioapic_intr127), 392 &IDTVEC(ioapic_intr128), 393 &IDTVEC(ioapic_intr129), 394 &IDTVEC(ioapic_intr130), 395 &IDTVEC(ioapic_intr131), 396 &IDTVEC(ioapic_intr132), 397 &IDTVEC(ioapic_intr133), 398 &IDTVEC(ioapic_intr134), 399 &IDTVEC(ioapic_intr135), 400 &IDTVEC(ioapic_intr136), 401 &IDTVEC(ioapic_intr137), 402 &IDTVEC(ioapic_intr138), 403 &IDTVEC(ioapic_intr139), 404 &IDTVEC(ioapic_intr140), 405 &IDTVEC(ioapic_intr141), 406 &IDTVEC(ioapic_intr142), 407 &IDTVEC(ioapic_intr143), 408 &IDTVEC(ioapic_intr144), 409 &IDTVEC(ioapic_intr145), 410 &IDTVEC(ioapic_intr146), 411 &IDTVEC(ioapic_intr147), 412 &IDTVEC(ioapic_intr148), 413 &IDTVEC(ioapic_intr149), 414 &IDTVEC(ioapic_intr150), 415 &IDTVEC(ioapic_intr151), 416 &IDTVEC(ioapic_intr152), 417 &IDTVEC(ioapic_intr153), 418 &IDTVEC(ioapic_intr154), 419 &IDTVEC(ioapic_intr155), 420 &IDTVEC(ioapic_intr156), 421 &IDTVEC(ioapic_intr157), 422 &IDTVEC(ioapic_intr158), 423 &IDTVEC(ioapic_intr159), 424 &IDTVEC(ioapic_intr160), 425 &IDTVEC(ioapic_intr161), 426 &IDTVEC(ioapic_intr162), 427 &IDTVEC(ioapic_intr163), 428 &IDTVEC(ioapic_intr164), 429 &IDTVEC(ioapic_intr165), 430 &IDTVEC(ioapic_intr166), 431 &IDTVEC(ioapic_intr167), 432 &IDTVEC(ioapic_intr168), 433 &IDTVEC(ioapic_intr169), 434 &IDTVEC(ioapic_intr170), 435 &IDTVEC(ioapic_intr171), 436 &IDTVEC(ioapic_intr172), 437 &IDTVEC(ioapic_intr173), 438 &IDTVEC(ioapic_intr174), 439 &IDTVEC(ioapic_intr175), 440 &IDTVEC(ioapic_intr176), 441 &IDTVEC(ioapic_intr177), 442 &IDTVEC(ioapic_intr178), 443 &IDTVEC(ioapic_intr179), 444 &IDTVEC(ioapic_intr180), 445 &IDTVEC(ioapic_intr181), 446 &IDTVEC(ioapic_intr182), 447 &IDTVEC(ioapic_intr183), 448 &IDTVEC(ioapic_intr184), 449 &IDTVEC(ioapic_intr185), 450 &IDTVEC(ioapic_intr186), 451 &IDTVEC(ioapic_intr187), 452 &IDTVEC(ioapic_intr188), 453 &IDTVEC(ioapic_intr189), 454 &IDTVEC(ioapic_intr190), 455 &IDTVEC(ioapic_intr191) 456 }; 457 458 #define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET) 459 460 static struct ioapic_irqmap { 461 int im_type; /* IOAPIC_IMT_ */ 462 enum intr_trigger im_trig; 463 enum intr_polarity im_pola; 464 int im_gsi; 465 int im_msi_base; 466 uint32_t im_flags; /* IOAPIC_IMF_ */ 467 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS]; 468 469 static struct lwkt_token ioapic_irqmap_tok = 470 LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token); 471 472 #define IOAPIC_IMT_UNUSED 0 473 #define IOAPIC_IMT_RESERVED 1 474 #define IOAPIC_IMT_LEGACY 2 475 #define IOAPIC_IMT_SYSCALL 3 476 #define IOAPIC_IMT_MSI 4 477 #define IOAPIC_IMT_MSIX 5 478 479 #define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \ 480 (map)->im_type != IOAPIC_IMT_SYSCALL) 481 482 #define IOAPIC_IMF_CONF 0x1 483 484 extern void IOAPIC_INTREN(int); 485 extern void IOAPIC_INTRDIS(int); 486 487 extern int imcr_present; 488 489 static void ioapic_abi_intr_enable(int); 490 static void ioapic_abi_intr_disable(int); 491 static void ioapic_abi_intr_setup(int, int); 492 static void ioapic_abi_intr_teardown(int); 493 494 static void ioapic_abi_legacy_intr_config(int, 495 enum intr_trigger, enum intr_polarity); 496 static int ioapic_abi_legacy_intr_cpuid(int); 497 static int ioapic_abi_legacy_intr_find(int, 498 enum intr_trigger, enum intr_polarity); 499 static int ioapic_abi_legacy_intr_find_bygsi(int, 500 enum intr_trigger, enum intr_polarity); 501 502 static int ioapic_abi_msi_alloc(int [], int, int); 503 static void ioapic_abi_msi_release(const int [], int, int); 504 static void ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int); 505 static int ioapic_abi_msix_alloc(int *, int); 506 static void ioapic_abi_msix_release(int, int); 507 508 static int ioapic_abi_msi_alloc_intern(int, const char *, 509 int [], int, int); 510 static void ioapic_abi_msi_release_intern(int, const char *, 511 const int [], int, int); 512 513 static void ioapic_abi_finalize(void); 514 static void ioapic_abi_cleanup(void); 515 static void ioapic_abi_setdefault(void); 516 static void ioapic_abi_stabilize(void); 517 static void ioapic_abi_initmap(void); 518 static void ioapic_abi_rman_setup(struct rman *); 519 520 static int ioapic_abi_gsi_cpuid(int, int); 521 static int ioapic_find_unused_irqmap(int); 522 523 struct machintr_abi MachIntrABI_IOAPIC = { 524 MACHINTR_IOAPIC, 525 .intr_disable = ioapic_abi_intr_disable, 526 .intr_enable = ioapic_abi_intr_enable, 527 .intr_setup = ioapic_abi_intr_setup, 528 .intr_teardown = ioapic_abi_intr_teardown, 529 530 .legacy_intr_config = ioapic_abi_legacy_intr_config, 531 .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid, 532 .legacy_intr_find = ioapic_abi_legacy_intr_find, 533 .legacy_intr_find_bygsi = ioapic_abi_legacy_intr_find_bygsi, 534 535 .msi_alloc = ioapic_abi_msi_alloc, 536 .msi_release = ioapic_abi_msi_release, 537 .msi_map = ioapic_abi_msi_map, 538 .msix_alloc = ioapic_abi_msix_alloc, 539 .msix_release = ioapic_abi_msix_release, 540 541 .finalize = ioapic_abi_finalize, 542 .cleanup = ioapic_abi_cleanup, 543 .setdefault = ioapic_abi_setdefault, 544 .stabilize = ioapic_abi_stabilize, 545 .initmap = ioapic_abi_initmap, 546 .rman_setup = ioapic_abi_rman_setup 547 }; 548 549 static int ioapic_abi_extint_irq = -1; 550 static int ioapic_abi_legacy_irq_max; 551 static int ioapic_abi_gsi_balance; 552 static int ioapic_abi_msi_start; /* NOTE: for testing only */ 553 554 struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS]; 555 556 static void 557 ioapic_abi_intr_enable(int irq) 558 { 559 const struct ioapic_irqmap *map; 560 561 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS, 562 ("ioapic enable, invalid irq %d", irq)); 563 564 map = &ioapic_irqmaps[mycpuid][irq]; 565 KASSERT(IOAPIC_IMT_ISHWI(map), 566 ("ioapic enable, not hwi irq %d, type %d, cpu%d", 567 irq, map->im_type, mycpuid)); 568 if (map->im_type != IOAPIC_IMT_LEGACY) 569 return; 570 571 IOAPIC_INTREN(irq); 572 } 573 574 static void 575 ioapic_abi_intr_disable(int irq) 576 { 577 const struct ioapic_irqmap *map; 578 579 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS, 580 ("ioapic disable, invalid irq %d", irq)); 581 582 map = &ioapic_irqmaps[mycpuid][irq]; 583 KASSERT(IOAPIC_IMT_ISHWI(map), 584 ("ioapic disable, not hwi irq %d, type %d, cpu%d", 585 irq, map->im_type, mycpuid)); 586 if (map->im_type != IOAPIC_IMT_LEGACY) 587 return; 588 589 IOAPIC_INTRDIS(irq); 590 } 591 592 static void 593 ioapic_abi_finalize(void) 594 { 595 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC); 596 KKASSERT(ioapic_enable); 597 598 /* 599 * If an IMCR is present, program bit 0 to disconnect the 8259 600 * from the BSP. 601 */ 602 if (imcr_present) { 603 outb(0x22, 0x70); /* select IMCR */ 604 outb(0x23, 0x01); /* disconnect 8259 */ 605 } 606 } 607 608 /* 609 * This routine is called after physical interrupts are enabled but before 610 * the critical section is released. We need to clean out any interrupts 611 * that had already been posted to the cpu. 612 */ 613 static void 614 ioapic_abi_cleanup(void) 615 { 616 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 617 } 618 619 /* Must never be called */ 620 static void 621 ioapic_abi_stabilize(void) 622 { 623 panic("ioapic_stabilize is called"); 624 } 625 626 static void 627 ioapic_abi_intr_setup(int intr, int flags) 628 { 629 const struct ioapic_irqmap *map; 630 int vector, select; 631 uint32_t value; 632 register_t ef; 633 634 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 635 ("ioapic setup, invalid irq %d", intr)); 636 637 map = &ioapic_irqmaps[mycpuid][intr]; 638 KASSERT(IOAPIC_IMT_ISHWI(map), 639 ("ioapic setup, not hwi irq %d, type %d, cpu%d", 640 intr, map->im_type, mycpuid)); 641 if (map->im_type != IOAPIC_IMT_LEGACY) 642 return; 643 644 KASSERT(ioapic_irqs[intr].io_addr != NULL, 645 ("ioapic setup, no GSI information, irq %d", intr)); 646 647 ef = read_rflags(); 648 cpu_disable_intr(); 649 650 vector = IDT_OFFSET + intr; 651 652 /* 653 * Now reprogram the vector in the IO APIC. In order to avoid 654 * losing an EOI for a level interrupt, which is vector based, 655 * make sure that the IO APIC is programmed for edge-triggering 656 * first, then reprogrammed with the new vector. This should 657 * clear the IRR bit. 658 */ 659 imen_lock(); 660 661 select = ioapic_irqs[intr].io_idx; 662 value = ioapic_read(ioapic_irqs[intr].io_addr, select); 663 value |= IOART_INTMSET; 664 665 ioapic_write(ioapic_irqs[intr].io_addr, select, 666 (value & ~APIC_TRIGMOD_MASK)); 667 ioapic_write(ioapic_irqs[intr].io_addr, select, 668 (value & ~IOART_INTVEC) | vector); 669 670 imen_unlock(); 671 672 IOAPIC_INTREN(intr); 673 674 write_rflags(ef); 675 } 676 677 static void 678 ioapic_abi_intr_teardown(int intr) 679 { 680 const struct ioapic_irqmap *map; 681 int vector, select; 682 uint32_t value; 683 register_t ef; 684 685 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 686 ("ioapic teardown, invalid irq %d", intr)); 687 688 map = &ioapic_irqmaps[mycpuid][intr]; 689 KASSERT(IOAPIC_IMT_ISHWI(map), 690 ("ioapic teardown, not hwi irq %d, type %d, cpu%d", 691 intr, map->im_type, mycpuid)); 692 if (map->im_type != IOAPIC_IMT_LEGACY) 693 return; 694 695 KASSERT(ioapic_irqs[intr].io_addr != NULL, 696 ("ioapic teardown, no GSI information, irq %d", intr)); 697 698 ef = read_rflags(); 699 cpu_disable_intr(); 700 701 /* 702 * Teardown an interrupt vector. The vector should already be 703 * installed in the cpu's IDT, but make sure. 704 */ 705 IOAPIC_INTRDIS(intr); 706 707 vector = IDT_OFFSET + intr; 708 709 /* 710 * In order to avoid losing an EOI for a level interrupt, which 711 * is vector based, make sure that the IO APIC is programmed for 712 * edge-triggering first, then reprogrammed with the new vector. 713 * This should clear the IRR bit. 714 */ 715 imen_lock(); 716 717 select = ioapic_irqs[intr].io_idx; 718 value = ioapic_read(ioapic_irqs[intr].io_addr, select); 719 720 ioapic_write(ioapic_irqs[intr].io_addr, select, 721 (value & ~APIC_TRIGMOD_MASK)); 722 ioapic_write(ioapic_irqs[intr].io_addr, select, 723 (value & ~IOART_INTVEC) | vector); 724 725 imen_unlock(); 726 727 write_rflags(ef); 728 } 729 730 static void 731 ioapic_abi_setdefault(void) 732 { 733 int intr; 734 735 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) { 736 if (intr == IOAPIC_HWI_SYSCALL) 737 continue; 738 setidt_global(IDT_OFFSET + intr, ioapic_intr[intr], 739 SDT_SYSIGT, SEL_KPL, 0); 740 } 741 } 742 743 static void 744 ioapic_abi_initmap(void) 745 { 746 int cpu; 747 748 kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance); 749 750 kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start); 751 ioapic_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ 752 753 /* 754 * NOTE: ncpus is not ready yet 755 */ 756 for (cpu = 0; cpu < MAXCPU; ++cpu) { 757 int i; 758 759 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) { 760 ioapic_irqmaps[cpu][i].im_gsi = -1; 761 ioapic_irqmaps[cpu][i].im_msi_base = -1; 762 } 763 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type = 764 IOAPIC_IMT_SYSCALL; 765 } 766 } 767 768 static int 769 ioapic_find_unused_irqmap(int gsi) 770 { 771 int cpuid, i; 772 773 cpuid = ioapic_abi_gsi_cpuid(-1, gsi); 774 775 for (i = ISA_IRQ_CNT; i < IOAPIC_HWI_VECTORS; ++i) { 776 if (i == acpi_sci_irqno()) 777 continue; 778 if (ioapic_irqmaps[cpuid][i].im_type == IOAPIC_IMT_UNUSED) 779 return i; 780 } 781 return -1; 782 } 783 784 void 785 ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig, 786 enum intr_polarity pola) 787 { 788 struct ioapic_irqinfo *info; 789 struct ioapic_irqmap *map; 790 void *ioaddr; 791 int pin, cpuid; 792 793 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 794 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW); 795 796 KKASSERT(irq >= 0); 797 if (irq >= IOAPIC_HWI_VECTORS) { 798 /* 799 * Some BIOSes seem to assume that all 256 IDT vectors 800 * could be used, while we limit the available IDT 801 * vectors to 192; find an unused IRQ for this GSI. 802 */ 803 irq = ioapic_find_unused_irqmap(gsi); 804 if (irq < 0) { 805 kprintf("failed to find unused irq for gsi %d, " 806 "overflow\n", gsi); 807 return; 808 } 809 } 810 KKASSERT(irq < IOAPIC_HWI_VECTORS); 811 812 cpuid = ioapic_abi_gsi_cpuid(irq, gsi); 813 map = &ioapic_irqmaps[cpuid][irq]; 814 815 if (map->im_type != IOAPIC_IMT_UNUSED) { 816 /* 817 * There are so many IOAPICs, that 1:1 mapping 818 * of GSI and IRQ hits SYSCALL entry. 819 */ 820 irq = ioapic_find_unused_irqmap(gsi); 821 if (irq < 0) { 822 kprintf("failed to find unused irq for gsi %d, " 823 "conflict\n", gsi); 824 return; 825 } 826 KKASSERT(irq < IOAPIC_HWI_VECTORS); 827 828 cpuid = ioapic_abi_gsi_cpuid(irq, gsi); 829 map = &ioapic_irqmaps[cpuid][irq]; 830 } 831 832 if (irq > ioapic_abi_legacy_irq_max) 833 ioapic_abi_legacy_irq_max = irq; 834 835 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED); 836 map->im_type = IOAPIC_IMT_LEGACY; 837 838 map->im_gsi = gsi; 839 map->im_trig = trig; 840 map->im_pola = pola; 841 842 if (bootverbose) { 843 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n", 844 irq, map->im_gsi, 845 intr_str_trigger(map->im_trig), 846 intr_str_polarity(map->im_pola)); 847 } 848 849 pin = ioapic_gsi_pin(map->im_gsi); 850 ioaddr = ioapic_gsi_ioaddr(map->im_gsi); 851 852 info = &ioapic_irqs[irq]; 853 854 imen_lock(); 855 856 info->io_addr = ioaddr; 857 info->io_idx = IOAPIC_REDTBL + (2 * pin); 858 info->io_flags = IOAPIC_IRQI_FLAG_MASKED; 859 if (map->im_trig == INTR_TRIGGER_LEVEL) 860 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL; 861 862 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq, 863 map->im_trig, map->im_pola, cpuid); 864 865 imen_unlock(); 866 } 867 868 void 869 ioapic_fixup_legacy_irqmaps(void) 870 { 871 int cpu; 872 873 for (cpu = 0; cpu < ncpus; ++cpu) { 874 int i; 875 876 for (i = 0; i < ISA_IRQ_CNT; ++i) { 877 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i]; 878 879 if (map->im_type == IOAPIC_IMT_UNUSED) { 880 map->im_type = IOAPIC_IMT_RESERVED; 881 if (bootverbose) { 882 kprintf("IOAPIC: " 883 "cpu%d irq %d reserved\n", cpu, i); 884 } 885 } 886 } 887 } 888 889 ioapic_abi_legacy_irq_max += 1; 890 if (bootverbose) { 891 kprintf("IOAPIC: legacy irq max %d\n", 892 ioapic_abi_legacy_irq_max); 893 } 894 } 895 896 static int 897 ioapic_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig, 898 enum intr_polarity pola) 899 { 900 int cpu; 901 902 #ifdef INVARIANTS 903 if (trig == INTR_TRIGGER_CONFORM) { 904 KKASSERT(pola == INTR_POLARITY_CONFORM); 905 } else { 906 KKASSERT(trig == INTR_TRIGGER_EDGE || 907 trig == INTR_TRIGGER_LEVEL); 908 KKASSERT(pola == INTR_POLARITY_HIGH || 909 pola == INTR_POLARITY_LOW); 910 } 911 #endif 912 913 for (cpu = 0; cpu < ncpus; ++cpu) { 914 int irq; 915 916 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) { 917 const struct ioapic_irqmap *map = 918 &ioapic_irqmaps[cpu][irq]; 919 920 if (map->im_gsi == gsi) { 921 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY); 922 923 if ((map->im_flags & IOAPIC_IMF_CONF) && 924 trig != INTR_TRIGGER_CONFORM && 925 pola != INTR_POLARITY_CONFORM) { 926 if (map->im_trig != trig || 927 map->im_pola != pola) 928 return -1; 929 } 930 return irq; 931 } 932 } 933 } 934 return -1; 935 } 936 937 static int 938 ioapic_abi_legacy_intr_find(int irq, enum intr_trigger trig, 939 enum intr_polarity pola) 940 { 941 int cpu; 942 943 #ifdef INVARIANTS 944 if (trig == INTR_TRIGGER_CONFORM) { 945 KKASSERT(pola == INTR_POLARITY_CONFORM); 946 } else { 947 KKASSERT(trig == INTR_TRIGGER_EDGE || 948 trig == INTR_TRIGGER_LEVEL); 949 KKASSERT(pola == INTR_POLARITY_HIGH || 950 pola == INTR_POLARITY_LOW); 951 } 952 #endif 953 954 if (irq < 0 || irq >= ioapic_abi_legacy_irq_max) 955 return -1; 956 957 for (cpu = 0; cpu < ncpus; ++cpu) { 958 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq]; 959 960 if (map->im_type == IOAPIC_IMT_LEGACY) { 961 if ((map->im_flags & IOAPIC_IMF_CONF) && 962 trig != INTR_TRIGGER_CONFORM && 963 pola != INTR_POLARITY_CONFORM) { 964 if (map->im_trig != trig || 965 map->im_pola != pola) 966 return -1; 967 } 968 return irq; 969 } 970 } 971 return -1; 972 } 973 974 static void 975 ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig, 976 enum intr_polarity pola) 977 { 978 struct ioapic_irqinfo *info; 979 struct ioapic_irqmap *map = NULL; 980 void *ioaddr; 981 int pin, cpuid; 982 983 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 984 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW); 985 986 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max); 987 for (cpuid = 0; cpuid < ncpus; ++cpuid) { 988 map = &ioapic_irqmaps[cpuid][irq]; 989 if (map->im_type == IOAPIC_IMT_LEGACY) 990 break; 991 } 992 KKASSERT(cpuid < ncpus); 993 994 #ifdef notyet 995 if (map->im_flags & IOAPIC_IMF_CONF) { 996 if (trig != map->im_trig) { 997 panic("ioapic_intr_config: trig %s -> %s", 998 intr_str_trigger(map->im_trig), 999 intr_str_trigger(trig)); 1000 } 1001 if (pola != map->im_pola) { 1002 panic("ioapic_intr_config: pola %s -> %s", 1003 intr_str_polarity(map->im_pola), 1004 intr_str_polarity(pola)); 1005 } 1006 return; 1007 } 1008 #endif 1009 map->im_flags |= IOAPIC_IMF_CONF; 1010 1011 if (trig == map->im_trig && pola == map->im_pola) 1012 return; 1013 1014 if (bootverbose) { 1015 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n", 1016 irq, map->im_gsi, 1017 intr_str_trigger(map->im_trig), 1018 intr_str_polarity(map->im_pola), 1019 intr_str_trigger(trig), 1020 intr_str_polarity(pola)); 1021 } 1022 map->im_trig = trig; 1023 map->im_pola = pola; 1024 1025 pin = ioapic_gsi_pin(map->im_gsi); 1026 ioaddr = ioapic_gsi_ioaddr(map->im_gsi); 1027 1028 info = &ioapic_irqs[irq]; 1029 1030 imen_lock(); 1031 1032 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL; 1033 if (map->im_trig == INTR_TRIGGER_LEVEL) 1034 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL; 1035 1036 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq, 1037 map->im_trig, map->im_pola, cpuid); 1038 1039 imen_unlock(); 1040 } 1041 1042 int 1043 ioapic_conf_legacy_extint(int irq) 1044 { 1045 struct ioapic_irqinfo *info; 1046 struct ioapic_irqmap *map; 1047 void *ioaddr; 1048 int pin, error, vec; 1049 1050 /* XXX only irq0 is allowed */ 1051 KKASSERT(irq == 0); 1052 1053 vec = IDT_OFFSET + irq; 1054 1055 if (ioapic_abi_extint_irq == irq) 1056 return 0; 1057 else if (ioapic_abi_extint_irq >= 0) 1058 return EEXIST; 1059 1060 error = icu_ioapic_extint(irq, vec); 1061 if (error) 1062 return error; 1063 1064 /* ExtINT is always targeted to cpu0 */ 1065 map = &ioapic_irqmaps[0][irq]; 1066 1067 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED || 1068 map->im_type == IOAPIC_IMT_LEGACY); 1069 if (map->im_type == IOAPIC_IMT_LEGACY) { 1070 if (map->im_flags & IOAPIC_IMF_CONF) 1071 return EEXIST; 1072 } 1073 ioapic_abi_extint_irq = irq; 1074 1075 map->im_type = IOAPIC_IMT_LEGACY; 1076 map->im_trig = INTR_TRIGGER_EDGE; 1077 map->im_pola = INTR_POLARITY_HIGH; 1078 map->im_flags = IOAPIC_IMF_CONF; 1079 1080 map->im_gsi = ioapic_extpin_gsi(); 1081 KKASSERT(map->im_gsi >= 0); 1082 1083 if (bootverbose) { 1084 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n", 1085 irq, map->im_gsi, 1086 intr_str_trigger(map->im_trig), 1087 intr_str_polarity(map->im_pola)); 1088 } 1089 1090 pin = ioapic_gsi_pin(map->im_gsi); 1091 ioaddr = ioapic_gsi_ioaddr(map->im_gsi); 1092 1093 info = &ioapic_irqs[irq]; 1094 1095 imen_lock(); 1096 1097 info->io_addr = ioaddr; 1098 info->io_idx = IOAPIC_REDTBL + (2 * pin); 1099 info->io_flags = IOAPIC_IRQI_FLAG_MASKED; 1100 1101 ioapic_extpin_setup(ioaddr, pin, vec); 1102 1103 imen_unlock(); 1104 1105 return 0; 1106 } 1107 1108 static int 1109 ioapic_abi_legacy_intr_cpuid(int irq) 1110 { 1111 const struct ioapic_irqmap *map = NULL; 1112 int cpuid; 1113 1114 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max); 1115 1116 for (cpuid = 0; cpuid < ncpus; ++cpuid) { 1117 map = &ioapic_irqmaps[cpuid][irq]; 1118 if (map->im_type == IOAPIC_IMT_LEGACY) 1119 return cpuid; 1120 } 1121 1122 /* XXX some drivers tries to peek at reserved IRQs */ 1123 for (cpuid = 0; cpuid < ncpus; ++cpuid) { 1124 map = &ioapic_irqmaps[cpuid][irq]; 1125 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED); 1126 } 1127 return 0; 1128 } 1129 1130 static int 1131 ioapic_abi_gsi_cpuid(int irq, int gsi) 1132 { 1133 char envpath[32]; 1134 int cpuid = -1; 1135 1136 KKASSERT(gsi >= 0); 1137 1138 if (irq == 0 || gsi == 0) { 1139 KKASSERT(irq >= 0); 1140 if (bootverbose) { 1141 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n", 1142 irq, gsi); 1143 } 1144 return 0; 1145 } 1146 1147 if (irq >= 0 && irq == acpi_sci_irqno()) { 1148 if (bootverbose) { 1149 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n", 1150 irq, gsi); 1151 } 1152 return 0; 1153 } 1154 1155 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi); 1156 kgetenv_int(envpath, &cpuid); 1157 1158 if (cpuid < 0) { 1159 if (!ioapic_abi_gsi_balance) { 1160 if (irq >= 0 && bootverbose) { 1161 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 " 1162 "(fixed)\n", irq, gsi); 1163 } 1164 return 0; 1165 } 1166 1167 cpuid = gsi % ncpus; 1168 if (irq >= 0 && bootverbose) { 1169 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n", 1170 irq, gsi, cpuid); 1171 } 1172 } else if (cpuid >= ncpus) { 1173 cpuid = ncpus - 1; 1174 if (irq >= 0 && bootverbose) { 1175 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n", 1176 irq, gsi, cpuid); 1177 } 1178 } else { 1179 if (irq >= 0 && bootverbose) { 1180 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n", 1181 irq, gsi, cpuid); 1182 } 1183 } 1184 return cpuid; 1185 } 1186 1187 static void 1188 ioapic_abi_rman_setup(struct rman *rm) 1189 { 1190 int start, end, i; 1191 1192 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, 1193 ("invalid rman cpuid %d", rm->rm_cpuid)); 1194 1195 start = end = -1; 1196 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) { 1197 const struct ioapic_irqmap *map = 1198 &ioapic_irqmaps[rm->rm_cpuid][i]; 1199 1200 if (start < 0) { 1201 if (IOAPIC_IMT_ISHWI(map)) 1202 start = end = i; 1203 } else { 1204 if (IOAPIC_IMT_ISHWI(map)) { 1205 end = i; 1206 } else { 1207 KKASSERT(end >= 0); 1208 if (bootverbose) { 1209 kprintf("IOAPIC: rman cpu%d %d - %d\n", 1210 rm->rm_cpuid, start, end); 1211 } 1212 if (rman_manage_region(rm, start, end)) { 1213 panic("rman_manage_region" 1214 "(cpu%d %d - %d)", rm->rm_cpuid, 1215 start, end); 1216 } 1217 start = end = -1; 1218 } 1219 } 1220 } 1221 if (start >= 0) { 1222 KKASSERT(end >= 0); 1223 if (bootverbose) { 1224 kprintf("IOAPIC: rman cpu%d %d - %d\n", 1225 rm->rm_cpuid, start, end); 1226 } 1227 if (rman_manage_region(rm, start, end)) { 1228 panic("rman_manage_region(cpu%d %d - %d)", 1229 rm->rm_cpuid, start, end); 1230 } 1231 } 1232 } 1233 1234 static int 1235 ioapic_abi_msi_alloc_intern(int type, const char *desc, 1236 int intrs[], int count, int cpuid) 1237 { 1238 int i, error; 1239 1240 KASSERT(cpuid >= 0 && cpuid < ncpus, 1241 ("invalid cpuid %d", cpuid)); 1242 1243 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 1244 KASSERT((count & (count - 1)) == 0, 1245 ("count %d is not power of 2", count)); 1246 1247 lwkt_gettoken(&ioapic_irqmap_tok); 1248 1249 /* 1250 * NOTE: 1251 * Since IDT_OFFSET is 32, which is the maximum valid 'count', 1252 * we do not need to find out the first properly aligned 1253 * interrupt vector. 1254 */ 1255 1256 error = EMSGSIZE; 1257 for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) { 1258 int j; 1259 1260 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED) 1261 continue; 1262 1263 for (j = 1; j < count; ++j) { 1264 if (ioapic_irqmaps[cpuid][i + j].im_type != 1265 IOAPIC_IMT_UNUSED) 1266 break; 1267 } 1268 if (j != count) 1269 continue; 1270 1271 for (j = 0; j < count; ++j) { 1272 struct ioapic_irqmap *map; 1273 int intr = i + j; 1274 1275 map = &ioapic_irqmaps[cpuid][intr]; 1276 KASSERT(map->im_msi_base < 0, 1277 ("intr %d, stale %s-base %d", 1278 intr, desc, map->im_msi_base)); 1279 1280 map->im_type = type; 1281 map->im_msi_base = i; 1282 1283 intrs[j] = intr; 1284 msi_setup(intr, cpuid); 1285 1286 if (bootverbose) { 1287 kprintf("alloc %s intr %d on cpu%d\n", 1288 desc, intr, cpuid); 1289 } 1290 } 1291 error = 0; 1292 break; 1293 } 1294 1295 lwkt_reltoken(&ioapic_irqmap_tok); 1296 1297 return error; 1298 } 1299 1300 static void 1301 ioapic_abi_msi_release_intern(int type, const char *desc, 1302 const int intrs[], int count, int cpuid) 1303 { 1304 int i, msi_base = -1, intr_next = -1, mask; 1305 1306 KASSERT(cpuid >= 0 && cpuid < ncpus, 1307 ("invalid cpuid %d", cpuid)); 1308 1309 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 1310 1311 mask = count - 1; 1312 KASSERT((count & mask) == 0, ("count %d is not power of 2", count)); 1313 1314 lwkt_gettoken(&ioapic_irqmap_tok); 1315 1316 for (i = 0; i < count; ++i) { 1317 struct ioapic_irqmap *map; 1318 int intr = intrs[i]; 1319 1320 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 1321 ("invalid intr %d", intr)); 1322 1323 map = &ioapic_irqmaps[cpuid][intr]; 1324 KASSERT(map->im_type == type, 1325 ("trying to release non-%s intr %d, type %d", desc, 1326 intr, map->im_type)); 1327 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 1328 ("intr %d, invalid %s-base %d", intr, desc, 1329 map->im_msi_base)); 1330 KASSERT((map->im_msi_base & mask) == 0, 1331 ("intr %d, %s-base %d is not properly aligned %d", 1332 intr, desc, map->im_msi_base, count)); 1333 1334 if (msi_base < 0) { 1335 msi_base = map->im_msi_base; 1336 } else { 1337 KASSERT(map->im_msi_base == msi_base, 1338 ("intr %d, inconsistent %s-base, " 1339 "was %d, now %d", 1340 intr, desc, msi_base, map->im_msi_base)); 1341 } 1342 1343 if (intr_next < intr) 1344 intr_next = intr; 1345 1346 map->im_type = IOAPIC_IMT_UNUSED; 1347 map->im_msi_base = -1; 1348 1349 if (bootverbose) { 1350 kprintf("release %s intr %d on cpu%d\n", 1351 desc, intr, cpuid); 1352 } 1353 } 1354 1355 KKASSERT(intr_next > 0); 1356 KKASSERT(msi_base >= 0); 1357 1358 ++intr_next; 1359 if (intr_next < IOAPIC_HWI_VECTORS) { 1360 const struct ioapic_irqmap *map = 1361 &ioapic_irqmaps[cpuid][intr_next]; 1362 1363 if (map->im_type == type) { 1364 KASSERT(map->im_msi_base != msi_base, 1365 ("more than %d %s was allocated", count, desc)); 1366 } 1367 } 1368 1369 lwkt_reltoken(&ioapic_irqmap_tok); 1370 } 1371 1372 static int 1373 ioapic_abi_msi_alloc(int intrs[], int count, int cpuid) 1374 { 1375 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSI, "MSI", 1376 intrs, count, cpuid); 1377 } 1378 1379 static void 1380 ioapic_abi_msi_release(const int intrs[], int count, int cpuid) 1381 { 1382 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSI, "MSI", 1383 intrs, count, cpuid); 1384 } 1385 1386 static int 1387 ioapic_abi_msix_alloc(int *intr, int cpuid) 1388 { 1389 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSIX, "MSI-X", 1390 intr, 1, cpuid); 1391 } 1392 1393 static void 1394 ioapic_abi_msix_release(int intr, int cpuid) 1395 { 1396 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSIX, "MSI-X", 1397 &intr, 1, cpuid); 1398 } 1399 1400 static void 1401 ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) 1402 { 1403 const struct ioapic_irqmap *map; 1404 1405 KASSERT(cpuid >= 0 && cpuid < ncpus, 1406 ("invalid cpuid %d", cpuid)); 1407 1408 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, 1409 ("invalid intr %d", intr)); 1410 1411 lwkt_gettoken(&ioapic_irqmap_tok); 1412 1413 map = &ioapic_irqmaps[cpuid][intr]; 1414 KASSERT(map->im_type == IOAPIC_IMT_MSI || 1415 map->im_type == IOAPIC_IMT_MSIX, 1416 ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type)); 1417 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 1418 ("intr %d, invalid %s-base %d", intr, 1419 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X", 1420 map->im_msi_base)); 1421 1422 msi_map(map->im_msi_base, addr, data, cpuid); 1423 1424 if (bootverbose) { 1425 kprintf("map %s intr %d on cpu%d\n", 1426 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X", 1427 intr, cpuid); 1428 } 1429 1430 lwkt_reltoken(&ioapic_irqmap_tok); 1431 } 1432