1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/kernel.h> 31 #include <sys/ktr.h> 32 #include <sys/bus.h> 33 #include <sys/machintr.h> 34 #include <sys/sysctl.h> 35 #include <machine/globaldata.h> 36 #include <machine/clock.h> 37 #include <machine/limits.h> 38 #include <machine/smp.h> 39 #include <machine/md_var.h> 40 #include <machine/pmap.h> 41 #include <machine/specialreg.h> 42 #include <machine_base/apic/lapic.h> 43 #include <machine_base/apic/ioapic.h> 44 #include <machine_base/apic/ioapic_abi.h> 45 #include <machine_base/apic/apicvar.h> 46 #include <machine_base/icu/icu_var.h> 47 #include <machine/segments.h> 48 #include <sys/spinlock2.h> 49 50 #include <machine/cputypes.h> 51 #include <machine/intr_machdep.h> 52 53 #if !defined(KTR_LAPIC) 54 #define KTR_LAPIC KTR_ALL 55 #endif 56 KTR_INFO_MASTER(lapic); 57 KTR_INFO(KTR_LAPIC, lapic, mem_eoi, 0, "mem_eoi"); 58 KTR_INFO(KTR_LAPIC, lapic, msr_eoi, 0, "msr_eoi"); 59 #define log_lapic(name) KTR_LOG(lapic_ ## name) 60 61 extern int naps; 62 63 volatile lapic_t *lapic_mem; 64 65 static void lapic_timer_calibrate(void); 66 static void lapic_timer_set_divisor(int); 67 static void lapic_timer_fixup_handler(void *); 68 static void lapic_timer_restart_handler(void *); 69 70 static int lapic_timer_c1e_test = -1; /* auto-detect */ 71 TUNABLE_INT("hw.lapic_timer_c1e_test", &lapic_timer_c1e_test); 72 73 static int lapic_timer_enable = 1; 74 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable); 75 76 static int lapic_timer_tscdeadline = 1; 77 TUNABLE_INT("hw.lapic_timer_tscdeadline", &lapic_timer_tscdeadline); 78 79 static int lapic_calibrate_test = 0; 80 TUNABLE_INT("hw.lapic_calibrate_test", &lapic_calibrate_test); 81 82 static int lapic_calibrate_fast = 1; 83 TUNABLE_INT("hw.lapic_calibrate_fast", &lapic_calibrate_fast); 84 85 static void lapic_timer_tscdlt_reload(struct cputimer_intr *, sysclock_t); 86 static void lapic_mem_timer_intr_reload(struct cputimer_intr *, sysclock_t); 87 static void lapic_msr_timer_intr_reload(struct cputimer_intr *, sysclock_t); 88 static void lapic_timer_intr_enable(struct cputimer_intr *); 89 static void lapic_timer_intr_restart(struct cputimer_intr *); 90 static void lapic_timer_intr_pmfixup(struct cputimer_intr *); 91 92 static struct cputimer_intr lapic_cputimer_intr = { 93 .freq = 0, 94 .reload = lapic_mem_timer_intr_reload, 95 .enable = lapic_timer_intr_enable, 96 .config = cputimer_intr_default_config, 97 .restart = lapic_timer_intr_restart, 98 .pmfixup = lapic_timer_intr_pmfixup, 99 .initclock = cputimer_intr_default_initclock, 100 .pcpuhand = NULL, 101 .next = SLIST_ENTRY_INITIALIZER, 102 .name = "lapic", 103 .type = CPUTIMER_INTR_LAPIC, 104 .prio = CPUTIMER_INTR_PRIO_LAPIC, 105 .caps = CPUTIMER_INTR_CAP_NONE, 106 .priv = NULL 107 }; 108 109 static int lapic_timer_divisor_idx = -1; 110 static const uint32_t lapic_timer_divisors[] = { 111 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 112 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1 113 }; 114 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors)) 115 116 static int lapic_use_tscdeadline = 0; 117 /* The raw TSC frequency might not fit into a sysclock_t value. */ 118 static int lapic_timer_tscfreq_shift; 119 120 /* 121 * APIC ID <-> CPU ID mapping structures. 122 */ 123 int cpu_id_to_apic_id[NAPICID]; 124 int apic_id_to_cpu_id[NAPICID]; 125 int lapic_enable = 1; 126 int lapic_usable = 0; 127 int x2apic_enable = 1; 128 129 SYSCTL_INT(_hw, OID_AUTO, x2apic_enable, CTLFLAG_RD, &x2apic_enable, 0, ""); 130 131 /* Separate cachelines for each cpu's info. */ 132 struct deadlines { 133 uint64_t timestamp; 134 uint64_t downcount_time; 135 uint64_t padding[6]; 136 }; 137 struct deadlines *tsc_deadlines = NULL; 138 139 static void lapic_mem_eoi(void); 140 static int lapic_mem_ipi(int dest_type, int vector, int delivery_mode); 141 static void lapic_mem_single_ipi(int cpu, int vector, int delivery_mode); 142 143 static void lapic_msr_eoi(void); 144 static int lapic_msr_ipi(int dest_type, int vector, int delivery_mode); 145 static void lapic_msr_single_ipi(int cpu, int vector, int delivery_mode); 146 147 void (*lapic_eoi)(void); 148 int (*apic_ipi)(int dest_type, int vector, int delivery_mode); 149 void (*single_apic_ipi)(int cpu, int vector, int delivery_mode); 150 151 static __inline void 152 lapic_mem_icr_set(uint32_t apic_id, uint32_t icr_lo_val) 153 { 154 uint32_t icr_lo, icr_hi; 155 156 icr_hi = (LAPIC_MEM_READ(icr_hi) & ~APIC_ID_MASK) | 157 (apic_id << APIC_ID_SHIFT); 158 icr_lo = (LAPIC_MEM_READ(icr_lo) & APIC_ICRLO_RESV_MASK) | icr_lo_val; 159 160 LAPIC_MEM_WRITE(icr_hi, icr_hi); 161 LAPIC_MEM_WRITE(icr_lo, icr_lo); 162 } 163 164 static __inline void 165 lapic_msr_icr_set(uint32_t apic_id, uint32_t icr_lo_val) 166 { 167 LAPIC_MSR_WRITE(MSR_X2APIC_ICR, 168 ((uint64_t)apic_id << 32) | ((uint64_t)icr_lo_val)); 169 } 170 171 /* 172 * Enable LAPIC, configure interrupts. 173 */ 174 void 175 lapic_init(boolean_t bsp) 176 { 177 uint32_t timer; 178 u_int temp; 179 180 if (bsp) { 181 /* Decide whether we want to use TSC Deadline mode. */ 182 if (lapic_timer_tscdeadline != 0 && 183 (cpu_feature2 & CPUID2_TSCDLT) && 184 tsc_invariant && tsc_frequency != 0) { 185 lapic_use_tscdeadline = 1; 186 tsc_deadlines = kmalloc_cachealign( 187 sizeof(struct deadlines) * (naps + 1), 188 M_DEVBUF, M_WAITOK | M_ZERO); 189 } 190 } 191 192 /* 193 * Install vectors 194 * 195 * Since IDT is shared between BSP and APs, these vectors 196 * only need to be installed once; we do it on BSP. 197 */ 198 if (bsp) { 199 if (cpu_vendor_id == CPU_VENDOR_AMD && 200 CPUID_TO_FAMILY(cpu_id) >= 0x0f && 201 CPUID_TO_FAMILY(cpu_id) < 0x17) { /* XXX */ 202 uint32_t tcr; 203 204 /* 205 * Set the LINTEN bit in the HyperTransport 206 * Transaction Control Register. 207 * 208 * This will cause EXTINT and NMI interrupts 209 * routed over the hypertransport bus to be 210 * fed into the LAPIC LINT0/LINT1. If the bit 211 * isn't set, the interrupts will go to the 212 * general cpu INTR/NMI pins. On a dual-core 213 * cpu the interrupt winds up going to BOTH cpus. 214 * The first cpu that does the interrupt ack 215 * cycle will get the correct interrupt. The 216 * second cpu that does it will get a spurious 217 * interrupt vector (typically IRQ 7). 218 */ 219 outl(0x0cf8, 220 (1 << 31) | /* enable */ 221 (0 << 16) | /* bus */ 222 (0x18 << 11) | /* dev (cpu + 0x18) */ 223 (0 << 8) | /* func */ 224 0x68 /* reg */ 225 ); 226 tcr = inl(0xcfc); 227 if ((tcr & 0x00010000) == 0) { 228 kprintf("LAPIC: AMD LINTEN on\n"); 229 outl(0xcfc, tcr|0x00010000); 230 } 231 outl(0x0cf8, 0); 232 } 233 234 /* Install a 'Spurious INTerrupt' vector */ 235 setidt_global(XSPURIOUSINT_OFFSET, Xspuriousint, 236 SDT_SYSIGT, SEL_KPL, 0); 237 238 /* Install a timer vector */ 239 setidt_global(XTIMER_OFFSET, Xtimer, 240 SDT_SYSIGT, SEL_KPL, 0); 241 242 /* Install an inter-CPU IPI for TLB invalidation */ 243 setidt_global(XINVLTLB_OFFSET, Xinvltlb, 244 SDT_SYSIGT, SEL_KPL, 0); 245 246 /* Install an inter-CPU IPI for IPIQ messaging */ 247 setidt_global(XIPIQ_OFFSET, Xipiq, 248 SDT_SYSIGT, SEL_KPL, 0); 249 250 /* Install an inter-CPU IPI for CPU stop/restart */ 251 setidt_global(XCPUSTOP_OFFSET, Xcpustop, 252 SDT_SYSIGT, SEL_KPL, 0); 253 254 /* Install an inter-CPU IPI for TLB invalidation */ 255 setidt_global(XSNIFF_OFFSET, Xsniff, 256 SDT_SYSIGT, SEL_KPL, 0); 257 } 258 259 /* 260 * Setup LINT0 as ExtINT on the BSP. This is theoretically an 261 * aggregate interrupt input from the 8259. The INTA cycle 262 * will be routed to the external controller (the 8259) which 263 * is expected to supply the vector. 264 * 265 * Must be setup edge triggered, active high. 266 * 267 * Disable LINT0 on BSP, if I/O APIC is enabled. 268 * 269 * Disable LINT0 on the APs. It doesn't matter what delivery 270 * mode we use because we leave it masked. 271 */ 272 temp = LAPIC_READ(lvt_lint0); 273 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 274 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); 275 if (bsp) { 276 temp |= APIC_LVT_DM_EXTINT; 277 if (ioapic_enable) 278 temp |= APIC_LVT_MASKED; 279 } else { 280 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED; 281 } 282 LAPIC_WRITE(lvt_lint0, temp); 283 284 /* 285 * Setup LINT1 as NMI. 286 * 287 * Must be setup edge trigger, active high. 288 * 289 * Enable LINT1 on BSP, if I/O APIC is enabled. 290 * 291 * Disable LINT1 on the APs. 292 */ 293 temp = LAPIC_READ(lvt_lint1); 294 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 295 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); 296 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI; 297 if (bsp && ioapic_enable) 298 temp &= ~APIC_LVT_MASKED; 299 LAPIC_WRITE(lvt_lint1, temp); 300 301 /* 302 * Mask the LAPIC error interrupt, LAPIC performance counter 303 * interrupt. 304 */ 305 LAPIC_WRITE(lvt_error, LAPIC_READ(lvt_error) | APIC_LVT_MASKED); 306 LAPIC_WRITE(lvt_pcint, LAPIC_READ(lvt_pcint) | APIC_LVT_MASKED); 307 308 /* 309 * Set LAPIC timer vector and mask the LAPIC timer interrupt. 310 */ 311 timer = LAPIC_READ(lvt_timer); 312 timer &= ~APIC_LVTT_VECTOR; 313 timer |= XTIMER_OFFSET; 314 timer |= APIC_LVTT_MASKED; 315 LAPIC_WRITE(lvt_timer, timer); 316 317 /* 318 * Set the Task Priority Register as needed. At the moment allow 319 * interrupts on all cpus (the APs will remain CLId until they are 320 * ready to deal). 321 */ 322 temp = LAPIC_READ(tpr); 323 temp &= ~APIC_TPR_PRIO; /* clear priority field */ 324 LAPIC_WRITE(tpr, temp); 325 326 /* 327 * AMD specific setup 328 */ 329 if (cpu_vendor_id == CPU_VENDOR_AMD && lapic_mem != NULL && 330 (LAPIC_MEM_READ(version) & APIC_VER_AMD_EXT_SPACE)) { 331 uint32_t ext_feat; 332 uint32_t count; 333 uint32_t max_count; 334 uint32_t lvt; 335 uint32_t i; 336 337 ext_feat = LAPIC_MEM_READ(ext_feat); 338 count = (ext_feat & APIC_EXTFEAT_MASK) >> APIC_EXTFEAT_SHIFT; 339 max_count = sizeof(lapic_mem->ext_lvt) / 340 sizeof(lapic_mem->ext_lvt[0]); 341 if (count > max_count) 342 count = max_count; 343 for (i = 0; i < count; ++i) { 344 lvt = LAPIC_MEM_READ(ext_lvt[i].lvt); 345 346 lvt &= ~(APIC_LVT_POLARITY_MASK | APIC_LVT_TRIG_MASK | 347 APIC_LVT_DM_MASK | APIC_LVT_MASKED); 348 lvt |= APIC_LVT_MASKED | APIC_LVT_DM_FIXED; 349 350 switch(i) { 351 case APIC_EXTLVT_IBS: 352 break; 353 case APIC_EXTLVT_MCA: 354 break; 355 case APIC_EXTLVT_DEI: 356 break; 357 case APIC_EXTLVT_SBI: 358 break; 359 default: 360 break; 361 } 362 if (bsp) { 363 kprintf(" LAPIC AMD elvt%d: 0x%08x", 364 i, LAPIC_MEM_READ(ext_lvt[i].lvt)); 365 if (LAPIC_MEM_READ(ext_lvt[i].lvt) != lvt) 366 kprintf(" -> 0x%08x", lvt); 367 kprintf("\n"); 368 } 369 LAPIC_MEM_WRITE(ext_lvt[i].lvt, lvt); 370 } 371 } 372 373 /* 374 * Enable the LAPIC 375 */ 376 temp = LAPIC_READ(svr); 377 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */ 378 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */ 379 380 if (LAPIC_READ(version) & APIC_VER_EOI_SUPP) { 381 if (temp & APIC_SVR_EOI_SUPP) { 382 temp &= ~APIC_SVR_EOI_SUPP; 383 if (bsp) 384 kprintf(" LAPIC disabling EOI supp\n"); 385 } 386 } 387 388 /* 389 * Set the spurious interrupt vector. The low 4 bits of the vector 390 * must be 1111. 391 */ 392 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F) 393 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET); 394 temp &= ~APIC_SVR_VECTOR; 395 temp |= XSPURIOUSINT_OFFSET; 396 397 LAPIC_WRITE(svr, temp); 398 399 /* 400 * Pump out a few EOIs to clean out interrupts that got through 401 * before we were able to set the TPR. 402 */ 403 LAPIC_WRITE(eoi, 0); 404 LAPIC_WRITE(eoi, 0); 405 LAPIC_WRITE(eoi, 0); 406 407 if (bsp) { 408 lapic_timer_calibrate(); 409 if (lapic_timer_enable) { 410 if (cpu_thermal_feature & CPUID_THERMAL_ARAT) { 411 /* 412 * Local APIC timer will not stop 413 * in deep C-state. 414 */ 415 lapic_cputimer_intr.caps |= 416 CPUTIMER_INTR_CAP_PS; 417 } 418 if (lapic_use_tscdeadline) { 419 lapic_cputimer_intr.reload = 420 lapic_timer_tscdlt_reload; 421 } 422 cputimer_intr_register(&lapic_cputimer_intr); 423 cputimer_intr_select(&lapic_cputimer_intr, 0); 424 } 425 } else if (!lapic_use_tscdeadline) { 426 lapic_timer_set_divisor(lapic_timer_divisor_idx); 427 } 428 429 if (bootverbose) 430 apic_dump("apic_initialize()"); 431 } 432 433 static void 434 lapic_timer_set_divisor(int divisor_idx) 435 { 436 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS); 437 LAPIC_WRITE(dcr_timer, lapic_timer_divisors[divisor_idx]); 438 } 439 440 static void 441 lapic_timer_oneshot(u_int count) 442 { 443 uint32_t value; 444 445 value = LAPIC_READ(lvt_timer); 446 value &= ~(APIC_LVTT_PERIODIC | APIC_LVTT_TSCDLT); 447 LAPIC_WRITE(lvt_timer, value); 448 LAPIC_WRITE(icr_timer, count); 449 } 450 451 static void 452 lapic_timer_oneshot_quick(u_int count) 453 { 454 LAPIC_WRITE(icr_timer, count); 455 } 456 457 static void 458 lapic_timer_tscdeadline_quick(uint64_t diff) 459 { 460 uint64_t val = rdtsc() + diff; 461 462 wrmsr(MSR_TSC_DEADLINE, val); 463 tsc_deadlines[mycpuid].timestamp = val; 464 } 465 466 static uint64_t 467 lapic_scale_to_tsc(unsigned value, unsigned scale) 468 { 469 uint64_t val; 470 471 val = value; 472 val *= tsc_frequency; 473 val += (scale - 1); 474 val /= scale; 475 return val; 476 } 477 478 #define MAX_MEASURE_RETRIES 100 479 480 static u_int64_t 481 do_tsc_calibration(u_int us, u_int64_t apic_delay_tsc) 482 { 483 u_int64_t old_tsc1, old_tsc2, new_tsc1, new_tsc2; 484 u_int64_t diff, count; 485 u_int64_t a; 486 u_int32_t start, end; 487 int retries1 = 0, retries2 = 0; 488 489 retry1: 490 lapic_timer_oneshot_quick(APIC_TIMER_MAX_COUNT); 491 old_tsc1 = rdtsc_ordered(); 492 start = LAPIC_READ(ccr_timer); 493 old_tsc2 = rdtsc_ordered(); 494 if (apic_delay_tsc > 0 && retries1 < MAX_MEASURE_RETRIES && 495 old_tsc2 - old_tsc1 > 2 * apic_delay_tsc) { 496 retries1++; 497 goto retry1; 498 } 499 DELAY(us); 500 retry2: 501 new_tsc1 = rdtsc_ordered(); 502 end = LAPIC_READ(ccr_timer); 503 new_tsc2 = rdtsc_ordered(); 504 if (apic_delay_tsc > 0 && retries2 < MAX_MEASURE_RETRIES && 505 new_tsc2 - new_tsc1 > 2 * apic_delay_tsc) { 506 retries2++; 507 goto retry2; 508 } 509 if (end == 0) 510 return 0; 511 512 count = start - end; 513 514 /* Make sure the lapic can count for up to 2s */ 515 a = (unsigned)APIC_TIMER_MAX_COUNT; 516 if (us < 2000000 && (u_int64_t)count * 2000000 >= a * us) 517 return 0; 518 519 if (lapic_calibrate_test > 0 && (retries1 > 0 || retries2 > 0)) { 520 kprintf("%s: retries1=%d retries2=%d\n", 521 __func__, retries1, retries2); 522 } 523 524 diff = (new_tsc1 - old_tsc1) + (new_tsc2 - old_tsc2); 525 /* XXX First estimate if the total TSC diff value makes sense */ 526 /* This will almost overflow, but only almost :) */ 527 count = (2 * count * tsc_frequency) / diff; 528 529 return count; 530 } 531 532 static uint64_t 533 do_cputimer_calibration(u_int us) 534 { 535 sysclock_t value; 536 sysclock_t start, end, beginning, finish; 537 538 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 539 beginning = LAPIC_READ(ccr_timer); 540 start = sys_cputimer->count(); 541 DELAY(us); 542 end = sys_cputimer->count(); 543 finish = LAPIC_READ(ccr_timer); 544 if (finish == 0) 545 return 0; 546 /* value is the LAPIC timer difference. */ 547 value = beginning - finish; 548 /* end is the sys_cputimer difference. */ 549 end -= start; 550 if (end == 0) 551 return 0; 552 value = ((uint64_t)value * sys_cputimer->freq) / end; 553 return value; 554 } 555 556 static void 557 lapic_timer_calibrate(void) 558 { 559 sysclock_t value; 560 u_int64_t apic_delay_tsc = 0; 561 int use_tsc_calibration = 0; 562 563 /* No need to calibrate lapic_timer, if we will use TSC Deadline mode */ 564 if (lapic_use_tscdeadline) { 565 lapic_timer_tscfreq_shift = 0; 566 while ((tsc_frequency >> lapic_timer_tscfreq_shift) > INT_MAX) 567 lapic_timer_tscfreq_shift++; 568 lapic_cputimer_intr.freq = 569 tsc_frequency >> lapic_timer_tscfreq_shift; 570 kprintf( 571 "lapic: TSC Deadline Mode: shift %d, frequency %u Hz\n", 572 lapic_timer_tscfreq_shift, lapic_cputimer_intr.freq); 573 return; 574 } 575 576 /* 577 * On real hardware, tsc_invariant == 0 wouldn't be an issue, but in 578 * a virtual machine the frequency may get changed by the host. 579 */ 580 if (tsc_frequency != 0 && tsc_invariant && lapic_calibrate_fast) 581 use_tsc_calibration = 1; 582 583 if (use_tsc_calibration) { 584 u_int64_t min_apic_tsc = 0, max_apic_tsc = 0; 585 u_int64_t old_tsc, new_tsc; 586 sysclock_t val; 587 int i; 588 589 /* warm up */ 590 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 591 for (i = 0; i < 10; i++) 592 val = LAPIC_READ(ccr_timer); 593 594 for (i = 0; i < 100; i++) { 595 old_tsc = rdtsc_ordered(); 596 val = LAPIC_READ(ccr_timer); 597 new_tsc = rdtsc_ordered(); 598 new_tsc -= old_tsc; 599 apic_delay_tsc += new_tsc; 600 if (min_apic_tsc == 0 || 601 min_apic_tsc > new_tsc) { 602 min_apic_tsc = new_tsc; 603 } 604 if (max_apic_tsc < new_tsc) 605 max_apic_tsc = new_tsc; 606 } 607 apic_delay_tsc /= 100; 608 kprintf( 609 "LAPIC latency (in TSC ticks): %lu min: %lu max: %lu\n", 610 apic_delay_tsc, min_apic_tsc, max_apic_tsc); 611 apic_delay_tsc = min_apic_tsc; 612 } 613 614 if (!use_tsc_calibration) { 615 int i; 616 617 /* 618 * Do some exercising of the lapic timer access. This improves 619 * precision of the subsequent calibration run in at least some 620 * virtualization cases. 621 */ 622 lapic_timer_set_divisor(0); 623 for (i = 0; i < 10; i++) 624 (void)do_cputimer_calibration(100); 625 } 626 /* Try to calibrate the local APIC timer. */ 627 for (lapic_timer_divisor_idx = 0; 628 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS; 629 lapic_timer_divisor_idx++) { 630 lapic_timer_set_divisor(lapic_timer_divisor_idx); 631 if (use_tsc_calibration) { 632 value = do_tsc_calibration(200*1000, apic_delay_tsc); 633 } else { 634 value = do_cputimer_calibration(2*1000*1000); 635 } 636 if (value != 0) 637 break; 638 } 639 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS) 640 panic("lapic: no proper timer divisor?!"); 641 lapic_cputimer_intr.freq = value; 642 643 kprintf("lapic: divisor index %d, frequency %u Hz\n", 644 lapic_timer_divisor_idx, lapic_cputimer_intr.freq); 645 646 if (lapic_calibrate_test > 0) { 647 uint64_t freq; 648 int i; 649 650 for (i = 1; i <= 20; i++) { 651 if (use_tsc_calibration) { 652 freq = do_tsc_calibration(i*100*1000, 653 apic_delay_tsc); 654 } else { 655 freq = do_cputimer_calibration(i*100*1000); 656 } 657 if (freq != 0) 658 kprintf("%ums: %lu\n", i * 100, freq); 659 } 660 } 661 } 662 663 static void 664 lapic_timer_tscdlt_reload(struct cputimer_intr *cti, sysclock_t reload) 665 { 666 struct globaldata *gd = mycpu; 667 uint64_t diff, now, val; 668 669 if (reload > 1000*1000*1000) 670 reload = 1000*1000*1000; 671 diff = (uint64_t)reload * tsc_frequency / sys_cputimer->freq; 672 if (diff < 4) 673 diff = 4; 674 if (cpu_vendor_id == CPU_VENDOR_INTEL) 675 cpu_lfence(); 676 else 677 cpu_mfence(); 678 now = rdtsc(); 679 val = now + diff; 680 if (gd->gd_timer_running) { 681 uint64_t deadline = tsc_deadlines[mycpuid].timestamp; 682 if (deadline == 0 || now > deadline || val < deadline) { 683 wrmsr(MSR_TSC_DEADLINE, val); 684 tsc_deadlines[mycpuid].timestamp = val; 685 } 686 } else { 687 gd->gd_timer_running = 1; 688 wrmsr(MSR_TSC_DEADLINE, val); 689 tsc_deadlines[mycpuid].timestamp = val; 690 } 691 } 692 693 static void 694 lapic_mem_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 695 { 696 struct globaldata *gd = mycpu; 697 698 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 699 if (reload < 2) 700 reload = 2; 701 702 if (gd->gd_timer_running) { 703 if (reload < LAPIC_MEM_READ(ccr_timer)) 704 LAPIC_MEM_WRITE(icr_timer, reload); 705 } else { 706 gd->gd_timer_running = 1; 707 LAPIC_MEM_WRITE(icr_timer, reload); 708 } 709 } 710 711 static void 712 lapic_msr_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 713 { 714 struct globaldata *gd = mycpu; 715 716 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 717 if (reload < 2) 718 reload = 2; 719 720 if (gd->gd_timer_running) { 721 if (reload < LAPIC_MSR_READ(MSR_X2APIC_CCR_TIMER)) 722 LAPIC_MSR_WRITE(MSR_X2APIC_ICR_TIMER, reload); 723 } else { 724 gd->gd_timer_running = 1; 725 LAPIC_MSR_WRITE(MSR_X2APIC_ICR_TIMER, reload); 726 } 727 } 728 729 static void 730 lapic_timer_intr_enable(struct cputimer_intr *cti __unused) 731 { 732 uint32_t timer; 733 734 timer = LAPIC_READ(lvt_timer); 735 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC | APIC_LVTT_TSCDLT); 736 if (lapic_use_tscdeadline) 737 timer |= APIC_LVTT_TSCDLT; 738 LAPIC_WRITE(lvt_timer, timer); 739 if (lapic_use_tscdeadline) 740 cpu_mfence(); 741 742 lapic_timer_fixup_handler(NULL); 743 } 744 745 static void 746 lapic_timer_fixup_handler(void *arg) 747 { 748 int *started = arg; 749 750 if (started != NULL) 751 *started = 0; 752 753 if (cpu_vendor_id == CPU_VENDOR_AMD) { 754 int c1e_test = lapic_timer_c1e_test; 755 756 if (c1e_test < 0) { 757 if (vmm_guest == VMM_GUEST_NONE) { 758 c1e_test = 1; 759 } else { 760 /* 761 * Don't do this C1E testing and adjustment 762 * on virtual machines, the best case for 763 * accessing this MSR is a NOOP; the worst 764 * cases could be pretty nasty, e.g. crash. 765 */ 766 c1e_test = 0; 767 } 768 } 769 770 /* 771 * Detect the presence of C1E capability mostly on latest 772 * dual-cores (or future) k8 family. This feature renders 773 * the local APIC timer dead, so we disable it by reading 774 * the Interrupt Pending Message register and clearing both 775 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 776 * 777 * Reference: 778 * "BIOS and Kernel Developer's Guide for AMD NPT 779 * Family 0Fh Processors" 780 * #32559 revision 3.00 781 */ 782 if ((cpu_id & 0x00000f00) == 0x00000f00 && 783 (cpu_id & 0x0fff0000) >= 0x00040000 && 784 c1e_test) { 785 uint64_t msr; 786 787 msr = rdmsr(0xc0010055); 788 if (msr & 0x18000000) { 789 struct globaldata *gd = mycpu; 790 791 kprintf("cpu%d: AMD C1E detected\n", 792 gd->gd_cpuid); 793 wrmsr(0xc0010055, msr & ~0x18000000ULL); 794 795 /* 796 * We are kinda stalled; 797 * kick start again. 798 */ 799 gd->gd_timer_running = 1; 800 if (lapic_use_tscdeadline) { 801 /* Maybe reached in Virtual Machines? */ 802 lapic_timer_tscdeadline_quick(5000); 803 } else { 804 lapic_timer_oneshot_quick(2); 805 } 806 807 if (started != NULL) 808 *started = 1; 809 } 810 } 811 } 812 } 813 814 static void 815 lapic_timer_restart_handler(void *dummy __unused) 816 { 817 int started; 818 819 lapic_timer_fixup_handler(&started); 820 if (!started) { 821 struct globaldata *gd = mycpu; 822 823 gd->gd_timer_running = 1; 824 if (lapic_use_tscdeadline) { 825 /* Maybe reached in Virtual Machines? */ 826 lapic_timer_tscdeadline_quick(5000); 827 } else { 828 lapic_timer_oneshot_quick(2); 829 } 830 } 831 } 832 833 /* 834 * This function is called only by ACPICA code currently: 835 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI 836 * module controls PM. So once ACPICA is attached, we try 837 * to apply the fixup to prevent LAPIC timer from hanging. 838 */ 839 static void 840 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused) 841 { 842 lwkt_send_ipiq_mask(smp_active_mask, 843 lapic_timer_fixup_handler, NULL); 844 } 845 846 static void 847 lapic_timer_intr_restart(struct cputimer_intr *cti __unused) 848 { 849 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL); 850 } 851 852 853 /* 854 * dump contents of local APIC registers 855 */ 856 void 857 apic_dump(char* str) 858 { 859 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str); 860 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 861 LAPIC_READ(lvt_lint0), LAPIC_READ(lvt_lint1), LAPIC_READ(tpr), 862 LAPIC_READ(svr)); 863 } 864 865 /* 866 * Inter Processor Interrupt functions. 867 */ 868 869 static __inline void 870 lapic_mem_icr_unpend(const char *func) 871 { 872 if (LAPIC_MEM_READ(icr_lo) & APIC_DELSTAT_PEND) { 873 int64_t tsc; 874 int loops = 1; 875 876 tsc = rdtsc(); 877 while (LAPIC_MEM_READ(icr_lo) & APIC_DELSTAT_PEND) { 878 cpu_pause(); 879 if ((tsc_sclock_t)(rdtsc() - 880 (tsc + tsc_frequency)) > 0) { 881 tsc = rdtsc(); 882 if (++loops > 30) { 883 panic("%s: cpu%d apic stalled", 884 func, mycpuid); 885 } else { 886 kprintf("%s: cpu%d apic stalled\n", 887 func, mycpuid); 888 } 889 } 890 } 891 } 892 } 893 894 /* 895 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'. 896 * 897 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF 898 * vector is any valid SYSTEM INT vector 899 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO 900 * 901 * WARNINGS! 902 * 903 * We now implement a per-cpu interlock (gd->gd_npoll) to prevent more than 904 * one IPI from being sent to any given cpu at a time. Thus we no longer 905 * have to process incoming IPIs while waiting for the status to clear. 906 * No deadlock should be possible. 907 * 908 * We now physically disable interrupts for the lapic ICR operation. If 909 * we do not do this then it looks like an EOI sent to the lapic (which 910 * occurs even with a critical section) can interfere with the command 911 * register ready status and cause an IPI to be lost. 912 * 913 * e.g. an interrupt can occur, issue the EOI, IRET, and cause the command 914 * register to busy just before we write to icr_lo, resulting in a lost 915 * issuance. This only appears to occur on Intel cpus and is not 916 * documented. It could simply be that cpus are so fast these days that 917 * it was always an issue, but is only now rearing its ugly head. This 918 * is conjecture. 919 */ 920 static int 921 lapic_mem_ipi(int dest_type, int vector, int delivery_mode) 922 { 923 lapic_mem_icr_unpend(__func__); 924 lapic_mem_icr_set(0, 925 dest_type | APIC_LEVEL_ASSERT | delivery_mode | vector); 926 return 0; 927 } 928 929 static int 930 lapic_msr_ipi(int dest_type, int vector, int delivery_mode) 931 { 932 lapic_msr_icr_set(0, 933 dest_type | APIC_LEVEL_ASSERT | delivery_mode | vector); 934 return 0; 935 } 936 937 /* 938 * Interrupts must be hard-disabled by caller 939 */ 940 static void 941 lapic_mem_single_ipi(int cpu, int vector, int delivery_mode) 942 { 943 lapic_mem_icr_unpend(__func__); 944 lapic_mem_icr_set(CPUID_TO_APICID(cpu), 945 APIC_DEST_DESTFLD | APIC_LEVEL_ASSERT | delivery_mode | vector); 946 } 947 948 static void 949 lapic_msr_single_ipi(int cpu, int vector, int delivery_mode) 950 { 951 lapic_msr_icr_set(CPUID_TO_APICID(cpu), 952 APIC_DEST_DESTFLD | APIC_LEVEL_ASSERT | delivery_mode | vector); 953 } 954 955 /* 956 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'. 957 * 958 * target is a bitmask of destination cpus. Vector is any 959 * valid system INT vector. Delivery mode may be either 960 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO. 961 * 962 * Interrupts must be hard-disabled by caller 963 */ 964 void 965 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode) 966 { 967 while (CPUMASK_TESTNZERO(target)) { 968 int n = BSFCPUMASK(target); 969 CPUMASK_NANDBIT(target, n); 970 single_apic_ipi(n, vector, delivery_mode); 971 } 972 } 973 974 /* 975 * Load a 'downcount time' in uSeconds. 976 */ 977 void 978 set_apic_timer(int us) 979 { 980 u_int count; 981 982 if (lapic_use_tscdeadline) { 983 uint64_t val; 984 985 val = lapic_scale_to_tsc(us, 1000000); 986 val += rdtsc(); 987 /* No need to arm the lapic here, just track the timeout. */ 988 tsc_deadlines[mycpuid].downcount_time = val; 989 return; 990 } 991 992 /* 993 * When we reach here, lapic timer's frequency 994 * must have been calculated as well as the 995 * divisor (lapic->dcr_timer is setup during the 996 * divisor calculation). 997 */ 998 KKASSERT(lapic_cputimer_intr.freq != 0 && 999 lapic_timer_divisor_idx >= 0); 1000 1001 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000; 1002 lapic_timer_oneshot(count); 1003 } 1004 1005 1006 /* 1007 * Read remaining time in timer, in microseconds (rounded up). 1008 */ 1009 int 1010 read_apic_timer(void) 1011 { 1012 uint64_t val; 1013 1014 if (lapic_use_tscdeadline) { 1015 uint64_t now; 1016 1017 val = tsc_deadlines[mycpuid].downcount_time; 1018 now = rdtsc(); 1019 if (val == 0 || now > val) { 1020 return 0; 1021 } else { 1022 val -= now; 1023 val *= 1000000; 1024 val += (tsc_frequency - 1); 1025 val /= tsc_frequency; 1026 if (val > INT_MAX) 1027 val = INT_MAX; 1028 return val; 1029 } 1030 } 1031 1032 val = LAPIC_READ(ccr_timer); 1033 if (val == 0) 1034 return 0; 1035 1036 KKASSERT(lapic_cputimer_intr.freq > 0); 1037 val *= 1000000; 1038 val += (lapic_cputimer_intr.freq - 1); 1039 val /= lapic_cputimer_intr.freq; 1040 if (val > INT_MAX) 1041 val = INT_MAX; 1042 return val; 1043 } 1044 1045 1046 /* 1047 * Spin-style delay, set delay time in uS, spin till it drains. 1048 */ 1049 void 1050 u_sleep(int count) 1051 { 1052 set_apic_timer(count); 1053 while (read_apic_timer()) 1054 /* spin */ ; 1055 } 1056 1057 int 1058 lapic_unused_apic_id(int start) 1059 { 1060 int i; 1061 1062 for (i = start; i < APICID_MAX; ++i) { 1063 if (APICID_TO_CPUID(i) == -1) 1064 return i; 1065 } 1066 return NAPICID; 1067 } 1068 1069 void 1070 lapic_map(vm_paddr_t lapic_addr) 1071 { 1072 lapic_mem = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC)); 1073 } 1074 1075 void 1076 lapic_x2apic_enter(boolean_t bsp) 1077 { 1078 uint64_t apic_base; 1079 1080 KASSERT(x2apic_enable, ("X2APIC mode is not enabled")); 1081 1082 /* 1083 * X2APIC mode is requested, if it has not been enabled by the BIOS, 1084 * enable it now. 1085 */ 1086 apic_base = rdmsr(MSR_APICBASE); 1087 if ((apic_base & APICBASE_X2APIC) == 0) { 1088 wrmsr(MSR_APICBASE, 1089 apic_base | APICBASE_X2APIC | APICBASE_ENABLED); 1090 } 1091 if (bsp) { 1092 lapic_eoi = lapic_msr_eoi; 1093 apic_ipi = lapic_msr_ipi; 1094 single_apic_ipi = lapic_msr_single_ipi; 1095 lapic_cputimer_intr.reload = lapic_msr_timer_intr_reload; 1096 } 1097 } 1098 1099 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators = 1100 TAILQ_HEAD_INITIALIZER(lapic_enumerators); 1101 1102 int 1103 lapic_config(void) 1104 { 1105 struct lapic_enumerator *e; 1106 uint64_t apic_base; 1107 int error, i, ap_max; 1108 1109 KKASSERT(lapic_enable); 1110 1111 lapic_eoi = lapic_mem_eoi; 1112 apic_ipi = lapic_mem_ipi; 1113 single_apic_ipi = lapic_mem_single_ipi; 1114 1115 TUNABLE_INT_FETCH("hw.x2apic_enable", &x2apic_enable); 1116 if (x2apic_enable < 0) 1117 x2apic_enable = 1; 1118 1119 if ((cpu_feature2 & CPUID2_X2APIC) == 0) { 1120 /* X2APIC is not supported. */ 1121 x2apic_enable = 0; 1122 } else if (!x2apic_enable) { 1123 /* 1124 * If the BIOS enabled the X2APIC mode, then we would stick 1125 * with the X2APIC mode. 1126 */ 1127 apic_base = rdmsr(MSR_APICBASE); 1128 if (apic_base & APICBASE_X2APIC) { 1129 kprintf("LAPIC: BIOS enabled X2APIC mode\n"); 1130 x2apic_enable = 1; 1131 } 1132 } 1133 1134 if (x2apic_enable) { 1135 /* 1136 * Enter X2APIC mode. 1137 */ 1138 kprintf("LAPIC: enter X2APIC mode\n"); 1139 lapic_x2apic_enter(TRUE); 1140 } 1141 1142 for (i = 0; i < NAPICID; ++i) 1143 APICID_TO_CPUID(i) = -1; 1144 1145 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { 1146 error = e->lapic_probe(e); 1147 if (!error) 1148 break; 1149 } 1150 if (e == NULL) { 1151 kprintf("LAPIC: Can't find LAPIC\n"); 1152 return ENXIO; 1153 } 1154 1155 error = e->lapic_enumerate(e); 1156 if (error) { 1157 kprintf("LAPIC: enumeration failed\n"); 1158 return ENXIO; 1159 } 1160 1161 /* LAPIC is usable now. */ 1162 lapic_usable = 1; 1163 1164 ap_max = MAXCPU - 1; 1165 TUNABLE_INT_FETCH("hw.ap_max", &ap_max); 1166 if (ap_max > MAXCPU - 1) 1167 ap_max = MAXCPU - 1; 1168 1169 if (naps > ap_max) { 1170 kprintf("LAPIC: Warning use only %d out of %d " 1171 "available APs\n", 1172 ap_max, naps); 1173 naps = ap_max; 1174 } 1175 1176 return 0; 1177 } 1178 1179 void 1180 lapic_enumerator_register(struct lapic_enumerator *ne) 1181 { 1182 struct lapic_enumerator *e; 1183 1184 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { 1185 if (e->lapic_prio < ne->lapic_prio) { 1186 TAILQ_INSERT_BEFORE(e, ne, lapic_link); 1187 return; 1188 } 1189 } 1190 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link); 1191 } 1192 1193 void 1194 lapic_set_cpuid(int cpu_id, int apic_id) 1195 { 1196 CPUID_TO_APICID(cpu_id) = apic_id; 1197 APICID_TO_CPUID(apic_id) = cpu_id; 1198 } 1199 1200 void 1201 lapic_fixup_noioapic(void) 1202 { 1203 u_int temp; 1204 1205 /* Only allowed on BSP */ 1206 KKASSERT(mycpuid == 0); 1207 KKASSERT(!ioapic_enable); 1208 1209 temp = LAPIC_READ(lvt_lint0); 1210 temp &= ~APIC_LVT_MASKED; 1211 LAPIC_WRITE(lvt_lint0, temp); 1212 1213 temp = LAPIC_READ(lvt_lint1); 1214 temp |= APIC_LVT_MASKED; 1215 LAPIC_WRITE(lvt_lint1, temp); 1216 } 1217 1218 static void 1219 lapic_mem_eoi(void) 1220 { 1221 log_lapic(mem_eoi); 1222 LAPIC_MEM_WRITE(eoi, 0); 1223 } 1224 1225 static void 1226 lapic_msr_eoi(void) 1227 { 1228 log_lapic(msr_eoi); 1229 LAPIC_MSR_WRITE(MSR_X2APIC_EOI, 0); 1230 } 1231 1232 static void 1233 lapic_mem_seticr_sync(uint32_t apic_id, uint32_t icr_lo_val) 1234 { 1235 lapic_mem_icr_set(apic_id, icr_lo_val); 1236 while (LAPIC_MEM_READ(icr_lo) & APIC_DELSTAT_PEND) 1237 /* spin */; 1238 } 1239 1240 void 1241 lapic_seticr_sync(uint32_t apic_id, uint32_t icr_lo_val) 1242 { 1243 if (x2apic_enable) 1244 lapic_msr_icr_set(apic_id, icr_lo_val); 1245 else 1246 lapic_mem_seticr_sync(apic_id, icr_lo_val); 1247 } 1248 1249 static void 1250 lapic_sysinit(void *dummy __unused) 1251 { 1252 if (lapic_enable) { 1253 int error; 1254 1255 error = lapic_config(); 1256 if (error) 1257 lapic_enable = 0; 1258 } 1259 if (!lapic_enable) 1260 x2apic_enable = 0; 1261 1262 if (lapic_enable) { 1263 /* Initialize BSP's local APIC */ 1264 lapic_init(TRUE); 1265 } else if (ioapic_enable) { 1266 ioapic_enable = 0; 1267 icu_reinit_noioapic(); 1268 } 1269 } 1270 SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL); 1271