xref: /dragonfly/sys/platform/pc64/icu/icu.c (revision 0db87cb7)
1 /*-
2  * Copyright (c) 1991 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * This code is derived from software contributed to Berkeley by
6  * William Jolitz.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by the University of
19  *	California, Berkeley and its contributors.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
37  * $FreeBSD: src/sys/i386/isa/intr_machdep.c,v 1.29.2.5 2001/10/14 06:54:27 luigi Exp $
38  * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.c,v 1.48 2008/08/02 01:14:43 dillon Exp $
39  */
40 /*
41  * This file contains an aggregated module marked:
42  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
43  * All rights reserved.
44  * See the notice for details.
45  */
46 
47 #include "opt_auto_eoi.h"
48 
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/machintr.h>
52 #include <sys/interrupt.h>
53 #include <sys/thread2.h>
54 
55 #include <bus/isa/isareg.h>
56 #include <cpu/cpufunc.h>
57 
58 #include <machine/intr_machdep.h>
59 #include <machine_base/icu/icu.h>
60 #include <machine_base/icu/icu_var.h>
61 #include <machine_base/apic/ioapic.h>
62 
63 static void	icu_init(void);
64 
65 static void
66 icu_init(void)
67 {
68 #ifdef AUTO_EOI_1
69 	int auto_eoi = 2;		/* auto EOI, 8086 mode */
70 #else
71 	int auto_eoi = 0;		/* 8086 mode */
72 #endif
73 
74 	if (ioapic_enable)
75 		auto_eoi = 2;		/* auto EOI, 8086 mode */
76 
77 	/*
78 	 * Program master
79 	 */
80 	outb(IO_ICU1, 0x11);		/* reset; program device, four bytes */
81 	outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_OFFSET);
82 					/* starting at this vector index */
83 	outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << ICU_IRQ_SLAVE);
84 					/* slave on line 2 */
85 	outb(IO_ICU1 + ICU_IMR_OFFSET, auto_eoi | 1); /* 8086 mode */
86 
87 	outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
88 	outb(IO_ICU1, 0x0a);		/* default to IRR on read */
89 	outb(IO_ICU1, 0xc0 | (3 - 1));	/* pri order 3-7, 0-2 (com2 first) */
90 
91 	/*
92 	 * Program slave
93 	 */
94 	outb(IO_ICU2, 0x11);		/* reset; program device, four bytes */
95 	outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_OFFSET + 8);
96 					/* staring at this vector index */
97 	outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_IRQ_SLAVE);
98 #ifdef AUTO_EOI_2
99 	outb(IO_ICU2 + ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
100 #else
101 	outb(IO_ICU2 + ICU_IMR_OFFSET, 1); /* 8086 mode */
102 #endif
103 
104 	outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
105 	outb(IO_ICU2, 0x0a);		/* default to IRR on read */
106 }
107 
108 void
109 icu_definit(void)
110 {
111 	register_t ef;
112 
113 	KKASSERT(MachIntrABI.type == MACHINTR_ICU);
114 
115 	ef = read_rflags();
116 	cpu_disable_intr();
117 
118 	/* Leave interrupts masked */
119 	outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
120 	outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
121 
122 	MachIntrABI.setdefault();
123 	icu_init();
124 
125 	write_rflags(ef);
126 }
127 
128 /*
129  *  ICU reinitialize when ICU configuration has lost.
130  */
131 void
132 icu_reinit(void)
133 {
134 #ifdef foo
135 	int i;
136 
137 	icu_init();
138 	for (i = 0; i < MAX_HARDINTS; ++i) {
139 		if (count_registered_ints(i))
140 			machintr_intr_enable(i);
141 	}
142 #else
143 	icu_init();
144 #endif
145 }
146 
147 /*
148  * Return a bitmap of the current interrupt requests.  This is 8259-specific
149  * and is only suitable for use at probe time.
150  */
151 intrmask_t
152 icu_irq_pending(void)
153 {
154 	u_char irr1;
155 	u_char irr2;
156 
157 	irr1 = inb(IO_ICU1);
158 	irr2 = inb(IO_ICU2);
159 	return ((irr2 << 8) | irr1);
160 }
161 
162 int
163 icu_ioapic_extint(int irq, int vec)
164 {
165 	uint8_t mask;
166 
167 	/*
168 	 * Only first 8 interrupt is supported.
169 	 * Don't allow setup for the slave link.
170 	 */
171 	if (irq >= 8 || irq == 2)
172 		return EOPNOTSUPP;
173 
174 	mask = ~(1 << irq);
175 
176 	/*
177 	 * Re-initialize master 8259:
178 	 *   reset; prog 4 bytes, single ICU, edge triggered
179 	 */
180 	outb(IO_ICU1, 0x13);
181 	outb(IO_ICU1 + 1, vec);		/* start vector (unused) */
182 	outb(IO_ICU1 + 1, 0x00);	/* ignore slave */
183 	outb(IO_ICU1 + 1, 0x03);	/* auto EOI, 8086 */
184 	outb(IO_ICU1 + 1, mask);
185 
186 	return 0;
187 }
188 
189 void
190 icu_reinit_noioapic(void)
191 {
192 	register_t ef;
193 
194 	KKASSERT(MachIntrABI.type == MACHINTR_ICU);
195 	KKASSERT(ioapic_enable == 0);
196 
197 	crit_enter();
198 	ef = read_rflags();
199 	cpu_disable_intr();
200 
201 	/* Leave interrupts masked */
202 	outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
203 	outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
204 
205 	icu_init();
206 	MachIntrABI.stabilize();
207 
208 	write_rflags(ef);
209 
210 	MachIntrABI.cleanup();
211 	crit_exit();
212 }
213