1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 33 * $FreeBSD: src/sys/i386/isa/intr_machdep.c,v 1.29.2.5 2001/10/14 06:54:27 luigi Exp $ 34 * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.c,v 1.48 2008/08/02 01:14:43 dillon Exp $ 35 */ 36 /* 37 * This file contains an aggregated module marked: 38 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 39 * All rights reserved. 40 * See the notice for details. 41 */ 42 43 #include "opt_auto_eoi.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/machintr.h> 48 #include <sys/interrupt.h> 49 #include <sys/thread2.h> 50 51 #include <bus/isa/isareg.h> 52 #include <cpu/cpufunc.h> 53 54 #include <machine/intr_machdep.h> 55 #include <machine_base/icu/icu.h> 56 #include <machine_base/icu/icu_var.h> 57 #include <machine_base/apic/ioapic.h> 58 59 static void icu_init(void); 60 61 static void 62 icu_init(void) 63 { 64 #ifdef AUTO_EOI_1 65 int auto_eoi = 2; /* auto EOI, 8086 mode */ 66 #else 67 int auto_eoi = 0; /* 8086 mode */ 68 #endif 69 70 if (ioapic_enable) 71 auto_eoi = 2; /* auto EOI, 8086 mode */ 72 73 /* 74 * Program master 75 */ 76 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 77 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_OFFSET); 78 /* starting at this vector index */ 79 outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << ICU_IRQ_SLAVE); 80 /* slave on line 2 */ 81 outb(IO_ICU1 + ICU_IMR_OFFSET, auto_eoi | 1); /* 8086 mode */ 82 83 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ 84 outb(IO_ICU1, 0x0a); /* default to IRR on read */ 85 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 86 87 /* 88 * Program slave 89 */ 90 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 91 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_OFFSET + 8); 92 /* staring at this vector index */ 93 outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_IRQ_SLAVE); 94 #ifdef AUTO_EOI_2 95 outb(IO_ICU2 + ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ 96 #else 97 outb(IO_ICU2 + ICU_IMR_OFFSET, 1); /* 8086 mode */ 98 #endif 99 100 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ 101 outb(IO_ICU2, 0x0a); /* default to IRR on read */ 102 } 103 104 void 105 icu_definit(void) 106 { 107 register_t ef; 108 109 KKASSERT(MachIntrABI.type == MACHINTR_ICU); 110 111 ef = read_rflags(); 112 cpu_disable_intr(); 113 114 /* Leave interrupts masked */ 115 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); 116 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff); 117 118 MachIntrABI.setdefault(); 119 icu_init(); 120 121 write_rflags(ef); 122 } 123 124 /* 125 * ICU reinitialize when ICU configuration has lost. 126 */ 127 void 128 icu_reinit(void) 129 { 130 #ifdef foo 131 int i; 132 133 icu_init(); 134 for (i = 0; i < MAX_HARDINTS; ++i) { 135 if (count_registered_ints(i)) 136 machintr_intr_enable(i); 137 } 138 #else 139 icu_init(); 140 #endif 141 } 142 143 /* 144 * Return a bitmap of the current interrupt requests. This is 8259-specific 145 * and is only suitable for use at probe time. 146 */ 147 intrmask_t 148 icu_irq_pending(void) 149 { 150 u_char irr1; 151 u_char irr2; 152 153 irr1 = inb(IO_ICU1); 154 irr2 = inb(IO_ICU2); 155 return ((irr2 << 8) | irr1); 156 } 157 158 int 159 icu_ioapic_extint(int irq, int vec) 160 { 161 uint8_t mask; 162 163 /* 164 * Only first 8 interrupt is supported. 165 * Don't allow setup for the slave link. 166 */ 167 if (irq >= 8 || irq == 2) 168 return EOPNOTSUPP; 169 170 mask = ~(1 << irq); 171 172 /* 173 * Re-initialize master 8259: 174 * reset; prog 4 bytes, single ICU, edge triggered 175 */ 176 outb(IO_ICU1, 0x13); 177 outb(IO_ICU1 + 1, vec); /* start vector (unused) */ 178 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 179 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 180 outb(IO_ICU1 + 1, mask); 181 182 return 0; 183 } 184 185 void 186 icu_reinit_noioapic(void) 187 { 188 register_t ef; 189 190 KKASSERT(MachIntrABI.type == MACHINTR_ICU); 191 KKASSERT(ioapic_enable == 0); 192 193 crit_enter(); 194 ef = read_rflags(); 195 cpu_disable_intr(); 196 197 /* Leave interrupts masked */ 198 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); 199 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff); 200 201 icu_init(); 202 MachIntrABI.stabilize(); 203 204 write_rflags(ef); 205 206 MachIntrABI.cleanup(); 207 crit_exit(); 208 } 209