1 /* 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2005,2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Matthew Dillon <dillon@backplane.com> 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in 20 * the documentation and/or other materials provided with the 21 * distribution. 22 * 3. Neither the name of The DragonFly Project nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific, prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/machintr.h> 44 #include <sys/interrupt.h> 45 #include <sys/rman.h> 46 #include <sys/bus.h> 47 48 #include <machine/segments.h> 49 #include <machine/md_var.h> 50 #include <machine/intr_machdep.h> 51 #include <machine/globaldata.h> 52 #include <machine/smp.h> 53 #include <machine/msi_var.h> 54 55 #include <machine_base/icu/elcr_var.h> 56 57 #include <machine_base/icu/icu.h> 58 #include <machine_base/icu/icu_ipl.h> 59 #include <machine_base/apic/ioapic.h> 60 61 extern inthand_t 62 IDTVEC(icu_intr0), IDTVEC(icu_intr1), 63 IDTVEC(icu_intr2), IDTVEC(icu_intr3), 64 IDTVEC(icu_intr4), IDTVEC(icu_intr5), 65 IDTVEC(icu_intr6), IDTVEC(icu_intr7), 66 IDTVEC(icu_intr8), IDTVEC(icu_intr9), 67 IDTVEC(icu_intr10), IDTVEC(icu_intr11), 68 IDTVEC(icu_intr12), IDTVEC(icu_intr13), 69 IDTVEC(icu_intr14), IDTVEC(icu_intr15); 70 71 static inthand_t *icu_intr[ICU_HWI_VECTORS] = { 72 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1), 73 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3), 74 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5), 75 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7), 76 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9), 77 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11), 78 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13), 79 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15) 80 }; 81 82 static struct icu_irqmap { 83 int im_type; /* ICU_IMT_ */ 84 enum intr_trigger im_trig; 85 int im_msi_base; 86 uint32_t im_flags; /* ICU_IMF_ */ 87 } icu_irqmaps[MAXCPU][IDT_HWI_VECTORS]; 88 89 static struct lwkt_token icu_irqmap_tok = 90 LWKT_TOKEN_INITIALIZER(icu_irqmap_token); 91 92 #define ICU_IMT_UNUSED 0 /* KEEP THIS */ 93 #define ICU_IMT_RESERVED 1 94 #define ICU_IMT_LEGACY 2 95 #define ICU_IMT_SYSCALL 3 96 #define ICU_IMT_MSI 4 97 #define ICU_IMT_MSIX 5 98 99 #define ICU_IMT_ISHWI(map) ((map)->im_type != ICU_IMT_RESERVED && \ 100 (map)->im_type != ICU_IMT_SYSCALL) 101 102 #define ICU_IMF_CONF 0x1 103 104 extern void ICU_INTREN(int); 105 extern void ICU_INTRDIS(int); 106 107 extern int imcr_present; 108 109 static void icu_abi_intr_enable(int); 110 static void icu_abi_intr_disable(int); 111 static void icu_abi_intr_setup(int, int); 112 static void icu_abi_intr_teardown(int); 113 114 static void icu_abi_legacy_intr_config(int, enum intr_trigger, 115 enum intr_polarity); 116 static int icu_abi_legacy_intr_cpuid(int); 117 static int icu_abi_legacy_intr_find(int, enum intr_trigger, 118 enum intr_polarity); 119 static int icu_abi_legacy_intr_find_bygsi(int, enum intr_trigger, 120 enum intr_polarity); 121 122 static int icu_abi_msi_alloc(int [], int, int); 123 static void icu_abi_msi_release(const int [], int, int); 124 static void icu_abi_msi_map(int, uint64_t *, uint32_t *, int); 125 static int icu_abi_msix_alloc(int *, int); 126 static void icu_abi_msix_release(int, int); 127 128 static int icu_abi_msi_alloc_intern(int, const char *, 129 int [], int, int); 130 static void icu_abi_msi_release_intern(int, const char *, 131 const int [], int, int); 132 133 static void icu_abi_finalize(void); 134 static void icu_abi_cleanup(void); 135 static void icu_abi_setdefault(void); 136 static void icu_abi_stabilize(void); 137 static void icu_abi_initmap(void); 138 static void icu_abi_rman_setup(struct rman *); 139 140 struct machintr_abi MachIntrABI_ICU = { 141 MACHINTR_ICU, 142 .intr_disable = icu_abi_intr_disable, 143 .intr_enable = icu_abi_intr_enable, 144 .intr_setup = icu_abi_intr_setup, 145 .intr_teardown = icu_abi_intr_teardown, 146 147 .legacy_intr_config = icu_abi_legacy_intr_config, 148 .legacy_intr_cpuid = icu_abi_legacy_intr_cpuid, 149 .legacy_intr_find = icu_abi_legacy_intr_find, 150 .legacy_intr_find_bygsi = icu_abi_legacy_intr_find_bygsi, 151 152 .msi_alloc = icu_abi_msi_alloc, 153 .msi_release = icu_abi_msi_release, 154 .msi_map = icu_abi_msi_map, 155 .msix_alloc = icu_abi_msix_alloc, 156 .msix_release = icu_abi_msix_release, 157 158 .finalize = icu_abi_finalize, 159 .cleanup = icu_abi_cleanup, 160 .setdefault = icu_abi_setdefault, 161 .stabilize = icu_abi_stabilize, 162 .initmap = icu_abi_initmap, 163 .rman_setup = icu_abi_rman_setup 164 }; 165 166 static int icu_abi_msi_start; /* NOTE: for testing only */ 167 168 /* 169 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 170 */ 171 172 static void 173 icu_abi_intr_enable(int irq) 174 { 175 const struct icu_irqmap *map; 176 177 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, 178 ("icu enable, invalid irq %d", irq)); 179 180 map = &icu_irqmaps[mycpuid][irq]; 181 KASSERT(ICU_IMT_ISHWI(map), 182 ("icu enable, not hwi irq %d, type %d, cpu%d", 183 irq, map->im_type, mycpuid)); 184 if (map->im_type != ICU_IMT_LEGACY) 185 return; 186 187 ICU_INTREN(irq); 188 } 189 190 static void 191 icu_abi_intr_disable(int irq) 192 { 193 const struct icu_irqmap *map; 194 195 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, 196 ("icu disable, invalid irq %d", irq)); 197 198 map = &icu_irqmaps[mycpuid][irq]; 199 KASSERT(ICU_IMT_ISHWI(map), 200 ("icu disable, not hwi irq %d, type %d, cpu%d", 201 irq, map->im_type, mycpuid)); 202 if (map->im_type != ICU_IMT_LEGACY) 203 return; 204 205 ICU_INTRDIS(irq); 206 } 207 208 /* 209 * Called before interrupts are physically enabled 210 */ 211 static void 212 icu_abi_stabilize(void) 213 { 214 int intr; 215 216 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) 217 ICU_INTRDIS(intr); 218 ICU_INTREN(ICU_IRQ_SLAVE); 219 } 220 221 /* 222 * Called after interrupts physically enabled but before the 223 * critical section is released. 224 */ 225 static void 226 icu_abi_cleanup(void) 227 { 228 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 229 } 230 231 /* 232 * Called after stablize and cleanup; critical section is not 233 * held and interrupts are not physically disabled. 234 */ 235 static void 236 icu_abi_finalize(void) 237 { 238 KKASSERT(MachIntrABI.type == MACHINTR_ICU); 239 KKASSERT(!ioapic_enable); 240 241 /* 242 * If an IMCR is present, programming bit 0 disconnects the 8259 243 * from the BSP. The 8259 may still be connected to LINT0 on the 244 * BSP's LAPIC. 245 * 246 * If we are running SMP the LAPIC is active, try to use virtual 247 * wire mode so we can use other interrupt sources within the LAPIC 248 * in addition to the 8259. 249 */ 250 if (imcr_present) { 251 outb(0x22, 0x70); 252 outb(0x23, 0x01); 253 } 254 } 255 256 static void 257 icu_abi_intr_setup(int intr, int flags) 258 { 259 const struct icu_irqmap *map; 260 register_t ef; 261 262 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 263 ("icu setup, invalid irq %d", intr)); 264 265 map = &icu_irqmaps[mycpuid][intr]; 266 KASSERT(ICU_IMT_ISHWI(map), 267 ("icu setup, not hwi irq %d, type %d, cpu%d", 268 intr, map->im_type, mycpuid)); 269 if (map->im_type != ICU_IMT_LEGACY) 270 return; 271 272 ef = read_rflags(); 273 cpu_disable_intr(); 274 275 ICU_INTREN(intr); 276 277 write_rflags(ef); 278 } 279 280 static void 281 icu_abi_intr_teardown(int intr) 282 { 283 const struct icu_irqmap *map; 284 register_t ef; 285 286 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 287 ("icu teardown, invalid irq %d", intr)); 288 289 map = &icu_irqmaps[mycpuid][intr]; 290 KASSERT(ICU_IMT_ISHWI(map), 291 ("icu teardown, not hwi irq %d, type %d, cpu%d", 292 intr, map->im_type, mycpuid)); 293 if (map->im_type != ICU_IMT_LEGACY) 294 return; 295 296 ef = read_rflags(); 297 cpu_disable_intr(); 298 299 ICU_INTRDIS(intr); 300 301 write_rflags(ef); 302 } 303 304 static void 305 icu_abi_setdefault(void) 306 { 307 int intr; 308 309 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) { 310 if (intr == ICU_IRQ_SLAVE) 311 continue; 312 setidt_global(IDT_OFFSET + intr, icu_intr[intr], 313 SDT_SYSIGT, SEL_KPL, 0); 314 } 315 } 316 317 static void 318 icu_abi_initmap(void) 319 { 320 int cpu; 321 322 kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start); 323 icu_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ 324 325 /* 326 * NOTE: ncpus is not ready yet 327 */ 328 for (cpu = 0; cpu < MAXCPU; ++cpu) { 329 int i; 330 331 if (cpu != 0) { 332 for (i = 0; i < ICU_HWI_VECTORS; ++i) 333 icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED; 334 } else { 335 for (i = 0; i < ICU_HWI_VECTORS; ++i) 336 icu_irqmaps[cpu][i].im_type = ICU_IMT_LEGACY; 337 icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type = 338 ICU_IMT_RESERVED; 339 340 if (elcr_found) { 341 for (i = 0; i < ICU_HWI_VECTORS; ++i) { 342 icu_irqmaps[cpu][i].im_trig = 343 elcr_read_trigger(i); 344 } 345 } else { 346 /* 347 * NOTE: Trigger mode does not matter at all 348 */ 349 for (i = 0; i < ICU_HWI_VECTORS; ++i) { 350 icu_irqmaps[cpu][i].im_trig = 351 INTR_TRIGGER_EDGE; 352 } 353 } 354 } 355 356 for (i = 0; i < IDT_HWI_VECTORS; ++i) 357 icu_irqmaps[cpu][i].im_msi_base = -1; 358 359 icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = 360 ICU_IMT_SYSCALL; 361 } 362 } 363 364 static void 365 icu_abi_legacy_intr_config(int irq, enum intr_trigger trig, 366 enum intr_polarity pola __unused) 367 { 368 struct icu_irqmap *map; 369 370 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 371 372 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS); 373 map = &icu_irqmaps[0][irq]; 374 375 KKASSERT(map->im_type == ICU_IMT_LEGACY); 376 377 /* TODO: Check whether it is configured or not */ 378 map->im_flags |= ICU_IMF_CONF; 379 380 if (trig == map->im_trig) 381 return; 382 383 if (bootverbose) { 384 kprintf("ICU: irq %d, %s -> %s\n", irq, 385 intr_str_trigger(map->im_trig), 386 intr_str_trigger(trig)); 387 } 388 map->im_trig = trig; 389 390 if (!elcr_found) { 391 if (bootverbose) 392 kprintf("ICU: no ELCR, skip irq %d config\n", irq); 393 return; 394 } 395 elcr_write_trigger(irq, map->im_trig); 396 } 397 398 static int 399 icu_abi_legacy_intr_cpuid(int irq __unused) 400 { 401 return 0; 402 } 403 404 static void 405 icu_abi_rman_setup(struct rman *rm) 406 { 407 int start, end, i; 408 409 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, 410 ("invalid rman cpuid %d", rm->rm_cpuid)); 411 412 start = end = -1; 413 for (i = 0; i < IDT_HWI_VECTORS; ++i) { 414 const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i]; 415 416 if (start < 0) { 417 if (ICU_IMT_ISHWI(map)) 418 start = end = i; 419 } else { 420 if (ICU_IMT_ISHWI(map)) { 421 end = i; 422 } else { 423 KKASSERT(end >= 0); 424 if (bootverbose) { 425 kprintf("ICU: rman cpu%d %d - %d\n", 426 rm->rm_cpuid, start, end); 427 } 428 if (rman_manage_region(rm, start, end)) { 429 panic("rman_manage_region" 430 "(cpu%d %d - %d)", rm->rm_cpuid, 431 start, end); 432 } 433 start = end = -1; 434 } 435 } 436 } 437 if (start >= 0) { 438 KKASSERT(end >= 0); 439 if (bootverbose) { 440 kprintf("ICU: rman cpu%d %d - %d\n", 441 rm->rm_cpuid, start, end); 442 } 443 if (rman_manage_region(rm, start, end)) { 444 panic("rman_manage_region(cpu%d %d - %d)", 445 rm->rm_cpuid, start, end); 446 } 447 } 448 } 449 450 static int 451 icu_abi_msi_alloc_intern(int type, const char *desc, 452 int intrs[], int count, int cpuid) 453 { 454 int i, error; 455 456 KASSERT(cpuid >= 0 && cpuid < ncpus, 457 ("invalid cpuid %d", cpuid)); 458 459 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 460 KASSERT(powerof2(count), ("count %d is not power of 2", count)); 461 462 lwkt_gettoken(&icu_irqmap_tok); 463 464 /* 465 * NOTE: 466 * Since IDT_OFFSET is 32, which is the maximum valid 'count', 467 * we do not need to find out the first properly aligned 468 * interrupt vector. 469 */ 470 471 error = EMSGSIZE; 472 for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) { 473 int j; 474 475 if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED) 476 continue; 477 478 for (j = 1; j < count; ++j) { 479 if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED) 480 break; 481 } 482 if (j != count) 483 continue; 484 485 for (j = 0; j < count; ++j) { 486 struct icu_irqmap *map; 487 int intr = i + j; 488 489 map = &icu_irqmaps[cpuid][intr]; 490 KASSERT(map->im_msi_base < 0, 491 ("intr %d, stale %s-base %d", 492 intr, desc, map->im_msi_base)); 493 494 map->im_type = type; 495 map->im_msi_base = i; 496 497 intrs[j] = intr; 498 msi_setup(intr, cpuid); 499 500 if (bootverbose) { 501 kprintf("alloc %s intr %d on cpu%d\n", 502 desc, intr, cpuid); 503 } 504 } 505 error = 0; 506 break; 507 } 508 509 lwkt_reltoken(&icu_irqmap_tok); 510 511 return error; 512 } 513 514 static void 515 icu_abi_msi_release_intern(int type, const char *desc, 516 const int intrs[], int count, int cpuid) 517 { 518 int i, msi_base = -1, intr_next = -1, mask; 519 520 KASSERT(cpuid >= 0 && cpuid < ncpus, 521 ("invalid cpuid %d", cpuid)); 522 523 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 524 525 mask = count - 1; 526 KASSERT((count & mask) == 0, ("count %d is not power of 2", count)); 527 528 lwkt_gettoken(&icu_irqmap_tok); 529 530 for (i = 0; i < count; ++i) { 531 struct icu_irqmap *map; 532 int intr = intrs[i]; 533 534 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 535 ("invalid intr %d", intr)); 536 537 map = &icu_irqmaps[cpuid][intr]; 538 KASSERT(map->im_type == type, 539 ("trying to release non-%s intr %d, type %d", desc, 540 intr, map->im_type)); 541 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 542 ("intr %d, invalid %s-base %d", intr, desc, 543 map->im_msi_base)); 544 KASSERT((map->im_msi_base & mask) == 0, 545 ("intr %d, %s-base %d is not properly aligned %d", 546 intr, desc, map->im_msi_base, count)); 547 548 if (msi_base < 0) { 549 msi_base = map->im_msi_base; 550 } else { 551 KASSERT(map->im_msi_base == msi_base, 552 ("intr %d, inconsistent %s-base, " 553 "was %d, now %d", 554 intr, desc, msi_base, map->im_msi_base)); 555 } 556 557 if (intr_next < intr) 558 intr_next = intr; 559 560 map->im_type = ICU_IMT_UNUSED; 561 map->im_msi_base = -1; 562 563 if (bootverbose) { 564 kprintf("release %s intr %d on cpu%d\n", 565 desc, intr, cpuid); 566 } 567 } 568 569 KKASSERT(intr_next > 0); 570 KKASSERT(msi_base >= 0); 571 572 ++intr_next; 573 if (intr_next < IDT_HWI_VECTORS) { 574 const struct icu_irqmap *map = &icu_irqmaps[cpuid][intr_next]; 575 576 if (map->im_type == type) { 577 KASSERT(map->im_msi_base != msi_base, 578 ("more than %d %s was allocated", count, desc)); 579 } 580 } 581 582 lwkt_reltoken(&icu_irqmap_tok); 583 } 584 585 static int 586 icu_abi_msi_alloc(int intrs[], int count, int cpuid) 587 { 588 return icu_abi_msi_alloc_intern(ICU_IMT_MSI, "MSI", 589 intrs, count, cpuid); 590 } 591 592 static void 593 icu_abi_msi_release(const int intrs[], int count, int cpuid) 594 { 595 icu_abi_msi_release_intern(ICU_IMT_MSI, "MSI", 596 intrs, count, cpuid); 597 } 598 599 static int 600 icu_abi_msix_alloc(int *intr, int cpuid) 601 { 602 return icu_abi_msi_alloc_intern(ICU_IMT_MSIX, "MSI-X", 603 intr, 1, cpuid); 604 } 605 606 static void 607 icu_abi_msix_release(int intr, int cpuid) 608 { 609 icu_abi_msi_release_intern(ICU_IMT_MSIX, "MSI-X", 610 &intr, 1, cpuid); 611 } 612 613 static void 614 icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) 615 { 616 const struct icu_irqmap *map; 617 618 KASSERT(cpuid >= 0 && cpuid < ncpus, 619 ("invalid cpuid %d", cpuid)); 620 621 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 622 ("invalid intr %d", intr)); 623 624 lwkt_gettoken(&icu_irqmap_tok); 625 626 map = &icu_irqmaps[cpuid][intr]; 627 KASSERT(map->im_type == ICU_IMT_MSI || 628 map->im_type == ICU_IMT_MSIX, 629 ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type)); 630 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 631 ("intr %d, invalid %s-base %d", intr, 632 map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X", 633 map->im_msi_base)); 634 635 msi_map(map->im_msi_base, addr, data, cpuid); 636 637 if (bootverbose) { 638 kprintf("map %s intr %d on cpu%d\n", 639 map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X", 640 intr, cpuid); 641 } 642 643 lwkt_reltoken(&icu_irqmap_tok); 644 } 645 646 static int 647 icu_abi_legacy_intr_find(int irq, enum intr_trigger trig, 648 enum intr_polarity pola __unused) 649 { 650 const struct icu_irqmap *map; 651 652 #ifdef INVARIANTS 653 if (trig == INTR_TRIGGER_CONFORM) { 654 KKASSERT(pola == INTR_POLARITY_CONFORM); 655 } else { 656 KKASSERT(trig == INTR_TRIGGER_EDGE || 657 trig == INTR_TRIGGER_LEVEL); 658 KKASSERT(pola == INTR_POLARITY_HIGH || 659 pola == INTR_POLARITY_LOW); 660 } 661 #endif 662 663 if (irq < 0 || irq >= ICU_HWI_VECTORS) 664 return -1; 665 666 map = &icu_irqmaps[0][irq]; 667 if (map->im_type == ICU_IMT_LEGACY) { 668 if ((map->im_flags & ICU_IMF_CONF) && 669 trig != INTR_TRIGGER_CONFORM) { 670 if (map->im_trig != trig) 671 return -1; 672 } 673 return irq; 674 } 675 return -1; 676 } 677 678 static int 679 icu_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig, 680 enum intr_polarity pola) 681 { 682 /* GSI and IRQ has 1:1 mapping */ 683 return icu_abi_legacy_intr_find(gsi, trig, pola); 684 } 685