1 /* 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2005,2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Matthew Dillon <dillon@backplane.com> 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in 20 * the documentation and/or other materials provided with the 21 * distribution. 22 * 3. Neither the name of The DragonFly Project nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific, prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/machintr.h> 44 #include <sys/interrupt.h> 45 #include <sys/rman.h> 46 #include <sys/bus.h> 47 48 #include <machine/segments.h> 49 #include <machine/md_var.h> 50 #include <machine/intr_machdep.h> 51 #include <machine/globaldata.h> 52 #include <machine/smp.h> 53 #include <machine/msi_var.h> 54 55 #include <sys/thread2.h> 56 57 #include <machine_base/icu/elcr_var.h> 58 59 #include <machine_base/icu/icu.h> 60 #include <machine_base/icu/icu_ipl.h> 61 #include <machine_base/apic/ioapic.h> 62 63 extern inthand_t 64 IDTVEC(icu_intr0), IDTVEC(icu_intr1), 65 IDTVEC(icu_intr2), IDTVEC(icu_intr3), 66 IDTVEC(icu_intr4), IDTVEC(icu_intr5), 67 IDTVEC(icu_intr6), IDTVEC(icu_intr7), 68 IDTVEC(icu_intr8), IDTVEC(icu_intr9), 69 IDTVEC(icu_intr10), IDTVEC(icu_intr11), 70 IDTVEC(icu_intr12), IDTVEC(icu_intr13), 71 IDTVEC(icu_intr14), IDTVEC(icu_intr15); 72 73 static inthand_t *icu_intr[ICU_HWI_VECTORS] = { 74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1), 75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3), 76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5), 77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7), 78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9), 79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11), 80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13), 81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15) 82 }; 83 84 static struct icu_irqmap { 85 int im_type; /* ICU_IMT_ */ 86 enum intr_trigger im_trig; 87 int im_msi_base; 88 uint32_t im_flags; /* ICU_IMF_ */ 89 } icu_irqmaps[MAXCPU][IDT_HWI_VECTORS]; 90 91 static struct lwkt_token icu_irqmap_tok = 92 LWKT_TOKEN_INITIALIZER(icu_irqmap_token); 93 94 #define ICU_IMT_UNUSED 0 /* KEEP THIS */ 95 #define ICU_IMT_RESERVED 1 96 #define ICU_IMT_LEGACY 2 97 #define ICU_IMT_SYSCALL 3 98 #define ICU_IMT_MSI 4 99 #define ICU_IMT_MSIX 5 100 101 #define ICU_IMT_ISHWI(map) ((map)->im_type != ICU_IMT_RESERVED && \ 102 (map)->im_type != ICU_IMT_SYSCALL) 103 104 #define ICU_IMF_CONF 0x1 105 106 extern void ICU_INTREN(int); 107 extern void ICU_INTRDIS(int); 108 109 extern int imcr_present; 110 111 static void icu_abi_intr_enable(int); 112 static void icu_abi_intr_disable(int); 113 static void icu_abi_intr_setup(int, int); 114 static void icu_abi_intr_teardown(int); 115 116 static void icu_abi_legacy_intr_config(int, enum intr_trigger, 117 enum intr_polarity); 118 static int icu_abi_legacy_intr_cpuid(int); 119 static int icu_abi_legacy_intr_find(int, enum intr_trigger, 120 enum intr_polarity); 121 static int icu_abi_legacy_intr_find_bygsi(int, enum intr_trigger, 122 enum intr_polarity); 123 124 static int icu_abi_msi_alloc(int [], int, int); 125 static void icu_abi_msi_release(const int [], int, int); 126 static void icu_abi_msi_map(int, uint64_t *, uint32_t *, int); 127 static int icu_abi_msix_alloc(int *, int); 128 static void icu_abi_msix_release(int, int); 129 130 static int icu_abi_msi_alloc_intern(int, const char *, 131 int [], int, int); 132 static void icu_abi_msi_release_intern(int, const char *, 133 const int [], int, int); 134 135 static void icu_abi_finalize(void); 136 static void icu_abi_cleanup(void); 137 static void icu_abi_setdefault(void); 138 static void icu_abi_stabilize(void); 139 static void icu_abi_initmap(void); 140 static void icu_abi_rman_setup(struct rman *); 141 142 struct machintr_abi MachIntrABI_ICU = { 143 MACHINTR_ICU, 144 .intr_disable = icu_abi_intr_disable, 145 .intr_enable = icu_abi_intr_enable, 146 .intr_setup = icu_abi_intr_setup, 147 .intr_teardown = icu_abi_intr_teardown, 148 149 .legacy_intr_config = icu_abi_legacy_intr_config, 150 .legacy_intr_cpuid = icu_abi_legacy_intr_cpuid, 151 .legacy_intr_find = icu_abi_legacy_intr_find, 152 .legacy_intr_find_bygsi = icu_abi_legacy_intr_find_bygsi, 153 154 .msi_alloc = icu_abi_msi_alloc, 155 .msi_release = icu_abi_msi_release, 156 .msi_map = icu_abi_msi_map, 157 .msix_alloc = icu_abi_msix_alloc, 158 .msix_release = icu_abi_msix_release, 159 160 .finalize = icu_abi_finalize, 161 .cleanup = icu_abi_cleanup, 162 .setdefault = icu_abi_setdefault, 163 .stabilize = icu_abi_stabilize, 164 .initmap = icu_abi_initmap, 165 .rman_setup = icu_abi_rman_setup 166 }; 167 168 static int icu_abi_msi_start; /* NOTE: for testing only */ 169 170 /* 171 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 172 */ 173 174 static void 175 icu_abi_intr_enable(int irq) 176 { 177 const struct icu_irqmap *map; 178 179 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, 180 ("icu enable, invalid irq %d", irq)); 181 182 map = &icu_irqmaps[mycpuid][irq]; 183 KASSERT(ICU_IMT_ISHWI(map), 184 ("icu enable, not hwi irq %d, type %d, cpu%d", 185 irq, map->im_type, mycpuid)); 186 if (map->im_type != ICU_IMT_LEGACY) 187 return; 188 189 ICU_INTREN(irq); 190 } 191 192 static void 193 icu_abi_intr_disable(int irq) 194 { 195 const struct icu_irqmap *map; 196 197 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, 198 ("icu disable, invalid irq %d", irq)); 199 200 map = &icu_irqmaps[mycpuid][irq]; 201 KASSERT(ICU_IMT_ISHWI(map), 202 ("icu disable, not hwi irq %d, type %d, cpu%d", 203 irq, map->im_type, mycpuid)); 204 if (map->im_type != ICU_IMT_LEGACY) 205 return; 206 207 ICU_INTRDIS(irq); 208 } 209 210 /* 211 * Called before interrupts are physically enabled 212 */ 213 static void 214 icu_abi_stabilize(void) 215 { 216 int intr; 217 218 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) 219 ICU_INTRDIS(intr); 220 ICU_INTREN(ICU_IRQ_SLAVE); 221 } 222 223 /* 224 * Called after interrupts physically enabled but before the 225 * critical section is released. 226 */ 227 static void 228 icu_abi_cleanup(void) 229 { 230 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 231 } 232 233 /* 234 * Called after stablize and cleanup; critical section is not 235 * held and interrupts are not physically disabled. 236 */ 237 static void 238 icu_abi_finalize(void) 239 { 240 KKASSERT(MachIntrABI.type == MACHINTR_ICU); 241 KKASSERT(!ioapic_enable); 242 243 /* 244 * If an IMCR is present, programming bit 0 disconnects the 8259 245 * from the BSP. The 8259 may still be connected to LINT0 on the 246 * BSP's LAPIC. 247 * 248 * If we are running SMP the LAPIC is active, try to use virtual 249 * wire mode so we can use other interrupt sources within the LAPIC 250 * in addition to the 8259. 251 */ 252 if (imcr_present) { 253 outb(0x22, 0x70); 254 outb(0x23, 0x01); 255 } 256 } 257 258 static void 259 icu_abi_intr_setup(int intr, int flags) 260 { 261 const struct icu_irqmap *map; 262 register_t ef; 263 264 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 265 ("icu setup, invalid irq %d", intr)); 266 267 map = &icu_irqmaps[mycpuid][intr]; 268 KASSERT(ICU_IMT_ISHWI(map), 269 ("icu setup, not hwi irq %d, type %d, cpu%d", 270 intr, map->im_type, mycpuid)); 271 if (map->im_type != ICU_IMT_LEGACY) 272 return; 273 274 ef = read_rflags(); 275 cpu_disable_intr(); 276 277 ICU_INTREN(intr); 278 279 write_rflags(ef); 280 } 281 282 static void 283 icu_abi_intr_teardown(int intr) 284 { 285 const struct icu_irqmap *map; 286 register_t ef; 287 288 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 289 ("icu teardown, invalid irq %d", intr)); 290 291 map = &icu_irqmaps[mycpuid][intr]; 292 KASSERT(ICU_IMT_ISHWI(map), 293 ("icu teardown, not hwi irq %d, type %d, cpu%d", 294 intr, map->im_type, mycpuid)); 295 if (map->im_type != ICU_IMT_LEGACY) 296 return; 297 298 ef = read_rflags(); 299 cpu_disable_intr(); 300 301 ICU_INTRDIS(intr); 302 303 write_rflags(ef); 304 } 305 306 static void 307 icu_abi_setdefault(void) 308 { 309 int intr; 310 311 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) { 312 if (intr == ICU_IRQ_SLAVE) 313 continue; 314 setidt_global(IDT_OFFSET + intr, icu_intr[intr], 315 SDT_SYSIGT, SEL_KPL, 0); 316 } 317 } 318 319 static void 320 icu_abi_initmap(void) 321 { 322 int cpu; 323 324 kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start); 325 icu_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ 326 327 /* 328 * NOTE: ncpus is not ready yet 329 */ 330 for (cpu = 0; cpu < MAXCPU; ++cpu) { 331 int i; 332 333 if (cpu != 0) { 334 for (i = 0; i < ICU_HWI_VECTORS; ++i) 335 icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED; 336 } else { 337 for (i = 0; i < ICU_HWI_VECTORS; ++i) 338 icu_irqmaps[cpu][i].im_type = ICU_IMT_LEGACY; 339 icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type = 340 ICU_IMT_RESERVED; 341 342 if (elcr_found) { 343 for (i = 0; i < ICU_HWI_VECTORS; ++i) { 344 icu_irqmaps[cpu][i].im_trig = 345 elcr_read_trigger(i); 346 } 347 } else { 348 /* 349 * NOTE: Trigger mode does not matter at all 350 */ 351 for (i = 0; i < ICU_HWI_VECTORS; ++i) { 352 icu_irqmaps[cpu][i].im_trig = 353 INTR_TRIGGER_EDGE; 354 } 355 } 356 } 357 358 for (i = 0; i < IDT_HWI_VECTORS; ++i) 359 icu_irqmaps[cpu][i].im_msi_base = -1; 360 361 icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = 362 ICU_IMT_SYSCALL; 363 } 364 } 365 366 static void 367 icu_abi_legacy_intr_config(int irq, enum intr_trigger trig, 368 enum intr_polarity pola __unused) 369 { 370 struct icu_irqmap *map; 371 372 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 373 374 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS); 375 map = &icu_irqmaps[0][irq]; 376 377 KKASSERT(map->im_type == ICU_IMT_LEGACY); 378 379 /* TODO: Check whether it is configured or not */ 380 map->im_flags |= ICU_IMF_CONF; 381 382 if (trig == map->im_trig) 383 return; 384 385 if (bootverbose) { 386 kprintf("ICU: irq %d, %s -> %s\n", irq, 387 intr_str_trigger(map->im_trig), 388 intr_str_trigger(trig)); 389 } 390 map->im_trig = trig; 391 392 if (!elcr_found) { 393 if (bootverbose) 394 kprintf("ICU: no ELCR, skip irq %d config\n", irq); 395 return; 396 } 397 elcr_write_trigger(irq, map->im_trig); 398 } 399 400 static int 401 icu_abi_legacy_intr_cpuid(int irq __unused) 402 { 403 return 0; 404 } 405 406 static void 407 icu_abi_rman_setup(struct rman *rm) 408 { 409 int start, end, i; 410 411 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, 412 ("invalid rman cpuid %d", rm->rm_cpuid)); 413 414 start = end = -1; 415 for (i = 0; i < IDT_HWI_VECTORS; ++i) { 416 const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i]; 417 418 if (start < 0) { 419 if (ICU_IMT_ISHWI(map)) 420 start = end = i; 421 } else { 422 if (ICU_IMT_ISHWI(map)) { 423 end = i; 424 } else { 425 KKASSERT(end >= 0); 426 if (bootverbose) { 427 kprintf("ICU: rman cpu%d %d - %d\n", 428 rm->rm_cpuid, start, end); 429 } 430 if (rman_manage_region(rm, start, end)) { 431 panic("rman_manage_region" 432 "(cpu%d %d - %d)", rm->rm_cpuid, 433 start, end); 434 } 435 start = end = -1; 436 } 437 } 438 } 439 if (start >= 0) { 440 KKASSERT(end >= 0); 441 if (bootverbose) { 442 kprintf("ICU: rman cpu%d %d - %d\n", 443 rm->rm_cpuid, start, end); 444 } 445 if (rman_manage_region(rm, start, end)) { 446 panic("rman_manage_region(cpu%d %d - %d)", 447 rm->rm_cpuid, start, end); 448 } 449 } 450 } 451 452 static int 453 icu_abi_msi_alloc_intern(int type, const char *desc, 454 int intrs[], int count, int cpuid) 455 { 456 int i, error; 457 458 KASSERT(cpuid >= 0 && cpuid < ncpus, 459 ("invalid cpuid %d", cpuid)); 460 461 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 462 KASSERT((count & (count - 1)) == 0, 463 ("count %d is not power of 2", count)); 464 465 lwkt_gettoken(&icu_irqmap_tok); 466 467 /* 468 * NOTE: 469 * Since IDT_OFFSET is 32, which is the maximum valid 'count', 470 * we do not need to find out the first properly aligned 471 * interrupt vector. 472 */ 473 474 error = EMSGSIZE; 475 for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) { 476 int j; 477 478 if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED) 479 continue; 480 481 for (j = 1; j < count; ++j) { 482 if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED) 483 break; 484 } 485 if (j != count) 486 continue; 487 488 for (j = 0; j < count; ++j) { 489 struct icu_irqmap *map; 490 int intr = i + j; 491 492 map = &icu_irqmaps[cpuid][intr]; 493 KASSERT(map->im_msi_base < 0, 494 ("intr %d, stale %s-base %d", 495 intr, desc, map->im_msi_base)); 496 497 map->im_type = type; 498 map->im_msi_base = i; 499 500 intrs[j] = intr; 501 msi_setup(intr, cpuid); 502 503 if (bootverbose) { 504 kprintf("alloc %s intr %d on cpu%d\n", 505 desc, intr, cpuid); 506 } 507 } 508 error = 0; 509 break; 510 } 511 512 lwkt_reltoken(&icu_irqmap_tok); 513 514 return error; 515 } 516 517 static void 518 icu_abi_msi_release_intern(int type, const char *desc, 519 const int intrs[], int count, int cpuid) 520 { 521 int i, msi_base = -1, intr_next = -1, mask; 522 523 KASSERT(cpuid >= 0 && cpuid < ncpus, 524 ("invalid cpuid %d", cpuid)); 525 526 KASSERT(count > 0 && count <= 32, ("invalid count %d", count)); 527 528 mask = count - 1; 529 KASSERT((count & mask) == 0, ("count %d is not power of 2", count)); 530 531 lwkt_gettoken(&icu_irqmap_tok); 532 533 for (i = 0; i < count; ++i) { 534 struct icu_irqmap *map; 535 int intr = intrs[i]; 536 537 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 538 ("invalid intr %d", intr)); 539 540 map = &icu_irqmaps[cpuid][intr]; 541 KASSERT(map->im_type == type, 542 ("trying to release non-%s intr %d, type %d", desc, 543 intr, map->im_type)); 544 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 545 ("intr %d, invalid %s-base %d", intr, desc, 546 map->im_msi_base)); 547 KASSERT((map->im_msi_base & mask) == 0, 548 ("intr %d, %s-base %d is not properly aligned %d", 549 intr, desc, map->im_msi_base, count)); 550 551 if (msi_base < 0) { 552 msi_base = map->im_msi_base; 553 } else { 554 KASSERT(map->im_msi_base == msi_base, 555 ("intr %d, inconsistent %s-base, " 556 "was %d, now %d", 557 intr, desc, msi_base, map->im_msi_base)); 558 } 559 560 if (intr_next < intr) 561 intr_next = intr; 562 563 map->im_type = ICU_IMT_UNUSED; 564 map->im_msi_base = -1; 565 566 if (bootverbose) { 567 kprintf("release %s intr %d on cpu%d\n", 568 desc, intr, cpuid); 569 } 570 } 571 572 KKASSERT(intr_next > 0); 573 KKASSERT(msi_base >= 0); 574 575 ++intr_next; 576 if (intr_next < IDT_HWI_VECTORS) { 577 const struct icu_irqmap *map = &icu_irqmaps[cpuid][intr_next]; 578 579 if (map->im_type == type) { 580 KASSERT(map->im_msi_base != msi_base, 581 ("more than %d %s was allocated", count, desc)); 582 } 583 } 584 585 lwkt_reltoken(&icu_irqmap_tok); 586 } 587 588 static int 589 icu_abi_msi_alloc(int intrs[], int count, int cpuid) 590 { 591 return icu_abi_msi_alloc_intern(ICU_IMT_MSI, "MSI", 592 intrs, count, cpuid); 593 } 594 595 static void 596 icu_abi_msi_release(const int intrs[], int count, int cpuid) 597 { 598 icu_abi_msi_release_intern(ICU_IMT_MSI, "MSI", 599 intrs, count, cpuid); 600 } 601 602 static int 603 icu_abi_msix_alloc(int *intr, int cpuid) 604 { 605 return icu_abi_msi_alloc_intern(ICU_IMT_MSIX, "MSI-X", 606 intr, 1, cpuid); 607 } 608 609 static void 610 icu_abi_msix_release(int intr, int cpuid) 611 { 612 icu_abi_msi_release_intern(ICU_IMT_MSIX, "MXI-X", 613 &intr, 1, cpuid); 614 } 615 616 static void 617 icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) 618 { 619 const struct icu_irqmap *map; 620 621 KASSERT(cpuid >= 0 && cpuid < ncpus, 622 ("invalid cpuid %d", cpuid)); 623 624 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 625 ("invalid intr %d", intr)); 626 627 lwkt_gettoken(&icu_irqmap_tok); 628 629 map = &icu_irqmaps[cpuid][intr]; 630 KASSERT(map->im_type == ICU_IMT_MSI || 631 map->im_type == ICU_IMT_MSIX, 632 ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type)); 633 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 634 ("intr %d, invalid %s-base %d", intr, 635 map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X", 636 map->im_msi_base)); 637 638 msi_map(map->im_msi_base, addr, data, cpuid); 639 640 if (bootverbose) { 641 kprintf("map %s intr %d on cpu%d\n", 642 map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X", 643 intr, cpuid); 644 } 645 646 lwkt_reltoken(&icu_irqmap_tok); 647 } 648 649 static int 650 icu_abi_legacy_intr_find(int irq, enum intr_trigger trig, 651 enum intr_polarity pola __unused) 652 { 653 const struct icu_irqmap *map; 654 655 #ifdef INVARIANTS 656 if (trig == INTR_TRIGGER_CONFORM) { 657 KKASSERT(pola == INTR_POLARITY_CONFORM); 658 } else { 659 KKASSERT(trig == INTR_TRIGGER_EDGE || 660 trig == INTR_TRIGGER_LEVEL); 661 KKASSERT(pola == INTR_POLARITY_HIGH || 662 pola == INTR_POLARITY_LOW); 663 } 664 #endif 665 666 if (irq < 0 || irq >= ICU_HWI_VECTORS) 667 return -1; 668 669 map = &icu_irqmaps[0][irq]; 670 if (map->im_type == ICU_IMT_LEGACY) { 671 if ((map->im_flags & ICU_IMF_CONF) && 672 trig != INTR_TRIGGER_CONFORM) { 673 if (map->im_trig != trig) 674 return -1; 675 } 676 return irq; 677 } 678 return -1; 679 } 680 681 static int 682 icu_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig, 683 enum intr_polarity pola) 684 { 685 /* GSI and IRQ has 1:1 mapping */ 686 return icu_abi_legacy_intr_find(gsi, trig, pola); 687 } 688