1 /* 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2005,2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Matthew Dillon <dillon@backplane.com> 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in 20 * the documentation and/or other materials provided with the 21 * distribution. 22 * 3. Neither the name of The DragonFly Project nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific, prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * $DragonFly: src/sys/platform/pc64/icu/icu_abi.c,v 1.1 2008/08/29 17:07:16 dillon Exp $ 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/machintr.h> 46 #include <sys/interrupt.h> 47 #include <sys/rman.h> 48 #include <sys/bus.h> 49 50 #include <machine/segments.h> 51 #include <machine/md_var.h> 52 #include <machine/intr_machdep.h> 53 #include <machine/globaldata.h> 54 #include <machine/smp.h> 55 #include <machine/msi_var.h> 56 57 #include <sys/thread2.h> 58 59 #include <machine_base/icu/elcr_var.h> 60 61 #include <machine_base/icu/icu.h> 62 #include <machine_base/icu/icu_ipl.h> 63 #include <machine_base/apic/ioapic.h> 64 65 extern inthand_t 66 IDTVEC(icu_intr0), IDTVEC(icu_intr1), 67 IDTVEC(icu_intr2), IDTVEC(icu_intr3), 68 IDTVEC(icu_intr4), IDTVEC(icu_intr5), 69 IDTVEC(icu_intr6), IDTVEC(icu_intr7), 70 IDTVEC(icu_intr8), IDTVEC(icu_intr9), 71 IDTVEC(icu_intr10), IDTVEC(icu_intr11), 72 IDTVEC(icu_intr12), IDTVEC(icu_intr13), 73 IDTVEC(icu_intr14), IDTVEC(icu_intr15); 74 75 static inthand_t *icu_intr[ICU_HWI_VECTORS] = { 76 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1), 77 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3), 78 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5), 79 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7), 80 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9), 81 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11), 82 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13), 83 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15) 84 }; 85 86 static struct icu_irqmap { 87 int im_type; /* ICU_IMT_ */ 88 enum intr_trigger im_trig; 89 int im_msi_base; 90 } icu_irqmaps[MAXCPU][IDT_HWI_VECTORS]; 91 92 static struct lwkt_token icu_irqmap_tok = 93 LWKT_TOKEN_INITIALIZER(icu_irqmap_token); 94 95 #define ICU_IMT_UNUSED 0 /* KEEP THIS */ 96 #define ICU_IMT_RESERVED 1 97 #define ICU_IMT_LINE 2 98 #define ICU_IMT_SYSCALL 3 99 #define ICU_IMT_MSI 4 100 101 #define ICU_IMT_ISHWI(map) ((map)->im_type != ICU_IMT_RESERVED && \ 102 (map)->im_type != ICU_IMT_SYSCALL) 103 104 extern void ICU_INTREN(int); 105 extern void ICU_INTRDIS(int); 106 107 extern int imcr_present; 108 109 static void icu_abi_intr_enable(int); 110 static void icu_abi_intr_disable(int); 111 static void icu_abi_intr_setup(int, int); 112 static void icu_abi_intr_teardown(int); 113 static void icu_abi_intr_config(int, enum intr_trigger, enum intr_polarity); 114 static int icu_abi_intr_cpuid(int); 115 116 static int icu_abi_msi_alloc(int [], int, int); 117 static void icu_abi_msi_release(const int [], int, int); 118 static void icu_abi_msi_map(int, uint64_t *, uint32_t *, int); 119 120 static void icu_abi_finalize(void); 121 static void icu_abi_cleanup(void); 122 static void icu_abi_setdefault(void); 123 static void icu_abi_stabilize(void); 124 static void icu_abi_initmap(void); 125 static void icu_abi_rman_setup(struct rman *); 126 127 struct machintr_abi MachIntrABI_ICU = { 128 MACHINTR_ICU, 129 .intr_disable = icu_abi_intr_disable, 130 .intr_enable = icu_abi_intr_enable, 131 .intr_setup = icu_abi_intr_setup, 132 .intr_teardown = icu_abi_intr_teardown, 133 .intr_config = icu_abi_intr_config, 134 .intr_cpuid = icu_abi_intr_cpuid, 135 136 .msi_alloc = icu_abi_msi_alloc, 137 .msi_release = icu_abi_msi_release, 138 .msi_map = icu_abi_msi_map, 139 140 .finalize = icu_abi_finalize, 141 .cleanup = icu_abi_cleanup, 142 .setdefault = icu_abi_setdefault, 143 .stabilize = icu_abi_stabilize, 144 .initmap = icu_abi_initmap, 145 .rman_setup = icu_abi_rman_setup 146 }; 147 148 static int icu_abi_msi_start; /* NOTE: for testing only */ 149 150 /* 151 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 152 */ 153 154 static void 155 icu_abi_intr_enable(int irq) 156 { 157 const struct icu_irqmap *map; 158 159 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, 160 ("icu enable, invalid irq %d\n", irq)); 161 162 map = &icu_irqmaps[mycpuid][irq]; 163 KASSERT(ICU_IMT_ISHWI(map), 164 ("icu enable, not hwi irq %d, type %d, cpu%d\n", 165 irq, map->im_type, mycpuid)); 166 if (map->im_type != ICU_IMT_LINE) 167 return; 168 169 ICU_INTREN(irq); 170 } 171 172 static void 173 icu_abi_intr_disable(int irq) 174 { 175 const struct icu_irqmap *map; 176 177 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, 178 ("icu disable, invalid irq %d\n", irq)); 179 180 map = &icu_irqmaps[mycpuid][irq]; 181 KASSERT(ICU_IMT_ISHWI(map), 182 ("icu disable, not hwi irq %d, type %d, cpu%d\n", 183 irq, map->im_type, mycpuid)); 184 if (map->im_type != ICU_IMT_LINE) 185 return; 186 187 ICU_INTRDIS(irq); 188 } 189 190 /* 191 * Called before interrupts are physically enabled 192 */ 193 static void 194 icu_abi_stabilize(void) 195 { 196 int intr; 197 198 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) 199 ICU_INTRDIS(intr); 200 ICU_INTREN(ICU_IRQ_SLAVE); 201 } 202 203 /* 204 * Called after interrupts physically enabled but before the 205 * critical section is released. 206 */ 207 static void 208 icu_abi_cleanup(void) 209 { 210 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 211 } 212 213 /* 214 * Called after stablize and cleanup; critical section is not 215 * held and interrupts are not physically disabled. 216 */ 217 static void 218 icu_abi_finalize(void) 219 { 220 KKASSERT(MachIntrABI.type == MACHINTR_ICU); 221 KKASSERT(!ioapic_enable); 222 223 /* 224 * If an IMCR is present, programming bit 0 disconnects the 8259 225 * from the BSP. The 8259 may still be connected to LINT0 on the 226 * BSP's LAPIC. 227 * 228 * If we are running SMP the LAPIC is active, try to use virtual 229 * wire mode so we can use other interrupt sources within the LAPIC 230 * in addition to the 8259. 231 */ 232 if (imcr_present) { 233 outb(0x22, 0x70); 234 outb(0x23, 0x01); 235 } 236 } 237 238 static void 239 icu_abi_intr_setup(int intr, int flags) 240 { 241 const struct icu_irqmap *map; 242 register_t ef; 243 244 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 245 ("icu setup, invalid irq %d\n", intr)); 246 247 map = &icu_irqmaps[mycpuid][intr]; 248 KASSERT(ICU_IMT_ISHWI(map), 249 ("icu setup, not hwi irq %d, type %d, cpu%d\n", 250 intr, map->im_type, mycpuid)); 251 if (map->im_type != ICU_IMT_LINE) 252 return; 253 254 ef = read_rflags(); 255 cpu_disable_intr(); 256 257 ICU_INTREN(intr); 258 259 write_rflags(ef); 260 } 261 262 static void 263 icu_abi_intr_teardown(int intr) 264 { 265 const struct icu_irqmap *map; 266 register_t ef; 267 268 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 269 ("icu teardown, invalid irq %d\n", intr)); 270 271 map = &icu_irqmaps[mycpuid][intr]; 272 KASSERT(ICU_IMT_ISHWI(map), 273 ("icu teardown, not hwi irq %d, type %d, cpu%d\n", 274 intr, map->im_type, mycpuid)); 275 if (map->im_type != ICU_IMT_LINE) 276 return; 277 278 ef = read_rflags(); 279 cpu_disable_intr(); 280 281 ICU_INTRDIS(intr); 282 283 write_rflags(ef); 284 } 285 286 static void 287 icu_abi_setdefault(void) 288 { 289 int intr; 290 291 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) { 292 if (intr == ICU_IRQ_SLAVE) 293 continue; 294 setidt_global(IDT_OFFSET + intr, icu_intr[intr], 295 SDT_SYSIGT, SEL_KPL, 0); 296 } 297 } 298 299 static void 300 icu_abi_initmap(void) 301 { 302 int cpu; 303 304 kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start); 305 icu_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ 306 307 /* 308 * NOTE: ncpus is not ready yet 309 */ 310 for (cpu = 0; cpu < MAXCPU; ++cpu) { 311 int i; 312 313 if (cpu != 0) { 314 for (i = 0; i < ICU_HWI_VECTORS; ++i) 315 icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED; 316 } else { 317 for (i = 0; i < ICU_HWI_VECTORS; ++i) 318 icu_irqmaps[cpu][i].im_type = ICU_IMT_LINE; 319 icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type = 320 ICU_IMT_RESERVED; 321 322 if (elcr_found) { 323 for (i = 0; i < ICU_HWI_VECTORS; ++i) { 324 icu_irqmaps[cpu][i].im_trig = 325 elcr_read_trigger(i); 326 } 327 } else { 328 /* 329 * NOTE: Trigger mode does not matter at all 330 */ 331 for (i = 0; i < ICU_HWI_VECTORS; ++i) { 332 icu_irqmaps[cpu][i].im_trig = 333 INTR_TRIGGER_EDGE; 334 } 335 } 336 } 337 338 for (i = 0; i < IDT_HWI_VECTORS; ++i) 339 icu_irqmaps[cpu][i].im_msi_base = -1; 340 341 icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = 342 ICU_IMT_SYSCALL; 343 } 344 } 345 346 static void 347 icu_abi_intr_config(int irq, enum intr_trigger trig, 348 enum intr_polarity pola __unused) 349 { 350 struct icu_irqmap *map; 351 352 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); 353 354 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS); 355 map = &icu_irqmaps[0][irq]; 356 357 KKASSERT(map->im_type == ICU_IMT_LINE); 358 359 /* TODO: Check whether it is configured or not */ 360 361 if (trig == map->im_trig) 362 return; 363 364 if (bootverbose) { 365 kprintf("ICU: irq %d, %s -> %s\n", irq, 366 intr_str_trigger(map->im_trig), 367 intr_str_trigger(trig)); 368 } 369 map->im_trig = trig; 370 371 if (!elcr_found) { 372 if (bootverbose) 373 kprintf("ICU: no ELCR, skip irq %d config\n", irq); 374 return; 375 } 376 elcr_write_trigger(irq, map->im_trig); 377 } 378 379 static int 380 icu_abi_intr_cpuid(int irq __unused) 381 { 382 return 0; 383 } 384 385 static void 386 icu_abi_rman_setup(struct rman *rm) 387 { 388 int start, end, i; 389 390 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, 391 ("invalid rman cpuid %d", rm->rm_cpuid)); 392 393 start = end = -1; 394 for (i = 0; i < IDT_HWI_VECTORS; ++i) { 395 const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i]; 396 397 if (start < 0) { 398 if (ICU_IMT_ISHWI(map)) 399 start = end = i; 400 } else { 401 if (ICU_IMT_ISHWI(map)) { 402 end = i; 403 } else { 404 KKASSERT(end >= 0); 405 if (bootverbose) { 406 kprintf("ICU: rman cpu%d %d - %d\n", 407 rm->rm_cpuid, start, end); 408 } 409 if (rman_manage_region(rm, start, end)) { 410 panic("rman_manage_region" 411 "(cpu%d %d - %d)", rm->rm_cpuid, 412 start, end); 413 } 414 start = end = -1; 415 } 416 } 417 } 418 if (start >= 0) { 419 KKASSERT(end >= 0); 420 if (bootverbose) { 421 kprintf("ICU: rman cpu%d %d - %d\n", 422 rm->rm_cpuid, start, end); 423 } 424 if (rman_manage_region(rm, start, end)) { 425 panic("rman_manage_region(cpu%d %d - %d)", 426 rm->rm_cpuid, start, end); 427 } 428 } 429 } 430 431 static int 432 icu_abi_msi_alloc(int intrs[], int count, int cpuid) 433 { 434 int i, error; 435 436 KASSERT(cpuid >= 0 && cpuid < ncpus, 437 ("invalid cpuid %d", cpuid)); 438 439 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count)); 440 KASSERT((count & (count - 1)) == 0, 441 ("count %d is not power of 2\n", count)); 442 443 lwkt_gettoken(&icu_irqmap_tok); 444 445 /* 446 * NOTE: 447 * Since IDT_OFFSET is 32, which is the maximum valid 'count', 448 * we do not need to find out the first properly aligned 449 * interrupt vector. 450 */ 451 452 error = EMSGSIZE; 453 for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) { 454 int j; 455 456 if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED) 457 continue; 458 459 for (j = 1; j < count; ++j) { 460 if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED) 461 break; 462 } 463 if (j != count) 464 continue; 465 466 for (j = 0; j < count; ++j) { 467 struct icu_irqmap *map; 468 int intr = i + j; 469 470 map = &icu_irqmaps[cpuid][intr]; 471 KASSERT(map->im_msi_base < 0, 472 ("intr %d, stale MSI-base %d\n", 473 intr, map->im_msi_base)); 474 475 map->im_type = ICU_IMT_MSI; 476 map->im_msi_base = i; 477 478 intrs[j] = intr; 479 msi_setup(intr, cpuid); 480 481 if (bootverbose) { 482 kprintf("alloc MSI intr %d on cpu%d\n", 483 intr, cpuid); 484 } 485 } 486 error = 0; 487 break; 488 } 489 490 lwkt_reltoken(&icu_irqmap_tok); 491 492 return error; 493 } 494 495 static void 496 icu_abi_msi_release(const int intrs[], int count, int cpuid) 497 { 498 int i, msi_base = -1, intr_next = -1, mask; 499 500 KASSERT(cpuid >= 0 && cpuid < ncpus, 501 ("invalid cpuid %d", cpuid)); 502 503 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count)); 504 505 mask = count - 1; 506 KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count)); 507 508 lwkt_gettoken(&icu_irqmap_tok); 509 510 for (i = 0; i < count; ++i) { 511 struct icu_irqmap *map; 512 int intr = intrs[i]; 513 514 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 515 ("invalid intr %d\n", intr)); 516 517 map = &icu_irqmaps[cpuid][intr]; 518 KASSERT(map->im_type == ICU_IMT_MSI, 519 ("try release non-MSI intr %d, type %d\n", 520 intr, map->im_type)); 521 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 522 ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base)); 523 KASSERT((map->im_msi_base & mask) == 0, 524 ("intr %d, MSI-base %d is not proper aligned %d\n", 525 intr, map->im_msi_base, count)); 526 527 if (msi_base < 0) { 528 msi_base = map->im_msi_base; 529 } else { 530 KASSERT(map->im_msi_base == msi_base, 531 ("intr %d, inconsistent MSI-base, " 532 "was %d, now %d\n", 533 intr, msi_base, map->im_msi_base)); 534 } 535 536 if (intr_next < intr) 537 intr_next = intr; 538 539 map->im_type = ICU_IMT_UNUSED; 540 map->im_msi_base = -1; 541 542 if (bootverbose) 543 kprintf("release MSI intr %d on cpu%d\n", intr, cpuid); 544 } 545 546 KKASSERT(intr_next > 0); 547 KKASSERT(msi_base >= 0); 548 549 ++intr_next; 550 if (intr_next < IDT_HWI_VECTORS) { 551 const struct icu_irqmap *map = &icu_irqmaps[cpuid][intr_next]; 552 553 if (map->im_type == ICU_IMT_MSI) { 554 KASSERT(map->im_msi_base != msi_base, 555 ("more than %d MSI was allocated\n", count)); 556 } 557 } 558 559 lwkt_reltoken(&icu_irqmap_tok); 560 } 561 562 static void 563 icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) 564 { 565 const struct icu_irqmap *map; 566 567 KASSERT(cpuid >= 0 && cpuid < ncpus, 568 ("invalid cpuid %d", cpuid)); 569 570 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, 571 ("invalid intr %d\n", intr)); 572 573 lwkt_gettoken(&icu_irqmap_tok); 574 575 map = &icu_irqmaps[cpuid][intr]; 576 KASSERT(map->im_type == ICU_IMT_MSI, 577 ("try map non-MSI intr %d, type %d\n", intr, map->im_type)); 578 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, 579 ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base)); 580 581 msi_map(map->im_msi_base, addr, data, cpuid); 582 583 if (bootverbose) 584 kprintf("map MSI intr %d on cpu%d\n", intr, cpuid); 585 586 lwkt_reltoken(&icu_irqmap_tok); 587 } 588