1/* 2 * Copyright (c) 2008 The DragonFly Project. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 3. Neither the name of The DragonFly Project nor the names of its 15 * contributors may be used to endorse or promote products derived 16 * from this software without specific, prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * from: vector.s, 386BSD 0.1 unknown origin 32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $ 33 */ 34/* 35 * WARNING! SMP builds can use the ICU now so this code must be MP safe. 36 */ 37 38#include "opt_auto_eoi.h" 39 40#include <machine/asmacros.h> 41#include <machine/lock.h> 42#include <machine/psl.h> 43#include <machine/trap.h> 44#include <machine/segments.h> 45#include <machine_base/icu/icu.h> 46#include <machine_base/icu/icu_ipl.h> 47 48#include <bus/isa/isa.h> 49 50#include "assym.s" 51 52#define ICU_EOI 0x20 /* XXX - define elsewhere */ 53 54#define IRQ_LBIT(irq_num) (1 << (irq_num)) 55#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8)) 56#define IRQ_BYTE(irq_num) ((irq_num) >> 3) 57 58#ifdef AUTO_EOI_1 59#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */ 60#define OUTB_ICU1 61#else 62#define ENABLE_ICU1 \ 63 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \ 64 OUTB_ICU1 ; /* ... to clear in service bit */ \ 65 66#define OUTB_ICU1 \ 67 outb %al,$IO_ICU1 ; \ 68 69#endif 70 71#ifdef AUTO_EOI_2 72/* 73 * The data sheet says no auto-EOI on slave, but it sometimes works. 74 */ 75#define ENABLE_ICU1_AND_2 ENABLE_ICU1 76#else 77#define ENABLE_ICU1_AND_2 \ 78 movb $ICU_EOI,%al ; /* as above */ \ 79 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \ 80 OUTB_ICU1 ; /* ... then first icu (if !AUTO_EOI_1) */ \ 81 82#endif 83 84/* 85 * Macro helpers 86 */ 87#define ICU_PUSH_FRAME \ 88 PUSH_FRAME_TFRIP ; /* 15 regs + space for 5 extras */ \ 89 movl $0,TF_XFLAGS(%rsp) ; \ 90 movl $0,TF_TRAPNO(%rsp) ; \ 91 movl $0,TF_ADDR(%rsp) ; \ 92 movl $0,TF_FLAGS(%rsp) ; \ 93 movl $0,TF_ERR(%rsp) ; \ 94 cld ; \ 95 96#define MASK_IRQ(icu, irq_num) \ 97 ICU_IMASK_LOCK ; \ 98 movb icu_imen + IRQ_BYTE(irq_num),%al ; \ 99 orb $IRQ_BIT(irq_num),%al ; \ 100 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \ 101 outb %al,$icu+ICU_IMR_OFFSET ; \ 102 ICU_IMASK_UNLOCK ; \ 103 104#define UNMASK_IRQ(icu, irq_num) \ 105 cmpl $0,%eax ; \ 106 jnz 8f ; \ 107 ICU_IMASK_LOCK ; \ 108 movb icu_imen + IRQ_BYTE(irq_num),%al ; \ 109 andb $~IRQ_BIT(irq_num),%al ; \ 110 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \ 111 outb %al,$icu+ICU_IMR_OFFSET ; \ 112 ICU_IMASK_UNLOCK ; \ 1138: ; \ 114 115/* 116 * Interrupt call handlers run in the following sequence: 117 * 118 * - Push the trap frame required by doreti. 119 * - Mask the interrupt and reenable its source. 120 * - If we cannot take the interrupt set its ipending bit and 121 * doreti. 122 * - If we can take the interrupt clear its ipending bit, 123 * call the handler, then unmask the interrupt and doreti. 124 * 125 * YYY can cache gd base pointer instead of using hidden %fs 126 * prefixes. 127 */ 128 129#define INTR_HANDLER(irq_num, icu, enable_icus) \ 130 .text ; \ 131 SUPERALIGN_TEXT ; \ 132IDTVEC(icu_intr##irq_num) ; \ 133 ICU_PUSH_FRAME ; \ 134 FAKE_MCOUNT(TF_RIP(%rsp)) ; \ 135 MASK_IRQ(icu, irq_num) ; \ 136 enable_icus ; \ 137 movq PCPU(curthread),%rbx ; \ 138 testl $-1,TD_NEST_COUNT(%rbx) ; \ 139 jne 1f ; \ 140 testl $-1,TD_CRITCOUNT(%rbx) ; \ 141 je 2f ; \ 1421: ; \ 143 /* set pending bit and return, leave interrupt masked */ \ 144 movq $0,%rdx ; \ 145 orq $IRQ_LBIT(irq_num),PCPU_E8(ipending,%rdx) ; \ 146 orl $RQF_INTPEND, PCPU(reqflags) ; \ 147 jmp 5f ; \ 1482: ; \ 149 /* clear pending bit, run handler */ \ 150 movq $0,%rdx ; \ 151 andq $~IRQ_LBIT(irq_num),PCPU_E8(ipending,%rdx) ; \ 152 pushq $irq_num ; \ 153 movq %rsp,%rdi ; /* rdi = call argument */ \ 154 incl TD_CRITCOUNT(%rbx) ; \ 155 sti ; \ 156 call ithread_fast_handler ; /* returns 0 to unmask int */ \ 157 decl TD_CRITCOUNT(%rbx) ; \ 158 addq $8,%rsp ; /* intr frame -> trap frame */ \ 159 UNMASK_IRQ(icu, irq_num) ; \ 1605: ; \ 161 MEXITCOUNT ; \ 162 jmp doreti ; \ 163 164MCOUNT_LABEL(bintr) 165 INTR_HANDLER(0, IO_ICU1, ENABLE_ICU1) 166 INTR_HANDLER(1, IO_ICU1, ENABLE_ICU1) 167 INTR_HANDLER(2, IO_ICU1, ENABLE_ICU1) 168 INTR_HANDLER(3, IO_ICU1, ENABLE_ICU1) 169 INTR_HANDLER(4, IO_ICU1, ENABLE_ICU1) 170 INTR_HANDLER(5, IO_ICU1, ENABLE_ICU1) 171 INTR_HANDLER(6, IO_ICU1, ENABLE_ICU1) 172 INTR_HANDLER(7, IO_ICU1, ENABLE_ICU1) 173 INTR_HANDLER(8, IO_ICU2, ENABLE_ICU1_AND_2) 174 INTR_HANDLER(9, IO_ICU2, ENABLE_ICU1_AND_2) 175 INTR_HANDLER(10, IO_ICU2, ENABLE_ICU1_AND_2) 176 INTR_HANDLER(11, IO_ICU2, ENABLE_ICU1_AND_2) 177 INTR_HANDLER(12, IO_ICU2, ENABLE_ICU1_AND_2) 178 INTR_HANDLER(13, IO_ICU2, ENABLE_ICU1_AND_2) 179 INTR_HANDLER(14, IO_ICU2, ENABLE_ICU1_AND_2) 180 INTR_HANDLER(15, IO_ICU2, ENABLE_ICU1_AND_2) 181MCOUNT_LABEL(eintr) 182 183 .data 184 185 .text 186