157a9c56bSSepherosa Ziehau /*- 257a9c56bSSepherosa Ziehau * Copyright (c) 1991 The Regents of the University of California. 357a9c56bSSepherosa Ziehau * Copyright (c) 2008 The DragonFly Project. 457a9c56bSSepherosa Ziehau * All rights reserved. 557a9c56bSSepherosa Ziehau * 657a9c56bSSepherosa Ziehau * Redistribution and use in source and binary forms, with or without 757a9c56bSSepherosa Ziehau * modification, are permitted provided that the following conditions 857a9c56bSSepherosa Ziehau * are met: 957a9c56bSSepherosa Ziehau * 1. Redistributions of source code must retain the above copyright 1057a9c56bSSepherosa Ziehau * notice, this list of conditions and the following disclaimer. 1157a9c56bSSepherosa Ziehau * 2. Redistributions in binary form must reproduce the above copyright 1257a9c56bSSepherosa Ziehau * notice, this list of conditions and the following disclaimer in the 1357a9c56bSSepherosa Ziehau * documentation and/or other materials provided with the distribution. 142c64e990Szrj * 3. Neither the name of the University nor the names of its contributors 1557a9c56bSSepherosa Ziehau * may be used to endorse or promote products derived from this software 1657a9c56bSSepherosa Ziehau * without specific prior written permission. 1757a9c56bSSepherosa Ziehau * 1857a9c56bSSepherosa Ziehau * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 1957a9c56bSSepherosa Ziehau * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2057a9c56bSSepherosa Ziehau * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2157a9c56bSSepherosa Ziehau * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2257a9c56bSSepherosa Ziehau * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2357a9c56bSSepherosa Ziehau * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2457a9c56bSSepherosa Ziehau * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2557a9c56bSSepherosa Ziehau * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2657a9c56bSSepherosa Ziehau * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2757a9c56bSSepherosa Ziehau * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2857a9c56bSSepherosa Ziehau * SUCH DAMAGE. 2957a9c56bSSepherosa Ziehau * 3057a9c56bSSepherosa Ziehau * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $ 3157a9c56bSSepherosa Ziehau */ 3257a9c56bSSepherosa Ziehau 3357a9c56bSSepherosa Ziehau #ifndef _ARCH_INTR_MACHDEP_H_ 3457a9c56bSSepherosa Ziehau #define _ARCH_INTR_MACHDEP_H_ 3557a9c56bSSepherosa Ziehau 3657a9c56bSSepherosa Ziehau #ifndef LOCORE 3757a9c56bSSepherosa Ziehau #ifndef _SYS_TYPES_H_ 3857a9c56bSSepherosa Ziehau #include <sys/types.h> 3957a9c56bSSepherosa Ziehau #endif 4057a9c56bSSepherosa Ziehau #endif 4157a9c56bSSepherosa Ziehau 4257a9c56bSSepherosa Ziehau /* 4357a9c56bSSepherosa Ziehau * Low level interrupt code. 4457a9c56bSSepherosa Ziehau */ 4557a9c56bSSepherosa Ziehau 4657a9c56bSSepherosa Ziehau #ifdef _KERNEL 4757a9c56bSSepherosa Ziehau 4857a9c56bSSepherosa Ziehau #define IDT_OFFSET 0x20 4957a9c56bSSepherosa Ziehau #define IDT_OFFSET_SYSCALL 0x80 50*70f74b76SMatthew Dillon #define IDT_OFFSET_IPI 0xe0 5157a9c56bSSepherosa Ziehau 52451af8d9SSepherosa Ziehau #define IDT_HWI_VECTORS (IDT_OFFSET_IPI - IDT_OFFSET) 53451af8d9SSepherosa Ziehau 5457a9c56bSSepherosa Ziehau /* 5557a9c56bSSepherosa Ziehau * Local APIC TPR priority vector levels: 5657a9c56bSSepherosa Ziehau * 5757a9c56bSSepherosa Ziehau * 0xff (255) +-------------+ 58*70f74b76SMatthew Dillon * | | 15 (IPIs: Xcpustop, Xspuriousint) 5957a9c56bSSepherosa Ziehau * 0xf0 (240) +-------------+ 60*70f74b76SMatthew Dillon * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer, Xsniff) 6157a9c56bSSepherosa Ziehau * 0xe0 (224) +-------------+ 6257a9c56bSSepherosa Ziehau * | | 13 6357a9c56bSSepherosa Ziehau * 0xd0 (208) +-------------+ 6457a9c56bSSepherosa Ziehau * | | 12 6557a9c56bSSepherosa Ziehau * 0xc0 (192) +-------------+ 6657a9c56bSSepherosa Ziehau * | | 11 6757a9c56bSSepherosa Ziehau * 0xb0 (176) +-------------+ 6857a9c56bSSepherosa Ziehau * | | 10 6957a9c56bSSepherosa Ziehau * 0xa0 (160) +-------------+ 7057a9c56bSSepherosa Ziehau * | | 9 7157a9c56bSSepherosa Ziehau * 0x90 (144) +-------------+ 7257a9c56bSSepherosa Ziehau * | | 8 (syscall at 0x80) 7357a9c56bSSepherosa Ziehau * 0x80 (128) +-------------+ 7457a9c56bSSepherosa Ziehau * | | 7 7557a9c56bSSepherosa Ziehau * 0x70 (112) +-------------+ 7657a9c56bSSepherosa Ziehau * | | 6 7757a9c56bSSepherosa Ziehau * 0x60 (96) +-------------+ 7857a9c56bSSepherosa Ziehau * | | 5 7957a9c56bSSepherosa Ziehau * 0x50 (80) +-------------+ 8057a9c56bSSepherosa Ziehau * | | 4 8157a9c56bSSepherosa Ziehau * 0x40 (64) +-------------+ 8257a9c56bSSepherosa Ziehau * | | 3 8357a9c56bSSepherosa Ziehau * 0x30 (48) +-------------+ 8457a9c56bSSepherosa Ziehau * | | 2 (hardware INTs) 8557a9c56bSSepherosa Ziehau * 0x20 (32) +-------------+ 8657a9c56bSSepherosa Ziehau * | | 1 (exceptions, traps, etc.) 8757a9c56bSSepherosa Ziehau * 0x10 (16) +-------------+ 8857a9c56bSSepherosa Ziehau * | | 0 (exceptions, traps, etc.) 8957a9c56bSSepherosa Ziehau * 0x00 (0) +-------------+ 9057a9c56bSSepherosa Ziehau */ 9157a9c56bSSepherosa Ziehau #define TPR_STEP 0x10 9257a9c56bSSepherosa Ziehau 9357a9c56bSSepherosa Ziehau /* Local APIC Task Priority Register */ 9457a9c56bSSepherosa Ziehau #define TPR_IPI (IDT_OFFSET_IPI - 1) 9557a9c56bSSepherosa Ziehau 9657a9c56bSSepherosa Ziehau 9757a9c56bSSepherosa Ziehau /* 98*70f74b76SMatthew Dillon * IPI group1 9957a9c56bSSepherosa Ziehau */ 100*70f74b76SMatthew Dillon #define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI 10157a9c56bSSepherosa Ziehau 102*70f74b76SMatthew Dillon /* TLB shootdowns */ 103*70f74b76SMatthew Dillon #define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0) 10457a9c56bSSepherosa Ziehau 105*70f74b76SMatthew Dillon /* IPI group1 1: unused (was inter-cpu clock handling) */ 106*70f74b76SMatthew Dillon /* IPI group1 2: unused (was inter-cpu rendezvous) */ 107*70f74b76SMatthew Dillon 108*70f74b76SMatthew Dillon /* IPIQ rendezvous */ 109*70f74b76SMatthew Dillon #define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3) 110*70f74b76SMatthew Dillon 111*70f74b76SMatthew Dillon /* TIMER rendezvous */ 112*70f74b76SMatthew Dillon #define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4) 113*70f74b76SMatthew Dillon 114*70f74b76SMatthew Dillon /* SNIFF rendezvous */ 115*70f74b76SMatthew Dillon #define XSNIFF_OFFSET (IDT_OFFSET_IPIG1 + 5) 116*70f74b76SMatthew Dillon 117*70f74b76SMatthew Dillon /* IPI group1 6 ~ 15: unused */ 118*70f74b76SMatthew Dillon 119*70f74b76SMatthew Dillon 120*70f74b76SMatthew Dillon /* 121*70f74b76SMatthew Dillon * IPI group2 122*70f74b76SMatthew Dillon */ 123*70f74b76SMatthew Dillon #define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP) 124*70f74b76SMatthew Dillon 125*70f74b76SMatthew Dillon /* IPI to signal CPUs to stop and wait for another CPU to restart them */ 126*70f74b76SMatthew Dillon #define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0) 127*70f74b76SMatthew Dillon 128*70f74b76SMatthew Dillon /* IPI group2 1 ~ 14: unused */ 129*70f74b76SMatthew Dillon 130*70f74b76SMatthew Dillon /* NOTE: this vector MUST be xxxx1111 */ 131*70f74b76SMatthew Dillon #define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15) 13257a9c56bSSepherosa Ziehau 13357a9c56bSSepherosa Ziehau #ifndef LOCORE 13457a9c56bSSepherosa Ziehau 13557a9c56bSSepherosa Ziehau /* 13657a9c56bSSepherosa Ziehau * Type of the first (asm) part of an interrupt handler. 13757a9c56bSSepherosa Ziehau */ 13857a9c56bSSepherosa Ziehau typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 13957a9c56bSSepherosa Ziehau 14057a9c56bSSepherosa Ziehau #define IDTVEC(name) __CONCAT(X,name) 14157a9c56bSSepherosa Ziehau 1429a4bd8f3SSepherosa Ziehau inthand_t 1439a4bd8f3SSepherosa Ziehau Xspuriousint, /* handle APIC "spurious INTs" */ 144b8a64c88SSepherosa Ziehau Xtimer; /* handle per-cpu timer INT */ 1459a4bd8f3SSepherosa Ziehau 14657a9c56bSSepherosa Ziehau inthand_t 14757a9c56bSSepherosa Ziehau Xinvltlb, /* TLB shootdowns */ 14857a9c56bSSepherosa Ziehau Xcpustop, /* CPU stops & waits for another CPU to restart it */ 149e32d3244SMatthew Dillon Xipiq, /* handle lwkt_send_ipiq() requests */ 150e32d3244SMatthew Dillon Xsniff; /* sniff CPU */ 15157a9c56bSSepherosa Ziehau 15257a9c56bSSepherosa Ziehau #endif /* LOCORE */ 15357a9c56bSSepherosa Ziehau 15457a9c56bSSepherosa Ziehau #endif /* _KERNEL */ 15557a9c56bSSepherosa Ziehau 15657a9c56bSSepherosa Ziehau #endif /* !_ARCH_INTR_MACHDEP_H_ */ 157