1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "opt_clock.h" 54 #endif 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/eventhandler.h> 59 #include <sys/time.h> 60 #include <sys/kernel.h> 61 #include <sys/bus.h> 62 #include <sys/sysctl.h> 63 #include <sys/cons.h> 64 #include <sys/systimer.h> 65 #include <sys/globaldata.h> 66 #include <sys/thread2.h> 67 #include <sys/machintr.h> 68 #include <sys/interrupt.h> 69 70 #include <machine/clock.h> 71 #include <machine/cputypes.h> 72 #include <machine/frame.h> 73 #include <machine/ipl.h> 74 #include <machine/limits.h> 75 #include <machine/md_var.h> 76 #include <machine/psl.h> 77 #include <machine/segments.h> 78 #include <machine/smp.h> 79 #include <machine/specialreg.h> 80 #include <machine/intr_machdep.h> 81 82 #include <machine_base/apic/ioapic.h> 83 #include <machine_base/apic/ioapic_abi.h> 84 #include <machine_base/icu/icu.h> 85 #include <bus/isa/isa.h> 86 #include <bus/isa/rtc.h> 87 #include <machine_base/isa/timerreg.h> 88 89 static void i8254_restore(void); 90 static void resettodr_on_shutdown(void *arg __unused); 91 92 /* 93 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 94 * can use a simple formula for leap years. 95 */ 96 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 97 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 98 99 #ifndef TIMER_FREQ 100 #define TIMER_FREQ 1193182 101 #endif 102 103 static uint8_t i8254_walltimer_sel; 104 static uint16_t i8254_walltimer_cntr; 105 106 int adjkerntz; /* local offset from GMT in seconds */ 107 int disable_rtc_set; /* disable resettodr() if != 0 */ 108 int tsc_present; 109 int tsc_invariant; 110 int tsc_mpsync; 111 int64_t tsc_frequency; 112 int tsc_is_broken; 113 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 114 int timer0_running; 115 enum tstate { RELEASED, ACQUIRED }; 116 enum tstate timer0_state; 117 enum tstate timer1_state; 118 enum tstate timer2_state; 119 120 static int beeping = 0; 121 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 122 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 123 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 124 static int rtc_loaded; 125 126 static int i8254_cputimer_div; 127 128 static int i8254_nointr; 129 static int i8254_intr_disable = 1; 130 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 131 132 static struct callout sysbeepstop_ch; 133 134 static sysclock_t i8254_cputimer_count(void); 135 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 136 static void i8254_cputimer_destruct(struct cputimer *cputimer); 137 138 static struct cputimer i8254_cputimer = { 139 SLIST_ENTRY_INITIALIZER, 140 "i8254", 141 CPUTIMER_PRI_8254, 142 0, 143 i8254_cputimer_count, 144 cputimer_default_fromhz, 145 cputimer_default_fromus, 146 i8254_cputimer_construct, 147 i8254_cputimer_destruct, 148 TIMER_FREQ, 149 0, 0, 0 150 }; 151 152 static sysclock_t tsc_cputimer_count(void); 153 static void tsc_cputimer_construct(struct cputimer *, sysclock_t); 154 155 static struct cputimer tsc_cputimer = { 156 SLIST_ENTRY_INITIALIZER, 157 "TSC", 158 CPUTIMER_PRI_TSC, 159 CPUTIMER_TSC, 160 tsc_cputimer_count, 161 cputimer_default_fromhz, 162 cputimer_default_fromus, 163 tsc_cputimer_construct, 164 cputimer_default_destruct, 165 0, 166 0, 0, 0 167 }; 168 169 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 170 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 171 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 172 173 static struct cputimer_intr i8254_cputimer_intr = { 174 .freq = TIMER_FREQ, 175 .reload = i8254_intr_reload, 176 .enable = cputimer_intr_default_enable, 177 .config = i8254_intr_config, 178 .restart = cputimer_intr_default_restart, 179 .pmfixup = cputimer_intr_default_pmfixup, 180 .initclock = i8254_intr_initclock, 181 .next = SLIST_ENTRY_INITIALIZER, 182 .name = "i8254", 183 .type = CPUTIMER_INTR_8254, 184 .prio = CPUTIMER_INTR_PRIO_8254, 185 .caps = CPUTIMER_INTR_CAP_PS 186 }; 187 188 /* 189 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 190 * counting as of this interrupt. We use timer1 in free-running mode (not 191 * generating any interrupts) as our main counter. Each cpu has timeouts 192 * pending. 193 * 194 * This code is INTR_MPSAFE and may be called without the BGL held. 195 */ 196 static void 197 clkintr(void *dummy, void *frame_arg) 198 { 199 static sysclock_t sysclock_count; /* NOTE! Must be static */ 200 struct globaldata *gd = mycpu; 201 struct globaldata *gscan; 202 int n; 203 204 /* 205 * SWSTROBE mode is a one-shot, the timer is no longer running 206 */ 207 timer0_running = 0; 208 209 /* 210 * XXX the dispatcher needs work. right now we call systimer_intr() 211 * directly or via IPI for any cpu with systimers queued, which is 212 * usually *ALL* of them. We need to use the LAPIC timer for this. 213 */ 214 sysclock_count = sys_cputimer->count(); 215 for (n = 0; n < ncpus; ++n) { 216 gscan = globaldata_find(n); 217 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 218 continue; 219 if (gscan != gd) { 220 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 221 &sysclock_count, 1); 222 } else { 223 systimer_intr(&sysclock_count, 0, frame_arg); 224 } 225 } 226 } 227 228 229 /* 230 * NOTE! not MP safe. 231 */ 232 int 233 acquire_timer2(int mode) 234 { 235 if (timer2_state != RELEASED) 236 return (-1); 237 timer2_state = ACQUIRED; 238 239 /* 240 * This access to the timer registers is as atomic as possible 241 * because it is a single instruction. We could do better if we 242 * knew the rate. 243 */ 244 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 245 return (0); 246 } 247 248 int 249 release_timer2(void) 250 { 251 if (timer2_state != ACQUIRED) 252 return (-1); 253 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 254 timer2_state = RELEASED; 255 return (0); 256 } 257 258 #include "opt_ddb.h" 259 #ifdef DDB 260 #include <ddb/ddb.h> 261 262 DB_SHOW_COMMAND(rtc, rtc) 263 { 264 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 265 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 266 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 267 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 268 } 269 #endif /* DDB */ 270 271 /* 272 * Return the current cpu timer count as a 32 bit integer. 273 */ 274 static 275 sysclock_t 276 i8254_cputimer_count(void) 277 { 278 static __uint16_t cputimer_last; 279 __uint16_t count; 280 sysclock_t ret; 281 282 clock_lock(); 283 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 284 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 285 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 286 count = -count; /* -> countup */ 287 if (count < cputimer_last) /* rollover */ 288 i8254_cputimer.base += 0x00010000; 289 ret = i8254_cputimer.base | count; 290 cputimer_last = count; 291 clock_unlock(); 292 return(ret); 293 } 294 295 /* 296 * This function is called whenever the system timebase changes, allowing 297 * us to calculate what is needed to convert a system timebase tick 298 * into an 8254 tick for the interrupt timer. If we can convert to a 299 * simple shift, multiplication, or division, we do so. Otherwise 64 300 * bit arithmatic is required every time the interrupt timer is reloaded. 301 */ 302 static void 303 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 304 { 305 int freq; 306 int div; 307 308 /* 309 * Will a simple divide do the trick? 310 */ 311 div = (timer->freq + (cti->freq / 2)) / cti->freq; 312 freq = cti->freq * div; 313 314 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 315 i8254_cputimer_div = div; 316 else 317 i8254_cputimer_div = 0; 318 } 319 320 /* 321 * Reload for the next timeout. It is possible for the reload value 322 * to be 0 or negative, indicating that an immediate timer interrupt 323 * is desired. For now make the minimum 2 ticks. 324 * 325 * We may have to convert from the system timebase to the 8254 timebase. 326 */ 327 static void 328 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 329 { 330 __uint16_t count; 331 332 if (i8254_cputimer_div) 333 reload /= i8254_cputimer_div; 334 else 335 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 336 337 if ((int)reload < 2) 338 reload = 2; 339 340 clock_lock(); 341 if (timer0_running) { 342 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 343 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 344 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 345 if (reload < count) { 346 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 347 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 348 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 349 } 350 } else { 351 timer0_running = 1; 352 if (reload > 0xFFFF) 353 reload = 0; /* full count */ 354 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 355 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 356 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 357 } 358 clock_unlock(); 359 } 360 361 /* 362 * DELAY(usec) - Spin for the specified number of microseconds. 363 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 364 * but do a thread switch in the loop 365 * 366 * Relies on timer 1 counting down from (cputimer_freq / hz) 367 * Note: timer had better have been programmed before this is first used! 368 */ 369 static void 370 DODELAY(int n, int doswitch) 371 { 372 ssysclock_t delta, ticks_left; 373 sysclock_t prev_tick, tick; 374 375 #ifdef DELAYDEBUG 376 int getit_calls = 1; 377 int n1; 378 static int state = 0; 379 380 if (state == 0) { 381 state = 1; 382 for (n1 = 1; n1 <= 10000000; n1 *= 10) 383 DELAY(n1); 384 state = 2; 385 } 386 if (state == 1) 387 kprintf("DELAY(%d)...", n); 388 #endif 389 /* 390 * Guard against the timer being uninitialized if we are called 391 * early for console i/o. 392 */ 393 if (timer0_state == RELEASED) 394 i8254_restore(); 395 396 /* 397 * Read the counter first, so that the rest of the setup overhead is 398 * counted. Then calculate the number of hardware timer ticks 399 * required, rounding up to be sure we delay at least the requested 400 * number of microseconds. 401 */ 402 prev_tick = sys_cputimer->count(); 403 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 404 1000000; 405 406 /* 407 * Loop until done. 408 */ 409 while (ticks_left > 0) { 410 tick = sys_cputimer->count(); 411 #ifdef DELAYDEBUG 412 ++getit_calls; 413 #endif 414 delta = tick - prev_tick; 415 prev_tick = tick; 416 if (delta < 0) 417 delta = 0; 418 ticks_left -= delta; 419 if (doswitch && ticks_left > 0) 420 lwkt_switch(); 421 cpu_pause(); 422 } 423 #ifdef DELAYDEBUG 424 if (state == 1) 425 kprintf(" %d calls to getit() at %d usec each\n", 426 getit_calls, (n + 5) / getit_calls); 427 #endif 428 } 429 430 /* 431 * DELAY() never switches. 432 */ 433 void 434 DELAY(int n) 435 { 436 DODELAY(n, 0); 437 } 438 439 /* 440 * Returns non-zero if the specified time period has elapsed. Call 441 * first with last_clock set to 0. 442 */ 443 int 444 CHECKTIMEOUT(TOTALDELAY *tdd) 445 { 446 sysclock_t delta; 447 int us; 448 449 if (tdd->started == 0) { 450 if (timer0_state == RELEASED) 451 i8254_restore(); 452 tdd->last_clock = sys_cputimer->count(); 453 tdd->started = 1; 454 return(0); 455 } 456 delta = sys_cputimer->count() - tdd->last_clock; 457 us = (u_int64_t)delta * (u_int64_t)1000000 / 458 (u_int64_t)sys_cputimer->freq; 459 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 460 1000000; 461 tdd->us -= us; 462 return (tdd->us < 0); 463 } 464 465 466 /* 467 * DRIVERSLEEP() does not switch if called with a spinlock held or 468 * from a hard interrupt. 469 */ 470 void 471 DRIVERSLEEP(int usec) 472 { 473 globaldata_t gd = mycpu; 474 475 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) { 476 DODELAY(usec, 0); 477 } else { 478 DODELAY(usec, 1); 479 } 480 } 481 482 static void 483 sysbeepstop(void *chan) 484 { 485 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 486 beeping = 0; 487 release_timer2(); 488 } 489 490 int 491 sysbeep(int pitch, int period) 492 { 493 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 494 return(-1); 495 if (sysbeep_enable == 0) 496 return(-1); 497 /* 498 * Nobody else is using timer2, we do not need the clock lock 499 */ 500 outb(TIMER_CNTR2, pitch); 501 outb(TIMER_CNTR2, (pitch>>8)); 502 if (!beeping) { 503 /* enable counter2 output to speaker */ 504 outb(IO_PPI, inb(IO_PPI) | 3); 505 beeping = period; 506 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 507 } 508 return (0); 509 } 510 511 /* 512 * RTC support routines 513 */ 514 515 int 516 rtcin(int reg) 517 { 518 u_char val; 519 520 crit_enter(); 521 outb(IO_RTC, reg); 522 inb(0x84); 523 val = inb(IO_RTC + 1); 524 inb(0x84); 525 crit_exit(); 526 return (val); 527 } 528 529 static __inline void 530 writertc(u_char reg, u_char val) 531 { 532 crit_enter(); 533 inb(0x84); 534 outb(IO_RTC, reg); 535 inb(0x84); 536 outb(IO_RTC + 1, val); 537 inb(0x84); /* XXX work around wrong order in rtcin() */ 538 crit_exit(); 539 } 540 541 static __inline int 542 readrtc(int port) 543 { 544 return(bcd2bin(rtcin(port))); 545 } 546 547 static u_int 548 calibrate_clocks(void) 549 { 550 u_int64_t old_tsc; 551 u_int tot_count; 552 sysclock_t count, prev_count; 553 int sec, start_sec, timeout; 554 555 if (bootverbose) 556 kprintf("Calibrating clock(s) ...\n"); 557 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 558 goto fail; 559 timeout = 100000000; 560 561 /* Read the mc146818A seconds counter. */ 562 for (;;) { 563 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 564 sec = rtcin(RTC_SEC); 565 break; 566 } 567 if (--timeout == 0) 568 goto fail; 569 } 570 571 /* Wait for the mC146818A seconds counter to change. */ 572 start_sec = sec; 573 for (;;) { 574 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 575 sec = rtcin(RTC_SEC); 576 if (sec != start_sec) 577 break; 578 } 579 if (--timeout == 0) 580 goto fail; 581 } 582 583 /* Start keeping track of the i8254 counter. */ 584 prev_count = sys_cputimer->count(); 585 tot_count = 0; 586 587 if (tsc_present) 588 old_tsc = rdtsc(); 589 else 590 old_tsc = 0; /* shut up gcc */ 591 592 /* 593 * Wait for the mc146818A seconds counter to change. Read the i8254 594 * counter for each iteration since this is convenient and only 595 * costs a few usec of inaccuracy. The timing of the final reads 596 * of the counters almost matches the timing of the initial reads, 597 * so the main cause of inaccuracy is the varying latency from 598 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 599 * rtcin(RTC_SEC) that returns a changed seconds count. The 600 * maximum inaccuracy from this cause is < 10 usec on 486's. 601 */ 602 start_sec = sec; 603 for (;;) { 604 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 605 sec = rtcin(RTC_SEC); 606 count = sys_cputimer->count(); 607 tot_count += (int)(count - prev_count); 608 prev_count = count; 609 if (sec != start_sec) 610 break; 611 if (--timeout == 0) 612 goto fail; 613 } 614 615 /* 616 * Read the cpu cycle counter. The timing considerations are 617 * similar to those for the i8254 clock. 618 */ 619 if (tsc_present) { 620 tsc_frequency = rdtsc() - old_tsc; 621 } 622 623 if (tsc_present) { 624 kprintf("TSC%s clock: %llu Hz, ", 625 tsc_invariant ? " invariant" : "", 626 (long long)tsc_frequency); 627 } 628 kprintf("i8254 clock: %u Hz\n", tot_count); 629 return (tot_count); 630 631 fail: 632 kprintf("failed, using default i8254 clock of %u Hz\n", 633 i8254_cputimer.freq); 634 return (i8254_cputimer.freq); 635 } 636 637 static void 638 i8254_restore(void) 639 { 640 timer0_state = ACQUIRED; 641 642 clock_lock(); 643 644 /* 645 * Timer0 is our fine-grained variable clock interrupt 646 */ 647 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 648 outb(TIMER_CNTR0, 2); /* lsb */ 649 outb(TIMER_CNTR0, 0); /* msb */ 650 clock_unlock(); 651 652 if (!i8254_nointr) { 653 cputimer_intr_register(&i8254_cputimer_intr); 654 cputimer_intr_select(&i8254_cputimer_intr, 0); 655 } 656 657 /* 658 * Timer1 or timer2 is our free-running clock, but only if another 659 * has not been selected. 660 */ 661 cputimer_register(&i8254_cputimer); 662 cputimer_select(&i8254_cputimer, 0); 663 } 664 665 static void 666 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 667 { 668 int which; 669 670 /* 671 * Should we use timer 1 or timer 2 ? 672 */ 673 which = 0; 674 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 675 if (which != 1 && which != 2) 676 which = 2; 677 678 switch(which) { 679 case 1: 680 timer->name = "i8254_timer1"; 681 timer->type = CPUTIMER_8254_SEL1; 682 i8254_walltimer_sel = TIMER_SEL1; 683 i8254_walltimer_cntr = TIMER_CNTR1; 684 timer1_state = ACQUIRED; 685 break; 686 case 2: 687 timer->name = "i8254_timer2"; 688 timer->type = CPUTIMER_8254_SEL2; 689 i8254_walltimer_sel = TIMER_SEL2; 690 i8254_walltimer_cntr = TIMER_CNTR2; 691 timer2_state = ACQUIRED; 692 break; 693 } 694 695 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 696 697 clock_lock(); 698 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 699 outb(i8254_walltimer_cntr, 0); /* lsb */ 700 outb(i8254_walltimer_cntr, 0); /* msb */ 701 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 702 clock_unlock(); 703 } 704 705 static void 706 i8254_cputimer_destruct(struct cputimer *timer) 707 { 708 switch(timer->type) { 709 case CPUTIMER_8254_SEL1: 710 timer1_state = RELEASED; 711 break; 712 case CPUTIMER_8254_SEL2: 713 timer2_state = RELEASED; 714 break; 715 default: 716 break; 717 } 718 timer->type = 0; 719 } 720 721 static void 722 rtc_restore(void) 723 { 724 /* Restore all of the RTC's "status" (actually, control) registers. */ 725 writertc(RTC_STATUSB, RTCSB_24HR); 726 writertc(RTC_STATUSA, rtc_statusa); 727 writertc(RTC_STATUSB, rtc_statusb); 728 } 729 730 /* 731 * Restore all the timers. 732 * 733 * This function is called to resynchronize our core timekeeping after a 734 * long halt, e.g. from apm_default_resume() and friends. It is also 735 * called if after a BIOS call we have detected munging of the 8254. 736 * It is necessary because cputimer_count() counter's delta may have grown 737 * too large for nanouptime() and friends to handle, or (in the case of 8254 738 * munging) might cause the SYSTIMER code to prematurely trigger. 739 */ 740 void 741 timer_restore(void) 742 { 743 crit_enter(); 744 i8254_restore(); /* restore timer_freq and hz */ 745 rtc_restore(); /* reenable RTC interrupts */ 746 crit_exit(); 747 } 748 749 /* 750 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 751 */ 752 void 753 startrtclock(void) 754 { 755 u_int delta, freq; 756 757 /* 758 * Can we use the TSC? 759 */ 760 if (cpu_feature & CPUID_TSC) { 761 tsc_present = 1; 762 if ((cpu_vendor_id == CPU_VENDOR_INTEL || 763 cpu_vendor_id == CPU_VENDOR_AMD) && 764 cpu_exthigh >= 0x80000007) { 765 u_int regs[4]; 766 767 do_cpuid(0x80000007, regs); 768 if (regs[3] & 0x100) 769 tsc_invariant = 1; 770 } 771 } else { 772 tsc_present = 0; 773 } 774 775 /* 776 * Initial RTC state, don't do anything unexpected 777 */ 778 writertc(RTC_STATUSA, rtc_statusa); 779 writertc(RTC_STATUSB, RTCSB_24HR); 780 781 /* 782 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 783 * generate an interrupt, which we will ignore for now. 784 * 785 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 786 * (so it counts a full 2^16 and repeats). We will use this timer 787 * for our counting. 788 */ 789 i8254_restore(); 790 freq = calibrate_clocks(); 791 #ifdef CLK_CALIBRATION_LOOP 792 if (bootverbose) { 793 kprintf( 794 "Press a key on the console to abort clock calibration\n"); 795 while (cncheckc() == -1) 796 calibrate_clocks(); 797 } 798 #endif 799 800 /* 801 * Use the calibrated i8254 frequency if it seems reasonable. 802 * Otherwise use the default, and don't use the calibrated i586 803 * frequency. 804 */ 805 delta = freq > i8254_cputimer.freq ? 806 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 807 if (delta < i8254_cputimer.freq / 100) { 808 #ifndef CLK_USE_I8254_CALIBRATION 809 if (bootverbose) 810 kprintf( 811 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 812 freq = i8254_cputimer.freq; 813 #endif 814 /* 815 * NOTE: 816 * Interrupt timer's freq must be adjusted 817 * before we change the cuptimer's frequency. 818 */ 819 i8254_cputimer_intr.freq = freq; 820 cputimer_set_frequency(&i8254_cputimer, freq); 821 } else { 822 if (bootverbose) 823 kprintf( 824 "%d Hz differs from default of %d Hz by more than 1%%\n", 825 freq, i8254_cputimer.freq); 826 tsc_frequency = 0; 827 } 828 829 #ifndef CLK_USE_TSC_CALIBRATION 830 if (tsc_frequency != 0) { 831 if (bootverbose) 832 kprintf( 833 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 834 tsc_frequency = 0; 835 } 836 #endif 837 if (tsc_present && tsc_frequency == 0) { 838 /* 839 * Calibration of the i586 clock relative to the mc146818A 840 * clock failed. Do a less accurate calibration relative 841 * to the i8254 clock. 842 */ 843 u_int64_t old_tsc = rdtsc(); 844 845 DELAY(1000000); 846 tsc_frequency = rdtsc() - old_tsc; 847 #ifdef CLK_USE_TSC_CALIBRATION 848 if (bootverbose) { 849 kprintf("TSC clock: %llu Hz (Method B)\n", 850 tsc_frequency); 851 } 852 #endif 853 } 854 855 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 856 } 857 858 /* 859 * Sync the time of day back to the RTC on shutdown, but only if 860 * we have already loaded it and have not crashed. 861 */ 862 static void 863 resettodr_on_shutdown(void *arg __unused) 864 { 865 if (rtc_loaded && panicstr == NULL) { 866 resettodr(); 867 } 868 } 869 870 /* 871 * Initialize the time of day register, based on the time base which is, e.g. 872 * from a filesystem. 873 */ 874 void 875 inittodr(time_t base) 876 { 877 unsigned long sec, days; 878 int year, month; 879 int y, m; 880 struct timespec ts; 881 882 if (base) { 883 ts.tv_sec = base; 884 ts.tv_nsec = 0; 885 set_timeofday(&ts); 886 } 887 888 /* Look if we have a RTC present and the time is valid */ 889 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 890 goto wrong_time; 891 892 /* wait for time update to complete */ 893 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 894 crit_enter(); 895 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 896 crit_exit(); 897 crit_enter(); 898 } 899 900 days = 0; 901 #ifdef USE_RTC_CENTURY 902 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 903 #else 904 year = readrtc(RTC_YEAR) + 1900; 905 if (year < 1970) 906 year += 100; 907 #endif 908 if (year < 1970) { 909 crit_exit(); 910 goto wrong_time; 911 } 912 month = readrtc(RTC_MONTH); 913 for (m = 1; m < month; m++) 914 days += daysinmonth[m-1]; 915 if ((month > 2) && LEAPYEAR(year)) 916 days ++; 917 days += readrtc(RTC_DAY) - 1; 918 for (y = 1970; y < year; y++) 919 days += DAYSPERYEAR + LEAPYEAR(y); 920 sec = ((( days * 24 + 921 readrtc(RTC_HRS)) * 60 + 922 readrtc(RTC_MIN)) * 60 + 923 readrtc(RTC_SEC)); 924 /* sec now contains the number of seconds, since Jan 1 1970, 925 in the local time zone */ 926 927 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 928 929 y = (int)(time_second - sec); 930 if (y <= -2 || y >= 2) { 931 /* badly off, adjust it */ 932 ts.tv_sec = sec; 933 ts.tv_nsec = 0; 934 set_timeofday(&ts); 935 } 936 rtc_loaded = 1; 937 crit_exit(); 938 return; 939 940 wrong_time: 941 kprintf("Invalid time in real time clock.\n"); 942 kprintf("Check and reset the date immediately!\n"); 943 } 944 945 /* 946 * Write system time back to RTC 947 */ 948 void 949 resettodr(void) 950 { 951 struct timeval tv; 952 unsigned long tm; 953 int m; 954 int y; 955 956 if (disable_rtc_set) 957 return; 958 959 microtime(&tv); 960 tm = tv.tv_sec; 961 962 crit_enter(); 963 /* Disable RTC updates and interrupts. */ 964 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 965 966 /* Calculate local time to put in RTC */ 967 968 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 969 970 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 971 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 972 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 973 974 /* We have now the days since 01-01-1970 in tm */ 975 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 976 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 977 tm >= m; 978 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 979 tm -= m; 980 981 /* Now we have the years in y and the day-of-the-year in tm */ 982 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 983 #ifdef USE_RTC_CENTURY 984 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 985 #endif 986 for (m = 0; ; m++) { 987 int ml; 988 989 ml = daysinmonth[m]; 990 if (m == 1 && LEAPYEAR(y)) 991 ml++; 992 if (tm < ml) 993 break; 994 tm -= ml; 995 } 996 997 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 998 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 999 1000 /* Reenable RTC updates and interrupts. */ 1001 writertc(RTC_STATUSB, rtc_statusb); 1002 crit_exit(); 1003 } 1004 1005 static int 1006 i8254_ioapic_trial(int irq, struct cputimer_intr *cti) 1007 { 1008 sysclock_t base; 1009 long lastcnt; 1010 1011 /* 1012 * Following code assumes the 8254 is the cpu timer, 1013 * so make sure it is. 1014 */ 1015 KKASSERT(sys_cputimer == &i8254_cputimer); 1016 KKASSERT(cti == &i8254_cputimer_intr); 1017 1018 lastcnt = get_interrupt_counter(irq, mycpuid); 1019 1020 /* 1021 * Force an 8254 Timer0 interrupt and wait 1/100s for 1022 * it to happen, then see if we got it. 1023 */ 1024 kprintf("IOAPIC: testing 8254 interrupt delivery\n"); 1025 1026 i8254_intr_reload(cti, 2); 1027 base = sys_cputimer->count(); 1028 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1029 ; /* nothing */ 1030 1031 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0) 1032 return ENOENT; 1033 return 0; 1034 } 1035 1036 /* 1037 * Start both clocks running. DragonFly note: the stat clock is no longer 1038 * used. Instead, 8254 based systimers are used for all major clock 1039 * interrupts. 1040 */ 1041 static void 1042 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1043 { 1044 void *clkdesc = NULL; 1045 int irq = 0, mixed_mode = 0, error; 1046 1047 KKASSERT(mycpuid == 0); 1048 callout_init_mp(&sysbeepstop_ch); 1049 1050 if (!selected && i8254_intr_disable) 1051 goto nointr; 1052 1053 /* 1054 * The stat interrupt mask is different without the 1055 * statistics clock. Also, don't set the interrupt 1056 * flag which would normally cause the RTC to generate 1057 * interrupts. 1058 */ 1059 rtc_statusb = RTCSB_24HR; 1060 1061 /* Finish initializing 8254 timer 0. */ 1062 if (ioapic_enable) { 1063 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE, 1064 INTR_POLARITY_HIGH); 1065 if (irq < 0) { 1066 mixed_mode_setup: 1067 error = ioapic_conf_legacy_extint(0); 1068 if (!error) { 1069 irq = machintr_legacy_intr_find(0, 1070 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); 1071 if (irq < 0) 1072 error = ENOENT; 1073 } 1074 1075 if (error) { 1076 if (!selected) { 1077 kprintf("IOAPIC: setup mixed mode for " 1078 "irq 0 failed: %d\n", error); 1079 goto nointr; 1080 } else { 1081 panic("IOAPIC: setup mixed mode for " 1082 "irq 0 failed: %d\n", error); 1083 } 1084 } 1085 mixed_mode = 1; 1086 } 1087 clkdesc = register_int(irq, clkintr, NULL, "clk", 1088 NULL, 1089 INTR_EXCL | INTR_CLOCK | 1090 INTR_NOPOLL | INTR_MPSAFE | 1091 INTR_NOENTROPY, 0); 1092 } else { 1093 register_int(0, clkintr, NULL, "clk", NULL, 1094 INTR_EXCL | INTR_CLOCK | 1095 INTR_NOPOLL | INTR_MPSAFE | 1096 INTR_NOENTROPY, 0); 1097 } 1098 1099 /* Initialize RTC. */ 1100 writertc(RTC_STATUSA, rtc_statusa); 1101 writertc(RTC_STATUSB, RTCSB_24HR); 1102 1103 if (ioapic_enable) { 1104 error = i8254_ioapic_trial(irq, cti); 1105 if (error) { 1106 if (mixed_mode) { 1107 if (!selected) { 1108 kprintf("IOAPIC: mixed mode for irq %d " 1109 "trial failed: %d\n", 1110 irq, error); 1111 goto nointr; 1112 } else { 1113 panic("IOAPIC: mixed mode for irq %d " 1114 "trial failed: %d\n", irq, error); 1115 } 1116 } else { 1117 kprintf("IOAPIC: warning 8254 is not connected " 1118 "to the correct pin, try mixed mode\n"); 1119 unregister_int(clkdesc, 0); 1120 goto mixed_mode_setup; 1121 } 1122 } 1123 } 1124 return; 1125 1126 nointr: 1127 i8254_nointr = 1; /* don't try to register again */ 1128 cputimer_intr_deregister(cti); 1129 } 1130 1131 void 1132 setstatclockrate(int newhz) 1133 { 1134 if (newhz == RTC_PROFRATE) 1135 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1136 else 1137 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1138 writertc(RTC_STATUSA, rtc_statusa); 1139 } 1140 1141 #if 0 1142 static unsigned 1143 tsc_get_timecount(struct timecounter *tc) 1144 { 1145 return (rdtsc()); 1146 } 1147 #endif 1148 1149 #ifdef KERN_TIMESTAMP 1150 #define KERN_TIMESTAMP_SIZE 16384 1151 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1152 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1153 sizeof(tsc), "LU", "Kernel timestamps"); 1154 void 1155 _TSTMP(u_int32_t x) 1156 { 1157 static int i; 1158 1159 tsc[i] = (u_int32_t)rdtsc(); 1160 tsc[i+1] = x; 1161 i = i + 2; 1162 if (i >= KERN_TIMESTAMP_SIZE) 1163 i = 0; 1164 tsc[i] = 0; /* mark last entry */ 1165 } 1166 #endif /* KERN_TIMESTAMP */ 1167 1168 /* 1169 * 1170 */ 1171 1172 static int 1173 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1174 { 1175 sysclock_t count; 1176 __uint64_t tscval; 1177 char buf[32]; 1178 1179 crit_enter(); 1180 if (sys_cputimer == &i8254_cputimer) 1181 count = sys_cputimer->count(); 1182 else 1183 count = 0; 1184 if (tsc_present) 1185 tscval = rdtsc(); 1186 else 1187 tscval = 0; 1188 crit_exit(); 1189 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1190 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1191 } 1192 1193 static uint64_t tsc_mpsync_target; 1194 1195 static void 1196 tsc_mpsync_test_remote(void *arg __unused) 1197 { 1198 uint64_t tsc; 1199 1200 tsc = rdtsc(); 1201 if (tsc < tsc_mpsync_target) 1202 tsc_mpsync = 0; 1203 } 1204 1205 static void 1206 tsc_mpsync_test(void) 1207 { 1208 struct globaldata *gd = mycpu; 1209 uint64_t test_end, test_begin; 1210 u_int i; 1211 1212 if (!tsc_invariant) { 1213 /* Not even invariant TSC */ 1214 return; 1215 } 1216 1217 if (ncpus == 1) { 1218 /* Only one CPU */ 1219 tsc_mpsync = 1; 1220 return; 1221 } 1222 1223 if (cpu_vendor_id != CPU_VENDOR_INTEL) { 1224 /* XXX only Intel works */ 1225 return; 1226 } 1227 1228 kprintf("TSC testing MP synchronization ...\n"); 1229 tsc_mpsync = 1; 1230 1231 /* Run test for 100ms */ 1232 test_begin = rdtsc(); 1233 test_end = test_begin + (tsc_frequency / 10); 1234 1235 #define TSC_TEST_TRYMAX 1000000 /* Make sure we could stop */ 1236 1237 for (i = 0; i < TSC_TEST_TRYMAX; ++i) { 1238 struct lwkt_cpusync cs; 1239 1240 crit_enter(); 1241 lwkt_cpusync_init(&cs, gd->gd_other_cpus, 1242 tsc_mpsync_test_remote, NULL); 1243 lwkt_cpusync_interlock(&cs); 1244 tsc_mpsync_target = rdtsc(); 1245 cpu_mfence(); 1246 lwkt_cpusync_deinterlock(&cs); 1247 crit_exit(); 1248 1249 if (!tsc_mpsync) { 1250 kprintf("TSC is not MP synchronized @%u\n", i); 1251 break; 1252 } 1253 if (tsc_mpsync_target > test_end) 1254 break; 1255 } 1256 1257 #undef TSC_TEST_TRYMAX 1258 1259 if (tsc_mpsync) { 1260 if (tsc_mpsync_target == test_begin) { 1261 kprintf("TSC does not tick?!"); 1262 /* XXX disable TSC? */ 1263 tsc_invariant = 0; 1264 tsc_mpsync = 0; 1265 return; 1266 } 1267 1268 kprintf("TSC is MP synchronized"); 1269 if (bootverbose) 1270 kprintf(", after %u tries", i); 1271 kprintf("\n"); 1272 } 1273 } 1274 SYSINIT(tsc_mpsync, SI_BOOT2_FINISH_SMP, SI_ORDER_ANY, tsc_mpsync_test, NULL); 1275 1276 #define TSC_CPUTIMER_FREQMAX 128000000 /* 128Mhz */ 1277 1278 static int tsc_cputimer_shift; 1279 1280 static void 1281 tsc_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 1282 { 1283 timer->base = 0; 1284 timer->base = oldclock - tsc_cputimer_count(); 1285 } 1286 1287 static sysclock_t 1288 tsc_cputimer_count(void) 1289 { 1290 uint64_t tsc; 1291 1292 tsc = rdtsc(); 1293 tsc >>= tsc_cputimer_shift; 1294 1295 return (tsc + tsc_cputimer.base); 1296 } 1297 1298 static void 1299 tsc_cputimer_register(void) 1300 { 1301 uint64_t freq; 1302 int enable = 1; 1303 1304 if (!tsc_mpsync) 1305 return; 1306 1307 TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable); 1308 if (!enable) 1309 return; 1310 1311 freq = tsc_frequency; 1312 while (freq > TSC_CPUTIMER_FREQMAX) { 1313 freq >>= 1; 1314 ++tsc_cputimer_shift; 1315 } 1316 kprintf("TSC: cputimer freq %ju, shift %d\n", 1317 (uintmax_t)freq, tsc_cputimer_shift); 1318 1319 tsc_cputimer.freq = freq; 1320 1321 cputimer_register(&tsc_cputimer); 1322 cputimer_select(&tsc_cputimer, 0); 1323 } 1324 SYSINIT(tsc_cputimer_reg, SI_BOOT2_MACHDEP, SI_ORDER_ANY, 1325 tsc_cputimer_register, NULL); 1326 1327 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1328 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1329 "frequency"); 1330 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1331 0, 0, hw_i8254_timestamp, "A", ""); 1332 1333 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1334 &tsc_present, 0, "TSC Available"); 1335 SYSCTL_INT(_hw, OID_AUTO, tsc_invariant, CTLFLAG_RD, 1336 &tsc_invariant, 0, "Invariant TSC"); 1337 SYSCTL_INT(_hw, OID_AUTO, tsc_mpsync, CTLFLAG_RD, 1338 &tsc_mpsync, 0, "TSC is synchronized across CPUs"); 1339 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1340 &tsc_frequency, 0, "TSC Frequency"); 1341