1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "use_apm.h" 54 #include "opt_clock.h" 55 #endif 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/eventhandler.h> 60 #include <sys/time.h> 61 #include <sys/kernel.h> 62 #include <sys/bus.h> 63 #ifndef SMP 64 #include <sys/lock.h> 65 #endif 66 #include <sys/sysctl.h> 67 #include <sys/cons.h> 68 #include <sys/systimer.h> 69 #include <sys/globaldata.h> 70 #include <sys/thread2.h> 71 #include <sys/systimer.h> 72 #include <sys/machintr.h> 73 74 #include <machine/clock.h> 75 #ifdef CLK_CALIBRATION_LOOP 76 #endif 77 #include <machine/cputypes.h> 78 #include <machine/frame.h> 79 #include <machine/ipl.h> 80 #include <machine/limits.h> 81 #include <machine/md_var.h> 82 #include <machine/psl.h> 83 #include <machine/segments.h> 84 #include <machine/smp.h> 85 #include <machine/specialreg.h> 86 87 #include <machine_base/icu/icu.h> 88 #include <bus/isa/isa.h> 89 #include <bus/isa/rtc.h> 90 #include <machine_base/isa/timerreg.h> 91 92 #include <machine_base/isa/intr_machdep.h> 93 94 #ifdef APIC_IO 95 /* The interrupt triggered by the 8254 (timer) chip */ 96 int apic_8254_intr; 97 static void setup_8254_mixed_mode (void); 98 #endif 99 static void i8254_restore(void); 100 static void resettodr_on_shutdown(void *arg __unused); 101 102 /* 103 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 104 * can use a simple formula for leap years. 105 */ 106 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 107 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 108 109 #ifndef TIMER_FREQ 110 #define TIMER_FREQ 1193182 111 #endif 112 113 static uint8_t i8254_walltimer_sel; 114 static uint16_t i8254_walltimer_cntr; 115 116 int adjkerntz; /* local offset from GMT in seconds */ 117 int disable_rtc_set; /* disable resettodr() if != 0 */ 118 int statclock_disable = 1; /* we don't use the statclock right now */ 119 int tsc_present; 120 int64_t tsc_frequency; 121 int tsc_is_broken; 122 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 123 int timer0_running; 124 enum tstate { RELEASED, ACQUIRED }; 125 enum tstate timer0_state; 126 enum tstate timer1_state; 127 enum tstate timer2_state; 128 129 static int beeping = 0; 130 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 131 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 132 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 133 static int rtc_loaded; 134 135 static int i8254_cputimer_div; 136 137 static int i8254_nointr; 138 static int i8254_intr_disable = 0; 139 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 140 141 static struct callout sysbeepstop_ch; 142 143 static sysclock_t i8254_cputimer_count(void); 144 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 145 static void i8254_cputimer_destruct(struct cputimer *cputimer); 146 147 static struct cputimer i8254_cputimer = { 148 SLIST_ENTRY_INITIALIZER, 149 "i8254", 150 CPUTIMER_PRI_8254, 151 0, 152 i8254_cputimer_count, 153 cputimer_default_fromhz, 154 cputimer_default_fromus, 155 i8254_cputimer_construct, 156 i8254_cputimer_destruct, 157 TIMER_FREQ, 158 0, 0, 0 159 }; 160 161 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 162 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 163 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 164 165 static struct cputimer_intr i8254_cputimer_intr = { 166 .freq = TIMER_FREQ, 167 .reload = i8254_intr_reload, 168 .enable = cputimer_intr_default_enable, 169 .config = i8254_intr_config, 170 .restart = cputimer_intr_default_restart, 171 .pmfixup = cputimer_intr_default_pmfixup, 172 .initclock = i8254_intr_initclock, 173 .next = SLIST_ENTRY_INITIALIZER, 174 .name = "i8254", 175 .type = CPUTIMER_INTR_8254, 176 .prio = CPUTIMER_INTR_PRIO_8254, 177 .caps = CPUTIMER_INTR_CAP_PS 178 }; 179 180 /* 181 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 182 * counting as of this interrupt. We use timer1 in free-running mode (not 183 * generating any interrupts) as our main counter. Each cpu has timeouts 184 * pending. 185 * 186 * This code is INTR_MPSAFE and may be called without the BGL held. 187 */ 188 static void 189 clkintr(void *dummy, void *frame_arg) 190 { 191 static sysclock_t sysclock_count; /* NOTE! Must be static */ 192 struct globaldata *gd = mycpu; 193 #ifdef SMP 194 struct globaldata *gscan; 195 int n; 196 #endif 197 198 /* 199 * SWSTROBE mode is a one-shot, the timer is no longer running 200 */ 201 timer0_running = 0; 202 203 /* 204 * XXX the dispatcher needs work. right now we call systimer_intr() 205 * directly or via IPI for any cpu with systimers queued, which is 206 * usually *ALL* of them. We need to use the LAPIC timer for this. 207 */ 208 sysclock_count = sys_cputimer->count(); 209 #ifdef SMP 210 for (n = 0; n < ncpus; ++n) { 211 gscan = globaldata_find(n); 212 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 213 continue; 214 if (gscan != gd) { 215 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 216 &sysclock_count, 0); 217 } else { 218 systimer_intr(&sysclock_count, 0, frame_arg); 219 } 220 } 221 #else 222 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) 223 systimer_intr(&sysclock_count, 0, frame_arg); 224 #endif 225 } 226 227 228 /* 229 * NOTE! not MP safe. 230 */ 231 int 232 acquire_timer2(int mode) 233 { 234 if (timer2_state != RELEASED) 235 return (-1); 236 timer2_state = ACQUIRED; 237 238 /* 239 * This access to the timer registers is as atomic as possible 240 * because it is a single instruction. We could do better if we 241 * knew the rate. 242 */ 243 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 244 return (0); 245 } 246 247 int 248 release_timer2(void) 249 { 250 if (timer2_state != ACQUIRED) 251 return (-1); 252 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 253 timer2_state = RELEASED; 254 return (0); 255 } 256 257 /* 258 * This routine receives statistical clock interrupts from the RTC. 259 * As explained above, these occur at 128 interrupts per second. 260 * When profiling, we receive interrupts at a rate of 1024 Hz. 261 * 262 * This does not actually add as much overhead as it sounds, because 263 * when the statistical clock is active, the hardclock driver no longer 264 * needs to keep (inaccurate) statistics on its own. This decouples 265 * statistics gathering from scheduling interrupts. 266 * 267 * The RTC chip requires that we read status register C (RTC_INTR) 268 * to acknowledge an interrupt, before it will generate the next one. 269 * Under high interrupt load, rtcintr() can be indefinitely delayed and 270 * the clock can tick immediately after the read from RTC_INTR. In this 271 * case, the mc146818A interrupt signal will not drop for long enough 272 * to register with the 8259 PIC. If an interrupt is missed, the stat 273 * clock will halt, considerably degrading system performance. This is 274 * why we use 'while' rather than a more straightforward 'if' below. 275 * Stat clock ticks can still be lost, causing minor loss of accuracy 276 * in the statistics, but the stat clock will no longer stop. 277 */ 278 static void 279 rtcintr(void *dummy, void *frame) 280 { 281 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 282 ; 283 /* statclock(frame); no longer used */ 284 } 285 286 #include "opt_ddb.h" 287 #ifdef DDB 288 #include <ddb/ddb.h> 289 290 DB_SHOW_COMMAND(rtc, rtc) 291 { 292 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 293 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 294 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 295 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 296 } 297 #endif /* DDB */ 298 299 /* 300 * Return the current cpu timer count as a 32 bit integer. 301 */ 302 static 303 sysclock_t 304 i8254_cputimer_count(void) 305 { 306 static __uint16_t cputimer_last; 307 __uint16_t count; 308 sysclock_t ret; 309 310 clock_lock(); 311 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 312 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 313 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 314 count = -count; /* -> countup */ 315 if (count < cputimer_last) /* rollover */ 316 i8254_cputimer.base += 0x00010000; 317 ret = i8254_cputimer.base | count; 318 cputimer_last = count; 319 clock_unlock(); 320 return(ret); 321 } 322 323 /* 324 * This function is called whenever the system timebase changes, allowing 325 * us to calculate what is needed to convert a system timebase tick 326 * into an 8254 tick for the interrupt timer. If we can convert to a 327 * simple shift, multiplication, or division, we do so. Otherwise 64 328 * bit arithmatic is required every time the interrupt timer is reloaded. 329 */ 330 static void 331 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 332 { 333 int freq; 334 int div; 335 336 /* 337 * Will a simple divide do the trick? 338 */ 339 div = (timer->freq + (cti->freq / 2)) / cti->freq; 340 freq = cti->freq * div; 341 342 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 343 i8254_cputimer_div = div; 344 else 345 i8254_cputimer_div = 0; 346 } 347 348 /* 349 * Reload for the next timeout. It is possible for the reload value 350 * to be 0 or negative, indicating that an immediate timer interrupt 351 * is desired. For now make the minimum 2 ticks. 352 * 353 * We may have to convert from the system timebase to the 8254 timebase. 354 */ 355 static void 356 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 357 { 358 __uint16_t count; 359 360 if (i8254_cputimer_div) 361 reload /= i8254_cputimer_div; 362 else 363 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 364 365 if ((int)reload < 2) 366 reload = 2; 367 368 clock_lock(); 369 if (timer0_running) { 370 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 371 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 372 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 373 if (reload < count) { 374 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 375 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 376 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 377 } 378 } else { 379 timer0_running = 1; 380 if (reload > 0xFFFF) 381 reload = 0; /* full count */ 382 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 383 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 384 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 385 } 386 clock_unlock(); 387 } 388 389 /* 390 * DELAY(usec) - Spin for the specified number of microseconds. 391 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 392 * but do a thread switch in the loop 393 * 394 * Relies on timer 1 counting down from (cputimer_freq / hz) 395 * Note: timer had better have been programmed before this is first used! 396 */ 397 static void 398 DODELAY(int n, int doswitch) 399 { 400 int delta, prev_tick, tick, ticks_left; 401 402 #ifdef DELAYDEBUG 403 int getit_calls = 1; 404 int n1; 405 static int state = 0; 406 407 if (state == 0) { 408 state = 1; 409 for (n1 = 1; n1 <= 10000000; n1 *= 10) 410 DELAY(n1); 411 state = 2; 412 } 413 if (state == 1) 414 kprintf("DELAY(%d)...", n); 415 #endif 416 /* 417 * Guard against the timer being uninitialized if we are called 418 * early for console i/o. 419 */ 420 if (timer0_state == RELEASED) 421 i8254_restore(); 422 423 /* 424 * Read the counter first, so that the rest of the setup overhead is 425 * counted. Then calculate the number of hardware timer ticks 426 * required, rounding up to be sure we delay at least the requested 427 * number of microseconds. 428 */ 429 prev_tick = sys_cputimer->count(); 430 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 431 1000000; 432 433 /* 434 * Loop until done. 435 */ 436 while (ticks_left > 0) { 437 tick = sys_cputimer->count(); 438 #ifdef DELAYDEBUG 439 ++getit_calls; 440 #endif 441 delta = tick - prev_tick; 442 prev_tick = tick; 443 if (delta < 0) 444 delta = 0; 445 ticks_left -= delta; 446 if (doswitch && ticks_left > 0) 447 lwkt_switch(); 448 } 449 #ifdef DELAYDEBUG 450 if (state == 1) 451 kprintf(" %d calls to getit() at %d usec each\n", 452 getit_calls, (n + 5) / getit_calls); 453 #endif 454 } 455 456 void 457 DELAY(int n) 458 { 459 DODELAY(n, 0); 460 } 461 462 void 463 DRIVERSLEEP(int usec) 464 { 465 globaldata_t gd = mycpu; 466 467 if (gd->gd_intr_nesting_level || 468 gd->gd_spinlock_rd || 469 gd->gd_spinlocks_wr) { 470 DODELAY(usec, 0); 471 } else { 472 DODELAY(usec, 1); 473 } 474 } 475 476 static void 477 sysbeepstop(void *chan) 478 { 479 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 480 beeping = 0; 481 release_timer2(); 482 } 483 484 int 485 sysbeep(int pitch, int period) 486 { 487 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 488 return(-1); 489 /* 490 * Nobody else is using timer2, we do not need the clock lock 491 */ 492 outb(TIMER_CNTR2, pitch); 493 outb(TIMER_CNTR2, (pitch>>8)); 494 if (!beeping) { 495 /* enable counter2 output to speaker */ 496 outb(IO_PPI, inb(IO_PPI) | 3); 497 beeping = period; 498 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 499 } 500 return (0); 501 } 502 503 /* 504 * RTC support routines 505 */ 506 507 int 508 rtcin(int reg) 509 { 510 u_char val; 511 512 crit_enter(); 513 outb(IO_RTC, reg); 514 inb(0x84); 515 val = inb(IO_RTC + 1); 516 inb(0x84); 517 crit_exit(); 518 return (val); 519 } 520 521 static __inline void 522 writertc(u_char reg, u_char val) 523 { 524 crit_enter(); 525 inb(0x84); 526 outb(IO_RTC, reg); 527 inb(0x84); 528 outb(IO_RTC + 1, val); 529 inb(0x84); /* XXX work around wrong order in rtcin() */ 530 crit_exit(); 531 } 532 533 static __inline int 534 readrtc(int port) 535 { 536 return(bcd2bin(rtcin(port))); 537 } 538 539 static u_int 540 calibrate_clocks(void) 541 { 542 u_int64_t old_tsc; 543 u_int count, prev_count, tot_count; 544 int sec, start_sec, timeout; 545 546 if (bootverbose) 547 kprintf("Calibrating clock(s) ... "); 548 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 549 goto fail; 550 timeout = 100000000; 551 552 /* Read the mc146818A seconds counter. */ 553 for (;;) { 554 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 555 sec = rtcin(RTC_SEC); 556 break; 557 } 558 if (--timeout == 0) 559 goto fail; 560 } 561 562 /* Wait for the mC146818A seconds counter to change. */ 563 start_sec = sec; 564 for (;;) { 565 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 566 sec = rtcin(RTC_SEC); 567 if (sec != start_sec) 568 break; 569 } 570 if (--timeout == 0) 571 goto fail; 572 } 573 574 /* Start keeping track of the i8254 counter. */ 575 prev_count = sys_cputimer->count(); 576 tot_count = 0; 577 578 if (tsc_present) 579 old_tsc = rdtsc(); 580 else 581 old_tsc = 0; /* shut up gcc */ 582 583 /* 584 * Wait for the mc146818A seconds counter to change. Read the i8254 585 * counter for each iteration since this is convenient and only 586 * costs a few usec of inaccuracy. The timing of the final reads 587 * of the counters almost matches the timing of the initial reads, 588 * so the main cause of inaccuracy is the varying latency from 589 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 590 * rtcin(RTC_SEC) that returns a changed seconds count. The 591 * maximum inaccuracy from this cause is < 10 usec on 486's. 592 */ 593 start_sec = sec; 594 for (;;) { 595 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 596 sec = rtcin(RTC_SEC); 597 count = sys_cputimer->count(); 598 tot_count += (int)(count - prev_count); 599 prev_count = count; 600 if (sec != start_sec) 601 break; 602 if (--timeout == 0) 603 goto fail; 604 } 605 606 /* 607 * Read the cpu cycle counter. The timing considerations are 608 * similar to those for the i8254 clock. 609 */ 610 if (tsc_present) { 611 tsc_frequency = rdtsc() - old_tsc; 612 } 613 614 if (tsc_present) 615 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 616 kprintf("i8254 clock: %u Hz\n", tot_count); 617 return (tot_count); 618 619 fail: 620 kprintf("failed, using default i8254 clock of %u Hz\n", 621 i8254_cputimer.freq); 622 return (i8254_cputimer.freq); 623 } 624 625 static void 626 i8254_restore(void) 627 { 628 timer0_state = ACQUIRED; 629 630 clock_lock(); 631 632 /* 633 * Timer0 is our fine-grained variable clock interrupt 634 */ 635 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 636 outb(TIMER_CNTR0, 2); /* lsb */ 637 outb(TIMER_CNTR0, 0); /* msb */ 638 clock_unlock(); 639 640 if (!i8254_nointr) { 641 cputimer_intr_register(&i8254_cputimer_intr); 642 cputimer_intr_select(&i8254_cputimer_intr, 0); 643 } 644 645 /* 646 * Timer1 or timer2 is our free-running clock, but only if another 647 * has not been selected. 648 */ 649 cputimer_register(&i8254_cputimer); 650 cputimer_select(&i8254_cputimer, 0); 651 } 652 653 static void 654 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 655 { 656 int which; 657 658 /* 659 * Should we use timer 1 or timer 2 ? 660 */ 661 which = 0; 662 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 663 if (which != 1 && which != 2) 664 which = 2; 665 666 switch(which) { 667 case 1: 668 timer->name = "i8254_timer1"; 669 timer->type = CPUTIMER_8254_SEL1; 670 i8254_walltimer_sel = TIMER_SEL1; 671 i8254_walltimer_cntr = TIMER_CNTR1; 672 timer1_state = ACQUIRED; 673 break; 674 case 2: 675 timer->name = "i8254_timer2"; 676 timer->type = CPUTIMER_8254_SEL2; 677 i8254_walltimer_sel = TIMER_SEL2; 678 i8254_walltimer_cntr = TIMER_CNTR2; 679 timer2_state = ACQUIRED; 680 break; 681 } 682 683 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 684 685 clock_lock(); 686 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 687 outb(i8254_walltimer_cntr, 0); /* lsb */ 688 outb(i8254_walltimer_cntr, 0); /* msb */ 689 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 690 clock_unlock(); 691 } 692 693 static void 694 i8254_cputimer_destruct(struct cputimer *timer) 695 { 696 switch(timer->type) { 697 case CPUTIMER_8254_SEL1: 698 timer1_state = RELEASED; 699 break; 700 case CPUTIMER_8254_SEL2: 701 timer2_state = RELEASED; 702 break; 703 default: 704 break; 705 } 706 timer->type = 0; 707 } 708 709 static void 710 rtc_restore(void) 711 { 712 /* Restore all of the RTC's "status" (actually, control) registers. */ 713 writertc(RTC_STATUSB, RTCSB_24HR); 714 writertc(RTC_STATUSA, rtc_statusa); 715 writertc(RTC_STATUSB, rtc_statusb); 716 } 717 718 /* 719 * Restore all the timers. 720 * 721 * This function is called to resynchronize our core timekeeping after a 722 * long halt, e.g. from apm_default_resume() and friends. It is also 723 * called if after a BIOS call we have detected munging of the 8254. 724 * It is necessary because cputimer_count() counter's delta may have grown 725 * too large for nanouptime() and friends to handle, or (in the case of 8254 726 * munging) might cause the SYSTIMER code to prematurely trigger. 727 */ 728 void 729 timer_restore(void) 730 { 731 crit_enter(); 732 i8254_restore(); /* restore timer_freq and hz */ 733 rtc_restore(); /* reenable RTC interrupts */ 734 crit_exit(); 735 } 736 737 /* 738 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 739 */ 740 void 741 startrtclock(void) 742 { 743 u_int delta, freq; 744 745 /* 746 * Can we use the TSC? 747 */ 748 if (cpu_feature & CPUID_TSC) 749 tsc_present = 1; 750 else 751 tsc_present = 0; 752 753 /* 754 * Initial RTC state, don't do anything unexpected 755 */ 756 writertc(RTC_STATUSA, rtc_statusa); 757 writertc(RTC_STATUSB, RTCSB_24HR); 758 759 /* 760 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 761 * generate an interrupt, which we will ignore for now. 762 * 763 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 764 * (so it counts a full 2^16 and repeats). We will use this timer 765 * for our counting. 766 */ 767 i8254_restore(); 768 freq = calibrate_clocks(); 769 #ifdef CLK_CALIBRATION_LOOP 770 if (bootverbose) { 771 kprintf( 772 "Press a key on the console to abort clock calibration\n"); 773 while (cncheckc() == -1) 774 calibrate_clocks(); 775 } 776 #endif 777 778 /* 779 * Use the calibrated i8254 frequency if it seems reasonable. 780 * Otherwise use the default, and don't use the calibrated i586 781 * frequency. 782 */ 783 delta = freq > i8254_cputimer.freq ? 784 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 785 if (delta < i8254_cputimer.freq / 100) { 786 #ifndef CLK_USE_I8254_CALIBRATION 787 if (bootverbose) 788 kprintf( 789 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 790 freq = i8254_cputimer.freq; 791 #endif 792 /* 793 * NOTE: 794 * Interrupt timer's freq must be adjusted 795 * before we change the cuptimer's frequency. 796 */ 797 i8254_cputimer_intr.freq = freq; 798 cputimer_set_frequency(&i8254_cputimer, freq); 799 } else { 800 if (bootverbose) 801 kprintf( 802 "%d Hz differs from default of %d Hz by more than 1%%\n", 803 freq, i8254_cputimer.freq); 804 tsc_frequency = 0; 805 } 806 807 #ifndef CLK_USE_TSC_CALIBRATION 808 if (tsc_frequency != 0) { 809 if (bootverbose) 810 kprintf( 811 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 812 tsc_frequency = 0; 813 } 814 #endif 815 if (tsc_present && tsc_frequency == 0) { 816 /* 817 * Calibration of the i586 clock relative to the mc146818A 818 * clock failed. Do a less accurate calibration relative 819 * to the i8254 clock. 820 */ 821 u_int64_t old_tsc = rdtsc(); 822 823 DELAY(1000000); 824 tsc_frequency = rdtsc() - old_tsc; 825 #ifdef CLK_USE_TSC_CALIBRATION 826 if (bootverbose) { 827 kprintf("TSC clock: %llu Hz (Method B)\n", 828 tsc_frequency); 829 } 830 #endif 831 } 832 833 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 834 835 #if !defined(SMP) 836 /* 837 * We can not use the TSC in SMP mode, until we figure out a 838 * cheap (impossible), reliable and precise (yeah right!) way 839 * to synchronize the TSCs of all the CPUs. 840 * Curse Intel for leaving the counter out of the I/O APIC. 841 */ 842 843 #if NAPM > 0 844 /* 845 * We can not use the TSC if we support APM. Precise timekeeping 846 * on an APM'ed machine is at best a fools pursuit, since 847 * any and all of the time spent in various SMM code can't 848 * be reliably accounted for. Reading the RTC is your only 849 * source of reliable time info. The i8254 looses too of course 850 * but we need to have some kind of time... 851 * We don't know at this point whether APM is going to be used 852 * or not, nor when it might be activated. Play it safe. 853 */ 854 return; 855 #endif /* NAPM > 0 */ 856 857 #endif /* !defined(SMP) */ 858 } 859 860 /* 861 * Sync the time of day back to the RTC on shutdown, but only if 862 * we have already loaded it and have not crashed. 863 */ 864 static void 865 resettodr_on_shutdown(void *arg __unused) 866 { 867 if (rtc_loaded && panicstr == NULL) { 868 resettodr(); 869 } 870 } 871 872 /* 873 * Initialize the time of day register, based on the time base which is, e.g. 874 * from a filesystem. 875 */ 876 void 877 inittodr(time_t base) 878 { 879 unsigned long sec, days; 880 int yd; 881 int year, month; 882 int y, m; 883 struct timespec ts; 884 885 if (base) { 886 ts.tv_sec = base; 887 ts.tv_nsec = 0; 888 set_timeofday(&ts); 889 } 890 891 /* Look if we have a RTC present and the time is valid */ 892 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 893 goto wrong_time; 894 895 /* wait for time update to complete */ 896 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 897 crit_enter(); 898 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 899 crit_exit(); 900 crit_enter(); 901 } 902 903 days = 0; 904 #ifdef USE_RTC_CENTURY 905 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 906 #else 907 year = readrtc(RTC_YEAR) + 1900; 908 if (year < 1970) 909 year += 100; 910 #endif 911 if (year < 1970) { 912 crit_exit(); 913 goto wrong_time; 914 } 915 month = readrtc(RTC_MONTH); 916 for (m = 1; m < month; m++) 917 days += daysinmonth[m-1]; 918 if ((month > 2) && LEAPYEAR(year)) 919 days ++; 920 days += readrtc(RTC_DAY) - 1; 921 yd = days; 922 for (y = 1970; y < year; y++) 923 days += DAYSPERYEAR + LEAPYEAR(y); 924 sec = ((( days * 24 + 925 readrtc(RTC_HRS)) * 60 + 926 readrtc(RTC_MIN)) * 60 + 927 readrtc(RTC_SEC)); 928 /* sec now contains the number of seconds, since Jan 1 1970, 929 in the local time zone */ 930 931 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 932 933 y = time_second - sec; 934 if (y <= -2 || y >= 2) { 935 /* badly off, adjust it */ 936 ts.tv_sec = sec; 937 ts.tv_nsec = 0; 938 set_timeofday(&ts); 939 } 940 rtc_loaded = 1; 941 crit_exit(); 942 return; 943 944 wrong_time: 945 kprintf("Invalid time in real time clock.\n"); 946 kprintf("Check and reset the date immediately!\n"); 947 } 948 949 /* 950 * Write system time back to RTC 951 */ 952 void 953 resettodr(void) 954 { 955 struct timeval tv; 956 unsigned long tm; 957 int m; 958 int y; 959 960 if (disable_rtc_set) 961 return; 962 963 microtime(&tv); 964 tm = tv.tv_sec; 965 966 crit_enter(); 967 /* Disable RTC updates and interrupts. */ 968 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 969 970 /* Calculate local time to put in RTC */ 971 972 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 973 974 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 975 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 976 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 977 978 /* We have now the days since 01-01-1970 in tm */ 979 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 980 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 981 tm >= m; 982 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 983 tm -= m; 984 985 /* Now we have the years in y and the day-of-the-year in tm */ 986 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 987 #ifdef USE_RTC_CENTURY 988 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 989 #endif 990 for (m = 0; ; m++) { 991 int ml; 992 993 ml = daysinmonth[m]; 994 if (m == 1 && LEAPYEAR(y)) 995 ml++; 996 if (tm < ml) 997 break; 998 tm -= ml; 999 } 1000 1001 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1002 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1003 1004 /* Reenable RTC updates and interrupts. */ 1005 writertc(RTC_STATUSB, rtc_statusb); 1006 crit_exit(); 1007 } 1008 1009 1010 /* 1011 * Start both clocks running. DragonFly note: the stat clock is no longer 1012 * used. Instead, 8254 based systimers are used for all major clock 1013 * interrupts. statclock_disable is set by default. 1014 */ 1015 static void 1016 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1017 { 1018 int diag; 1019 #ifdef APIC_IO 1020 int apic_8254_trial; 1021 void *clkdesc; 1022 #endif /* APIC_IO */ 1023 1024 callout_init(&sysbeepstop_ch); 1025 1026 if (!selected && i8254_intr_disable) { 1027 i8254_nointr = 1; /* don't try to register again */ 1028 cputimer_intr_deregister(cti); 1029 return; 1030 } 1031 1032 if (statclock_disable) { 1033 /* 1034 * The stat interrupt mask is different without the 1035 * statistics clock. Also, don't set the interrupt 1036 * flag which would normally cause the RTC to generate 1037 * interrupts. 1038 */ 1039 rtc_statusb = RTCSB_24HR; 1040 } else { 1041 /* Setting stathz to nonzero early helps avoid races. */ 1042 stathz = RTC_NOPROFRATE; 1043 profhz = RTC_PROFRATE; 1044 } 1045 1046 /* Finish initializing 8253 timer 0. */ 1047 #ifdef APIC_IO 1048 1049 apic_8254_intr = isa_apic_irq(0); 1050 apic_8254_trial = 0; 1051 if (apic_8254_intr >= 0 ) { 1052 if (apic_int_type(0, 0) == 3) 1053 apic_8254_trial = 1; 1054 } else { 1055 /* look for ExtInt on pin 0 */ 1056 if (apic_int_type(0, 0) == 3) { 1057 apic_8254_intr = apic_irq(0, 0); 1058 setup_8254_mixed_mode(); 1059 } else 1060 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1061 } 1062 1063 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk", 1064 NULL, 1065 INTR_EXCL | INTR_FAST | 1066 INTR_NOPOLL | INTR_MPSAFE | 1067 INTR_NOENTROPY); 1068 machintr_intren(apic_8254_intr); 1069 1070 #else /* APIC_IO */ 1071 1072 register_int(0, clkintr, NULL, "clk", NULL, 1073 INTR_EXCL | INTR_FAST | 1074 INTR_NOPOLL | INTR_MPSAFE | 1075 INTR_NOENTROPY); 1076 machintr_intren(ICU_IRQ0); 1077 1078 #endif /* APIC_IO */ 1079 1080 /* Initialize RTC. */ 1081 writertc(RTC_STATUSA, rtc_statusa); 1082 writertc(RTC_STATUSB, RTCSB_24HR); 1083 1084 if (statclock_disable == 0) { 1085 diag = rtcin(RTC_DIAG); 1086 if (diag != 0) 1087 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1088 1089 #ifdef APIC_IO 1090 if (isa_apic_irq(8) != 8) 1091 panic("APIC RTC != 8"); 1092 #endif /* APIC_IO */ 1093 1094 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL, 1095 INTR_EXCL | INTR_FAST | INTR_NOPOLL | 1096 INTR_NOENTROPY); 1097 machintr_intren(8); 1098 1099 writertc(RTC_STATUSB, rtc_statusb); 1100 } 1101 1102 #ifdef APIC_IO 1103 if (apic_8254_trial) { 1104 sysclock_t base; 1105 long lastcnt; 1106 1107 /* 1108 * Following code assumes the 8254 is the cpu timer, 1109 * so make sure it is. 1110 */ 1111 KKASSERT(sys_cputimer == &i8254_cputimer); 1112 KKASSERT(cti == &i8254_cputimer_intr); 1113 1114 lastcnt = get_interrupt_counter(apic_8254_intr); 1115 1116 /* 1117 * Force an 8254 Timer0 interrupt and wait 1/100s for 1118 * it to happen, then see if we got it. 1119 */ 1120 kprintf("APIC_IO: Testing 8254 interrupt delivery\n"); 1121 i8254_intr_reload(cti, 2); 1122 base = sys_cputimer->count(); 1123 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1124 ; /* nothing */ 1125 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) { 1126 /* 1127 * The MP table is broken. 1128 * The 8254 was not connected to the specified pin 1129 * on the IO APIC. 1130 * Workaround: Limited variant of mixed mode. 1131 */ 1132 machintr_intrdis(apic_8254_intr); 1133 unregister_int(clkdesc); 1134 kprintf("APIC_IO: Broken MP table detected: " 1135 "8254 is not connected to " 1136 "IOAPIC #%d intpin %d\n", 1137 int_to_apicintpin[apic_8254_intr].ioapic, 1138 int_to_apicintpin[apic_8254_intr].int_pin); 1139 /* 1140 * Revoke current ISA IRQ 0 assignment and 1141 * configure a fallback interrupt routing from 1142 * the 8254 Timer via the 8259 PIC to the 1143 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1144 * We reuse the low level interrupt handler number. 1145 */ 1146 if (apic_irq(0, 0) < 0) { 1147 revoke_apic_irq(apic_8254_intr); 1148 assign_apic_irq(0, 0, apic_8254_intr); 1149 } 1150 apic_8254_intr = apic_irq(0, 0); 1151 setup_8254_mixed_mode(); 1152 register_int(apic_8254_intr, clkintr, NULL, "clk", 1153 NULL, 1154 INTR_EXCL | INTR_FAST | 1155 INTR_NOPOLL | INTR_MPSAFE | 1156 INTR_NOENTROPY); 1157 machintr_intren(apic_8254_intr); 1158 } 1159 } 1160 if (apic_int_type(0, 0) != 3 || 1161 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1162 int_to_apicintpin[apic_8254_intr].int_pin != 0) { 1163 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1164 int_to_apicintpin[apic_8254_intr].ioapic, 1165 int_to_apicintpin[apic_8254_intr].int_pin); 1166 } else { 1167 kprintf("APIC_IO: " 1168 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1169 } 1170 #endif 1171 } 1172 1173 #ifdef APIC_IO 1174 1175 static void 1176 setup_8254_mixed_mode(void) 1177 { 1178 /* 1179 * Allow 8254 timer to INTerrupt 8259: 1180 * re-initialize master 8259: 1181 * reset; prog 4 bytes, single ICU, edge triggered 1182 */ 1183 outb(IO_ICU1, 0x13); 1184 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */ 1185 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1186 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1187 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1188 1189 /* program IO APIC for type 3 INT on INT0 */ 1190 if (ext_int_setup(0, 0) < 0) 1191 panic("8254 redirect via APIC pin0 impossible!"); 1192 } 1193 #endif 1194 1195 void 1196 setstatclockrate(int newhz) 1197 { 1198 if (newhz == RTC_PROFRATE) 1199 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1200 else 1201 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1202 writertc(RTC_STATUSA, rtc_statusa); 1203 } 1204 1205 #if 0 1206 static unsigned 1207 tsc_get_timecount(struct timecounter *tc) 1208 { 1209 return (rdtsc()); 1210 } 1211 #endif 1212 1213 #ifdef KERN_TIMESTAMP 1214 #define KERN_TIMESTAMP_SIZE 16384 1215 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1216 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1217 sizeof(tsc), "LU", "Kernel timestamps"); 1218 void 1219 _TSTMP(u_int32_t x) 1220 { 1221 static int i; 1222 1223 tsc[i] = (u_int32_t)rdtsc(); 1224 tsc[i+1] = x; 1225 i = i + 2; 1226 if (i >= KERN_TIMESTAMP_SIZE) 1227 i = 0; 1228 tsc[i] = 0; /* mark last entry */ 1229 } 1230 #endif /* KERN_TIMESTAMP */ 1231 1232 /* 1233 * 1234 */ 1235 1236 static int 1237 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1238 { 1239 sysclock_t count; 1240 __uint64_t tscval; 1241 char buf[32]; 1242 1243 crit_enter(); 1244 if (sys_cputimer == &i8254_cputimer) 1245 count = sys_cputimer->count(); 1246 else 1247 count = 0; 1248 if (tsc_present) 1249 tscval = rdtsc(); 1250 else 1251 tscval = 0; 1252 crit_exit(); 1253 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1254 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1255 } 1256 1257 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1258 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1259 "frequency"); 1260 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1261 0, 0, hw_i8254_timestamp, "A", ""); 1262 1263 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1264 &tsc_present, 0, "TSC Available"); 1265 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1266 &tsc_frequency, 0, "TSC Frequency"); 1267 1268