1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "use_apm.h" 54 #include "opt_clock.h" 55 #endif 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/eventhandler.h> 60 #include <sys/time.h> 61 #include <sys/kernel.h> 62 #include <sys/bus.h> 63 #include <sys/sysctl.h> 64 #include <sys/cons.h> 65 #include <sys/systimer.h> 66 #include <sys/globaldata.h> 67 #include <sys/thread2.h> 68 #include <sys/systimer.h> 69 #include <sys/machintr.h> 70 #include <sys/interrupt.h> 71 72 #include <machine/clock.h> 73 #ifdef CLK_CALIBRATION_LOOP 74 #endif 75 #include <machine/cputypes.h> 76 #include <machine/frame.h> 77 #include <machine/ipl.h> 78 #include <machine/limits.h> 79 #include <machine/md_var.h> 80 #include <machine/psl.h> 81 #include <machine/segments.h> 82 #include <machine/smp.h> 83 #include <machine/specialreg.h> 84 #include <machine/intr_machdep.h> 85 86 #include <machine_base/apic/ioapic.h> 87 #include <machine_base/apic/ioapic_abi.h> 88 #include <machine_base/icu/icu.h> 89 #include <bus/isa/isa.h> 90 #include <bus/isa/rtc.h> 91 #include <machine_base/isa/timerreg.h> 92 93 static void i8254_restore(void); 94 static void resettodr_on_shutdown(void *arg __unused); 95 96 /* 97 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 98 * can use a simple formula for leap years. 99 */ 100 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 101 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 102 103 #ifndef TIMER_FREQ 104 #define TIMER_FREQ 1193182 105 #endif 106 107 static uint8_t i8254_walltimer_sel; 108 static uint16_t i8254_walltimer_cntr; 109 110 int adjkerntz; /* local offset from GMT in seconds */ 111 int disable_rtc_set; /* disable resettodr() if != 0 */ 112 int tsc_present; 113 int64_t tsc_frequency; 114 int tsc_is_broken; 115 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 116 int timer0_running; 117 enum tstate { RELEASED, ACQUIRED }; 118 enum tstate timer0_state; 119 enum tstate timer1_state; 120 enum tstate timer2_state; 121 122 static int beeping = 0; 123 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 124 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 125 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 126 static int rtc_loaded; 127 128 static int i8254_cputimer_div; 129 130 static int i8254_nointr; 131 static int i8254_intr_disable = 1; 132 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 133 134 static struct callout sysbeepstop_ch; 135 136 static sysclock_t i8254_cputimer_count(void); 137 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 138 static void i8254_cputimer_destruct(struct cputimer *cputimer); 139 140 static struct cputimer i8254_cputimer = { 141 SLIST_ENTRY_INITIALIZER, 142 "i8254", 143 CPUTIMER_PRI_8254, 144 0, 145 i8254_cputimer_count, 146 cputimer_default_fromhz, 147 cputimer_default_fromus, 148 i8254_cputimer_construct, 149 i8254_cputimer_destruct, 150 TIMER_FREQ, 151 0, 0, 0 152 }; 153 154 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 155 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 156 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 157 158 static struct cputimer_intr i8254_cputimer_intr = { 159 .freq = TIMER_FREQ, 160 .reload = i8254_intr_reload, 161 .enable = cputimer_intr_default_enable, 162 .config = i8254_intr_config, 163 .restart = cputimer_intr_default_restart, 164 .pmfixup = cputimer_intr_default_pmfixup, 165 .initclock = i8254_intr_initclock, 166 .next = SLIST_ENTRY_INITIALIZER, 167 .name = "i8254", 168 .type = CPUTIMER_INTR_8254, 169 .prio = CPUTIMER_INTR_PRIO_8254, 170 .caps = CPUTIMER_INTR_CAP_PS 171 }; 172 173 /* 174 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 175 * counting as of this interrupt. We use timer1 in free-running mode (not 176 * generating any interrupts) as our main counter. Each cpu has timeouts 177 * pending. 178 * 179 * This code is INTR_MPSAFE and may be called without the BGL held. 180 */ 181 static void 182 clkintr(void *dummy, void *frame_arg) 183 { 184 static sysclock_t sysclock_count; /* NOTE! Must be static */ 185 struct globaldata *gd = mycpu; 186 struct globaldata *gscan; 187 int n; 188 189 /* 190 * SWSTROBE mode is a one-shot, the timer is no longer running 191 */ 192 timer0_running = 0; 193 194 /* 195 * XXX the dispatcher needs work. right now we call systimer_intr() 196 * directly or via IPI for any cpu with systimers queued, which is 197 * usually *ALL* of them. We need to use the LAPIC timer for this. 198 */ 199 sysclock_count = sys_cputimer->count(); 200 for (n = 0; n < ncpus; ++n) { 201 gscan = globaldata_find(n); 202 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 203 continue; 204 if (gscan != gd) { 205 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 206 &sysclock_count, 1); 207 } else { 208 systimer_intr(&sysclock_count, 0, frame_arg); 209 } 210 } 211 } 212 213 214 /* 215 * NOTE! not MP safe. 216 */ 217 int 218 acquire_timer2(int mode) 219 { 220 if (timer2_state != RELEASED) 221 return (-1); 222 timer2_state = ACQUIRED; 223 224 /* 225 * This access to the timer registers is as atomic as possible 226 * because it is a single instruction. We could do better if we 227 * knew the rate. 228 */ 229 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 230 return (0); 231 } 232 233 int 234 release_timer2(void) 235 { 236 if (timer2_state != ACQUIRED) 237 return (-1); 238 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 239 timer2_state = RELEASED; 240 return (0); 241 } 242 243 #include "opt_ddb.h" 244 #ifdef DDB 245 #include <ddb/ddb.h> 246 247 DB_SHOW_COMMAND(rtc, rtc) 248 { 249 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 250 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 251 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 252 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 253 } 254 #endif /* DDB */ 255 256 /* 257 * Return the current cpu timer count as a 32 bit integer. 258 */ 259 static 260 sysclock_t 261 i8254_cputimer_count(void) 262 { 263 static __uint16_t cputimer_last; 264 __uint16_t count; 265 sysclock_t ret; 266 267 clock_lock(); 268 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 269 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 270 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 271 count = -count; /* -> countup */ 272 if (count < cputimer_last) /* rollover */ 273 i8254_cputimer.base += 0x00010000; 274 ret = i8254_cputimer.base | count; 275 cputimer_last = count; 276 clock_unlock(); 277 return(ret); 278 } 279 280 /* 281 * This function is called whenever the system timebase changes, allowing 282 * us to calculate what is needed to convert a system timebase tick 283 * into an 8254 tick for the interrupt timer. If we can convert to a 284 * simple shift, multiplication, or division, we do so. Otherwise 64 285 * bit arithmatic is required every time the interrupt timer is reloaded. 286 */ 287 static void 288 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 289 { 290 int freq; 291 int div; 292 293 /* 294 * Will a simple divide do the trick? 295 */ 296 div = (timer->freq + (cti->freq / 2)) / cti->freq; 297 freq = cti->freq * div; 298 299 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 300 i8254_cputimer_div = div; 301 else 302 i8254_cputimer_div = 0; 303 } 304 305 /* 306 * Reload for the next timeout. It is possible for the reload value 307 * to be 0 or negative, indicating that an immediate timer interrupt 308 * is desired. For now make the minimum 2 ticks. 309 * 310 * We may have to convert from the system timebase to the 8254 timebase. 311 */ 312 static void 313 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 314 { 315 __uint16_t count; 316 317 if (i8254_cputimer_div) 318 reload /= i8254_cputimer_div; 319 else 320 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 321 322 if ((int)reload < 2) 323 reload = 2; 324 325 clock_lock(); 326 if (timer0_running) { 327 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 328 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 329 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 330 if (reload < count) { 331 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 332 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 333 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 334 } 335 } else { 336 timer0_running = 1; 337 if (reload > 0xFFFF) 338 reload = 0; /* full count */ 339 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 340 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 341 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 342 } 343 clock_unlock(); 344 } 345 346 /* 347 * DELAY(usec) - Spin for the specified number of microseconds. 348 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 349 * but do a thread switch in the loop 350 * 351 * Relies on timer 1 counting down from (cputimer_freq / hz) 352 * Note: timer had better have been programmed before this is first used! 353 */ 354 static void 355 DODELAY(int n, int doswitch) 356 { 357 int delta, prev_tick, tick, ticks_left; 358 359 #ifdef DELAYDEBUG 360 int getit_calls = 1; 361 int n1; 362 static int state = 0; 363 364 if (state == 0) { 365 state = 1; 366 for (n1 = 1; n1 <= 10000000; n1 *= 10) 367 DELAY(n1); 368 state = 2; 369 } 370 if (state == 1) 371 kprintf("DELAY(%d)...", n); 372 #endif 373 /* 374 * Guard against the timer being uninitialized if we are called 375 * early for console i/o. 376 */ 377 if (timer0_state == RELEASED) 378 i8254_restore(); 379 380 /* 381 * Read the counter first, so that the rest of the setup overhead is 382 * counted. Then calculate the number of hardware timer ticks 383 * required, rounding up to be sure we delay at least the requested 384 * number of microseconds. 385 */ 386 prev_tick = sys_cputimer->count(); 387 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 388 1000000; 389 390 /* 391 * Loop until done. 392 */ 393 while (ticks_left > 0) { 394 tick = sys_cputimer->count(); 395 #ifdef DELAYDEBUG 396 ++getit_calls; 397 #endif 398 delta = tick - prev_tick; 399 prev_tick = tick; 400 if (delta < 0) 401 delta = 0; 402 ticks_left -= delta; 403 if (doswitch && ticks_left > 0) 404 lwkt_switch(); 405 cpu_pause(); 406 } 407 #ifdef DELAYDEBUG 408 if (state == 1) 409 kprintf(" %d calls to getit() at %d usec each\n", 410 getit_calls, (n + 5) / getit_calls); 411 #endif 412 } 413 414 /* 415 * DELAY() never switches. 416 */ 417 void 418 DELAY(int n) 419 { 420 DODELAY(n, 0); 421 } 422 423 /* 424 * Returns non-zero if the specified time period has elapsed. Call 425 * first with last_clock set to 0. 426 */ 427 int 428 CHECKTIMEOUT(TOTALDELAY *tdd) 429 { 430 sysclock_t delta; 431 int us; 432 433 if (tdd->started == 0) { 434 if (timer0_state == RELEASED) 435 i8254_restore(); 436 tdd->last_clock = sys_cputimer->count(); 437 tdd->started = 1; 438 return(0); 439 } 440 delta = sys_cputimer->count() - tdd->last_clock; 441 us = (u_int64_t)delta * (u_int64_t)1000000 / 442 (u_int64_t)sys_cputimer->freq; 443 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 444 1000000; 445 tdd->us -= us; 446 return (tdd->us < 0); 447 } 448 449 450 /* 451 * DRIVERSLEEP() does not switch if called with a spinlock held or 452 * from a hard interrupt. 453 */ 454 void 455 DRIVERSLEEP(int usec) 456 { 457 globaldata_t gd = mycpu; 458 459 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) { 460 DODELAY(usec, 0); 461 } else { 462 DODELAY(usec, 1); 463 } 464 } 465 466 static void 467 sysbeepstop(void *chan) 468 { 469 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 470 beeping = 0; 471 release_timer2(); 472 } 473 474 int 475 sysbeep(int pitch, int period) 476 { 477 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 478 return(-1); 479 if (sysbeep_enable == 0) 480 return(-1); 481 /* 482 * Nobody else is using timer2, we do not need the clock lock 483 */ 484 outb(TIMER_CNTR2, pitch); 485 outb(TIMER_CNTR2, (pitch>>8)); 486 if (!beeping) { 487 /* enable counter2 output to speaker */ 488 outb(IO_PPI, inb(IO_PPI) | 3); 489 beeping = period; 490 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 491 } 492 return (0); 493 } 494 495 /* 496 * RTC support routines 497 */ 498 499 int 500 rtcin(int reg) 501 { 502 u_char val; 503 504 crit_enter(); 505 outb(IO_RTC, reg); 506 inb(0x84); 507 val = inb(IO_RTC + 1); 508 inb(0x84); 509 crit_exit(); 510 return (val); 511 } 512 513 static __inline void 514 writertc(u_char reg, u_char val) 515 { 516 crit_enter(); 517 inb(0x84); 518 outb(IO_RTC, reg); 519 inb(0x84); 520 outb(IO_RTC + 1, val); 521 inb(0x84); /* XXX work around wrong order in rtcin() */ 522 crit_exit(); 523 } 524 525 static __inline int 526 readrtc(int port) 527 { 528 return(bcd2bin(rtcin(port))); 529 } 530 531 static u_int 532 calibrate_clocks(void) 533 { 534 u_int64_t old_tsc; 535 u_int count, prev_count, tot_count; 536 int sec, start_sec, timeout; 537 538 if (bootverbose) 539 kprintf("Calibrating clock(s) ... "); 540 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 541 goto fail; 542 timeout = 100000000; 543 544 /* Read the mc146818A seconds counter. */ 545 for (;;) { 546 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 547 sec = rtcin(RTC_SEC); 548 break; 549 } 550 if (--timeout == 0) 551 goto fail; 552 } 553 554 /* Wait for the mC146818A seconds counter to change. */ 555 start_sec = sec; 556 for (;;) { 557 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 558 sec = rtcin(RTC_SEC); 559 if (sec != start_sec) 560 break; 561 } 562 if (--timeout == 0) 563 goto fail; 564 } 565 566 /* Start keeping track of the i8254 counter. */ 567 prev_count = sys_cputimer->count(); 568 tot_count = 0; 569 570 if (tsc_present) 571 old_tsc = rdtsc(); 572 else 573 old_tsc = 0; /* shut up gcc */ 574 575 /* 576 * Wait for the mc146818A seconds counter to change. Read the i8254 577 * counter for each iteration since this is convenient and only 578 * costs a few usec of inaccuracy. The timing of the final reads 579 * of the counters almost matches the timing of the initial reads, 580 * so the main cause of inaccuracy is the varying latency from 581 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 582 * rtcin(RTC_SEC) that returns a changed seconds count. The 583 * maximum inaccuracy from this cause is < 10 usec on 486's. 584 */ 585 start_sec = sec; 586 for (;;) { 587 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 588 sec = rtcin(RTC_SEC); 589 count = sys_cputimer->count(); 590 tot_count += (int)(count - prev_count); 591 prev_count = count; 592 if (sec != start_sec) 593 break; 594 if (--timeout == 0) 595 goto fail; 596 } 597 598 /* 599 * Read the cpu cycle counter. The timing considerations are 600 * similar to those for the i8254 clock. 601 */ 602 if (tsc_present) { 603 tsc_frequency = rdtsc() - old_tsc; 604 } 605 606 if (tsc_present) 607 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 608 kprintf("i8254 clock: %u Hz\n", tot_count); 609 return (tot_count); 610 611 fail: 612 kprintf("failed, using default i8254 clock of %u Hz\n", 613 i8254_cputimer.freq); 614 return (i8254_cputimer.freq); 615 } 616 617 static void 618 i8254_restore(void) 619 { 620 timer0_state = ACQUIRED; 621 622 clock_lock(); 623 624 /* 625 * Timer0 is our fine-grained variable clock interrupt 626 */ 627 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 628 outb(TIMER_CNTR0, 2); /* lsb */ 629 outb(TIMER_CNTR0, 0); /* msb */ 630 clock_unlock(); 631 632 if (!i8254_nointr) { 633 cputimer_intr_register(&i8254_cputimer_intr); 634 cputimer_intr_select(&i8254_cputimer_intr, 0); 635 } 636 637 /* 638 * Timer1 or timer2 is our free-running clock, but only if another 639 * has not been selected. 640 */ 641 cputimer_register(&i8254_cputimer); 642 cputimer_select(&i8254_cputimer, 0); 643 } 644 645 static void 646 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 647 { 648 int which; 649 650 /* 651 * Should we use timer 1 or timer 2 ? 652 */ 653 which = 0; 654 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 655 if (which != 1 && which != 2) 656 which = 2; 657 658 switch(which) { 659 case 1: 660 timer->name = "i8254_timer1"; 661 timer->type = CPUTIMER_8254_SEL1; 662 i8254_walltimer_sel = TIMER_SEL1; 663 i8254_walltimer_cntr = TIMER_CNTR1; 664 timer1_state = ACQUIRED; 665 break; 666 case 2: 667 timer->name = "i8254_timer2"; 668 timer->type = CPUTIMER_8254_SEL2; 669 i8254_walltimer_sel = TIMER_SEL2; 670 i8254_walltimer_cntr = TIMER_CNTR2; 671 timer2_state = ACQUIRED; 672 break; 673 } 674 675 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 676 677 clock_lock(); 678 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 679 outb(i8254_walltimer_cntr, 0); /* lsb */ 680 outb(i8254_walltimer_cntr, 0); /* msb */ 681 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 682 clock_unlock(); 683 } 684 685 static void 686 i8254_cputimer_destruct(struct cputimer *timer) 687 { 688 switch(timer->type) { 689 case CPUTIMER_8254_SEL1: 690 timer1_state = RELEASED; 691 break; 692 case CPUTIMER_8254_SEL2: 693 timer2_state = RELEASED; 694 break; 695 default: 696 break; 697 } 698 timer->type = 0; 699 } 700 701 static void 702 rtc_restore(void) 703 { 704 /* Restore all of the RTC's "status" (actually, control) registers. */ 705 writertc(RTC_STATUSB, RTCSB_24HR); 706 writertc(RTC_STATUSA, rtc_statusa); 707 writertc(RTC_STATUSB, rtc_statusb); 708 } 709 710 /* 711 * Restore all the timers. 712 * 713 * This function is called to resynchronize our core timekeeping after a 714 * long halt, e.g. from apm_default_resume() and friends. It is also 715 * called if after a BIOS call we have detected munging of the 8254. 716 * It is necessary because cputimer_count() counter's delta may have grown 717 * too large for nanouptime() and friends to handle, or (in the case of 8254 718 * munging) might cause the SYSTIMER code to prematurely trigger. 719 */ 720 void 721 timer_restore(void) 722 { 723 crit_enter(); 724 i8254_restore(); /* restore timer_freq and hz */ 725 rtc_restore(); /* reenable RTC interrupts */ 726 crit_exit(); 727 } 728 729 /* 730 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 731 */ 732 void 733 startrtclock(void) 734 { 735 u_int delta, freq; 736 737 /* 738 * Can we use the TSC? 739 */ 740 if (cpu_feature & CPUID_TSC) 741 tsc_present = 1; 742 else 743 tsc_present = 0; 744 745 /* 746 * Initial RTC state, don't do anything unexpected 747 */ 748 writertc(RTC_STATUSA, rtc_statusa); 749 writertc(RTC_STATUSB, RTCSB_24HR); 750 751 /* 752 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 753 * generate an interrupt, which we will ignore for now. 754 * 755 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 756 * (so it counts a full 2^16 and repeats). We will use this timer 757 * for our counting. 758 */ 759 i8254_restore(); 760 freq = calibrate_clocks(); 761 #ifdef CLK_CALIBRATION_LOOP 762 if (bootverbose) { 763 kprintf( 764 "Press a key on the console to abort clock calibration\n"); 765 while (cncheckc() == -1) 766 calibrate_clocks(); 767 } 768 #endif 769 770 /* 771 * Use the calibrated i8254 frequency if it seems reasonable. 772 * Otherwise use the default, and don't use the calibrated i586 773 * frequency. 774 */ 775 delta = freq > i8254_cputimer.freq ? 776 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 777 if (delta < i8254_cputimer.freq / 100) { 778 #ifndef CLK_USE_I8254_CALIBRATION 779 if (bootverbose) 780 kprintf( 781 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 782 freq = i8254_cputimer.freq; 783 #endif 784 /* 785 * NOTE: 786 * Interrupt timer's freq must be adjusted 787 * before we change the cuptimer's frequency. 788 */ 789 i8254_cputimer_intr.freq = freq; 790 cputimer_set_frequency(&i8254_cputimer, freq); 791 } else { 792 if (bootverbose) 793 kprintf( 794 "%d Hz differs from default of %d Hz by more than 1%%\n", 795 freq, i8254_cputimer.freq); 796 tsc_frequency = 0; 797 } 798 799 #ifndef CLK_USE_TSC_CALIBRATION 800 if (tsc_frequency != 0) { 801 if (bootverbose) 802 kprintf( 803 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 804 tsc_frequency = 0; 805 } 806 #endif 807 if (tsc_present && tsc_frequency == 0) { 808 /* 809 * Calibration of the i586 clock relative to the mc146818A 810 * clock failed. Do a less accurate calibration relative 811 * to the i8254 clock. 812 */ 813 u_int64_t old_tsc = rdtsc(); 814 815 DELAY(1000000); 816 tsc_frequency = rdtsc() - old_tsc; 817 #ifdef CLK_USE_TSC_CALIBRATION 818 if (bootverbose) { 819 kprintf("TSC clock: %llu Hz (Method B)\n", 820 tsc_frequency); 821 } 822 #endif 823 } 824 825 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 826 } 827 828 /* 829 * Sync the time of day back to the RTC on shutdown, but only if 830 * we have already loaded it and have not crashed. 831 */ 832 static void 833 resettodr_on_shutdown(void *arg __unused) 834 { 835 if (rtc_loaded && panicstr == NULL) { 836 resettodr(); 837 } 838 } 839 840 /* 841 * Initialize the time of day register, based on the time base which is, e.g. 842 * from a filesystem. 843 */ 844 void 845 inittodr(time_t base) 846 { 847 unsigned long sec, days; 848 int year, month; 849 int y, m; 850 struct timespec ts; 851 852 if (base) { 853 ts.tv_sec = base; 854 ts.tv_nsec = 0; 855 set_timeofday(&ts); 856 } 857 858 /* Look if we have a RTC present and the time is valid */ 859 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 860 goto wrong_time; 861 862 /* wait for time update to complete */ 863 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 864 crit_enter(); 865 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 866 crit_exit(); 867 crit_enter(); 868 } 869 870 days = 0; 871 #ifdef USE_RTC_CENTURY 872 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 873 #else 874 year = readrtc(RTC_YEAR) + 1900; 875 if (year < 1970) 876 year += 100; 877 #endif 878 if (year < 1970) { 879 crit_exit(); 880 goto wrong_time; 881 } 882 month = readrtc(RTC_MONTH); 883 for (m = 1; m < month; m++) 884 days += daysinmonth[m-1]; 885 if ((month > 2) && LEAPYEAR(year)) 886 days ++; 887 days += readrtc(RTC_DAY) - 1; 888 for (y = 1970; y < year; y++) 889 days += DAYSPERYEAR + LEAPYEAR(y); 890 sec = ((( days * 24 + 891 readrtc(RTC_HRS)) * 60 + 892 readrtc(RTC_MIN)) * 60 + 893 readrtc(RTC_SEC)); 894 /* sec now contains the number of seconds, since Jan 1 1970, 895 in the local time zone */ 896 897 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 898 899 y = time_second - sec; 900 if (y <= -2 || y >= 2) { 901 /* badly off, adjust it */ 902 ts.tv_sec = sec; 903 ts.tv_nsec = 0; 904 set_timeofday(&ts); 905 } 906 rtc_loaded = 1; 907 crit_exit(); 908 return; 909 910 wrong_time: 911 kprintf("Invalid time in real time clock.\n"); 912 kprintf("Check and reset the date immediately!\n"); 913 } 914 915 /* 916 * Write system time back to RTC 917 */ 918 void 919 resettodr(void) 920 { 921 struct timeval tv; 922 unsigned long tm; 923 int m; 924 int y; 925 926 if (disable_rtc_set) 927 return; 928 929 microtime(&tv); 930 tm = tv.tv_sec; 931 932 crit_enter(); 933 /* Disable RTC updates and interrupts. */ 934 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 935 936 /* Calculate local time to put in RTC */ 937 938 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 939 940 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 941 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 942 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 943 944 /* We have now the days since 01-01-1970 in tm */ 945 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 946 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 947 tm >= m; 948 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 949 tm -= m; 950 951 /* Now we have the years in y and the day-of-the-year in tm */ 952 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 953 #ifdef USE_RTC_CENTURY 954 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 955 #endif 956 for (m = 0; ; m++) { 957 int ml; 958 959 ml = daysinmonth[m]; 960 if (m == 1 && LEAPYEAR(y)) 961 ml++; 962 if (tm < ml) 963 break; 964 tm -= ml; 965 } 966 967 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 968 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 969 970 /* Reenable RTC updates and interrupts. */ 971 writertc(RTC_STATUSB, rtc_statusb); 972 crit_exit(); 973 } 974 975 static int 976 i8254_ioapic_trial(int irq, struct cputimer_intr *cti) 977 { 978 sysclock_t base; 979 long lastcnt; 980 981 /* 982 * Following code assumes the 8254 is the cpu timer, 983 * so make sure it is. 984 */ 985 KKASSERT(sys_cputimer == &i8254_cputimer); 986 KKASSERT(cti == &i8254_cputimer_intr); 987 988 lastcnt = get_interrupt_counter(irq, mycpuid); 989 990 /* 991 * Force an 8254 Timer0 interrupt and wait 1/100s for 992 * it to happen, then see if we got it. 993 */ 994 kprintf("IOAPIC: testing 8254 interrupt delivery\n"); 995 996 i8254_intr_reload(cti, 2); 997 base = sys_cputimer->count(); 998 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 999 ; /* nothing */ 1000 1001 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0) 1002 return ENOENT; 1003 return 0; 1004 } 1005 1006 /* 1007 * Start both clocks running. DragonFly note: the stat clock is no longer 1008 * used. Instead, 8254 based systimers are used for all major clock 1009 * interrupts. 1010 */ 1011 static void 1012 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1013 { 1014 void *clkdesc = NULL; 1015 int irq = 0, mixed_mode = 0, error; 1016 1017 KKASSERT(mycpuid == 0); 1018 callout_init_mp(&sysbeepstop_ch); 1019 1020 if (!selected && i8254_intr_disable) 1021 goto nointr; 1022 1023 /* 1024 * The stat interrupt mask is different without the 1025 * statistics clock. Also, don't set the interrupt 1026 * flag which would normally cause the RTC to generate 1027 * interrupts. 1028 */ 1029 rtc_statusb = RTCSB_24HR; 1030 1031 /* Finish initializing 8254 timer 0. */ 1032 if (ioapic_enable) { 1033 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE, 1034 INTR_POLARITY_HIGH); 1035 if (irq < 0) { 1036 mixed_mode_setup: 1037 error = ioapic_conf_legacy_extint(0); 1038 if (!error) { 1039 irq = machintr_legacy_intr_find(0, 1040 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); 1041 if (irq < 0) 1042 error = ENOENT; 1043 } 1044 1045 if (error) { 1046 if (!selected) { 1047 kprintf("IOAPIC: setup mixed mode for " 1048 "irq 0 failed: %d\n", error); 1049 goto nointr; 1050 } else { 1051 panic("IOAPIC: setup mixed mode for " 1052 "irq 0 failed: %d\n", error); 1053 } 1054 } 1055 mixed_mode = 1; 1056 } 1057 clkdesc = register_int(irq, clkintr, NULL, "clk", 1058 NULL, 1059 INTR_EXCL | INTR_CLOCK | 1060 INTR_NOPOLL | INTR_MPSAFE | 1061 INTR_NOENTROPY, 0); 1062 } else { 1063 register_int(0, clkintr, NULL, "clk", NULL, 1064 INTR_EXCL | INTR_CLOCK | 1065 INTR_NOPOLL | INTR_MPSAFE | 1066 INTR_NOENTROPY, 0); 1067 } 1068 1069 /* Initialize RTC. */ 1070 writertc(RTC_STATUSA, rtc_statusa); 1071 writertc(RTC_STATUSB, RTCSB_24HR); 1072 1073 if (ioapic_enable) { 1074 error = i8254_ioapic_trial(irq, cti); 1075 if (error) { 1076 if (mixed_mode) { 1077 if (!selected) { 1078 kprintf("IOAPIC: mixed mode for irq %d " 1079 "trial failed: %d\n", 1080 irq, error); 1081 goto nointr; 1082 } else { 1083 panic("IOAPIC: mixed mode for irq %d " 1084 "trial failed: %d\n", irq, error); 1085 } 1086 } else { 1087 kprintf("IOAPIC: warning 8254 is not connected " 1088 "to the correct pin, try mixed mode\n"); 1089 unregister_int(clkdesc, 0); 1090 goto mixed_mode_setup; 1091 } 1092 } 1093 } 1094 return; 1095 1096 nointr: 1097 i8254_nointr = 1; /* don't try to register again */ 1098 cputimer_intr_deregister(cti); 1099 } 1100 1101 void 1102 setstatclockrate(int newhz) 1103 { 1104 if (newhz == RTC_PROFRATE) 1105 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1106 else 1107 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1108 writertc(RTC_STATUSA, rtc_statusa); 1109 } 1110 1111 #if 0 1112 static unsigned 1113 tsc_get_timecount(struct timecounter *tc) 1114 { 1115 return (rdtsc()); 1116 } 1117 #endif 1118 1119 #ifdef KERN_TIMESTAMP 1120 #define KERN_TIMESTAMP_SIZE 16384 1121 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1122 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1123 sizeof(tsc), "LU", "Kernel timestamps"); 1124 void 1125 _TSTMP(u_int32_t x) 1126 { 1127 static int i; 1128 1129 tsc[i] = (u_int32_t)rdtsc(); 1130 tsc[i+1] = x; 1131 i = i + 2; 1132 if (i >= KERN_TIMESTAMP_SIZE) 1133 i = 0; 1134 tsc[i] = 0; /* mark last entry */ 1135 } 1136 #endif /* KERN_TIMESTAMP */ 1137 1138 /* 1139 * 1140 */ 1141 1142 static int 1143 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1144 { 1145 sysclock_t count; 1146 __uint64_t tscval; 1147 char buf[32]; 1148 1149 crit_enter(); 1150 if (sys_cputimer == &i8254_cputimer) 1151 count = sys_cputimer->count(); 1152 else 1153 count = 0; 1154 if (tsc_present) 1155 tscval = rdtsc(); 1156 else 1157 tscval = 0; 1158 crit_exit(); 1159 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1160 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1161 } 1162 1163 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1164 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1165 "frequency"); 1166 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1167 0, 0, hw_i8254_timestamp, "A", ""); 1168 1169 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1170 &tsc_present, 0, "TSC Available"); 1171 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1172 &tsc_frequency, 0, "TSC Frequency"); 1173 1174