1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "use_apm.h" 54 #include "opt_clock.h" 55 #endif 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/eventhandler.h> 60 #include <sys/time.h> 61 #include <sys/kernel.h> 62 #include <sys/bus.h> 63 #ifndef SMP 64 #include <sys/lock.h> 65 #endif 66 #include <sys/sysctl.h> 67 #include <sys/cons.h> 68 #include <sys/systimer.h> 69 #include <sys/globaldata.h> 70 #include <sys/thread2.h> 71 #include <sys/systimer.h> 72 #include <sys/machintr.h> 73 #include <sys/interrupt.h> 74 75 #include <machine/clock.h> 76 #ifdef CLK_CALIBRATION_LOOP 77 #endif 78 #include <machine/cputypes.h> 79 #include <machine/frame.h> 80 #include <machine/ipl.h> 81 #include <machine/limits.h> 82 #include <machine/md_var.h> 83 #include <machine/psl.h> 84 #include <machine/segments.h> 85 #include <machine/smp.h> 86 #include <machine/specialreg.h> 87 #include <machine/intr_machdep.h> 88 89 #include <machine_base/apic/ioapic.h> 90 #include <machine_base/apic/ioapic_abi.h> 91 #include <machine_base/icu/icu.h> 92 #include <bus/isa/isa.h> 93 #include <bus/isa/rtc.h> 94 #include <machine_base/isa/timerreg.h> 95 96 static void i8254_restore(void); 97 static void resettodr_on_shutdown(void *arg __unused); 98 99 /* 100 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 101 * can use a simple formula for leap years. 102 */ 103 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 104 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 105 106 #ifndef TIMER_FREQ 107 #define TIMER_FREQ 1193182 108 #endif 109 110 static uint8_t i8254_walltimer_sel; 111 static uint16_t i8254_walltimer_cntr; 112 113 int adjkerntz; /* local offset from GMT in seconds */ 114 int disable_rtc_set; /* disable resettodr() if != 0 */ 115 int tsc_present; 116 int64_t tsc_frequency; 117 int tsc_is_broken; 118 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 119 int timer0_running; 120 enum tstate { RELEASED, ACQUIRED }; 121 enum tstate timer0_state; 122 enum tstate timer1_state; 123 enum tstate timer2_state; 124 125 static int beeping = 0; 126 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 127 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 128 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 129 static int rtc_loaded; 130 131 static int i8254_cputimer_div; 132 133 static int i8254_nointr; 134 static int i8254_intr_disable = 1; 135 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 136 137 static struct callout sysbeepstop_ch; 138 139 static sysclock_t i8254_cputimer_count(void); 140 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 141 static void i8254_cputimer_destruct(struct cputimer *cputimer); 142 143 static struct cputimer i8254_cputimer = { 144 SLIST_ENTRY_INITIALIZER, 145 "i8254", 146 CPUTIMER_PRI_8254, 147 0, 148 i8254_cputimer_count, 149 cputimer_default_fromhz, 150 cputimer_default_fromus, 151 i8254_cputimer_construct, 152 i8254_cputimer_destruct, 153 TIMER_FREQ, 154 0, 0, 0 155 }; 156 157 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 158 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 159 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 160 161 static struct cputimer_intr i8254_cputimer_intr = { 162 .freq = TIMER_FREQ, 163 .reload = i8254_intr_reload, 164 .enable = cputimer_intr_default_enable, 165 .config = i8254_intr_config, 166 .restart = cputimer_intr_default_restart, 167 .pmfixup = cputimer_intr_default_pmfixup, 168 .initclock = i8254_intr_initclock, 169 .next = SLIST_ENTRY_INITIALIZER, 170 .name = "i8254", 171 .type = CPUTIMER_INTR_8254, 172 .prio = CPUTIMER_INTR_PRIO_8254, 173 .caps = CPUTIMER_INTR_CAP_PS 174 }; 175 176 /* 177 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 178 * counting as of this interrupt. We use timer1 in free-running mode (not 179 * generating any interrupts) as our main counter. Each cpu has timeouts 180 * pending. 181 * 182 * This code is INTR_MPSAFE and may be called without the BGL held. 183 */ 184 static void 185 clkintr(void *dummy, void *frame_arg) 186 { 187 static sysclock_t sysclock_count; /* NOTE! Must be static */ 188 struct globaldata *gd = mycpu; 189 #ifdef SMP 190 struct globaldata *gscan; 191 int n; 192 #endif 193 194 /* 195 * SWSTROBE mode is a one-shot, the timer is no longer running 196 */ 197 timer0_running = 0; 198 199 /* 200 * XXX the dispatcher needs work. right now we call systimer_intr() 201 * directly or via IPI for any cpu with systimers queued, which is 202 * usually *ALL* of them. We need to use the LAPIC timer for this. 203 */ 204 sysclock_count = sys_cputimer->count(); 205 #ifdef SMP 206 for (n = 0; n < ncpus; ++n) { 207 gscan = globaldata_find(n); 208 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 209 continue; 210 if (gscan != gd) { 211 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 212 &sysclock_count, 1); 213 } else { 214 systimer_intr(&sysclock_count, 0, frame_arg); 215 } 216 } 217 #else 218 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) 219 systimer_intr(&sysclock_count, 0, frame_arg); 220 #endif 221 } 222 223 224 /* 225 * NOTE! not MP safe. 226 */ 227 int 228 acquire_timer2(int mode) 229 { 230 if (timer2_state != RELEASED) 231 return (-1); 232 timer2_state = ACQUIRED; 233 234 /* 235 * This access to the timer registers is as atomic as possible 236 * because it is a single instruction. We could do better if we 237 * knew the rate. 238 */ 239 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 240 return (0); 241 } 242 243 int 244 release_timer2(void) 245 { 246 if (timer2_state != ACQUIRED) 247 return (-1); 248 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 249 timer2_state = RELEASED; 250 return (0); 251 } 252 253 #include "opt_ddb.h" 254 #ifdef DDB 255 #include <ddb/ddb.h> 256 257 DB_SHOW_COMMAND(rtc, rtc) 258 { 259 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 260 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 261 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 262 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 263 } 264 #endif /* DDB */ 265 266 /* 267 * Return the current cpu timer count as a 32 bit integer. 268 */ 269 static 270 sysclock_t 271 i8254_cputimer_count(void) 272 { 273 static __uint16_t cputimer_last; 274 __uint16_t count; 275 sysclock_t ret; 276 277 clock_lock(); 278 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 279 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 280 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 281 count = -count; /* -> countup */ 282 if (count < cputimer_last) /* rollover */ 283 i8254_cputimer.base += 0x00010000; 284 ret = i8254_cputimer.base | count; 285 cputimer_last = count; 286 clock_unlock(); 287 return(ret); 288 } 289 290 /* 291 * This function is called whenever the system timebase changes, allowing 292 * us to calculate what is needed to convert a system timebase tick 293 * into an 8254 tick for the interrupt timer. If we can convert to a 294 * simple shift, multiplication, or division, we do so. Otherwise 64 295 * bit arithmatic is required every time the interrupt timer is reloaded. 296 */ 297 static void 298 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 299 { 300 int freq; 301 int div; 302 303 /* 304 * Will a simple divide do the trick? 305 */ 306 div = (timer->freq + (cti->freq / 2)) / cti->freq; 307 freq = cti->freq * div; 308 309 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 310 i8254_cputimer_div = div; 311 else 312 i8254_cputimer_div = 0; 313 } 314 315 /* 316 * Reload for the next timeout. It is possible for the reload value 317 * to be 0 or negative, indicating that an immediate timer interrupt 318 * is desired. For now make the minimum 2 ticks. 319 * 320 * We may have to convert from the system timebase to the 8254 timebase. 321 */ 322 static void 323 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 324 { 325 __uint16_t count; 326 327 if (i8254_cputimer_div) 328 reload /= i8254_cputimer_div; 329 else 330 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 331 332 if ((int)reload < 2) 333 reload = 2; 334 335 clock_lock(); 336 if (timer0_running) { 337 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 338 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 339 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 340 if (reload < count) { 341 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 342 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 343 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 344 } 345 } else { 346 timer0_running = 1; 347 if (reload > 0xFFFF) 348 reload = 0; /* full count */ 349 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 350 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 351 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 352 } 353 clock_unlock(); 354 } 355 356 /* 357 * DELAY(usec) - Spin for the specified number of microseconds. 358 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 359 * but do a thread switch in the loop 360 * 361 * Relies on timer 1 counting down from (cputimer_freq / hz) 362 * Note: timer had better have been programmed before this is first used! 363 */ 364 static void 365 DODELAY(int n, int doswitch) 366 { 367 int delta, prev_tick, tick, ticks_left; 368 369 #ifdef DELAYDEBUG 370 int getit_calls = 1; 371 int n1; 372 static int state = 0; 373 374 if (state == 0) { 375 state = 1; 376 for (n1 = 1; n1 <= 10000000; n1 *= 10) 377 DELAY(n1); 378 state = 2; 379 } 380 if (state == 1) 381 kprintf("DELAY(%d)...", n); 382 #endif 383 /* 384 * Guard against the timer being uninitialized if we are called 385 * early for console i/o. 386 */ 387 if (timer0_state == RELEASED) 388 i8254_restore(); 389 390 /* 391 * Read the counter first, so that the rest of the setup overhead is 392 * counted. Then calculate the number of hardware timer ticks 393 * required, rounding up to be sure we delay at least the requested 394 * number of microseconds. 395 */ 396 prev_tick = sys_cputimer->count(); 397 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 398 1000000; 399 400 /* 401 * Loop until done. 402 */ 403 while (ticks_left > 0) { 404 tick = sys_cputimer->count(); 405 #ifdef DELAYDEBUG 406 ++getit_calls; 407 #endif 408 delta = tick - prev_tick; 409 prev_tick = tick; 410 if (delta < 0) 411 delta = 0; 412 ticks_left -= delta; 413 if (doswitch && ticks_left > 0) 414 lwkt_switch(); 415 cpu_pause(); 416 } 417 #ifdef DELAYDEBUG 418 if (state == 1) 419 kprintf(" %d calls to getit() at %d usec each\n", 420 getit_calls, (n + 5) / getit_calls); 421 #endif 422 } 423 424 /* 425 * DELAY() never switches. 426 */ 427 void 428 DELAY(int n) 429 { 430 DODELAY(n, 0); 431 } 432 433 /* 434 * Returns non-zero if the specified time period has elapsed. Call 435 * first with last_clock set to 0. 436 */ 437 int 438 CHECKTIMEOUT(TOTALDELAY *tdd) 439 { 440 sysclock_t delta; 441 int us; 442 443 if (tdd->started == 0) { 444 if (timer0_state == RELEASED) 445 i8254_restore(); 446 tdd->last_clock = sys_cputimer->count(); 447 tdd->started = 1; 448 return(0); 449 } 450 delta = sys_cputimer->count() - tdd->last_clock; 451 us = (u_int64_t)delta * (u_int64_t)1000000 / 452 (u_int64_t)sys_cputimer->freq; 453 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 454 1000000; 455 tdd->us -= us; 456 return (tdd->us < 0); 457 } 458 459 460 /* 461 * DRIVERSLEEP() does not switch if called with a spinlock held or 462 * from a hard interrupt. 463 */ 464 void 465 DRIVERSLEEP(int usec) 466 { 467 globaldata_t gd = mycpu; 468 469 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) { 470 DODELAY(usec, 0); 471 } else { 472 DODELAY(usec, 1); 473 } 474 } 475 476 static void 477 sysbeepstop(void *chan) 478 { 479 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 480 beeping = 0; 481 release_timer2(); 482 } 483 484 int 485 sysbeep(int pitch, int period) 486 { 487 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 488 return(-1); 489 if (sysbeep_enable == 0) 490 return(-1); 491 /* 492 * Nobody else is using timer2, we do not need the clock lock 493 */ 494 outb(TIMER_CNTR2, pitch); 495 outb(TIMER_CNTR2, (pitch>>8)); 496 if (!beeping) { 497 /* enable counter2 output to speaker */ 498 outb(IO_PPI, inb(IO_PPI) | 3); 499 beeping = period; 500 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 501 } 502 return (0); 503 } 504 505 /* 506 * RTC support routines 507 */ 508 509 int 510 rtcin(int reg) 511 { 512 u_char val; 513 514 crit_enter(); 515 outb(IO_RTC, reg); 516 inb(0x84); 517 val = inb(IO_RTC + 1); 518 inb(0x84); 519 crit_exit(); 520 return (val); 521 } 522 523 static __inline void 524 writertc(u_char reg, u_char val) 525 { 526 crit_enter(); 527 inb(0x84); 528 outb(IO_RTC, reg); 529 inb(0x84); 530 outb(IO_RTC + 1, val); 531 inb(0x84); /* XXX work around wrong order in rtcin() */ 532 crit_exit(); 533 } 534 535 static __inline int 536 readrtc(int port) 537 { 538 return(bcd2bin(rtcin(port))); 539 } 540 541 static u_int 542 calibrate_clocks(void) 543 { 544 u_int64_t old_tsc; 545 u_int count, prev_count, tot_count; 546 int sec, start_sec, timeout; 547 548 if (bootverbose) 549 kprintf("Calibrating clock(s) ... "); 550 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 551 goto fail; 552 timeout = 100000000; 553 554 /* Read the mc146818A seconds counter. */ 555 for (;;) { 556 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 557 sec = rtcin(RTC_SEC); 558 break; 559 } 560 if (--timeout == 0) 561 goto fail; 562 } 563 564 /* Wait for the mC146818A seconds counter to change. */ 565 start_sec = sec; 566 for (;;) { 567 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 568 sec = rtcin(RTC_SEC); 569 if (sec != start_sec) 570 break; 571 } 572 if (--timeout == 0) 573 goto fail; 574 } 575 576 /* Start keeping track of the i8254 counter. */ 577 prev_count = sys_cputimer->count(); 578 tot_count = 0; 579 580 if (tsc_present) 581 old_tsc = rdtsc(); 582 else 583 old_tsc = 0; /* shut up gcc */ 584 585 /* 586 * Wait for the mc146818A seconds counter to change. Read the i8254 587 * counter for each iteration since this is convenient and only 588 * costs a few usec of inaccuracy. The timing of the final reads 589 * of the counters almost matches the timing of the initial reads, 590 * so the main cause of inaccuracy is the varying latency from 591 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 592 * rtcin(RTC_SEC) that returns a changed seconds count. The 593 * maximum inaccuracy from this cause is < 10 usec on 486's. 594 */ 595 start_sec = sec; 596 for (;;) { 597 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 598 sec = rtcin(RTC_SEC); 599 count = sys_cputimer->count(); 600 tot_count += (int)(count - prev_count); 601 prev_count = count; 602 if (sec != start_sec) 603 break; 604 if (--timeout == 0) 605 goto fail; 606 } 607 608 /* 609 * Read the cpu cycle counter. The timing considerations are 610 * similar to those for the i8254 clock. 611 */ 612 if (tsc_present) { 613 tsc_frequency = rdtsc() - old_tsc; 614 } 615 616 if (tsc_present) 617 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 618 kprintf("i8254 clock: %u Hz\n", tot_count); 619 return (tot_count); 620 621 fail: 622 kprintf("failed, using default i8254 clock of %u Hz\n", 623 i8254_cputimer.freq); 624 return (i8254_cputimer.freq); 625 } 626 627 static void 628 i8254_restore(void) 629 { 630 timer0_state = ACQUIRED; 631 632 clock_lock(); 633 634 /* 635 * Timer0 is our fine-grained variable clock interrupt 636 */ 637 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 638 outb(TIMER_CNTR0, 2); /* lsb */ 639 outb(TIMER_CNTR0, 0); /* msb */ 640 clock_unlock(); 641 642 if (!i8254_nointr) { 643 cputimer_intr_register(&i8254_cputimer_intr); 644 cputimer_intr_select(&i8254_cputimer_intr, 0); 645 } 646 647 /* 648 * Timer1 or timer2 is our free-running clock, but only if another 649 * has not been selected. 650 */ 651 cputimer_register(&i8254_cputimer); 652 cputimer_select(&i8254_cputimer, 0); 653 } 654 655 static void 656 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 657 { 658 int which; 659 660 /* 661 * Should we use timer 1 or timer 2 ? 662 */ 663 which = 0; 664 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 665 if (which != 1 && which != 2) 666 which = 2; 667 668 switch(which) { 669 case 1: 670 timer->name = "i8254_timer1"; 671 timer->type = CPUTIMER_8254_SEL1; 672 i8254_walltimer_sel = TIMER_SEL1; 673 i8254_walltimer_cntr = TIMER_CNTR1; 674 timer1_state = ACQUIRED; 675 break; 676 case 2: 677 timer->name = "i8254_timer2"; 678 timer->type = CPUTIMER_8254_SEL2; 679 i8254_walltimer_sel = TIMER_SEL2; 680 i8254_walltimer_cntr = TIMER_CNTR2; 681 timer2_state = ACQUIRED; 682 break; 683 } 684 685 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 686 687 clock_lock(); 688 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 689 outb(i8254_walltimer_cntr, 0); /* lsb */ 690 outb(i8254_walltimer_cntr, 0); /* msb */ 691 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 692 clock_unlock(); 693 } 694 695 static void 696 i8254_cputimer_destruct(struct cputimer *timer) 697 { 698 switch(timer->type) { 699 case CPUTIMER_8254_SEL1: 700 timer1_state = RELEASED; 701 break; 702 case CPUTIMER_8254_SEL2: 703 timer2_state = RELEASED; 704 break; 705 default: 706 break; 707 } 708 timer->type = 0; 709 } 710 711 static void 712 rtc_restore(void) 713 { 714 /* Restore all of the RTC's "status" (actually, control) registers. */ 715 writertc(RTC_STATUSB, RTCSB_24HR); 716 writertc(RTC_STATUSA, rtc_statusa); 717 writertc(RTC_STATUSB, rtc_statusb); 718 } 719 720 /* 721 * Restore all the timers. 722 * 723 * This function is called to resynchronize our core timekeeping after a 724 * long halt, e.g. from apm_default_resume() and friends. It is also 725 * called if after a BIOS call we have detected munging of the 8254. 726 * It is necessary because cputimer_count() counter's delta may have grown 727 * too large for nanouptime() and friends to handle, or (in the case of 8254 728 * munging) might cause the SYSTIMER code to prematurely trigger. 729 */ 730 void 731 timer_restore(void) 732 { 733 crit_enter(); 734 i8254_restore(); /* restore timer_freq and hz */ 735 rtc_restore(); /* reenable RTC interrupts */ 736 crit_exit(); 737 } 738 739 /* 740 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 741 */ 742 void 743 startrtclock(void) 744 { 745 u_int delta, freq; 746 747 /* 748 * Can we use the TSC? 749 */ 750 if (cpu_feature & CPUID_TSC) 751 tsc_present = 1; 752 else 753 tsc_present = 0; 754 755 /* 756 * Initial RTC state, don't do anything unexpected 757 */ 758 writertc(RTC_STATUSA, rtc_statusa); 759 writertc(RTC_STATUSB, RTCSB_24HR); 760 761 /* 762 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 763 * generate an interrupt, which we will ignore for now. 764 * 765 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 766 * (so it counts a full 2^16 and repeats). We will use this timer 767 * for our counting. 768 */ 769 i8254_restore(); 770 freq = calibrate_clocks(); 771 #ifdef CLK_CALIBRATION_LOOP 772 if (bootverbose) { 773 kprintf( 774 "Press a key on the console to abort clock calibration\n"); 775 while (cncheckc() == -1) 776 calibrate_clocks(); 777 } 778 #endif 779 780 /* 781 * Use the calibrated i8254 frequency if it seems reasonable. 782 * Otherwise use the default, and don't use the calibrated i586 783 * frequency. 784 */ 785 delta = freq > i8254_cputimer.freq ? 786 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 787 if (delta < i8254_cputimer.freq / 100) { 788 #ifndef CLK_USE_I8254_CALIBRATION 789 if (bootverbose) 790 kprintf( 791 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 792 freq = i8254_cputimer.freq; 793 #endif 794 /* 795 * NOTE: 796 * Interrupt timer's freq must be adjusted 797 * before we change the cuptimer's frequency. 798 */ 799 i8254_cputimer_intr.freq = freq; 800 cputimer_set_frequency(&i8254_cputimer, freq); 801 } else { 802 if (bootverbose) 803 kprintf( 804 "%d Hz differs from default of %d Hz by more than 1%%\n", 805 freq, i8254_cputimer.freq); 806 tsc_frequency = 0; 807 } 808 809 #ifndef CLK_USE_TSC_CALIBRATION 810 if (tsc_frequency != 0) { 811 if (bootverbose) 812 kprintf( 813 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 814 tsc_frequency = 0; 815 } 816 #endif 817 if (tsc_present && tsc_frequency == 0) { 818 /* 819 * Calibration of the i586 clock relative to the mc146818A 820 * clock failed. Do a less accurate calibration relative 821 * to the i8254 clock. 822 */ 823 u_int64_t old_tsc = rdtsc(); 824 825 DELAY(1000000); 826 tsc_frequency = rdtsc() - old_tsc; 827 #ifdef CLK_USE_TSC_CALIBRATION 828 if (bootverbose) { 829 kprintf("TSC clock: %llu Hz (Method B)\n", 830 tsc_frequency); 831 } 832 #endif 833 } 834 835 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 836 837 #if !defined(SMP) 838 /* 839 * We can not use the TSC in SMP mode, until we figure out a 840 * cheap (impossible), reliable and precise (yeah right!) way 841 * to synchronize the TSCs of all the CPUs. 842 * Curse Intel for leaving the counter out of the I/O APIC. 843 */ 844 845 #if NAPM > 0 846 /* 847 * We can not use the TSC if we support APM. Precise timekeeping 848 * on an APM'ed machine is at best a fools pursuit, since 849 * any and all of the time spent in various SMM code can't 850 * be reliably accounted for. Reading the RTC is your only 851 * source of reliable time info. The i8254 looses too of course 852 * but we need to have some kind of time... 853 * We don't know at this point whether APM is going to be used 854 * or not, nor when it might be activated. Play it safe. 855 */ 856 return; 857 #endif /* NAPM > 0 */ 858 859 #endif /* !defined(SMP) */ 860 } 861 862 /* 863 * Sync the time of day back to the RTC on shutdown, but only if 864 * we have already loaded it and have not crashed. 865 */ 866 static void 867 resettodr_on_shutdown(void *arg __unused) 868 { 869 if (rtc_loaded && panicstr == NULL) { 870 resettodr(); 871 } 872 } 873 874 /* 875 * Initialize the time of day register, based on the time base which is, e.g. 876 * from a filesystem. 877 */ 878 void 879 inittodr(time_t base) 880 { 881 unsigned long sec, days; 882 int year, month; 883 int y, m; 884 struct timespec ts; 885 886 if (base) { 887 ts.tv_sec = base; 888 ts.tv_nsec = 0; 889 set_timeofday(&ts); 890 } 891 892 /* Look if we have a RTC present and the time is valid */ 893 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 894 goto wrong_time; 895 896 /* wait for time update to complete */ 897 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 898 crit_enter(); 899 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 900 crit_exit(); 901 crit_enter(); 902 } 903 904 days = 0; 905 #ifdef USE_RTC_CENTURY 906 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 907 #else 908 year = readrtc(RTC_YEAR) + 1900; 909 if (year < 1970) 910 year += 100; 911 #endif 912 if (year < 1970) { 913 crit_exit(); 914 goto wrong_time; 915 } 916 month = readrtc(RTC_MONTH); 917 for (m = 1; m < month; m++) 918 days += daysinmonth[m-1]; 919 if ((month > 2) && LEAPYEAR(year)) 920 days ++; 921 days += readrtc(RTC_DAY) - 1; 922 for (y = 1970; y < year; y++) 923 days += DAYSPERYEAR + LEAPYEAR(y); 924 sec = ((( days * 24 + 925 readrtc(RTC_HRS)) * 60 + 926 readrtc(RTC_MIN)) * 60 + 927 readrtc(RTC_SEC)); 928 /* sec now contains the number of seconds, since Jan 1 1970, 929 in the local time zone */ 930 931 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 932 933 y = time_second - sec; 934 if (y <= -2 || y >= 2) { 935 /* badly off, adjust it */ 936 ts.tv_sec = sec; 937 ts.tv_nsec = 0; 938 set_timeofday(&ts); 939 } 940 rtc_loaded = 1; 941 crit_exit(); 942 return; 943 944 wrong_time: 945 kprintf("Invalid time in real time clock.\n"); 946 kprintf("Check and reset the date immediately!\n"); 947 } 948 949 /* 950 * Write system time back to RTC 951 */ 952 void 953 resettodr(void) 954 { 955 struct timeval tv; 956 unsigned long tm; 957 int m; 958 int y; 959 960 if (disable_rtc_set) 961 return; 962 963 microtime(&tv); 964 tm = tv.tv_sec; 965 966 crit_enter(); 967 /* Disable RTC updates and interrupts. */ 968 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 969 970 /* Calculate local time to put in RTC */ 971 972 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 973 974 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 975 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 976 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 977 978 /* We have now the days since 01-01-1970 in tm */ 979 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 980 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 981 tm >= m; 982 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 983 tm -= m; 984 985 /* Now we have the years in y and the day-of-the-year in tm */ 986 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 987 #ifdef USE_RTC_CENTURY 988 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 989 #endif 990 for (m = 0; ; m++) { 991 int ml; 992 993 ml = daysinmonth[m]; 994 if (m == 1 && LEAPYEAR(y)) 995 ml++; 996 if (tm < ml) 997 break; 998 tm -= ml; 999 } 1000 1001 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1002 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1003 1004 /* Reenable RTC updates and interrupts. */ 1005 writertc(RTC_STATUSB, rtc_statusb); 1006 crit_exit(); 1007 } 1008 1009 static int 1010 i8254_ioapic_trial(int irq, struct cputimer_intr *cti) 1011 { 1012 sysclock_t base; 1013 long lastcnt; 1014 1015 /* 1016 * Following code assumes the 8254 is the cpu timer, 1017 * so make sure it is. 1018 */ 1019 KKASSERT(sys_cputimer == &i8254_cputimer); 1020 KKASSERT(cti == &i8254_cputimer_intr); 1021 1022 lastcnt = get_interrupt_counter(irq, mycpuid); 1023 1024 /* 1025 * Force an 8254 Timer0 interrupt and wait 1/100s for 1026 * it to happen, then see if we got it. 1027 */ 1028 kprintf("IOAPIC: testing 8254 interrupt delivery\n"); 1029 1030 i8254_intr_reload(cti, 2); 1031 base = sys_cputimer->count(); 1032 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1033 ; /* nothing */ 1034 1035 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0) 1036 return ENOENT; 1037 return 0; 1038 } 1039 1040 /* 1041 * Start both clocks running. DragonFly note: the stat clock is no longer 1042 * used. Instead, 8254 based systimers are used for all major clock 1043 * interrupts. 1044 */ 1045 static void 1046 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1047 { 1048 void *clkdesc = NULL; 1049 int irq = 0, mixed_mode = 0, error; 1050 1051 KKASSERT(mycpuid == 0); 1052 callout_init_mp(&sysbeepstop_ch); 1053 1054 if (!selected && i8254_intr_disable) 1055 goto nointr; 1056 1057 /* 1058 * The stat interrupt mask is different without the 1059 * statistics clock. Also, don't set the interrupt 1060 * flag which would normally cause the RTC to generate 1061 * interrupts. 1062 */ 1063 rtc_statusb = RTCSB_24HR; 1064 1065 /* Finish initializing 8254 timer 0. */ 1066 if (ioapic_enable) { 1067 irq = ioapic_find_legacy_by_irq(0, INTR_TRIGGER_EDGE, 1068 INTR_POLARITY_HIGH); 1069 if (irq < 0) { 1070 mixed_mode_setup: 1071 error = ioapic_conf_legacy_extint(0); 1072 if (!error) { 1073 irq = ioapic_find_legacy_by_irq(0, 1074 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); 1075 if (irq < 0) 1076 error = ENOENT; 1077 } 1078 1079 if (error) { 1080 if (!selected) { 1081 kprintf("IOAPIC: setup mixed mode for " 1082 "irq 0 failed: %d\n", error); 1083 goto nointr; 1084 } else { 1085 panic("IOAPIC: setup mixed mode for " 1086 "irq 0 failed: %d\n", error); 1087 } 1088 } 1089 mixed_mode = 1; 1090 } 1091 clkdesc = register_int(irq, clkintr, NULL, "clk", 1092 NULL, 1093 INTR_EXCL | INTR_CLOCK | 1094 INTR_NOPOLL | INTR_MPSAFE | 1095 INTR_NOENTROPY, 0); 1096 } else { 1097 register_int(0, clkintr, NULL, "clk", NULL, 1098 INTR_EXCL | INTR_CLOCK | 1099 INTR_NOPOLL | INTR_MPSAFE | 1100 INTR_NOENTROPY, 0); 1101 } 1102 1103 /* Initialize RTC. */ 1104 writertc(RTC_STATUSA, rtc_statusa); 1105 writertc(RTC_STATUSB, RTCSB_24HR); 1106 1107 if (ioapic_enable) { 1108 error = i8254_ioapic_trial(irq, cti); 1109 if (error) { 1110 if (mixed_mode) { 1111 if (!selected) { 1112 kprintf("IOAPIC: mixed mode for irq %d " 1113 "trial failed: %d\n", 1114 irq, error); 1115 goto nointr; 1116 } else { 1117 panic("IOAPIC: mixed mode for irq %d " 1118 "trial failed: %d\n", irq, error); 1119 } 1120 } else { 1121 kprintf("IOAPIC: warning 8254 is not connected " 1122 "to the correct pin, try mixed mode\n"); 1123 unregister_int(clkdesc, 0); 1124 goto mixed_mode_setup; 1125 } 1126 } 1127 } 1128 return; 1129 1130 nointr: 1131 i8254_nointr = 1; /* don't try to register again */ 1132 cputimer_intr_deregister(cti); 1133 } 1134 1135 void 1136 setstatclockrate(int newhz) 1137 { 1138 if (newhz == RTC_PROFRATE) 1139 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1140 else 1141 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1142 writertc(RTC_STATUSA, rtc_statusa); 1143 } 1144 1145 #if 0 1146 static unsigned 1147 tsc_get_timecount(struct timecounter *tc) 1148 { 1149 return (rdtsc()); 1150 } 1151 #endif 1152 1153 #ifdef KERN_TIMESTAMP 1154 #define KERN_TIMESTAMP_SIZE 16384 1155 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1156 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1157 sizeof(tsc), "LU", "Kernel timestamps"); 1158 void 1159 _TSTMP(u_int32_t x) 1160 { 1161 static int i; 1162 1163 tsc[i] = (u_int32_t)rdtsc(); 1164 tsc[i+1] = x; 1165 i = i + 2; 1166 if (i >= KERN_TIMESTAMP_SIZE) 1167 i = 0; 1168 tsc[i] = 0; /* mark last entry */ 1169 } 1170 #endif /* KERN_TIMESTAMP */ 1171 1172 /* 1173 * 1174 */ 1175 1176 static int 1177 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1178 { 1179 sysclock_t count; 1180 __uint64_t tscval; 1181 char buf[32]; 1182 1183 crit_enter(); 1184 if (sys_cputimer == &i8254_cputimer) 1185 count = sys_cputimer->count(); 1186 else 1187 count = 0; 1188 if (tsc_present) 1189 tscval = rdtsc(); 1190 else 1191 tscval = 0; 1192 crit_exit(); 1193 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1194 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1195 } 1196 1197 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1198 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1199 "frequency"); 1200 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1201 0, 0, hw_i8254_timestamp, "A", ""); 1202 1203 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1204 &tsc_present, 0, "TSC Available"); 1205 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1206 &tsc_frequency, 0, "TSC Frequency"); 1207 1208