1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 34 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 35 */ 36 37 /* 38 * Routines to handle clock hardware. 39 */ 40 41 /* 42 * inittodr, settodr and support routines written 43 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 44 * 45 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 46 */ 47 48 #if 0 49 #include "opt_clock.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/eventhandler.h> 55 #include <sys/time.h> 56 #include <sys/kernel.h> 57 #include <sys/bus.h> 58 #include <sys/sysctl.h> 59 #include <sys/cons.h> 60 #include <sys/kbio.h> 61 #include <sys/systimer.h> 62 #include <sys/globaldata.h> 63 #include <sys/machintr.h> 64 #include <sys/interrupt.h> 65 66 #include <sys/thread2.h> 67 68 #include <machine/clock.h> 69 #include <machine/cputypes.h> 70 #include <machine/frame.h> 71 #include <machine/ipl.h> 72 #include <machine/limits.h> 73 #include <machine/md_var.h> 74 #include <machine/psl.h> 75 #include <machine/segments.h> 76 #include <machine/smp.h> 77 #include <machine/specialreg.h> 78 #include <machine/intr_machdep.h> 79 80 #include <machine_base/apic/ioapic.h> 81 #include <machine_base/apic/ioapic_abi.h> 82 #include <machine_base/icu/icu.h> 83 #include <bus/isa/isa.h> 84 #include <bus/isa/rtc.h> 85 #include <machine_base/isa/timerreg.h> 86 87 static void i8254_restore(void); 88 static void resettodr_on_shutdown(void *arg __unused); 89 90 /* 91 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 92 * can use a simple formula for leap years. 93 */ 94 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 95 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 96 97 #ifndef TIMER_FREQ 98 #define TIMER_FREQ 1193182 99 #endif 100 101 static uint8_t i8254_walltimer_sel; 102 static uint16_t i8254_walltimer_cntr; 103 104 int adjkerntz; /* local offset from GMT in seconds */ 105 int disable_rtc_set; /* disable resettodr() if != 0 */ 106 int tsc_present; 107 int tsc_invariant; 108 int tsc_mpsync; 109 int64_t tsc_frequency; 110 int tsc_is_broken; 111 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 112 int timer0_running; 113 enum tstate { RELEASED, ACQUIRED }; 114 enum tstate timer0_state; 115 enum tstate timer1_state; 116 enum tstate timer2_state; 117 118 static int beeping = 0; 119 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 120 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 121 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 122 static int rtc_loaded; 123 124 static int i8254_cputimer_div; 125 126 static int i8254_nointr; 127 static int i8254_intr_disable = 1; 128 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 129 130 static struct callout sysbeepstop_ch; 131 132 static sysclock_t i8254_cputimer_count(void); 133 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 134 static void i8254_cputimer_destruct(struct cputimer *cputimer); 135 136 static struct cputimer i8254_cputimer = { 137 .next = SLIST_ENTRY_INITIALIZER, 138 .name = "i8254", 139 .pri = CPUTIMER_PRI_8254, 140 .type = 0, /* determined later */ 141 .count = i8254_cputimer_count, 142 .fromhz = cputimer_default_fromhz, 143 .fromus = cputimer_default_fromus, 144 .construct = i8254_cputimer_construct, 145 .destruct = i8254_cputimer_destruct, 146 .freq = TIMER_FREQ 147 }; 148 149 static sysclock_t tsc_cputimer_count_mfence(void); 150 static sysclock_t tsc_cputimer_count_lfence(void); 151 static void tsc_cputimer_construct(struct cputimer *, sysclock_t); 152 153 static struct cputimer tsc_cputimer = { 154 .next = SLIST_ENTRY_INITIALIZER, 155 .name = "TSC", 156 .pri = CPUTIMER_PRI_TSC, 157 .type = CPUTIMER_TSC, 158 .count = NULL, /* determined later */ 159 .fromhz = cputimer_default_fromhz, 160 .fromus = cputimer_default_fromus, 161 .construct = tsc_cputimer_construct, 162 .destruct = cputimer_default_destruct, 163 .freq = 0 /* determined later */ 164 }; 165 166 static struct cpucounter tsc_cpucounter = { 167 .freq = 0, /* determined later */ 168 .count = NULL, /* determined later */ 169 .flags = 0, /* adjusted later */ 170 .prio = CPUCOUNTER_PRIO_TSC, 171 .type = CPUCOUNTER_TSC 172 }; 173 174 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 175 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 176 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 177 178 static struct cputimer_intr i8254_cputimer_intr = { 179 .freq = TIMER_FREQ, 180 .reload = i8254_intr_reload, 181 .enable = cputimer_intr_default_enable, 182 .config = i8254_intr_config, 183 .restart = cputimer_intr_default_restart, 184 .pmfixup = cputimer_intr_default_pmfixup, 185 .initclock = i8254_intr_initclock, 186 .pcpuhand = NULL, 187 .next = SLIST_ENTRY_INITIALIZER, 188 .name = "i8254", 189 .type = CPUTIMER_INTR_8254, 190 .prio = CPUTIMER_INTR_PRIO_8254, 191 .caps = CPUTIMER_INTR_CAP_PS, 192 .priv = NULL 193 }; 194 195 /* 196 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 197 * counting as of this interrupt. We use timer1 in free-running mode (not 198 * generating any interrupts) as our main counter. Each cpu has timeouts 199 * pending. 200 * 201 * This code is INTR_MPSAFE and may be called without the BGL held. 202 */ 203 static void 204 clkintr(void *dummy, void *frame_arg) 205 { 206 static sysclock_t sysclock_count; /* NOTE! Must be static */ 207 struct globaldata *gd = mycpu; 208 struct globaldata *gscan; 209 int n; 210 211 /* 212 * SWSTROBE mode is a one-shot, the timer is no longer running 213 */ 214 timer0_running = 0; 215 216 /* 217 * XXX the dispatcher needs work. right now we call systimer_intr() 218 * directly or via IPI for any cpu with systimers queued, which is 219 * usually *ALL* of them. We need to use the LAPIC timer for this. 220 */ 221 sysclock_count = sys_cputimer->count(); 222 for (n = 0; n < ncpus; ++n) { 223 gscan = globaldata_find(n); 224 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 225 continue; 226 if (gscan != gd) { 227 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 228 &sysclock_count, 1); 229 } else { 230 systimer_intr(&sysclock_count, 0, frame_arg); 231 } 232 } 233 } 234 235 236 /* 237 * NOTE! not MP safe. 238 */ 239 int 240 acquire_timer2(int mode) 241 { 242 if (timer2_state != RELEASED) 243 return (-1); 244 timer2_state = ACQUIRED; 245 246 /* 247 * This access to the timer registers is as atomic as possible 248 * because it is a single instruction. We could do better if we 249 * knew the rate. 250 */ 251 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 252 return (0); 253 } 254 255 int 256 release_timer2(void) 257 { 258 if (timer2_state != ACQUIRED) 259 return (-1); 260 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 261 timer2_state = RELEASED; 262 return (0); 263 } 264 265 #include "opt_ddb.h" 266 #ifdef DDB 267 #include <ddb/ddb.h> 268 269 DB_SHOW_COMMAND(rtc, rtc) 270 { 271 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 272 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 273 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 274 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 275 } 276 #endif /* DDB */ 277 278 /* 279 * Return the current cpu timer count as a 32 bit integer. 280 */ 281 static 282 sysclock_t 283 i8254_cputimer_count(void) 284 { 285 static uint16_t cputimer_last; 286 uint16_t count; 287 sysclock_t ret; 288 289 clock_lock(); 290 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 291 count = (uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 292 count |= ((uint8_t)inb(i8254_walltimer_cntr) << 8); 293 count = -count; /* -> countup */ 294 if (count < cputimer_last) /* rollover */ 295 i8254_cputimer.base += 0x00010000; 296 ret = i8254_cputimer.base | count; 297 cputimer_last = count; 298 clock_unlock(); 299 return(ret); 300 } 301 302 /* 303 * This function is called whenever the system timebase changes, allowing 304 * us to calculate what is needed to convert a system timebase tick 305 * into an 8254 tick for the interrupt timer. If we can convert to a 306 * simple shift, multiplication, or division, we do so. Otherwise 64 307 * bit arithmatic is required every time the interrupt timer is reloaded. 308 */ 309 static void 310 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 311 { 312 int freq; 313 int div; 314 315 /* 316 * Will a simple divide do the trick? 317 */ 318 div = (timer->freq + (cti->freq / 2)) / cti->freq; 319 freq = cti->freq * div; 320 321 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 322 i8254_cputimer_div = div; 323 else 324 i8254_cputimer_div = 0; 325 } 326 327 /* 328 * Reload for the next timeout. It is possible for the reload value 329 * to be 0 or negative, indicating that an immediate timer interrupt 330 * is desired. For now make the minimum 2 ticks. 331 * 332 * We may have to convert from the system timebase to the 8254 timebase. 333 */ 334 static void 335 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 336 { 337 uint16_t count; 338 339 if (i8254_cputimer_div) 340 reload /= i8254_cputimer_div; 341 else 342 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 343 344 if ((int)reload < 2) 345 reload = 2; 346 347 clock_lock(); 348 if (timer0_running) { 349 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 350 count = (uint8_t)inb(TIMER_CNTR0); /* lsb */ 351 count |= ((uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 352 if (reload < count) { 353 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 354 outb(TIMER_CNTR0, (uint8_t)reload); /* lsb */ 355 outb(TIMER_CNTR0, (uint8_t)(reload >> 8)); /* msb */ 356 } 357 } else { 358 timer0_running = 1; 359 if (reload > 0xFFFF) 360 reload = 0; /* full count */ 361 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 362 outb(TIMER_CNTR0, (uint8_t)reload); /* lsb */ 363 outb(TIMER_CNTR0, (uint8_t)(reload >> 8)); /* msb */ 364 } 365 clock_unlock(); 366 } 367 368 /* 369 * DELAY(usec) - Spin for the specified number of microseconds. 370 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 371 * but do a thread switch in the loop 372 * 373 * Relies on timer 1 counting down from (cputimer_freq / hz) 374 * Note: timer had better have been programmed before this is first used! 375 */ 376 static void 377 DODELAY(int n, int doswitch) 378 { 379 ssysclock_t delta, ticks_left; 380 sysclock_t prev_tick, tick; 381 382 #ifdef DELAYDEBUG 383 int getit_calls = 1; 384 int n1; 385 static int state = 0; 386 387 if (state == 0) { 388 state = 1; 389 for (n1 = 1; n1 <= 10000000; n1 *= 10) 390 DELAY(n1); 391 state = 2; 392 } 393 if (state == 1) 394 kprintf("DELAY(%d)...", n); 395 #endif 396 /* 397 * Guard against the timer being uninitialized if we are called 398 * early for console i/o. 399 */ 400 if (timer0_state == RELEASED) 401 i8254_restore(); 402 403 /* 404 * Read the counter first, so that the rest of the setup overhead is 405 * counted. Then calculate the number of hardware timer ticks 406 * required, rounding up to be sure we delay at least the requested 407 * number of microseconds. 408 */ 409 prev_tick = sys_cputimer->count(); 410 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 411 1000000; 412 413 /* 414 * Loop until done. 415 */ 416 while (ticks_left > 0) { 417 tick = sys_cputimer->count(); 418 #ifdef DELAYDEBUG 419 ++getit_calls; 420 #endif 421 delta = tick - prev_tick; 422 prev_tick = tick; 423 if (delta < 0) 424 delta = 0; 425 ticks_left -= delta; 426 if (doswitch && ticks_left > 0) 427 lwkt_switch(); 428 cpu_pause(); 429 } 430 #ifdef DELAYDEBUG 431 if (state == 1) 432 kprintf(" %d calls to getit() at %d usec each\n", 433 getit_calls, (n + 5) / getit_calls); 434 #endif 435 } 436 437 /* 438 * DELAY() never switches. 439 */ 440 void 441 DELAY(int n) 442 { 443 DODELAY(n, 0); 444 } 445 446 /* 447 * Returns non-zero if the specified time period has elapsed. Call 448 * first with last_clock set to 0. 449 */ 450 int 451 CHECKTIMEOUT(TOTALDELAY *tdd) 452 { 453 sysclock_t delta; 454 int us; 455 456 if (tdd->started == 0) { 457 if (timer0_state == RELEASED) 458 i8254_restore(); 459 tdd->last_clock = sys_cputimer->count(); 460 tdd->started = 1; 461 return(0); 462 } 463 delta = sys_cputimer->count() - tdd->last_clock; 464 us = (u_int64_t)delta * (u_int64_t)1000000 / 465 (u_int64_t)sys_cputimer->freq; 466 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 467 1000000; 468 tdd->us -= us; 469 return (tdd->us < 0); 470 } 471 472 473 /* 474 * DRIVERSLEEP() does not switch if called with a spinlock held or 475 * from a hard interrupt. 476 */ 477 void 478 DRIVERSLEEP(int usec) 479 { 480 globaldata_t gd = mycpu; 481 482 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) { 483 DODELAY(usec, 0); 484 } else { 485 DODELAY(usec, 1); 486 } 487 } 488 489 static void 490 sysbeepstop(void *chan) 491 { 492 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 493 beeping = 0; 494 release_timer2(); 495 } 496 497 int 498 sysbeep(int pitch, int period) 499 { 500 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 501 return(-1); 502 if (sysbeep_enable == 0) 503 return(-1); 504 /* 505 * Nobody else is using timer2, we do not need the clock lock 506 */ 507 outb(TIMER_CNTR2, pitch); 508 outb(TIMER_CNTR2, (pitch>>8)); 509 if (!beeping) { 510 /* enable counter2 output to speaker */ 511 outb(IO_PPI, inb(IO_PPI) | 3); 512 beeping = period; 513 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 514 } 515 return (0); 516 } 517 518 /* 519 * RTC support routines 520 */ 521 522 int 523 rtcin(int reg) 524 { 525 u_char val; 526 527 crit_enter(); 528 outb(IO_RTC, reg); 529 inb(0x84); 530 val = inb(IO_RTC + 1); 531 inb(0x84); 532 crit_exit(); 533 return (val); 534 } 535 536 static __inline void 537 writertc(u_char reg, u_char val) 538 { 539 crit_enter(); 540 inb(0x84); 541 outb(IO_RTC, reg); 542 inb(0x84); 543 outb(IO_RTC + 1, val); 544 inb(0x84); /* XXX work around wrong order in rtcin() */ 545 crit_exit(); 546 } 547 548 static __inline int 549 readrtc(int port) 550 { 551 return(bcd2bin(rtcin(port))); 552 } 553 554 static u_int 555 calibrate_clocks(void) 556 { 557 u_int64_t old_tsc; 558 u_int tot_count; 559 sysclock_t count, prev_count; 560 int sec, start_sec, timeout; 561 562 if (bootverbose) 563 kprintf("Calibrating clock(s) ...\n"); 564 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 565 goto fail; 566 timeout = 100000000; 567 568 /* Read the mc146818A seconds counter. */ 569 for (;;) { 570 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 571 sec = rtcin(RTC_SEC); 572 break; 573 } 574 if (--timeout == 0) 575 goto fail; 576 } 577 578 /* Wait for the mC146818A seconds counter to change. */ 579 start_sec = sec; 580 for (;;) { 581 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 582 sec = rtcin(RTC_SEC); 583 if (sec != start_sec) 584 break; 585 } 586 if (--timeout == 0) 587 goto fail; 588 } 589 590 /* Start keeping track of the i8254 counter. */ 591 prev_count = sys_cputimer->count(); 592 tot_count = 0; 593 594 if (tsc_present) 595 old_tsc = rdtsc(); 596 else 597 old_tsc = 0; /* shut up gcc */ 598 599 /* 600 * Wait for the mc146818A seconds counter to change. Read the i8254 601 * counter for each iteration since this is convenient and only 602 * costs a few usec of inaccuracy. The timing of the final reads 603 * of the counters almost matches the timing of the initial reads, 604 * so the main cause of inaccuracy is the varying latency from 605 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 606 * rtcin(RTC_SEC) that returns a changed seconds count. The 607 * maximum inaccuracy from this cause is < 10 usec on 486's. 608 */ 609 start_sec = sec; 610 for (;;) { 611 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 612 sec = rtcin(RTC_SEC); 613 count = sys_cputimer->count(); 614 tot_count += (int)(count - prev_count); 615 prev_count = count; 616 if (sec != start_sec) 617 break; 618 if (--timeout == 0) 619 goto fail; 620 } 621 622 /* 623 * Read the cpu cycle counter. The timing considerations are 624 * similar to those for the i8254 clock. 625 */ 626 if (tsc_present) { 627 tsc_frequency = rdtsc() - old_tsc; 628 if (bootverbose) { 629 kprintf("TSC clock: %jd Hz (Method A)\n", 630 (intmax_t)tsc_frequency); 631 } 632 } 633 634 kprintf("i8254 clock: %u Hz\n", tot_count); 635 return (tot_count); 636 637 fail: 638 kprintf("failed, using default i8254 clock of %u Hz\n", 639 i8254_cputimer.freq); 640 return (i8254_cputimer.freq); 641 } 642 643 static void 644 i8254_restore(void) 645 { 646 timer0_state = ACQUIRED; 647 648 clock_lock(); 649 650 /* 651 * Timer0 is our fine-grained variable clock interrupt 652 */ 653 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 654 outb(TIMER_CNTR0, 2); /* lsb */ 655 outb(TIMER_CNTR0, 0); /* msb */ 656 clock_unlock(); 657 658 if (!i8254_nointr) { 659 cputimer_intr_register(&i8254_cputimer_intr); 660 cputimer_intr_select(&i8254_cputimer_intr, 0); 661 } 662 663 /* 664 * Timer1 or timer2 is our free-running clock, but only if another 665 * has not been selected. 666 */ 667 cputimer_register(&i8254_cputimer); 668 cputimer_select(&i8254_cputimer, 0); 669 } 670 671 static void 672 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 673 { 674 int which; 675 676 /* 677 * Should we use timer 1 or timer 2 ? 678 */ 679 which = 0; 680 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 681 if (which != 1 && which != 2) 682 which = 2; 683 684 switch(which) { 685 case 1: 686 timer->name = "i8254_timer1"; 687 timer->type = CPUTIMER_8254_SEL1; 688 i8254_walltimer_sel = TIMER_SEL1; 689 i8254_walltimer_cntr = TIMER_CNTR1; 690 timer1_state = ACQUIRED; 691 break; 692 case 2: 693 timer->name = "i8254_timer2"; 694 timer->type = CPUTIMER_8254_SEL2; 695 i8254_walltimer_sel = TIMER_SEL2; 696 i8254_walltimer_cntr = TIMER_CNTR2; 697 timer2_state = ACQUIRED; 698 break; 699 } 700 701 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 702 703 clock_lock(); 704 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 705 outb(i8254_walltimer_cntr, 0); /* lsb */ 706 outb(i8254_walltimer_cntr, 0); /* msb */ 707 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 708 clock_unlock(); 709 } 710 711 static void 712 i8254_cputimer_destruct(struct cputimer *timer) 713 { 714 switch(timer->type) { 715 case CPUTIMER_8254_SEL1: 716 timer1_state = RELEASED; 717 break; 718 case CPUTIMER_8254_SEL2: 719 timer2_state = RELEASED; 720 break; 721 default: 722 break; 723 } 724 timer->type = 0; 725 } 726 727 static void 728 rtc_restore(void) 729 { 730 /* Restore all of the RTC's "status" (actually, control) registers. */ 731 writertc(RTC_STATUSB, RTCSB_24HR); 732 writertc(RTC_STATUSA, rtc_statusa); 733 writertc(RTC_STATUSB, rtc_statusb); 734 } 735 736 /* 737 * Restore all the timers. 738 * 739 * This function is called to resynchronize our core timekeeping after a 740 * long halt, e.g. from apm_default_resume() and friends. It is also 741 * called if after a BIOS call we have detected munging of the 8254. 742 * It is necessary because cputimer_count() counter's delta may have grown 743 * too large for nanouptime() and friends to handle, or (in the case of 8254 744 * munging) might cause the SYSTIMER code to prematurely trigger. 745 */ 746 void 747 timer_restore(void) 748 { 749 crit_enter(); 750 i8254_restore(); /* restore timer_freq and hz */ 751 rtc_restore(); /* reenable RTC interrupts */ 752 crit_exit(); 753 } 754 755 /* 756 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 757 */ 758 void 759 startrtclock(void) 760 { 761 u_int delta, freq; 762 763 /* 764 * Can we use the TSC? 765 * 766 * NOTE: If running under qemu, probably a good idea to force the 767 * TSC because we are not likely to detect it as being 768 * invariant or mpsyncd if you don't. This will greatly 769 * reduce SMP contention. 770 */ 771 if (cpu_feature & CPUID_TSC) { 772 tsc_present = 1; 773 TUNABLE_INT_FETCH("hw.tsc_cputimer_force", &tsc_invariant); 774 775 if ((cpu_vendor_id == CPU_VENDOR_INTEL || 776 cpu_vendor_id == CPU_VENDOR_AMD) && 777 cpu_exthigh >= 0x80000007) { 778 u_int regs[4]; 779 780 do_cpuid(0x80000007, regs); 781 if (regs[3] & 0x100) 782 tsc_invariant = 1; 783 } 784 } else { 785 tsc_present = 0; 786 } 787 788 /* 789 * Initial RTC state, don't do anything unexpected 790 */ 791 writertc(RTC_STATUSA, rtc_statusa); 792 writertc(RTC_STATUSB, RTCSB_24HR); 793 794 /* 795 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 796 * generate an interrupt, which we will ignore for now. 797 * 798 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 799 * (so it counts a full 2^16 and repeats). We will use this timer 800 * for our counting. 801 */ 802 i8254_restore(); 803 freq = calibrate_clocks(); 804 #ifdef CLK_CALIBRATION_LOOP 805 if (bootverbose) { 806 int c; 807 808 cnpoll(TRUE); 809 kprintf("Press a key on the console to " 810 "abort clock calibration\n"); 811 while ((c = cncheckc()) == -1 || c == NOKEY) 812 calibrate_clocks(); 813 cnpoll(FALSE); 814 } 815 #endif 816 817 /* 818 * Use the calibrated i8254 frequency if it seems reasonable. 819 * Otherwise use the default, and don't use the calibrated i586 820 * frequency. 821 */ 822 delta = freq > i8254_cputimer.freq ? 823 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 824 if (delta < i8254_cputimer.freq / 100) { 825 #ifndef CLK_USE_I8254_CALIBRATION 826 if (bootverbose) 827 kprintf( 828 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 829 freq = i8254_cputimer.freq; 830 #endif 831 /* 832 * NOTE: 833 * Interrupt timer's freq must be adjusted 834 * before we change the cuptimer's frequency. 835 */ 836 i8254_cputimer_intr.freq = freq; 837 cputimer_set_frequency(&i8254_cputimer, freq); 838 } else { 839 if (bootverbose) 840 kprintf( 841 "%d Hz differs from default of %d Hz by more than 1%%\n", 842 freq, i8254_cputimer.freq); 843 tsc_frequency = 0; 844 } 845 846 #ifndef CLK_USE_TSC_CALIBRATION 847 if (tsc_frequency != 0) { 848 if (bootverbose) 849 kprintf( 850 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 851 tsc_frequency = 0; 852 } 853 #endif 854 if (tsc_present && tsc_frequency == 0) { 855 /* 856 * Calibration of the i586 clock relative to the mc146818A 857 * clock failed. Do a less accurate calibration relative 858 * to the i8254 clock. 859 */ 860 u_int64_t old_tsc = rdtsc(); 861 862 DELAY(1000000); 863 tsc_frequency = rdtsc() - old_tsc; 864 #ifdef CLK_USE_TSC_CALIBRATION 865 if (bootverbose) { 866 kprintf("TSC clock: %jd Hz (Method B)\n", 867 (intmax_t)tsc_frequency); 868 } 869 #endif 870 } 871 872 if (tsc_present) { 873 kprintf("TSC%s clock: %jd Hz\n", 874 tsc_invariant ? " invariant" : "", 875 (intmax_t)tsc_frequency); 876 } 877 878 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 879 } 880 881 /* 882 * Sync the time of day back to the RTC on shutdown, but only if 883 * we have already loaded it and have not crashed. 884 */ 885 static void 886 resettodr_on_shutdown(void *arg __unused) 887 { 888 if (rtc_loaded && panicstr == NULL) { 889 resettodr(); 890 } 891 } 892 893 /* 894 * Initialize the time of day register, based on the time base which is, e.g. 895 * from a filesystem. 896 */ 897 void 898 inittodr(time_t base) 899 { 900 unsigned long sec, days; 901 int year, month; 902 int y, m; 903 struct timespec ts; 904 905 if (base) { 906 ts.tv_sec = base; 907 ts.tv_nsec = 0; 908 set_timeofday(&ts); 909 } 910 911 /* Look if we have a RTC present and the time is valid */ 912 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 913 goto wrong_time; 914 915 /* wait for time update to complete */ 916 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 917 crit_enter(); 918 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 919 crit_exit(); 920 crit_enter(); 921 } 922 923 days = 0; 924 #ifdef USE_RTC_CENTURY 925 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 926 #else 927 year = readrtc(RTC_YEAR) + 1900; 928 if (year < 1970) 929 year += 100; 930 #endif 931 if (year < 1970) { 932 crit_exit(); 933 goto wrong_time; 934 } 935 month = readrtc(RTC_MONTH); 936 for (m = 1; m < month; m++) 937 days += daysinmonth[m-1]; 938 if ((month > 2) && LEAPYEAR(year)) 939 days ++; 940 days += readrtc(RTC_DAY) - 1; 941 for (y = 1970; y < year; y++) 942 days += DAYSPERYEAR + LEAPYEAR(y); 943 sec = ((( days * 24 + 944 readrtc(RTC_HRS)) * 60 + 945 readrtc(RTC_MIN)) * 60 + 946 readrtc(RTC_SEC)); 947 /* sec now contains the number of seconds, since Jan 1 1970, 948 in the local time zone */ 949 950 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 951 952 y = (int)(time_second - sec); 953 if (y <= -2 || y >= 2) { 954 /* badly off, adjust it */ 955 ts.tv_sec = sec; 956 ts.tv_nsec = 0; 957 set_timeofday(&ts); 958 } 959 rtc_loaded = 1; 960 crit_exit(); 961 return; 962 963 wrong_time: 964 kprintf("Invalid time in real time clock.\n"); 965 kprintf("Check and reset the date immediately!\n"); 966 } 967 968 /* 969 * Write system time back to RTC 970 */ 971 void 972 resettodr(void) 973 { 974 struct timeval tv; 975 unsigned long tm; 976 int m; 977 int y; 978 979 if (disable_rtc_set) 980 return; 981 982 microtime(&tv); 983 tm = tv.tv_sec; 984 985 crit_enter(); 986 /* Disable RTC updates and interrupts. */ 987 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 988 989 /* Calculate local time to put in RTC */ 990 991 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 992 993 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 994 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 995 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 996 997 /* We have now the days since 01-01-1970 in tm */ 998 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 999 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1000 tm >= m; 1001 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1002 tm -= m; 1003 1004 /* Now we have the years in y and the day-of-the-year in tm */ 1005 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1006 #ifdef USE_RTC_CENTURY 1007 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1008 #endif 1009 for (m = 0; ; m++) { 1010 int ml; 1011 1012 ml = daysinmonth[m]; 1013 if (m == 1 && LEAPYEAR(y)) 1014 ml++; 1015 if (tm < ml) 1016 break; 1017 tm -= ml; 1018 } 1019 1020 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1021 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1022 1023 /* Reenable RTC updates and interrupts. */ 1024 writertc(RTC_STATUSB, rtc_statusb); 1025 crit_exit(); 1026 } 1027 1028 static int 1029 i8254_ioapic_trial(int irq, struct cputimer_intr *cti) 1030 { 1031 sysclock_t base; 1032 long lastcnt; 1033 1034 /* 1035 * Following code assumes the 8254 is the cpu timer, 1036 * so make sure it is. 1037 */ 1038 KKASSERT(sys_cputimer == &i8254_cputimer); 1039 KKASSERT(cti == &i8254_cputimer_intr); 1040 1041 lastcnt = get_interrupt_counter(irq, mycpuid); 1042 1043 /* 1044 * Force an 8254 Timer0 interrupt and wait 1/100s for 1045 * it to happen, then see if we got it. 1046 */ 1047 kprintf("IOAPIC: testing 8254 interrupt delivery\n"); 1048 1049 i8254_intr_reload(cti, 2); 1050 base = sys_cputimer->count(); 1051 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1052 ; /* nothing */ 1053 1054 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0) 1055 return ENOENT; 1056 return 0; 1057 } 1058 1059 /* 1060 * Start both clocks running. DragonFly note: the stat clock is no longer 1061 * used. Instead, 8254 based systimers are used for all major clock 1062 * interrupts. 1063 */ 1064 static void 1065 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1066 { 1067 void *clkdesc = NULL; 1068 int irq = 0, mixed_mode = 0, error; 1069 1070 KKASSERT(mycpuid == 0); 1071 callout_init_mp(&sysbeepstop_ch); 1072 1073 if (!selected && i8254_intr_disable) 1074 goto nointr; 1075 1076 /* 1077 * The stat interrupt mask is different without the 1078 * statistics clock. Also, don't set the interrupt 1079 * flag which would normally cause the RTC to generate 1080 * interrupts. 1081 */ 1082 rtc_statusb = RTCSB_24HR; 1083 1084 /* Finish initializing 8254 timer 0. */ 1085 if (ioapic_enable) { 1086 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE, 1087 INTR_POLARITY_HIGH); 1088 if (irq < 0) { 1089 mixed_mode_setup: 1090 error = ioapic_conf_legacy_extint(0); 1091 if (!error) { 1092 irq = machintr_legacy_intr_find(0, 1093 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); 1094 if (irq < 0) 1095 error = ENOENT; 1096 } 1097 1098 if (error) { 1099 if (!selected) { 1100 kprintf("IOAPIC: setup mixed mode for " 1101 "irq 0 failed: %d\n", error); 1102 goto nointr; 1103 } else { 1104 panic("IOAPIC: setup mixed mode for " 1105 "irq 0 failed: %d\n", error); 1106 } 1107 } 1108 mixed_mode = 1; 1109 } 1110 clkdesc = register_int(irq, clkintr, NULL, "clk", 1111 NULL, 1112 INTR_EXCL | INTR_CLOCK | 1113 INTR_NOPOLL | INTR_MPSAFE | 1114 INTR_NOENTROPY, 0); 1115 } else { 1116 register_int(0, clkintr, NULL, "clk", NULL, 1117 INTR_EXCL | INTR_CLOCK | 1118 INTR_NOPOLL | INTR_MPSAFE | 1119 INTR_NOENTROPY, 0); 1120 } 1121 1122 /* Initialize RTC. */ 1123 writertc(RTC_STATUSA, rtc_statusa); 1124 writertc(RTC_STATUSB, RTCSB_24HR); 1125 1126 if (ioapic_enable) { 1127 error = i8254_ioapic_trial(irq, cti); 1128 if (error) { 1129 if (mixed_mode) { 1130 if (!selected) { 1131 kprintf("IOAPIC: mixed mode for irq %d " 1132 "trial failed: %d\n", 1133 irq, error); 1134 goto nointr; 1135 } else { 1136 panic("IOAPIC: mixed mode for irq %d " 1137 "trial failed: %d\n", irq, error); 1138 } 1139 } else { 1140 kprintf("IOAPIC: warning 8254 is not connected " 1141 "to the correct pin, try mixed mode\n"); 1142 unregister_int(clkdesc, 0); 1143 goto mixed_mode_setup; 1144 } 1145 } 1146 } 1147 return; 1148 1149 nointr: 1150 i8254_nointr = 1; /* don't try to register again */ 1151 cputimer_intr_deregister(cti); 1152 } 1153 1154 void 1155 setstatclockrate(int newhz) 1156 { 1157 if (newhz == RTC_PROFRATE) 1158 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1159 else 1160 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1161 writertc(RTC_STATUSA, rtc_statusa); 1162 } 1163 1164 #if 0 1165 static unsigned 1166 tsc_get_timecount(struct timecounter *tc) 1167 { 1168 return (rdtsc()); 1169 } 1170 #endif 1171 1172 #ifdef KERN_TIMESTAMP 1173 #define KERN_TIMESTAMP_SIZE 16384 1174 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1175 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1176 sizeof(tsc), "LU", "Kernel timestamps"); 1177 void 1178 _TSTMP(u_int32_t x) 1179 { 1180 static int i; 1181 1182 tsc[i] = (u_int32_t)rdtsc(); 1183 tsc[i+1] = x; 1184 i = i + 2; 1185 if (i >= KERN_TIMESTAMP_SIZE) 1186 i = 0; 1187 tsc[i] = 0; /* mark last entry */ 1188 } 1189 #endif /* KERN_TIMESTAMP */ 1190 1191 /* 1192 * 1193 */ 1194 1195 static int 1196 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1197 { 1198 sysclock_t count; 1199 uint64_t tscval; 1200 char buf[32]; 1201 1202 crit_enter(); 1203 if (sys_cputimer == &i8254_cputimer) 1204 count = sys_cputimer->count(); 1205 else 1206 count = 0; 1207 if (tsc_present) 1208 tscval = rdtsc(); 1209 else 1210 tscval = 0; 1211 crit_exit(); 1212 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1213 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1214 } 1215 1216 struct tsc_mpsync_arg { 1217 volatile uint64_t tsc_target; 1218 volatile int tsc_mpsync; 1219 }; 1220 1221 struct tsc_mpsync_thr { 1222 volatile int tsc_done_cnt; 1223 volatile int tsc_mpsync_cnt; 1224 }; 1225 1226 static void 1227 tsc_mpsync_test_remote(void *xarg) 1228 { 1229 struct tsc_mpsync_arg *arg = xarg; 1230 uint64_t tsc; 1231 1232 tsc = rdtsc_ordered(); 1233 if (tsc < arg->tsc_target) 1234 arg->tsc_mpsync = 0; 1235 } 1236 1237 static void 1238 tsc_mpsync_test_loop(struct tsc_mpsync_arg *arg) 1239 { 1240 struct globaldata *gd = mycpu; 1241 uint64_t test_end, test_begin; 1242 u_int i; 1243 1244 if (bootverbose) { 1245 kprintf("cpu%d: TSC testing MP synchronization ...\n", 1246 gd->gd_cpuid); 1247 } 1248 1249 test_begin = rdtsc_ordered(); 1250 /* Run test for 100ms */ 1251 test_end = test_begin + (tsc_frequency / 10); 1252 1253 arg->tsc_mpsync = 1; 1254 arg->tsc_target = test_begin; 1255 1256 #define TSC_TEST_TRYMAX 1000000 /* Make sure we could stop */ 1257 #define TSC_TEST_TRYMIN 50000 1258 1259 for (i = 0; i < TSC_TEST_TRYMAX; ++i) { 1260 struct lwkt_cpusync cs; 1261 1262 crit_enter(); 1263 lwkt_cpusync_init(&cs, gd->gd_other_cpus, 1264 tsc_mpsync_test_remote, arg); 1265 lwkt_cpusync_interlock(&cs); 1266 arg->tsc_target = rdtsc_ordered(); 1267 cpu_mfence(); 1268 lwkt_cpusync_deinterlock(&cs); 1269 crit_exit(); 1270 1271 if (!arg->tsc_mpsync) { 1272 kprintf("cpu%d: TSC is not MP synchronized @%u\n", 1273 gd->gd_cpuid, i); 1274 break; 1275 } 1276 if (arg->tsc_target > test_end && i >= TSC_TEST_TRYMIN) 1277 break; 1278 } 1279 1280 #undef TSC_TEST_TRYMIN 1281 #undef TSC_TEST_TRYMAX 1282 1283 if (arg->tsc_target == test_begin) { 1284 kprintf("cpu%d: TSC does not tick?!\n", gd->gd_cpuid); 1285 /* XXX disable TSC? */ 1286 tsc_invariant = 0; 1287 arg->tsc_mpsync = 0; 1288 return; 1289 } 1290 1291 if (arg->tsc_mpsync && bootverbose) { 1292 kprintf("cpu%d: TSC is MP synchronized after %u tries\n", 1293 gd->gd_cpuid, i); 1294 } 1295 } 1296 1297 static void 1298 tsc_mpsync_ap_thread(void *xthr) 1299 { 1300 struct tsc_mpsync_thr *thr = xthr; 1301 struct tsc_mpsync_arg arg; 1302 1303 tsc_mpsync_test_loop(&arg); 1304 if (arg.tsc_mpsync) { 1305 atomic_add_int(&thr->tsc_mpsync_cnt, 1); 1306 cpu_sfence(); 1307 } 1308 atomic_add_int(&thr->tsc_done_cnt, 1); 1309 1310 lwkt_exit(); 1311 } 1312 1313 static void 1314 tsc_mpsync_test(void) 1315 { 1316 struct tsc_mpsync_arg arg; 1317 1318 if (!tsc_invariant) { 1319 /* Not even invariant TSC */ 1320 return; 1321 } 1322 1323 if (ncpus == 1) { 1324 /* Only one CPU */ 1325 tsc_mpsync = 1; 1326 return; 1327 } 1328 1329 /* 1330 * Forcing can be used w/qemu to reduce contention 1331 */ 1332 TUNABLE_INT_FETCH("hw.tsc_cputimer_force", &tsc_mpsync); 1333 1334 if (tsc_mpsync == 0) { 1335 switch(cpu_vendor_id) { 1336 case CPU_VENDOR_INTEL: 1337 /* 1338 * Intel probably works 1339 */ 1340 break; 1341 case CPU_VENDOR_AMD: 1342 /* 1343 * AMD < Ryzen probably doesn't work 1344 */ 1345 if (CPUID_TO_FAMILY(cpu_id) < 0x17) 1346 return; 1347 break; 1348 default: 1349 /* probably won't work */ 1350 return; 1351 } 1352 } 1353 1354 /* 1355 * Test even if forced above. If forced, we will use the TSC 1356 * even if the test fails. 1357 */ 1358 kprintf("TSC testing MP synchronization ...\n"); 1359 1360 tsc_mpsync_test_loop(&arg); 1361 if (arg.tsc_mpsync) { 1362 struct tsc_mpsync_thr thr; 1363 int cpu; 1364 1365 /* 1366 * Test TSC MP synchronization on APs. 1367 */ 1368 1369 thr.tsc_done_cnt = 1; 1370 thr.tsc_mpsync_cnt = 1; 1371 1372 for (cpu = 0; cpu < ncpus; ++cpu) { 1373 if (cpu == mycpuid) 1374 continue; 1375 1376 lwkt_create(tsc_mpsync_ap_thread, &thr, NULL, 1377 NULL, 0, cpu, "tsc mpsync %d", cpu); 1378 } 1379 1380 while (thr.tsc_done_cnt != ncpus) { 1381 cpu_pause(); 1382 cpu_lfence(); 1383 } 1384 if (thr.tsc_mpsync_cnt == ncpus) 1385 tsc_mpsync = 1; 1386 } 1387 1388 if (tsc_mpsync) 1389 kprintf("TSC is MP synchronized\n"); 1390 else 1391 kprintf("TSC is not MP synchronized\n"); 1392 } 1393 SYSINIT(tsc_mpsync, SI_BOOT2_FINISH_SMP, SI_ORDER_ANY, tsc_mpsync_test, NULL); 1394 1395 #define TSC_CPUTIMER_FREQMAX 128000000 /* 128Mhz */ 1396 1397 static int tsc_cputimer_shift; 1398 1399 static void 1400 tsc_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 1401 { 1402 timer->base = 0; 1403 timer->base = oldclock - timer->count(); 1404 } 1405 1406 static __inline sysclock_t 1407 tsc_cputimer_count(void) 1408 { 1409 uint64_t tsc; 1410 1411 tsc = rdtsc(); 1412 tsc >>= tsc_cputimer_shift; 1413 1414 return (tsc + tsc_cputimer.base); 1415 } 1416 1417 static sysclock_t 1418 tsc_cputimer_count_lfence(void) 1419 { 1420 cpu_lfence(); 1421 return tsc_cputimer_count(); 1422 } 1423 1424 static sysclock_t 1425 tsc_cputimer_count_mfence(void) 1426 { 1427 cpu_mfence(); 1428 return tsc_cputimer_count(); 1429 } 1430 1431 static uint64_t 1432 tsc_cpucounter_count_lfence(void) 1433 { 1434 1435 cpu_lfence(); 1436 return (rdtsc()); 1437 } 1438 1439 static uint64_t 1440 tsc_cpucounter_count_mfence(void) 1441 { 1442 1443 cpu_mfence(); 1444 return (rdtsc()); 1445 } 1446 1447 static void 1448 tsc_cputimer_register(void) 1449 { 1450 uint64_t freq; 1451 int enable = 1; 1452 1453 if (!tsc_mpsync) { 1454 if (tsc_invariant) { 1455 /* Per-cpu cpucounter still works. */ 1456 goto regcnt; 1457 } 1458 return; 1459 } 1460 1461 TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable); 1462 if (!enable) 1463 return; 1464 1465 freq = tsc_frequency; 1466 while (freq > TSC_CPUTIMER_FREQMAX) { 1467 freq >>= 1; 1468 ++tsc_cputimer_shift; 1469 } 1470 kprintf("TSC: cputimer freq %ju, shift %d\n", 1471 (uintmax_t)freq, tsc_cputimer_shift); 1472 1473 tsc_cputimer.freq = freq; 1474 1475 if (cpu_vendor_id == CPU_VENDOR_INTEL) 1476 tsc_cputimer.count = tsc_cputimer_count_lfence; 1477 else 1478 tsc_cputimer.count = tsc_cputimer_count_mfence; /* safe bet */ 1479 1480 cputimer_register(&tsc_cputimer); 1481 cputimer_select(&tsc_cputimer, 0); 1482 1483 tsc_cpucounter.flags |= CPUCOUNTER_FLAG_MPSYNC; 1484 regcnt: 1485 tsc_cpucounter.freq = tsc_frequency; 1486 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 1487 tsc_cpucounter.count = 1488 tsc_cpucounter_count_lfence; 1489 } else { 1490 tsc_cpucounter.count = 1491 tsc_cpucounter_count_mfence; /* safe bet */ 1492 } 1493 cpucounter_register(&tsc_cpucounter); 1494 } 1495 SYSINIT(tsc_cputimer_reg, SI_BOOT2_POST_SMP, SI_ORDER_FIRST, 1496 tsc_cputimer_register, NULL); 1497 1498 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1499 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1500 "frequency"); 1501 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1502 0, 0, hw_i8254_timestamp, "A", ""); 1503 1504 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1505 &tsc_present, 0, "TSC Available"); 1506 SYSCTL_INT(_hw, OID_AUTO, tsc_invariant, CTLFLAG_RD, 1507 &tsc_invariant, 0, "Invariant TSC"); 1508 SYSCTL_INT(_hw, OID_AUTO, tsc_mpsync, CTLFLAG_RD, 1509 &tsc_mpsync, 0, "TSC is synchronized across CPUs"); 1510 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1511 &tsc_frequency, 0, "TSC Frequency"); 1512