1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "use_apm.h" 54 #include "opt_clock.h" 55 #endif 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/eventhandler.h> 60 #include <sys/time.h> 61 #include <sys/kernel.h> 62 #include <sys/bus.h> 63 #ifndef SMP 64 #include <sys/lock.h> 65 #endif 66 #include <sys/sysctl.h> 67 #include <sys/cons.h> 68 #include <sys/systimer.h> 69 #include <sys/globaldata.h> 70 #include <sys/thread2.h> 71 #include <sys/systimer.h> 72 #include <sys/machintr.h> 73 #include <sys/interrupt.h> 74 75 #include <machine/clock.h> 76 #ifdef CLK_CALIBRATION_LOOP 77 #endif 78 #include <machine/cputypes.h> 79 #include <machine/frame.h> 80 #include <machine/ipl.h> 81 #include <machine/limits.h> 82 #include <machine/md_var.h> 83 #include <machine/psl.h> 84 #include <machine/segments.h> 85 #include <machine/smp.h> 86 #include <machine/specialreg.h> 87 #include <machine/intr_machdep.h> 88 89 #ifdef SMP 90 #include <machine_base/apic/ioapic.h> 91 #include <machine_base/apic/ioapic_abi.h> 92 #endif 93 #include <machine_base/icu/icu.h> 94 #include <bus/isa/isa.h> 95 #include <bus/isa/rtc.h> 96 #include <machine_base/isa/timerreg.h> 97 98 static void i8254_restore(void); 99 static void resettodr_on_shutdown(void *arg __unused); 100 101 /* 102 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 103 * can use a simple formula for leap years. 104 */ 105 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 106 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 107 108 #ifndef TIMER_FREQ 109 #define TIMER_FREQ 1193182 110 #endif 111 112 static uint8_t i8254_walltimer_sel; 113 static uint16_t i8254_walltimer_cntr; 114 115 int adjkerntz; /* local offset from GMT in seconds */ 116 int disable_rtc_set; /* disable resettodr() if != 0 */ 117 int tsc_present; 118 int64_t tsc_frequency; 119 int tsc_is_broken; 120 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 121 int timer0_running; 122 enum tstate { RELEASED, ACQUIRED }; 123 enum tstate timer0_state; 124 enum tstate timer1_state; 125 enum tstate timer2_state; 126 127 static int beeping = 0; 128 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 129 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 130 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 131 static int rtc_loaded; 132 133 static int i8254_cputimer_div; 134 135 static int i8254_nointr; 136 static int i8254_intr_disable = 1; 137 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 138 139 static struct callout sysbeepstop_ch; 140 141 static sysclock_t i8254_cputimer_count(void); 142 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 143 static void i8254_cputimer_destruct(struct cputimer *cputimer); 144 145 static struct cputimer i8254_cputimer = { 146 SLIST_ENTRY_INITIALIZER, 147 "i8254", 148 CPUTIMER_PRI_8254, 149 0, 150 i8254_cputimer_count, 151 cputimer_default_fromhz, 152 cputimer_default_fromus, 153 i8254_cputimer_construct, 154 i8254_cputimer_destruct, 155 TIMER_FREQ, 156 0, 0, 0 157 }; 158 159 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 160 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 161 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 162 163 static struct cputimer_intr i8254_cputimer_intr = { 164 .freq = TIMER_FREQ, 165 .reload = i8254_intr_reload, 166 .enable = cputimer_intr_default_enable, 167 .config = i8254_intr_config, 168 .restart = cputimer_intr_default_restart, 169 .pmfixup = cputimer_intr_default_pmfixup, 170 .initclock = i8254_intr_initclock, 171 .next = SLIST_ENTRY_INITIALIZER, 172 .name = "i8254", 173 .type = CPUTIMER_INTR_8254, 174 .prio = CPUTIMER_INTR_PRIO_8254, 175 .caps = CPUTIMER_INTR_CAP_PS 176 }; 177 178 /* 179 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 180 * counting as of this interrupt. We use timer1 in free-running mode (not 181 * generating any interrupts) as our main counter. Each cpu has timeouts 182 * pending. 183 * 184 * This code is INTR_MPSAFE and may be called without the BGL held. 185 */ 186 static void 187 clkintr(void *dummy, void *frame_arg) 188 { 189 static sysclock_t sysclock_count; /* NOTE! Must be static */ 190 struct globaldata *gd = mycpu; 191 #ifdef SMP 192 struct globaldata *gscan; 193 int n; 194 #endif 195 196 /* 197 * SWSTROBE mode is a one-shot, the timer is no longer running 198 */ 199 timer0_running = 0; 200 201 /* 202 * XXX the dispatcher needs work. right now we call systimer_intr() 203 * directly or via IPI for any cpu with systimers queued, which is 204 * usually *ALL* of them. We need to use the LAPIC timer for this. 205 */ 206 sysclock_count = sys_cputimer->count(); 207 #ifdef SMP 208 for (n = 0; n < ncpus; ++n) { 209 gscan = globaldata_find(n); 210 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 211 continue; 212 if (gscan != gd) { 213 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 214 &sysclock_count, 1); 215 } else { 216 systimer_intr(&sysclock_count, 0, frame_arg); 217 } 218 } 219 #else 220 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) 221 systimer_intr(&sysclock_count, 0, frame_arg); 222 #endif 223 } 224 225 226 /* 227 * NOTE! not MP safe. 228 */ 229 int 230 acquire_timer2(int mode) 231 { 232 if (timer2_state != RELEASED) 233 return (-1); 234 timer2_state = ACQUIRED; 235 236 /* 237 * This access to the timer registers is as atomic as possible 238 * because it is a single instruction. We could do better if we 239 * knew the rate. 240 */ 241 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 242 return (0); 243 } 244 245 int 246 release_timer2(void) 247 { 248 if (timer2_state != ACQUIRED) 249 return (-1); 250 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 251 timer2_state = RELEASED; 252 return (0); 253 } 254 255 #include "opt_ddb.h" 256 #ifdef DDB 257 #include <ddb/ddb.h> 258 259 DB_SHOW_COMMAND(rtc, rtc) 260 { 261 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 262 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 263 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 264 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 265 } 266 #endif /* DDB */ 267 268 /* 269 * Return the current cpu timer count as a 32 bit integer. 270 */ 271 static 272 sysclock_t 273 i8254_cputimer_count(void) 274 { 275 static __uint16_t cputimer_last; 276 __uint16_t count; 277 sysclock_t ret; 278 279 clock_lock(); 280 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 281 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 282 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 283 count = -count; /* -> countup */ 284 if (count < cputimer_last) /* rollover */ 285 i8254_cputimer.base += 0x00010000; 286 ret = i8254_cputimer.base | count; 287 cputimer_last = count; 288 clock_unlock(); 289 return(ret); 290 } 291 292 /* 293 * This function is called whenever the system timebase changes, allowing 294 * us to calculate what is needed to convert a system timebase tick 295 * into an 8254 tick for the interrupt timer. If we can convert to a 296 * simple shift, multiplication, or division, we do so. Otherwise 64 297 * bit arithmatic is required every time the interrupt timer is reloaded. 298 */ 299 static void 300 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 301 { 302 int freq; 303 int div; 304 305 /* 306 * Will a simple divide do the trick? 307 */ 308 div = (timer->freq + (cti->freq / 2)) / cti->freq; 309 freq = cti->freq * div; 310 311 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 312 i8254_cputimer_div = div; 313 else 314 i8254_cputimer_div = 0; 315 } 316 317 /* 318 * Reload for the next timeout. It is possible for the reload value 319 * to be 0 or negative, indicating that an immediate timer interrupt 320 * is desired. For now make the minimum 2 ticks. 321 * 322 * We may have to convert from the system timebase to the 8254 timebase. 323 */ 324 static void 325 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 326 { 327 __uint16_t count; 328 329 if (i8254_cputimer_div) 330 reload /= i8254_cputimer_div; 331 else 332 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 333 334 if ((int)reload < 2) 335 reload = 2; 336 337 clock_lock(); 338 if (timer0_running) { 339 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 340 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 341 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 342 if (reload < count) { 343 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 344 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 345 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 346 } 347 } else { 348 timer0_running = 1; 349 if (reload > 0xFFFF) 350 reload = 0; /* full count */ 351 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 352 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 353 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 354 } 355 clock_unlock(); 356 } 357 358 /* 359 * DELAY(usec) - Spin for the specified number of microseconds. 360 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 361 * but do a thread switch in the loop 362 * 363 * Relies on timer 1 counting down from (cputimer_freq / hz) 364 * Note: timer had better have been programmed before this is first used! 365 */ 366 static void 367 DODELAY(int n, int doswitch) 368 { 369 int delta, prev_tick, tick, ticks_left; 370 371 #ifdef DELAYDEBUG 372 int getit_calls = 1; 373 int n1; 374 static int state = 0; 375 376 if (state == 0) { 377 state = 1; 378 for (n1 = 1; n1 <= 10000000; n1 *= 10) 379 DELAY(n1); 380 state = 2; 381 } 382 if (state == 1) 383 kprintf("DELAY(%d)...", n); 384 #endif 385 /* 386 * Guard against the timer being uninitialized if we are called 387 * early for console i/o. 388 */ 389 if (timer0_state == RELEASED) 390 i8254_restore(); 391 392 /* 393 * Read the counter first, so that the rest of the setup overhead is 394 * counted. Then calculate the number of hardware timer ticks 395 * required, rounding up to be sure we delay at least the requested 396 * number of microseconds. 397 */ 398 prev_tick = sys_cputimer->count(); 399 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 400 1000000; 401 402 /* 403 * Loop until done. 404 */ 405 while (ticks_left > 0) { 406 tick = sys_cputimer->count(); 407 #ifdef DELAYDEBUG 408 ++getit_calls; 409 #endif 410 delta = tick - prev_tick; 411 prev_tick = tick; 412 if (delta < 0) 413 delta = 0; 414 ticks_left -= delta; 415 if (doswitch && ticks_left > 0) 416 lwkt_switch(); 417 cpu_pause(); 418 } 419 #ifdef DELAYDEBUG 420 if (state == 1) 421 kprintf(" %d calls to getit() at %d usec each\n", 422 getit_calls, (n + 5) / getit_calls); 423 #endif 424 } 425 426 /* 427 * DELAY() never switches. 428 */ 429 void 430 DELAY(int n) 431 { 432 DODELAY(n, 0); 433 } 434 435 /* 436 * Returns non-zero if the specified time period has elapsed. Call 437 * first with last_clock set to 0. 438 */ 439 int 440 CHECKTIMEOUT(TOTALDELAY *tdd) 441 { 442 sysclock_t delta; 443 int us; 444 445 if (tdd->started == 0) { 446 if (timer0_state == RELEASED) 447 i8254_restore(); 448 tdd->last_clock = sys_cputimer->count(); 449 tdd->started = 1; 450 return(0); 451 } 452 delta = sys_cputimer->count() - tdd->last_clock; 453 us = (u_int64_t)delta * (u_int64_t)1000000 / 454 (u_int64_t)sys_cputimer->freq; 455 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 456 1000000; 457 tdd->us -= us; 458 return (tdd->us < 0); 459 } 460 461 462 /* 463 * DRIVERSLEEP() does not switch if called with a spinlock held or 464 * from a hard interrupt. 465 */ 466 void 467 DRIVERSLEEP(int usec) 468 { 469 globaldata_t gd = mycpu; 470 471 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) { 472 DODELAY(usec, 0); 473 } else { 474 DODELAY(usec, 1); 475 } 476 } 477 478 static void 479 sysbeepstop(void *chan) 480 { 481 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 482 beeping = 0; 483 release_timer2(); 484 } 485 486 int 487 sysbeep(int pitch, int period) 488 { 489 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 490 return(-1); 491 if (sysbeep_enable == 0) 492 return(-1); 493 /* 494 * Nobody else is using timer2, we do not need the clock lock 495 */ 496 outb(TIMER_CNTR2, pitch); 497 outb(TIMER_CNTR2, (pitch>>8)); 498 if (!beeping) { 499 /* enable counter2 output to speaker */ 500 outb(IO_PPI, inb(IO_PPI) | 3); 501 beeping = period; 502 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 503 } 504 return (0); 505 } 506 507 /* 508 * RTC support routines 509 */ 510 511 int 512 rtcin(int reg) 513 { 514 u_char val; 515 516 crit_enter(); 517 outb(IO_RTC, reg); 518 inb(0x84); 519 val = inb(IO_RTC + 1); 520 inb(0x84); 521 crit_exit(); 522 return (val); 523 } 524 525 static __inline void 526 writertc(u_char reg, u_char val) 527 { 528 crit_enter(); 529 inb(0x84); 530 outb(IO_RTC, reg); 531 inb(0x84); 532 outb(IO_RTC + 1, val); 533 inb(0x84); /* XXX work around wrong order in rtcin() */ 534 crit_exit(); 535 } 536 537 static __inline int 538 readrtc(int port) 539 { 540 return(bcd2bin(rtcin(port))); 541 } 542 543 static u_int 544 calibrate_clocks(void) 545 { 546 u_int64_t old_tsc; 547 u_int count, prev_count, tot_count; 548 int sec, start_sec, timeout; 549 550 if (bootverbose) 551 kprintf("Calibrating clock(s) ... "); 552 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 553 goto fail; 554 timeout = 100000000; 555 556 /* Read the mc146818A seconds counter. */ 557 for (;;) { 558 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 559 sec = rtcin(RTC_SEC); 560 break; 561 } 562 if (--timeout == 0) 563 goto fail; 564 } 565 566 /* Wait for the mC146818A seconds counter to change. */ 567 start_sec = sec; 568 for (;;) { 569 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 570 sec = rtcin(RTC_SEC); 571 if (sec != start_sec) 572 break; 573 } 574 if (--timeout == 0) 575 goto fail; 576 } 577 578 /* Start keeping track of the i8254 counter. */ 579 prev_count = sys_cputimer->count(); 580 tot_count = 0; 581 582 if (tsc_present) 583 old_tsc = rdtsc(); 584 else 585 old_tsc = 0; /* shut up gcc */ 586 587 /* 588 * Wait for the mc146818A seconds counter to change. Read the i8254 589 * counter for each iteration since this is convenient and only 590 * costs a few usec of inaccuracy. The timing of the final reads 591 * of the counters almost matches the timing of the initial reads, 592 * so the main cause of inaccuracy is the varying latency from 593 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 594 * rtcin(RTC_SEC) that returns a changed seconds count. The 595 * maximum inaccuracy from this cause is < 10 usec on 486's. 596 */ 597 start_sec = sec; 598 for (;;) { 599 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 600 sec = rtcin(RTC_SEC); 601 count = sys_cputimer->count(); 602 tot_count += (int)(count - prev_count); 603 prev_count = count; 604 if (sec != start_sec) 605 break; 606 if (--timeout == 0) 607 goto fail; 608 } 609 610 /* 611 * Read the cpu cycle counter. The timing considerations are 612 * similar to those for the i8254 clock. 613 */ 614 if (tsc_present) { 615 tsc_frequency = rdtsc() - old_tsc; 616 } 617 618 if (tsc_present) 619 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 620 kprintf("i8254 clock: %u Hz\n", tot_count); 621 return (tot_count); 622 623 fail: 624 kprintf("failed, using default i8254 clock of %u Hz\n", 625 i8254_cputimer.freq); 626 return (i8254_cputimer.freq); 627 } 628 629 static void 630 i8254_restore(void) 631 { 632 timer0_state = ACQUIRED; 633 634 clock_lock(); 635 636 /* 637 * Timer0 is our fine-grained variable clock interrupt 638 */ 639 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 640 outb(TIMER_CNTR0, 2); /* lsb */ 641 outb(TIMER_CNTR0, 0); /* msb */ 642 clock_unlock(); 643 644 if (!i8254_nointr) { 645 cputimer_intr_register(&i8254_cputimer_intr); 646 cputimer_intr_select(&i8254_cputimer_intr, 0); 647 } 648 649 /* 650 * Timer1 or timer2 is our free-running clock, but only if another 651 * has not been selected. 652 */ 653 cputimer_register(&i8254_cputimer); 654 cputimer_select(&i8254_cputimer, 0); 655 } 656 657 static void 658 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 659 { 660 int which; 661 662 /* 663 * Should we use timer 1 or timer 2 ? 664 */ 665 which = 0; 666 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 667 if (which != 1 && which != 2) 668 which = 2; 669 670 switch(which) { 671 case 1: 672 timer->name = "i8254_timer1"; 673 timer->type = CPUTIMER_8254_SEL1; 674 i8254_walltimer_sel = TIMER_SEL1; 675 i8254_walltimer_cntr = TIMER_CNTR1; 676 timer1_state = ACQUIRED; 677 break; 678 case 2: 679 timer->name = "i8254_timer2"; 680 timer->type = CPUTIMER_8254_SEL2; 681 i8254_walltimer_sel = TIMER_SEL2; 682 i8254_walltimer_cntr = TIMER_CNTR2; 683 timer2_state = ACQUIRED; 684 break; 685 } 686 687 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 688 689 clock_lock(); 690 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 691 outb(i8254_walltimer_cntr, 0); /* lsb */ 692 outb(i8254_walltimer_cntr, 0); /* msb */ 693 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 694 clock_unlock(); 695 } 696 697 static void 698 i8254_cputimer_destruct(struct cputimer *timer) 699 { 700 switch(timer->type) { 701 case CPUTIMER_8254_SEL1: 702 timer1_state = RELEASED; 703 break; 704 case CPUTIMER_8254_SEL2: 705 timer2_state = RELEASED; 706 break; 707 default: 708 break; 709 } 710 timer->type = 0; 711 } 712 713 static void 714 rtc_restore(void) 715 { 716 /* Restore all of the RTC's "status" (actually, control) registers. */ 717 writertc(RTC_STATUSB, RTCSB_24HR); 718 writertc(RTC_STATUSA, rtc_statusa); 719 writertc(RTC_STATUSB, rtc_statusb); 720 } 721 722 /* 723 * Restore all the timers. 724 * 725 * This function is called to resynchronize our core timekeeping after a 726 * long halt, e.g. from apm_default_resume() and friends. It is also 727 * called if after a BIOS call we have detected munging of the 8254. 728 * It is necessary because cputimer_count() counter's delta may have grown 729 * too large for nanouptime() and friends to handle, or (in the case of 8254 730 * munging) might cause the SYSTIMER code to prematurely trigger. 731 */ 732 void 733 timer_restore(void) 734 { 735 crit_enter(); 736 i8254_restore(); /* restore timer_freq and hz */ 737 rtc_restore(); /* reenable RTC interrupts */ 738 crit_exit(); 739 } 740 741 /* 742 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 743 */ 744 void 745 startrtclock(void) 746 { 747 u_int delta, freq; 748 749 /* 750 * Can we use the TSC? 751 */ 752 if (cpu_feature & CPUID_TSC) 753 tsc_present = 1; 754 else 755 tsc_present = 0; 756 757 /* 758 * Initial RTC state, don't do anything unexpected 759 */ 760 writertc(RTC_STATUSA, rtc_statusa); 761 writertc(RTC_STATUSB, RTCSB_24HR); 762 763 /* 764 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 765 * generate an interrupt, which we will ignore for now. 766 * 767 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 768 * (so it counts a full 2^16 and repeats). We will use this timer 769 * for our counting. 770 */ 771 i8254_restore(); 772 freq = calibrate_clocks(); 773 #ifdef CLK_CALIBRATION_LOOP 774 if (bootverbose) { 775 kprintf( 776 "Press a key on the console to abort clock calibration\n"); 777 while (cncheckc() == -1) 778 calibrate_clocks(); 779 } 780 #endif 781 782 /* 783 * Use the calibrated i8254 frequency if it seems reasonable. 784 * Otherwise use the default, and don't use the calibrated i586 785 * frequency. 786 */ 787 delta = freq > i8254_cputimer.freq ? 788 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 789 if (delta < i8254_cputimer.freq / 100) { 790 #ifndef CLK_USE_I8254_CALIBRATION 791 if (bootverbose) 792 kprintf( 793 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 794 freq = i8254_cputimer.freq; 795 #endif 796 /* 797 * NOTE: 798 * Interrupt timer's freq must be adjusted 799 * before we change the cuptimer's frequency. 800 */ 801 i8254_cputimer_intr.freq = freq; 802 cputimer_set_frequency(&i8254_cputimer, freq); 803 } else { 804 if (bootverbose) 805 kprintf( 806 "%d Hz differs from default of %d Hz by more than 1%%\n", 807 freq, i8254_cputimer.freq); 808 tsc_frequency = 0; 809 } 810 811 #ifndef CLK_USE_TSC_CALIBRATION 812 if (tsc_frequency != 0) { 813 if (bootverbose) 814 kprintf( 815 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 816 tsc_frequency = 0; 817 } 818 #endif 819 if (tsc_present && tsc_frequency == 0) { 820 /* 821 * Calibration of the i586 clock relative to the mc146818A 822 * clock failed. Do a less accurate calibration relative 823 * to the i8254 clock. 824 */ 825 u_int64_t old_tsc = rdtsc(); 826 827 DELAY(1000000); 828 tsc_frequency = rdtsc() - old_tsc; 829 #ifdef CLK_USE_TSC_CALIBRATION 830 if (bootverbose) { 831 kprintf("TSC clock: %llu Hz (Method B)\n", 832 tsc_frequency); 833 } 834 #endif 835 } 836 837 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 838 839 #if !defined(SMP) 840 /* 841 * We can not use the TSC in SMP mode, until we figure out a 842 * cheap (impossible), reliable and precise (yeah right!) way 843 * to synchronize the TSCs of all the CPUs. 844 * Curse Intel for leaving the counter out of the I/O APIC. 845 */ 846 847 #if NAPM > 0 848 /* 849 * We can not use the TSC if we support APM. Precise timekeeping 850 * on an APM'ed machine is at best a fools pursuit, since 851 * any and all of the time spent in various SMM code can't 852 * be reliably accounted for. Reading the RTC is your only 853 * source of reliable time info. The i8254 looses too of course 854 * but we need to have some kind of time... 855 * We don't know at this point whether APM is going to be used 856 * or not, nor when it might be activated. Play it safe. 857 */ 858 return; 859 #endif /* NAPM > 0 */ 860 861 #endif /* !defined(SMP) */ 862 } 863 864 /* 865 * Sync the time of day back to the RTC on shutdown, but only if 866 * we have already loaded it and have not crashed. 867 */ 868 static void 869 resettodr_on_shutdown(void *arg __unused) 870 { 871 if (rtc_loaded && panicstr == NULL) { 872 resettodr(); 873 } 874 } 875 876 /* 877 * Initialize the time of day register, based on the time base which is, e.g. 878 * from a filesystem. 879 */ 880 void 881 inittodr(time_t base) 882 { 883 unsigned long sec, days; 884 int year, month; 885 int y, m; 886 struct timespec ts; 887 888 if (base) { 889 ts.tv_sec = base; 890 ts.tv_nsec = 0; 891 set_timeofday(&ts); 892 } 893 894 /* Look if we have a RTC present and the time is valid */ 895 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 896 goto wrong_time; 897 898 /* wait for time update to complete */ 899 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 900 crit_enter(); 901 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 902 crit_exit(); 903 crit_enter(); 904 } 905 906 days = 0; 907 #ifdef USE_RTC_CENTURY 908 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 909 #else 910 year = readrtc(RTC_YEAR) + 1900; 911 if (year < 1970) 912 year += 100; 913 #endif 914 if (year < 1970) { 915 crit_exit(); 916 goto wrong_time; 917 } 918 month = readrtc(RTC_MONTH); 919 for (m = 1; m < month; m++) 920 days += daysinmonth[m-1]; 921 if ((month > 2) && LEAPYEAR(year)) 922 days ++; 923 days += readrtc(RTC_DAY) - 1; 924 for (y = 1970; y < year; y++) 925 days += DAYSPERYEAR + LEAPYEAR(y); 926 sec = ((( days * 24 + 927 readrtc(RTC_HRS)) * 60 + 928 readrtc(RTC_MIN)) * 60 + 929 readrtc(RTC_SEC)); 930 /* sec now contains the number of seconds, since Jan 1 1970, 931 in the local time zone */ 932 933 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 934 935 y = time_second - sec; 936 if (y <= -2 || y >= 2) { 937 /* badly off, adjust it */ 938 ts.tv_sec = sec; 939 ts.tv_nsec = 0; 940 set_timeofday(&ts); 941 } 942 rtc_loaded = 1; 943 crit_exit(); 944 return; 945 946 wrong_time: 947 kprintf("Invalid time in real time clock.\n"); 948 kprintf("Check and reset the date immediately!\n"); 949 } 950 951 /* 952 * Write system time back to RTC 953 */ 954 void 955 resettodr(void) 956 { 957 struct timeval tv; 958 unsigned long tm; 959 int m; 960 int y; 961 962 if (disable_rtc_set) 963 return; 964 965 microtime(&tv); 966 tm = tv.tv_sec; 967 968 crit_enter(); 969 /* Disable RTC updates and interrupts. */ 970 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 971 972 /* Calculate local time to put in RTC */ 973 974 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 975 976 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 977 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 978 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 979 980 /* We have now the days since 01-01-1970 in tm */ 981 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 982 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 983 tm >= m; 984 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 985 tm -= m; 986 987 /* Now we have the years in y and the day-of-the-year in tm */ 988 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 989 #ifdef USE_RTC_CENTURY 990 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 991 #endif 992 for (m = 0; ; m++) { 993 int ml; 994 995 ml = daysinmonth[m]; 996 if (m == 1 && LEAPYEAR(y)) 997 ml++; 998 if (tm < ml) 999 break; 1000 tm -= ml; 1001 } 1002 1003 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1004 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1005 1006 /* Reenable RTC updates and interrupts. */ 1007 writertc(RTC_STATUSB, rtc_statusb); 1008 crit_exit(); 1009 } 1010 1011 #ifdef SMP 1012 1013 static int 1014 i8254_ioapic_trial(int irq, struct cputimer_intr *cti) 1015 { 1016 sysclock_t base; 1017 long lastcnt; 1018 1019 /* 1020 * Following code assumes the 8254 is the cpu timer, 1021 * so make sure it is. 1022 */ 1023 KKASSERT(sys_cputimer == &i8254_cputimer); 1024 KKASSERT(cti == &i8254_cputimer_intr); 1025 1026 lastcnt = get_interrupt_counter(irq); 1027 1028 /* 1029 * Force an 8254 Timer0 interrupt and wait 1/100s for 1030 * it to happen, then see if we got it. 1031 */ 1032 kprintf("IOAPIC: testing 8254 interrupt delivery\n"); 1033 1034 i8254_intr_reload(cti, 2); 1035 base = sys_cputimer->count(); 1036 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1037 ; /* nothing */ 1038 1039 if (get_interrupt_counter(irq) - lastcnt == 0) 1040 return ENOENT; 1041 return 0; 1042 } 1043 1044 #endif /* SMP */ 1045 1046 /* 1047 * Start both clocks running. DragonFly note: the stat clock is no longer 1048 * used. Instead, 8254 based systimers are used for all major clock 1049 * interrupts. 1050 */ 1051 static void 1052 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1053 { 1054 #ifdef SMP /* APIC-IO */ 1055 void *clkdesc = NULL; 1056 int irq = 0, mixed_mode = 0, error; 1057 #endif 1058 1059 callout_init(&sysbeepstop_ch); 1060 1061 if (!selected && i8254_intr_disable) 1062 goto nointr; 1063 1064 /* 1065 * The stat interrupt mask is different without the 1066 * statistics clock. Also, don't set the interrupt 1067 * flag which would normally cause the RTC to generate 1068 * interrupts. 1069 */ 1070 rtc_statusb = RTCSB_24HR; 1071 1072 /* Finish initializing 8254 timer 0. */ 1073 #ifdef SMP 1074 if (ioapic_enable) { 1075 irq = ioapic_abi_find_irq(0, INTR_TRIGGER_EDGE, 1076 INTR_POLARITY_HIGH); 1077 if (irq < 0) { 1078 mixed_mode_setup: 1079 error = ioapic_abi_extint_irqmap(0); 1080 if (!error) { 1081 irq = ioapic_abi_find_irq(0, INTR_TRIGGER_EDGE, 1082 INTR_POLARITY_HIGH); 1083 if (irq < 0) 1084 error = ENOENT; 1085 } 1086 1087 if (error) { 1088 if (!selected) { 1089 kprintf("IOAPIC: setup mixed mode for " 1090 "irq 0 failed: %d\n", error); 1091 goto nointr; 1092 } else { 1093 panic("IOAPIC: setup mixed mode for " 1094 "irq 0 failed: %d\n", error); 1095 } 1096 } 1097 mixed_mode = 1; 1098 } 1099 clkdesc = register_int(irq, clkintr, NULL, "clk", 1100 NULL, 1101 INTR_EXCL | INTR_CLOCK | 1102 INTR_NOPOLL | INTR_MPSAFE | 1103 INTR_NOENTROPY); 1104 machintr_intren(irq); 1105 } else { 1106 #endif 1107 register_int(0, clkintr, NULL, "clk", NULL, 1108 INTR_EXCL | INTR_CLOCK | 1109 INTR_NOPOLL | INTR_MPSAFE | 1110 INTR_NOENTROPY); 1111 machintr_intren(0); 1112 #ifdef SMP /* APIC-IO */ 1113 } 1114 #endif 1115 1116 /* Initialize RTC. */ 1117 writertc(RTC_STATUSA, rtc_statusa); 1118 writertc(RTC_STATUSB, RTCSB_24HR); 1119 1120 #ifdef SMP 1121 if (ioapic_enable) { 1122 error = i8254_ioapic_trial(irq, cti); 1123 if (error) { 1124 if (mixed_mode) { 1125 if (!selected) { 1126 kprintf("IOAPIC: mixed mode for irq %d " 1127 "trial failed: %d\n", 1128 irq, error); 1129 goto nointr; 1130 } else { 1131 panic("IOAPIC: mixed mode for irq %d " 1132 "trial failed: %d\n", irq, error); 1133 } 1134 } else { 1135 kprintf("IOAPIC: warning 8254 is not connected " 1136 "to the correct pin, try mixed mode\n"); 1137 machintr_intrdis(irq); 1138 unregister_int(clkdesc); 1139 goto mixed_mode_setup; 1140 } 1141 } 1142 } 1143 #endif 1144 return; 1145 1146 nointr: 1147 i8254_nointr = 1; /* don't try to register again */ 1148 cputimer_intr_deregister(cti); 1149 } 1150 1151 void 1152 setstatclockrate(int newhz) 1153 { 1154 if (newhz == RTC_PROFRATE) 1155 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1156 else 1157 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1158 writertc(RTC_STATUSA, rtc_statusa); 1159 } 1160 1161 #if 0 1162 static unsigned 1163 tsc_get_timecount(struct timecounter *tc) 1164 { 1165 return (rdtsc()); 1166 } 1167 #endif 1168 1169 #ifdef KERN_TIMESTAMP 1170 #define KERN_TIMESTAMP_SIZE 16384 1171 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1172 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1173 sizeof(tsc), "LU", "Kernel timestamps"); 1174 void 1175 _TSTMP(u_int32_t x) 1176 { 1177 static int i; 1178 1179 tsc[i] = (u_int32_t)rdtsc(); 1180 tsc[i+1] = x; 1181 i = i + 2; 1182 if (i >= KERN_TIMESTAMP_SIZE) 1183 i = 0; 1184 tsc[i] = 0; /* mark last entry */ 1185 } 1186 #endif /* KERN_TIMESTAMP */ 1187 1188 /* 1189 * 1190 */ 1191 1192 static int 1193 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1194 { 1195 sysclock_t count; 1196 __uint64_t tscval; 1197 char buf[32]; 1198 1199 crit_enter(); 1200 if (sys_cputimer == &i8254_cputimer) 1201 count = sys_cputimer->count(); 1202 else 1203 count = 0; 1204 if (tsc_present) 1205 tscval = rdtsc(); 1206 else 1207 tscval = 0; 1208 crit_exit(); 1209 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1210 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1211 } 1212 1213 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1214 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1215 "frequency"); 1216 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1217 0, 0, hw_i8254_timestamp, "A", ""); 1218 1219 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1220 &tsc_present, 0, "TSC Available"); 1221 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1222 &tsc_frequency, 0, "TSC Frequency"); 1223 1224