1 /*- 2 * Copyright (c) 1993 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp 35 * $FreeBSD: src/sys/i386/isa/timerreg.h,v 1.6 1999/08/28 00:45:04 peter Exp $ 36 * $DragonFly: src/sys/platform/pc64/isa/timerreg.h,v 1.1 2008/08/29 17:07:20 dillon Exp $ 37 */ 38 39 /* 40 * 41 * Register definitions for the Intel 8253 Programmable Interval Timer. 42 * 43 * This chip has three independent 16-bit down counters that can be 44 * read on the fly. There are three mode registers and three countdown 45 * registers. The countdown registers are addressed directly, via the 46 * first three I/O ports. The three mode registers are accessed via 47 * the fourth I/O port, with two bits in the mode byte indicating the 48 * register. (Why are hardware interfaces always so braindead?). 49 * 50 * To write a value into the countdown register, the mode register 51 * is first programmed with a command indicating the which byte of 52 * the two byte register is to be modified. The three possibilities 53 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then 54 * msb (TMR_MR_BOTH). 55 * 56 * To read the current value ("on the fly") from the countdown register, 57 * you write a "latch" command into the mode register, then read the stable 58 * value from the corresponding I/O port. For example, you write 59 * TMR_MR_LATCH into the corresponding mode register. Presumably, 60 * after doing this, a write operation to the I/O port would result 61 * in undefined behavior (but hopefully not fry the chip). 62 * Reading in this manner has no side effects. 63 * 64 * [IBM-PC] 65 * The outputs of the three timers are connected as follows: 66 * 67 * timer 0 -> irq 0 68 * timer 1 -> dma chan 0 (for dram refresh) 69 * timer 2 -> speaker (via keyboard controller) 70 * 71 * Timer 0 is used to call hardclock. 72 * Timer 2 is used to generate console beeps. 73 * 74 * [PC-9801] 75 * The outputs of the three timers are connected as follows: 76 * 77 * timer 0 -> irq 0 78 * timer 1 -> speaker (via keyboard controller) 79 * timer 2 -> RS232C 80 * 81 * Timer 0 is used to call hardclock. 82 * Timer 1 is used to generate console beeps. 83 * 84 * TIMER_INTTC: Interrupt on Terminal Count. OUT initially low, 85 * goes high on terminal count and remains 86 * high until a new count or a mode 0 control 87 * word is written. 88 * 89 * TIMER_ONESHOT: Hardware Retriggerable One Shot. Out initially high, 90 * out goes low following the trigger and remains low 91 * until terminal count, then goes high and remains 92 * high until the next trigger. 93 * 94 * TIMER_RATEGEN: Rate Generator. OUT is initially high. When the 95 * count has decremented to 1 OUT goes low for one CLK 96 * pulse, then goes high again. Counter reloads and 97 * the sequence is repeated. 98 * 99 * TIMER_SQWAVE: Square Wave Generator. OUT is initially high. When 100 * half the count is expired, OUT goes low. Counter 101 * reloads, OUT goes high, and the sequence repepats. 102 * 103 * TIMER_SWSTROBE: S/W Triggered Strobe. OUT initially high. On 104 * terminal count OUT goes low for one CLK pulse 105 * and then goes high again. Counting stops. 106 * The counting sequence is 'triggered' by writing 107 * the initial count. Writing a control word and 108 * initial count resets and reloads the counter. 109 * 110 * TIMER_HWSTROBE: H/W Triggered Strobe. OUT initially high. A rising 111 * edge on GATE loads the counter and counting begins. 112 * On terminal count OUT goes low for one CLK and then 113 * high again. 114 * 115 * NOTE: the largest possible initial count is 0x0000. This is equivalent 116 * to 2^16 binary and 10^4 BCD counts. The counter does not stop when it 117 * reaches zero. In Modes INTTC, ONESHOT, SWSTROBE, and HWSTROBE the 118 * counter wraps aroudn to the highest count (0xFFFF or 9999bcd) and 119 * continues counting. In MODES RATEGEN and SQWAVE (which are periodic) 120 * the counter reloads itself with the initial count and continues counting 121 * from there. 122 */ 123 124 /* 125 * Macros for specifying values to be written into a mode register. 126 */ 127 #define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ 128 #define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ 129 #define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ 130 #define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ 131 #define TIMER_SEL0 0x00 /* select counter 0 */ 132 #define TIMER_SEL1 0x40 /* select counter 1 */ 133 #define TIMER_SEL2 0x80 /* select counter 2 */ 134 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 135 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 136 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 137 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 138 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 139 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 140 #define TIMER_LATCH 0x00 /* latch counter for reading */ 141 #define TIMER_LSB 0x10 /* r/w counter LSB */ 142 #define TIMER_MSB 0x20 /* r/w counter MSB */ 143 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 144 #define TIMER_BCD 0x01 /* count in BCD */ 145 146