1/*- 2 * Copyright (c) 1989, 1990 William F. Jolitz. 3 * Copyright (c) 1990 The Regents of the University of California. 4 * Copyright (c) 2007 The FreeBSD Foundation 5 * Copyright (c) 2008 The DragonFly Project. 6 * Copyright (c) 2008 Jordan Gordeev. 7 * All rights reserved. 8 * 9 * Portions of this software were developed by A. Joseph Koshy under 10 * sponsorship from the FreeBSD Foundation and Google, Inc. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37#if JG 38#include "opt_atpic.h" 39#endif 40#include "opt_compat.h" 41 42#include <machine/asmacros.h> 43#include <machine/psl.h> 44#include <machine/trap.h> 45#include <machine/segments.h> 46 47#include "assym.s" 48 49 .text 50 51/*****************************************************************************/ 52/* Trap handling */ 53/*****************************************************************************/ 54/* 55 * Trap and fault vector routines. 56 * 57 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes 58 * state on the stack but also disables interrupts. This is important for 59 * us for the use of the swapgs instruction. We cannot be interrupted 60 * until the GS.base value is correct. For most traps, we automatically 61 * then enable interrupts if the interrupted context had them enabled. 62 * This is equivalent to the i386 port's use of SDT_SYS386TGT. 63 * 64 * The cpu will push a certain amount of state onto the kernel stack for 65 * the current process. See x86_64/include/frame.h. 66 * This includes the current RFLAGS (status register, which includes 67 * the interrupt disable state prior to the trap), the code segment register, 68 * and the return instruction pointer are pushed by the cpu. The cpu 69 * will also push an 'error' code for certain traps. We push a dummy 70 * error code for those traps where the cpu doesn't in order to maintain 71 * a consistent frame. We also push a contrived 'trap number'. 72 * 73 * The cpu does not push the general registers, we must do that, and we 74 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and 75 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we 76 * must load them with appropriate values for supervisor mode operation. 77 */ 78 79MCOUNT_LABEL(user) 80MCOUNT_LABEL(btrap) 81 82/* Traps that we leave interrupts disabled for.. */ 83#define TRAP_NOEN(a) \ 84 subq $TF_RIP,%rsp; \ 85 movq $0,TF_XFLAGS(%rsp) ; \ 86 movq $(a),TF_TRAPNO(%rsp) ; \ 87 movq $0,TF_ADDR(%rsp) ; \ 88 movq $0,TF_ERR(%rsp) ; \ 89 jmp alltraps_noen 90IDTVEC(dbg) 91 TRAP_NOEN(T_TRCTRAP) 92IDTVEC(bpt) 93 TRAP_NOEN(T_BPTFLT) 94 95/* Regular traps; The cpu does not supply tf_err for these. */ 96#define TRAP(a) \ 97 subq $TF_RIP,%rsp; \ 98 movq $0,TF_XFLAGS(%rsp) ; \ 99 movq $(a),TF_TRAPNO(%rsp) ; \ 100 movq $0,TF_ADDR(%rsp) ; \ 101 movq $0,TF_ERR(%rsp) ; \ 102 jmp alltraps 103IDTVEC(div) 104 TRAP(T_DIVIDE) 105IDTVEC(ofl) 106 TRAP(T_OFLOW) 107IDTVEC(bnd) 108 TRAP(T_BOUND) 109IDTVEC(ill) 110 TRAP(T_PRIVINFLT) 111IDTVEC(dna) 112 TRAP(T_DNA) 113IDTVEC(fpusegm) 114 TRAP(T_FPOPFLT) 115IDTVEC(mchk) 116 TRAP(T_MCHK) 117IDTVEC(rsvd) 118 TRAP(T_RESERVED) 119IDTVEC(fpu) 120 TRAP(T_ARITHTRAP) 121IDTVEC(xmm) 122 TRAP(T_XMMFLT) 123 124/* This group of traps have tf_err already pushed by the cpu */ 125#define TRAP_ERR(a) \ 126 subq $TF_ERR,%rsp; \ 127 movq $(a),TF_TRAPNO(%rsp) ; \ 128 movq $0,TF_ADDR(%rsp) ; \ 129 movq $0,TF_XFLAGS(%rsp) ; \ 130 jmp alltraps 131IDTVEC(tss) 132 TRAP_ERR(T_TSSFLT) 133IDTVEC(missing) 134 TRAP_ERR(T_SEGNPFLT) 135IDTVEC(stk) 136 TRAP_ERR(T_STKFLT) 137IDTVEC(align) 138 TRAP_ERR(T_ALIGNFLT) 139 140 /* 141 * alltraps entry point. Use swapgs if this is the first time in the 142 * kernel from userland. Reenable interrupts if they were enabled 143 * before the trap. This approximates SDT_SYS386TGT on the i386 port. 144 */ 145 146 SUPERALIGN_TEXT 147 .globl alltraps 148 .type alltraps,@function 149alltraps: 150 /* Fixup %gs if coming from userland */ 151 testb $SEL_RPL_MASK,TF_CS(%rsp) 152 jz alltraps_testi 153 swapgs 154alltraps_testi: 155 testq $PSL_I,TF_RFLAGS(%rsp) 156 jz alltraps_pushregs 157 sti 158alltraps_pushregs: 159 movq %rdi,TF_RDI(%rsp) 160alltraps_pushregs_no_rdi: 161 movq %rsi,TF_RSI(%rsp) 162 movq %rdx,TF_RDX(%rsp) 163 movq %rcx,TF_RCX(%rsp) 164 movq %r8,TF_R8(%rsp) 165 movq %r9,TF_R9(%rsp) 166 movq %rax,TF_RAX(%rsp) 167 movq %rbx,TF_RBX(%rsp) 168 movq %rbp,TF_RBP(%rsp) 169 movq %r10,TF_R10(%rsp) 170 movq %r11,TF_R11(%rsp) 171 movq %r12,TF_R12(%rsp) 172 movq %r13,TF_R13(%rsp) 173 movq %r14,TF_R14(%rsp) 174 movq %r15,TF_R15(%rsp) 175 FAKE_MCOUNT(TF_RIP(%rsp)) 176 .globl calltrap 177 .type calltrap,@function 178calltrap: 179 movq %rsp, %rdi 180 call trap 181 MEXITCOUNT 182 jmp doreti /* Handle any pending ASTs */ 183 184 /* 185 * alltraps_noen entry point. Unlike alltraps above, we want to 186 * leave the interrupts disabled. This corresponds to 187 * SDT_SYS386IGT on the i386 port. 188 */ 189 SUPERALIGN_TEXT 190 .globl alltraps_noen 191 .type alltraps_noen,@function 192alltraps_noen: 193 /* Fixup %gs if coming from userland */ 194 testb $SEL_RPL_MASK,TF_CS(%rsp) 195 jz alltraps_pushregs 196 swapgs 197 jmp alltraps_pushregs 198 199IDTVEC(dblfault) 200 subq $TF_ERR,%rsp 201 movq $T_DOUBLEFLT,TF_TRAPNO(%rsp) 202 movq $0,TF_ADDR(%rsp) 203 movq $0,TF_ERR(%rsp) 204 movq $0,TF_XFLAGS(%rsp) 205 movq %rdi,TF_RDI(%rsp) 206 movq %rsi,TF_RSI(%rsp) 207 movq %rdx,TF_RDX(%rsp) 208 movq %rcx,TF_RCX(%rsp) 209 movq %r8,TF_R8(%rsp) 210 movq %r9,TF_R9(%rsp) 211 movq %rax,TF_RAX(%rsp) 212 movq %rbx,TF_RBX(%rsp) 213 movq %rbp,TF_RBP(%rsp) 214 movq %r10,TF_R10(%rsp) 215 movq %r11,TF_R11(%rsp) 216 movq %r12,TF_R12(%rsp) 217 movq %r13,TF_R13(%rsp) 218 movq %r14,TF_R14(%rsp) 219 movq %r15,TF_R15(%rsp) 220 testb $SEL_RPL_MASK,TF_CS(%rsp) 221 jz 1f 222 swapgs 2231: movq %rsp, %rdi 224 call dblfault_handler 2252: hlt 226 jmp 2b 227 228IDTVEC(page) 229 subq $TF_ERR,%rsp 230 movq $T_PAGEFLT,TF_TRAPNO(%rsp) 231 /* Fixup %gs if coming from userland */ 232 testb $SEL_RPL_MASK,TF_CS(%rsp) 233 jz 1f 234 swapgs 2351: 236 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 237 movq %cr2,%rdi /* preserve %cr2 before .. */ 238 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */ 239 movq $0,TF_XFLAGS(%rsp) 240 testq $PSL_I,TF_RFLAGS(%rsp) 241 jz alltraps_pushregs_no_rdi 242 sti 243 jmp alltraps_pushregs_no_rdi 244 245 /* 246 * We have to special-case this one. If we get a trap in doreti() at 247 * the iretq stage, we'll reenter with the wrong gs state. We'll have 248 * to do a special the swapgs in this case even coming from the kernel. 249 * XXX linux has a trap handler for their equivalent of load_gs(). 250 */ 251IDTVEC(prot) 252 subq $TF_ERR,%rsp 253 movq $T_PROTFLT,TF_TRAPNO(%rsp) 254 movq $0,TF_ADDR(%rsp) 255 movq $0,TF_XFLAGS(%rsp) 256 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 257 258 /* 259 * Fixup %gs if coming from userland. Handle the special case where 260 * %fs faults in doreti at the iretq instruction itself. 261 */ 262 leaq doreti_iret(%rip),%rdi 263 cmpq %rdi,TF_RIP(%rsp) /* special iretq fault case */ 264 je 2f 265 testb $SEL_RPL_MASK,TF_CS(%rsp) /* check if from userland */ 266 jz 1f 2672: 268 swapgs 2691: 270 testq $PSL_I,TF_RFLAGS(%rsp) 271 jz alltraps_pushregs_no_rdi 272 sti 273 jmp alltraps_pushregs_no_rdi 274 275/* 276 * Fast syscall entry point. We enter here with just our new %cs/%ss set, 277 * and the new privilige level. We are still running on the old user stack 278 * pointer. We have to juggle a few things around to find our stack etc. 279 * swapgs gives us access to our PCPU space only. 280 */ 281IDTVEC(fast_syscall) 282 swapgs 283 movq %rsp,PCPU(scratch_rsp) 284 movq PCPU(common_tss) + TSS_RSP0, %rsp 285 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */ 286 subq $TF_SIZE,%rsp 287 /* defer TF_RSP till we have a spare register */ 288 movq %r11,TF_RFLAGS(%rsp) 289 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */ 290 movq PCPU(scratch_rsp),%r11 /* %r11 already saved */ 291 movq %r11,TF_RSP(%rsp) /* user stack pointer */ 292 sti 293 movq $KUDSEL,TF_SS(%rsp) 294 movq $KUCSEL,TF_CS(%rsp) 295 movq $2,TF_ERR(%rsp) 296 movq $T_FAST_SYSCALL,TF_TRAPNO(%rsp) /* for the vkernel */ 297 movq $0,TF_XFLAGS(%rsp) /* note: used in signal frame */ 298 movq %rdi,TF_RDI(%rsp) /* arg 1 */ 299 movq %rsi,TF_RSI(%rsp) /* arg 2 */ 300 movq %rdx,TF_RDX(%rsp) /* arg 3 */ 301 movq %r10,TF_RCX(%rsp) /* arg 4 */ 302 movq %r8,TF_R8(%rsp) /* arg 5 */ 303 movq %r9,TF_R9(%rsp) /* arg 6 */ 304 movq %rax,TF_RAX(%rsp) /* syscall number */ 305 movq %rbx,TF_RBX(%rsp) /* C preserved */ 306 movq %rbp,TF_RBP(%rsp) /* C preserved */ 307 movq %r12,TF_R12(%rsp) /* C preserved */ 308 movq %r13,TF_R13(%rsp) /* C preserved */ 309 movq %r14,TF_R14(%rsp) /* C preserved */ 310 movq %r15,TF_R15(%rsp) /* C preserved */ 311 FAKE_MCOUNT(TF_RIP(%rsp)) 312 movq %rsp, %rdi 313 call syscall2 314 MEXITCOUNT 315 jmp doreti 316 317/* 318 * Here for CYA insurance, in case a "syscall" instruction gets 319 * issued from 32 bit compatability mode. MSR_CSTAR has to point 320 * to *something* if EFER_SCE is enabled. 321 */ 322IDTVEC(fast_syscall32) 323 sysret 324 325/* 326 * NMI handling is special. 327 * 328 * First, NMIs do not respect the state of the processor's RFLAGS.IF 329 * bit and the NMI handler may be invoked at any time, including when 330 * the processor is in a critical section with RFLAGS.IF == 0. In 331 * particular, this means that the processor's GS.base values could be 332 * inconsistent on entry to the handler, and so we need to read 333 * MSR_GSBASE to determine if a 'swapgs' is needed. We use '%ebx', a 334 * C-preserved register, to remember whether to swap GS back on the 335 * exit path. 336 * 337 * Second, the processor treats NMIs specially, blocking further NMIs 338 * until an 'iretq' instruction is executed. We therefore need to 339 * execute the NMI handler with interrupts disabled to prevent a 340 * nested interrupt from executing an 'iretq' instruction and 341 * inadvertently taking the processor out of NMI mode. 342 * 343 * Third, the NMI handler runs on its own stack (tss_ist1), shared 344 * with the double fault handler. 345 */ 346 347IDTVEC(nmi) 348 subq $TF_RIP,%rsp 349 movq $(T_NMI),TF_TRAPNO(%rsp) 350 movq $0,TF_ADDR(%rsp) 351 movq $0,TF_ERR(%rsp) 352 movq $0,TF_XFLAGS(%rsp) 353 movq %rdi,TF_RDI(%rsp) 354 movq %rsi,TF_RSI(%rsp) 355 movq %rdx,TF_RDX(%rsp) 356 movq %rcx,TF_RCX(%rsp) 357 movq %r8,TF_R8(%rsp) 358 movq %r9,TF_R9(%rsp) 359 movq %rax,TF_RAX(%rsp) 360 movq %rbx,TF_RBX(%rsp) 361 movq %rbp,TF_RBP(%rsp) 362 movq %r10,TF_R10(%rsp) 363 movq %r11,TF_R11(%rsp) 364 movq %r12,TF_R12(%rsp) 365 movq %r13,TF_R13(%rsp) 366 movq %r14,TF_R14(%rsp) 367 movq %r15,TF_R15(%rsp) 368 xorl %ebx,%ebx 369 testb $SEL_RPL_MASK,TF_CS(%rsp) 370 jnz nmi_needswapgs /* we came from userland */ 371 movl $MSR_GSBASE,%ecx 372 rdmsr 373 cmpl $VM_MAX_USER_ADDRESS >> 32,%edx 374 jae nmi_calltrap /* GS.base holds a kernel VA */ 375nmi_needswapgs: 376 incl %ebx 377 swapgs 378/* Note: this label is also used by ddb and gdb: */ 379nmi_calltrap: 380 FAKE_MCOUNT(TF_RIP(%rsp)) 381 movq %rsp, %rdi 382 call trap 383 MEXITCOUNT 384 testl %ebx,%ebx 385 jz nmi_restoreregs 386 swapgs 387nmi_restoreregs: 388 movq TF_RDI(%rsp),%rdi 389 movq TF_RSI(%rsp),%rsi 390 movq TF_RDX(%rsp),%rdx 391 movq TF_RCX(%rsp),%rcx 392 movq TF_R8(%rsp),%r8 393 movq TF_R9(%rsp),%r9 394 movq TF_RAX(%rsp),%rax 395 movq TF_RBX(%rsp),%rbx 396 movq TF_RBP(%rsp),%rbp 397 movq TF_R10(%rsp),%r10 398 movq TF_R11(%rsp),%r11 399 movq TF_R12(%rsp),%r12 400 movq TF_R13(%rsp),%r13 401 movq TF_R14(%rsp),%r14 402 movq TF_R15(%rsp),%r15 403 addq $TF_RIP,%rsp 404 iretq 405 406/* 407 * This function is what cpu_heavy_restore jumps to after a new process 408 * is created. The LWKT subsystem switches while holding a critical 409 * section and we maintain that abstraction here (e.g. because 410 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of 411 * it before calling the initial function (typically fork_return()) and/or 412 * returning to user mode. 413 * 414 * The MP lock is not held at any point but the critcount is bumped 415 * on entry to prevent interruption of the trampoline at a bad point. 416 */ 417ENTRY(fork_trampoline) 418 movq PCPU(curthread),%rax 419 decl TD_CRITCOUNT(%rax) 420 421 /* 422 * cpu_set_fork_handler intercepts this function call to 423 * have this call a non-return function to stay in kernel mode. 424 * 425 * initproc has its own fork handler, start_init(), which DOES 426 * return. 427 * 428 * %rbx - chaining function (typically fork_return) 429 * %r12 -> %rdi (argument) 430 * frame-> %rsi (trap frame) 431 * 432 * void (func:rbx)(arg:rdi, trapframe:rsi) 433 */ 434 movq %rsp, %rsi /* pass trapframe by reference */ 435 movq %r12, %rdi /* arg1 */ 436 call *%rbx /* function */ 437 438 /* cut from syscall */ 439 440 sti 441 call splz 442 443 /* 444 * Return via doreti to handle ASTs. 445 * 446 * trapframe is at the top of the stack. 447 */ 448 MEXITCOUNT 449 jmp doreti 450 451/* 452 * To efficiently implement classification of trap and interrupt handlers 453 * for profiling, there must be only trap handlers between the labels btrap 454 * and bintr, and only interrupt handlers between the labels bintr and 455 * eintr. This is implemented (partly) by including files that contain 456 * some of the handlers. Before including the files, set up a normal asm 457 * environment so that the included files doen't need to know that they are 458 * included. 459 */ 460 461#ifdef COMPAT_IA32 462 .data 463 .p2align 4 464 .text 465 SUPERALIGN_TEXT 466 467#include <x86_64/ia32/ia32_exception.S> 468#endif 469 470 .data 471 .p2align 4 472 .text 473 SUPERALIGN_TEXT 474MCOUNT_LABEL(bintr) 475 476#if JG 477#include <x86_64/x86_64/apic_vector.S> 478#endif 479 480#ifdef DEV_ATPIC 481 .data 482 .p2align 4 483 .text 484 SUPERALIGN_TEXT 485 486#include <x86_64/isa/atpic_vector.S> 487#endif 488 489 .text 490MCOUNT_LABEL(eintr) 491 492