1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 40 */ 41 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/eventhandler.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/sysctl.h> 50 #include <sys/power.h> 51 52 #include <machine/asmacros.h> 53 #include <machine/clock.h> 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/segments.h> 57 #include <machine/specialreg.h> 58 #include <machine/md_var.h> 59 60 /* XXX - should be in header file: */ 61 void printcpuinfo(void); 62 void identify_cpu(void); 63 void earlysetcpuclass(void); 64 void panicifcpuunsupported(void); 65 66 static u_int find_cpu_vendor_id(void); 67 static void print_AMD_info(void); 68 static void print_AMD_assoc(int i); 69 static void print_via_padlock_info(void); 70 71 int cpu_class; 72 char machine[] = "x86_64"; 73 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 74 machine, 0, "Machine class"); 75 76 static char cpu_model[128]; 77 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 78 cpu_model, 0, "Machine model"); 79 80 static int hw_clockrate; 81 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 82 &hw_clockrate, 0, "CPU instruction clock rate"); 83 84 static char cpu_brand[48]; 85 86 static struct { 87 char *cpu_name; 88 int cpu_class; 89 } x86_64_cpus[] = { 90 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 91 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 92 }; 93 94 static struct { 95 char *vendor; 96 u_int vendor_id; 97 } cpu_vendors[] = { 98 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 99 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 100 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 101 }; 102 103 int cpu_cores; 104 int cpu_logical; 105 106 107 extern int pq_l2size; 108 extern int pq_l2nways; 109 110 void 111 printcpuinfo(void) 112 { 113 u_int regs[4], i; 114 char *brand; 115 116 cpu_class = x86_64_cpus[cpu].cpu_class; 117 kprintf("CPU: "); 118 strncpy(cpu_model, x86_64_cpus[cpu].cpu_name, sizeof (cpu_model)); 119 120 /* Check for extended CPUID information and a processor name. */ 121 if (cpu_exthigh >= 0x80000004) { 122 brand = cpu_brand; 123 for (i = 0x80000002; i < 0x80000005; i++) { 124 do_cpuid(i, regs); 125 memcpy(brand, regs, sizeof(regs)); 126 brand += sizeof(regs); 127 } 128 } 129 130 switch (cpu_vendor_id) { 131 case CPU_VENDOR_INTEL: 132 /* Please make up your mind folks! */ 133 strcat(cpu_model, "EM64T"); 134 break; 135 case CPU_VENDOR_AMD: 136 /* 137 * Values taken from AMD Processor Recognition 138 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 139 * (also describes ``Features'' encodings. 140 */ 141 strcpy(cpu_model, "AMD "); 142 if ((cpu_id & 0xf00) == 0xf00) 143 strcat(cpu_model, "AMD64 Processor"); 144 else 145 strcat(cpu_model, "Unknown"); 146 break; 147 case CPU_VENDOR_CENTAUR: 148 strcpy(cpu_model, "VIA "); 149 if ((cpu_id & 0xff0) == 0x6f0) 150 strcat(cpu_model, "Nano Processor"); 151 else 152 strcat(cpu_model, "Unknown"); 153 break; 154 default: 155 strcat(cpu_model, "Unknown"); 156 break; 157 } 158 159 /* 160 * Replace cpu_model with cpu_brand minus leading spaces if 161 * we have one. 162 */ 163 brand = cpu_brand; 164 while (*brand == ' ') 165 ++brand; 166 if (*brand != '\0') 167 strcpy(cpu_model, brand); 168 169 kprintf("%s (", cpu_model); 170 switch(cpu_class) { 171 case CPUCLASS_K8: 172 hw_clockrate = (tsc_frequency + 5000) / 1000000; 173 kprintf("%jd.%02d-MHz ", 174 (intmax_t)(tsc_frequency + 4999) / 1000000, 175 (u_int)((tsc_frequency + 4999) / 10000) % 100); 176 kprintf("K8"); 177 break; 178 default: 179 kprintf("Unknown"); /* will panic below... */ 180 } 181 kprintf("-class CPU)\n"); 182 if (*cpu_vendor) 183 kprintf(" Origin = \"%s\"", cpu_vendor); 184 if (cpu_id) 185 kprintf(" Id = 0x%x", cpu_id); 186 187 if (cpu_vendor_id == CPU_VENDOR_INTEL || 188 cpu_vendor_id == CPU_VENDOR_AMD || 189 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 190 kprintf(" Stepping = %u", cpu_id & 0xf); 191 if (cpu_high > 0) { 192 u_int cmp = 1, htt = 1; 193 194 /* 195 * Here we should probably set up flags indicating 196 * whether or not various features are available. 197 * The interesting ones are probably VME, PSE, PAE, 198 * and PGE. The code already assumes without bothering 199 * to check that all CPUs >= Pentium have a TSC and 200 * MSRs. 201 */ 202 kprintf("\n Features=0x%b", cpu_feature, 203 "\020" 204 "\001FPU" /* Integral FPU */ 205 "\002VME" /* Extended VM86 mode support */ 206 "\003DE" /* Debugging Extensions (CR4.DE) */ 207 "\004PSE" /* 4MByte page tables */ 208 "\005TSC" /* Timestamp counter */ 209 "\006MSR" /* Machine specific registers */ 210 "\007PAE" /* Physical address extension */ 211 "\010MCE" /* Machine Check support */ 212 "\011CX8" /* CMPEXCH8 instruction */ 213 "\012APIC" /* SMP local APIC */ 214 "\013oldMTRR" /* Previous implementation of MTRR */ 215 "\014SEP" /* Fast System Call */ 216 "\015MTRR" /* Memory Type Range Registers */ 217 "\016PGE" /* PG_G (global bit) support */ 218 "\017MCA" /* Machine Check Architecture */ 219 "\020CMOV" /* CMOV instruction */ 220 "\021PAT" /* Page attributes table */ 221 "\022PSE36" /* 36 bit address space support */ 222 "\023PN" /* Processor Serial number */ 223 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 224 "\025<b20>" 225 "\026DTS" /* Debug Trace Store */ 226 "\027ACPI" /* ACPI support */ 227 "\030MMX" /* MMX instructions */ 228 "\031FXSR" /* FXSAVE/FXRSTOR */ 229 "\032SSE" /* Streaming SIMD Extensions */ 230 "\033SSE2" /* Streaming SIMD Extensions #2 */ 231 "\034SS" /* Self snoop */ 232 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 233 "\036TM" /* Thermal Monitor clock slowdown */ 234 "\037IA64" /* CPU can execute IA64 instructions */ 235 "\040PBE" /* Pending Break Enable */ 236 ); 237 238 if (cpu_feature2 != 0) { 239 kprintf("\n Features2=0x%b", cpu_feature2, 240 "\020" 241 "\001SSE3" /* SSE3 */ 242 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 243 "\003DTES64" /* 64-bit Debug Trace */ 244 "\004MON" /* MONITOR/MWAIT Instructions */ 245 "\005DS_CPL" /* CPL Qualified Debug Store */ 246 "\006VMX" /* Virtual Machine Extensions */ 247 "\007SMX" /* Safer Mode Extensions */ 248 "\010EST" /* Enhanced SpeedStep */ 249 "\011TM2" /* Thermal Monitor 2 */ 250 "\012SSSE3" /* SSSE3 */ 251 "\013CNXT-ID" /* L1 context ID available */ 252 "\014<b11>" 253 "\015<b12>" 254 "\016CX16" /* CMPXCHG16B Instruction */ 255 "\017xTPR" /* Send Task Priority Messages */ 256 "\020PDCM" /* Perf/Debug Capability MSR */ 257 "\021<b16>" 258 "\022PCID" /* Process-context Identifiers */ 259 "\023DCA" /* Direct Cache Access */ 260 "\024SSE4.1" 261 "\025SSE4.2" 262 "\026x2APIC" /* xAPIC Extensions */ 263 "\027MOVBE" /* MOVBE instruction */ 264 "\030POPCNT" 265 "\031TSC-DL" /* TSC Deadline */ 266 "\032AESNI" /* AES Crypto */ 267 "\033XSAVE" 268 "\034OSXSAVE" 269 "\035AVX" /* Advanced Vector Extensions */ 270 "\036<b29>" 271 "\037<b30>" 272 "\040VMM" /* Running on a hypervisor */ 273 ); 274 } 275 276 /* 277 * AMD64 Architecture Programmer's Manual Volume 3: 278 * General-Purpose and System Instructions 279 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 280 * 281 * IA-32 Intel Architecture Software Developer's Manual, 282 * Volume 2A: Instruction Set Reference, A-M 283 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 284 */ 285 if (amd_feature != 0) { 286 kprintf("\n AMD Features=0x%b", amd_feature, 287 "\020" /* in hex */ 288 "\001<s0>" /* Same */ 289 "\002<s1>" /* Same */ 290 "\003<s2>" /* Same */ 291 "\004<s3>" /* Same */ 292 "\005<s4>" /* Same */ 293 "\006<s5>" /* Same */ 294 "\007<s6>" /* Same */ 295 "\010<s7>" /* Same */ 296 "\011<s8>" /* Same */ 297 "\012<s9>" /* Same */ 298 "\013<b10>" /* Undefined */ 299 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 300 "\015<s12>" /* Same */ 301 "\016<s13>" /* Same */ 302 "\017<s14>" /* Same */ 303 "\020<s15>" /* Same */ 304 "\021<s16>" /* Same */ 305 "\022<s17>" /* Same */ 306 "\023<b18>" /* Reserved, unknown */ 307 "\024MP" /* Multiprocessor Capable */ 308 "\025NX" /* Has EFER.NXE, NX */ 309 "\026<b21>" /* Undefined */ 310 "\027MMX+" /* AMD MMX Extensions */ 311 "\030<s23>" /* Same */ 312 "\031<s24>" /* Same */ 313 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 314 "\033Page1GB" /* 1-GB large page support */ 315 "\034RDTSCP" /* RDTSCP */ 316 "\035<b28>" /* Undefined */ 317 "\036LM" /* 64 bit long mode */ 318 "\0373DNow!+" /* AMD 3DNow! Extensions */ 319 "\0403DNow!" /* AMD 3DNow! */ 320 ); 321 } 322 323 if (amd_feature2 != 0) { 324 kprintf("\n AMD Features2=0x%b", amd_feature2, 325 "\020" 326 "\001LAHF" /* LAHF/SAHF in long mode */ 327 "\002CMP" /* CMP legacy */ 328 "\003SVM" /* Secure Virtual Mode */ 329 "\004ExtAPIC" /* Extended APIC register */ 330 "\005CR8" /* CR8 in legacy mode */ 331 "\006ABM" /* LZCNT instruction */ 332 "\007SSE4A" /* SSE4A */ 333 "\010MAS" /* Misaligned SSE mode */ 334 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 335 "\012OSVW" /* OS visible workaround */ 336 "\013IBS" /* Instruction based sampling */ 337 "\014SSE5" /* SSE5 */ 338 "\015SKINIT" /* SKINIT/STGI */ 339 "\016WDT" /* Watchdog timer */ 340 "\017<b14>" 341 "\020<b15>" 342 "\021<b16>" 343 "\022<b17>" 344 "\023<b18>" 345 "\024<b19>" 346 "\025<b20>" 347 "\026<b21>" 348 "\027<b22>" 349 "\030<b23>" 350 "\031<b24>" 351 "\032<b25>" 352 "\033<b26>" 353 "\034<b27>" 354 "\035<b28>" 355 "\036<b29>" 356 "\037<b30>" 357 "\040<b31>" 358 ); 359 } 360 361 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 362 print_via_padlock_info(); 363 364 if ((cpu_feature & CPUID_HTT) && 365 cpu_vendor_id == CPU_VENDOR_AMD) 366 cpu_feature &= ~CPUID_HTT; 367 368 /* 369 * If this CPU supports HTT or CMP then mention the 370 * number of physical/logical cores it contains. 371 */ 372 if (cpu_feature & CPUID_HTT) 373 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 374 if (cpu_vendor_id == CPU_VENDOR_AMD && 375 (amd_feature2 & AMDID2_CMP)) 376 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 377 else if (cpu_vendor_id == CPU_VENDOR_INTEL && 378 (cpu_high >= 4)) { 379 cpuid_count(4, 0, regs); 380 if ((regs[0] & 0x1f) != 0) 381 cmp = ((regs[0] >> 26) & 0x3f) + 1; 382 } 383 cpu_cores = cmp; 384 cpu_logical = htt / cmp; 385 if (cmp > 1) 386 kprintf("\n Cores per package: %d", cmp); 387 if ((htt / cmp) > 1) 388 kprintf("\n Logical CPUs per core: %d", 389 cpu_logical); 390 } 391 } 392 /* Avoid ugly blank lines: only print newline when we have to. */ 393 if (*cpu_vendor || cpu_id) 394 kprintf("\n"); 395 396 if (!bootverbose) 397 return; 398 399 if (cpu_vendor_id == CPU_VENDOR_AMD) 400 print_AMD_info(); 401 } 402 403 void 404 panicifcpuunsupported(void) 405 { 406 407 #ifndef HAMMER_CPU 408 #error "You need to specify a cpu type" 409 #endif 410 /* 411 * Now that we have told the user what they have, 412 * let them know if that machine type isn't configured. 413 */ 414 switch (cpu_class) { 415 case CPUCLASS_X86: 416 #ifndef HAMMER_CPU 417 case CPUCLASS_K8: 418 #endif 419 panic("CPU class not configured"); 420 default: 421 break; 422 } 423 } 424 425 426 #if JG 427 /* Update TSC freq with the value indicated by the caller. */ 428 static void 429 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 430 { 431 /* If there was an error during the transition, don't do anything. */ 432 if (status != 0) 433 return; 434 435 /* Total setting for this level gives the new frequency in MHz. */ 436 hw_clockrate = level->total_set.freq; 437 } 438 439 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 440 EVENTHANDLER_PRI_ANY); 441 #endif 442 443 /* 444 * Final stage of CPU identification. 445 */ 446 void 447 identify_cpu(void) 448 { 449 u_int regs[4]; 450 451 do_cpuid(0, regs); 452 cpu_high = regs[0]; 453 ((u_int *)&cpu_vendor)[0] = regs[1]; 454 ((u_int *)&cpu_vendor)[1] = regs[3]; 455 ((u_int *)&cpu_vendor)[2] = regs[2]; 456 cpu_vendor[12] = '\0'; 457 cpu_vendor_id = find_cpu_vendor_id(); 458 459 do_cpuid(1, regs); 460 cpu_id = regs[0]; 461 cpu_procinfo = regs[1]; 462 cpu_feature = regs[3]; 463 cpu_feature2 = regs[2]; 464 465 if (cpu_vendor_id == CPU_VENDOR_INTEL || 466 cpu_vendor_id == CPU_VENDOR_AMD || 467 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 468 do_cpuid(0x80000000, regs); 469 cpu_exthigh = regs[0]; 470 } 471 if (cpu_exthigh >= 0x80000001) { 472 do_cpuid(0x80000001, regs); 473 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 474 amd_feature2 = regs[2]; 475 } 476 if (cpu_exthigh >= 0x80000008) { 477 do_cpuid(0x80000008, regs); 478 cpu_procinfo2 = regs[2]; 479 } 480 481 /* XXX */ 482 cpu = CPU_CLAWHAMMER; 483 484 if (cpu_feature & CPUID_SSE2) 485 cpu_mi_feature |= CPU_MI_BZERONT; 486 487 if (cpu_feature2 & CPUID2_MON) 488 cpu_mi_feature |= CPU_MI_MONITOR; 489 } 490 491 static u_int 492 find_cpu_vendor_id(void) 493 { 494 int i; 495 496 for (i = 0; i < NELEM(cpu_vendors); i++) 497 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 498 return (cpu_vendors[i].vendor_id); 499 return (0); 500 } 501 502 static void 503 print_AMD_assoc(int i) 504 { 505 if (i == 255) 506 kprintf(", fully associative\n"); 507 else 508 kprintf(", %d-way associative\n", i); 509 } 510 511 static void 512 print_AMD_l2_assoc(int i) 513 { 514 switch (i & 0x0f) { 515 case 0: kprintf(", disabled/not present\n"); break; 516 case 1: kprintf(", direct mapped\n"); break; 517 case 2: kprintf(", 2-way associative\n"); break; 518 case 4: kprintf(", 4-way associative\n"); break; 519 case 6: kprintf(", 8-way associative\n"); break; 520 case 8: kprintf(", 16-way associative\n"); break; 521 case 15: kprintf(", fully associative\n"); break; 522 default: kprintf(", reserved configuration\n"); break; 523 } 524 } 525 526 static void 527 print_AMD_info(void) 528 { 529 u_int regs[4]; 530 531 if (cpu_exthigh < 0x80000005) 532 return; 533 534 do_cpuid(0x80000005, regs); 535 kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 536 print_AMD_assoc(regs[0] >> 24); 537 538 kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 539 print_AMD_assoc((regs[0] >> 8) & 0xff); 540 541 kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 542 print_AMD_assoc(regs[1] >> 24); 543 544 kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 545 print_AMD_assoc((regs[1] >> 8) & 0xff); 546 547 kprintf("L1 data cache: %d kbytes", regs[2] >> 24); 548 kprintf(", %d bytes/line", regs[2] & 0xff); 549 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff); 550 print_AMD_assoc((regs[2] >> 16) & 0xff); 551 552 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24); 553 kprintf(", %d bytes/line", regs[3] & 0xff); 554 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff); 555 print_AMD_assoc((regs[3] >> 16) & 0xff); 556 557 if (cpu_exthigh >= 0x80000006) { 558 do_cpuid(0x80000006, regs); 559 if ((regs[0] >> 16) != 0) { 560 kprintf("L2 2MB data TLB: %d entries", 561 (regs[0] >> 16) & 0xfff); 562 print_AMD_l2_assoc(regs[0] >> 28); 563 kprintf("L2 2MB instruction TLB: %d entries", 564 regs[0] & 0xfff); 565 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 566 } else { 567 kprintf("L2 2MB unified TLB: %d entries", 568 regs[0] & 0xfff); 569 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 570 } 571 if ((regs[1] >> 16) != 0) { 572 kprintf("L2 4KB data TLB: %d entries", 573 (regs[1] >> 16) & 0xfff); 574 print_AMD_l2_assoc(regs[1] >> 28); 575 576 kprintf("L2 4KB instruction TLB: %d entries", 577 (regs[1] >> 16) & 0xfff); 578 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 579 } else { 580 kprintf("L2 4KB unified TLB: %d entries", 581 (regs[1] >> 16) & 0xfff); 582 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 583 } 584 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16); 585 kprintf(", %d bytes/line", regs[2] & 0xff); 586 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 587 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 588 } 589 } 590 591 static void 592 print_via_padlock_info(void) 593 { 594 u_int regs[4]; 595 596 /* Check for supported models. */ 597 switch (cpu_id & 0xff0) { 598 case 0x690: 599 if ((cpu_id & 0xf) < 3) 600 return; 601 case 0x6a0: 602 case 0x6d0: 603 case 0x6f0: 604 break; 605 default: 606 return; 607 } 608 609 do_cpuid(0xc0000000, regs); 610 if (regs[0] >= 0xc0000001) 611 do_cpuid(0xc0000001, regs); 612 else 613 return; 614 615 kprintf("\n VIA Padlock Features=0x%b", regs[3], 616 "\020" 617 "\003RNG" /* RNG */ 618 "\007AES" /* ACE */ 619 "\011AES-CTR" /* ACE2 */ 620 "\013SHA1,SHA256" /* PHE */ 621 "\015RSA" /* PMM */ 622 ); 623 } 624