1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * Copyright (c) 2008 The DragonFly Project. 4 * 5 * All rights reserved. Unpublished rights reserved under the copyright 6 * laws of Japan. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer as 14 * the first lines of this file unmodified. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_cpu.h" 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/sysctl.h> 37 38 #include <machine/cputypes.h> 39 #include <machine/md_var.h> 40 #include <machine/specialreg.h> 41 #include <machine/smp.h> 42 43 #include <vm/vm.h> 44 #include <vm/pmap.h> 45 46 static int hw_instruction_sse; 47 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 48 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 49 50 int cpu; /* Are we 386, 386sx, 486, etc? */ 51 u_int cpu_feature; /* Feature flags */ 52 u_int cpu_feature2; /* Feature flags */ 53 u_int amd_feature; /* AMD feature flags */ 54 u_int amd_feature2; /* AMD feature flags */ 55 u_int via_feature_rng; /* VIA RNG features */ 56 u_int via_feature_xcrypt; /* VIA ACE features */ 57 u_int cpu_high; /* Highest arg to CPUID */ 58 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 59 u_int cpu_id; /* Stepping ID */ 60 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 61 u_int cpu_procinfo2; /* Multicore info */ 62 char cpu_vendor[20]; /* CPU Origin code */ 63 u_int cpu_vendor_id; /* CPU vendor ID */ 64 u_int cpu_fxsr; /* SSE enabled */ 65 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 66 u_int cpu_clflush_line_size = 32; /* Default CLFLUSH line size */ 67 68 /* 69 * -1: automatic (enable on h/w, disable on VMs) 70 * 0: disable 71 * 1: enable (where available) 72 */ 73 static int hw_clflush_enable = -1; 74 75 SYSCTL_INT(_hw, OID_AUTO, clflush_enable, CTLFLAG_RD, &hw_clflush_enable, 0, 76 ""); 77 78 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 79 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 80 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 81 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 82 83 /* 84 * Initialize special VIA C3/C7 features 85 */ 86 static void 87 init_via(void) 88 { 89 u_int regs[4], val; 90 u_int64_t msreg; 91 92 do_cpuid(0xc0000000, regs); 93 val = regs[0]; 94 if (val >= 0xc0000001) { 95 do_cpuid(0xc0000001, regs); 96 val = regs[3]; 97 } else 98 val = 0; 99 100 /* Enable RNG if present and disabled */ 101 if (val & VIA_CPUID_HAS_RNG) { 102 if (!(val & VIA_CPUID_DO_RNG)) { 103 msreg = rdmsr(0x110B); 104 msreg |= 0x40; 105 wrmsr(0x110B, msreg); 106 } 107 via_feature_rng = VIA_HAS_RNG; 108 } 109 /* Enable AES engine if present and disabled */ 110 if (val & VIA_CPUID_HAS_ACE) { 111 if (!(val & VIA_CPUID_DO_ACE)) { 112 msreg = rdmsr(0x1107); 113 msreg |= (0x01 << 28); 114 wrmsr(0x1107, msreg); 115 } 116 via_feature_xcrypt |= VIA_HAS_AES; 117 } 118 /* Enable ACE2 engine if present and disabled */ 119 if (val & VIA_CPUID_HAS_ACE2) { 120 if (!(val & VIA_CPUID_DO_ACE2)) { 121 msreg = rdmsr(0x1107); 122 msreg |= (0x01 << 28); 123 wrmsr(0x1107, msreg); 124 } 125 via_feature_xcrypt |= VIA_HAS_AESCTR; 126 } 127 /* Enable SHA engine if present and disabled */ 128 if (val & VIA_CPUID_HAS_PHE) { 129 if (!(val & VIA_CPUID_DO_PHE)) { 130 msreg = rdmsr(0x1107); 131 msreg |= (0x01 << 28/**/); 132 wrmsr(0x1107, msreg); 133 } 134 via_feature_xcrypt |= VIA_HAS_SHA; 135 } 136 /* Enable MM engine if present and disabled */ 137 if (val & VIA_CPUID_HAS_PMM) { 138 if (!(val & VIA_CPUID_DO_PMM)) { 139 msreg = rdmsr(0x1107); 140 msreg |= (0x01 << 28/**/); 141 wrmsr(0x1107, msreg); 142 } 143 via_feature_xcrypt |= VIA_HAS_MM; 144 } 145 } 146 147 /* 148 * Initialize CPU control registers 149 */ 150 void 151 initializecpu(void) 152 { 153 uint64_t msr; 154 155 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 156 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 157 cpu_fxsr = hw_instruction_sse = 1; 158 } 159 160 if (cpu_vendor_id == CPU_VENDOR_AMD) { 161 switch((cpu_id & 0xFF0000)) { 162 case 0x100000: 163 case 0x120000: 164 /* 165 * Errata 721 is the cpu bug found by your's truly 166 * (Matthew Dillon). It is a bug where a sequence 167 * of 5 or more popq's + a retq, under involved 168 * deep recursion circumstances, can cause the %rsp 169 * to not be properly updated, almost always 170 * resulting in a seg-fault soon after. 171 */ 172 msr = rdmsr(0xc0011029); 173 if ((msr & 1) == 0) { 174 kprintf("Errata 721 workaround installed\n"); 175 msr |= 1; 176 wrmsr(0xc0011029, msr); 177 } 178 break; 179 } 180 } 181 182 if ((amd_feature & AMDID_NX) != 0) { 183 msr = rdmsr(MSR_EFER) | EFER_NXE; 184 wrmsr(MSR_EFER, msr); 185 #if JG 186 pg_nx = PG_NX; 187 #endif 188 } 189 if (cpu_vendor_id == CPU_VENDOR_CENTAUR && 190 CPUID_TO_FAMILY(cpu_id) == 0x6 && 191 CPUID_TO_MODEL(cpu_id) >= 0xf) 192 init_via(); 193 194 if (cpu_feature2 & CPUID2_VMM) 195 vmm_guest = 1; 196 197 TUNABLE_INT_FETCH("hw.clflush_enable", &hw_clflush_enable); 198 if (cpu_feature & CPUID_CLFSH) { 199 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 200 201 if (hw_clflush_enable == 0 || 202 ((hw_clflush_enable == -1) && vmm_guest)) 203 cpu_feature &= ~CPUID_CLFSH; 204 } 205 } 206