1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * Copyright (c) 2008 The DragonFly Project. 4 * 5 * All rights reserved. Unpublished rights reserved under the copyright 6 * laws of Japan. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer as 14 * the first lines of this file unmodified. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_cpu.h" 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/sysctl.h> 37 38 #include <machine/cputypes.h> 39 #include <machine/md_var.h> 40 #include <machine/specialreg.h> 41 #include <machine/smp.h> 42 43 #include <vm/vm.h> 44 #include <vm/pmap.h> 45 46 static int hw_instruction_sse; 47 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 48 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 49 50 int cpu; /* Are we 386, 386sx, 486, etc? */ 51 u_int cpu_feature; /* Feature flags */ 52 u_int cpu_feature2; /* Feature flags */ 53 u_int amd_feature; /* AMD feature flags */ 54 u_int amd_feature2; /* AMD feature flags */ 55 u_int via_feature_rng; /* VIA RNG features */ 56 u_int via_feature_xcrypt; /* VIA ACE features */ 57 u_int cpu_high; /* Highest arg to CPUID */ 58 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 59 u_int cpu_id; /* Stepping ID */ 60 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 61 u_int cpu_procinfo2; /* Multicore info */ 62 char cpu_vendor[20]; /* CPU Origin code */ 63 u_int cpu_vendor_id; /* CPU vendor ID */ 64 u_int cpu_fxsr; /* SSE enabled */ 65 u_int cpu_xsave; /* AVX enabled by OS*/ 66 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 67 u_int cpu_clflush_line_size = 32; /* Default CLFLUSH line size */ 68 u_int cpu_stdext_feature; 69 u_int cpu_thermal_feature; 70 u_int cpu_mwait_feature; 71 u_int cpu_mwait_extemu; 72 73 /* 74 * -1: automatic (enable on h/w, disable on VMs) 75 * 0: disable 76 * 1: enable (where available) 77 */ 78 static int hw_clflush_enable = -1; 79 80 SYSCTL_INT(_hw, OID_AUTO, clflush_enable, CTLFLAG_RD, &hw_clflush_enable, 0, 81 ""); 82 83 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 84 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 85 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 86 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 87 88 /* 89 * Initialize special VIA C3/C7 features 90 */ 91 static void 92 init_via(void) 93 { 94 u_int regs[4], val; 95 u_int64_t msreg; 96 97 do_cpuid(0xc0000000, regs); 98 val = regs[0]; 99 if (val >= 0xc0000001) { 100 do_cpuid(0xc0000001, regs); 101 val = regs[3]; 102 } else 103 val = 0; 104 105 /* Enable RNG if present and disabled */ 106 if (val & VIA_CPUID_HAS_RNG) { 107 if (!(val & VIA_CPUID_DO_RNG)) { 108 msreg = rdmsr(0x110B); 109 msreg |= 0x40; 110 wrmsr(0x110B, msreg); 111 } 112 via_feature_rng = VIA_HAS_RNG; 113 } 114 /* Enable AES engine if present and disabled */ 115 if (val & VIA_CPUID_HAS_ACE) { 116 if (!(val & VIA_CPUID_DO_ACE)) { 117 msreg = rdmsr(0x1107); 118 msreg |= (0x01 << 28); 119 wrmsr(0x1107, msreg); 120 } 121 via_feature_xcrypt |= VIA_HAS_AES; 122 } 123 /* Enable ACE2 engine if present and disabled */ 124 if (val & VIA_CPUID_HAS_ACE2) { 125 if (!(val & VIA_CPUID_DO_ACE2)) { 126 msreg = rdmsr(0x1107); 127 msreg |= (0x01 << 28); 128 wrmsr(0x1107, msreg); 129 } 130 via_feature_xcrypt |= VIA_HAS_AESCTR; 131 } 132 /* Enable SHA engine if present and disabled */ 133 if (val & VIA_CPUID_HAS_PHE) { 134 if (!(val & VIA_CPUID_DO_PHE)) { 135 msreg = rdmsr(0x1107); 136 msreg |= (0x01 << 28/**/); 137 wrmsr(0x1107, msreg); 138 } 139 via_feature_xcrypt |= VIA_HAS_SHA; 140 } 141 /* Enable MM engine if present and disabled */ 142 if (val & VIA_CPUID_HAS_PMM) { 143 if (!(val & VIA_CPUID_DO_PMM)) { 144 msreg = rdmsr(0x1107); 145 msreg |= (0x01 << 28/**/); 146 wrmsr(0x1107, msreg); 147 } 148 via_feature_xcrypt |= VIA_HAS_MM; 149 } 150 } 151 152 /* 153 * Initialize CPU control registers 154 */ 155 void 156 initializecpu(int cpu) 157 { 158 uint64_t msr; 159 160 /*Check for FXSR and SSE support and enable if available.*/ 161 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 162 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 163 cpu_fxsr = hw_instruction_sse = 1; 164 } 165 166 /* Check if we are running in a hypervisor. */ 167 if (cpu_feature2 & CPUID2_VMM) 168 vmm_guest = 1; 169 170 #if !defined(CPU_DISABLE_AVX) 171 /*Check for XSAVE and AVX support and enable if available.*/ 172 if ((cpu_feature2 & CPUID2_AVX) && (cpu_feature2 & CPUID2_XSAVE) 173 && (cpu_feature & CPUID_SSE)) { 174 load_cr4(rcr4() | CR4_XSAVE); 175 176 /* Adjust size of savefpu in npx.h before adding to mask.*/ 177 xsetbv(0, CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0); 178 cpu_xsave = 1; 179 } 180 #endif 181 182 if (cpu_vendor_id == CPU_VENDOR_AMD) { 183 switch((cpu_id & 0xFF0000)) { 184 case 0x100000: 185 case 0x120000: 186 /* 187 * Errata 721 is the cpu bug found by your's truly 188 * (Matthew Dillon). It is a bug where a sequence 189 * of 5 or more popq's + a retq, under involved 190 * deep recursion circumstances, can cause the %rsp 191 * to not be properly updated, almost always 192 * resulting in a seg-fault soon after. 193 * 194 * Do not install the workaround when we are running 195 * in a virtual machine. 196 */ 197 if (vmm_guest) 198 break; 199 200 msr = rdmsr(MSR_AMD_DE_CFG); 201 if ((msr & 1) == 0) { 202 if (cpu == 0) 203 kprintf("Errata 721 workaround " 204 "installed\n"); 205 msr |= 1; 206 wrmsr(MSR_AMD_DE_CFG, msr); 207 } 208 break; 209 } 210 } 211 212 if ((amd_feature & AMDID_NX) != 0) { 213 msr = rdmsr(MSR_EFER) | EFER_NXE; 214 wrmsr(MSR_EFER, msr); 215 #if JG 216 pg_nx = PG_NX; 217 #endif 218 } 219 if (cpu_vendor_id == CPU_VENDOR_CENTAUR && 220 CPUID_TO_FAMILY(cpu_id) == 0x6 && 221 CPUID_TO_MODEL(cpu_id) >= 0xf) 222 init_via(); 223 224 TUNABLE_INT_FETCH("hw.clflush_enable", &hw_clflush_enable); 225 if (cpu_feature & CPUID_CLFSH) { 226 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 227 228 if (hw_clflush_enable == 0 || 229 ((hw_clflush_enable == -1) && vmm_guest)) 230 cpu_feature &= ~CPUID_CLFSH; 231 } 232 } 233