1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 #if 0 /* JG */ 137 extern void finishidentcpu(void); 138 #endif 139 extern void panicifcpuunsupported(void); 140 141 static void cpu_startup(void *); 142 static void pic_finish(void *); 143 static void cpu_finish(void *); 144 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 static void init_locks(void); 148 149 extern void pcpu_timer_always(struct intrframe *); 150 151 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 152 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 153 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 154 155 #ifdef DDB 156 extern vm_offset_t ksym_start, ksym_end; 157 #endif 158 159 struct privatespace CPU_prvspace_bsp __aligned(4096); 160 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 161 162 vm_paddr_t efi_systbl_phys; 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 cpumask_t smp_idleinvl_mask; 167 cpumask_t smp_idleinvl_reqs; 168 169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 170 171 #if defined(SWTCH_OPTIM_STATS) 172 extern int swtch_optim_stats; 173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 174 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 176 CTLFLAG_RD, &tlb_flush_count, 0, ""); 177 #endif 178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0, 181 "monitor/mwait target state"); 182 183 #define CPU_MWAIT_HAS_CX \ 184 ((cpu_feature2 & CPUID2_MON) && \ 185 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 186 187 #define CPU_MWAIT_CX_NAMELEN 16 188 189 #define CPU_MWAIT_C1 1 190 #define CPU_MWAIT_C2 2 191 #define CPU_MWAIT_C3 3 192 #define CPU_MWAIT_CX_MAX 8 193 194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 196 197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 199 200 struct cpu_mwait_cx { 201 int subcnt; 202 char name[4]; 203 struct sysctl_ctx_list sysctl_ctx; 204 struct sysctl_oid *sysctl_tree; 205 }; 206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 207 static char cpu_mwait_cx_supported[256]; 208 209 static int cpu_mwait_c1_hints_cnt; 210 static int cpu_mwait_hints_cnt; 211 static int *cpu_mwait_hints; 212 213 static int cpu_mwait_deep_hints_cnt; 214 static int *cpu_mwait_deep_hints; 215 216 #define CPU_IDLE_REPEAT_DEFAULT 750 217 218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 220 static u_int cpu_mwait_repeat_shift = 1; 221 222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 224 225 static int cpu_mwait_c3_preamble = 226 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 227 CPU_MWAIT_C3_PREAMBLE_BM_STS; 228 229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 230 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 233 234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 235 int *, boolean_t); 236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 239 240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 245 &cpu_mwait_repeat_shift, 0, ""); 246 247 long physmem = 0; 248 249 u_long ebda_addr = 0; 250 251 int imcr_present = 0; 252 253 int naps = 0; /* # of Applications processors */ 254 255 u_int base_memory; 256 257 static int 258 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 259 { 260 u_long pmem = ctob(physmem); 261 262 int error = sysctl_handle_long(oidp, &pmem, 0, req); 263 return (error); 264 } 265 266 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 267 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 268 269 static int 270 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 271 { 272 int error = sysctl_handle_int(oidp, 0, 273 ctob(physmem - vmstats.v_wire_count), req); 274 return (error); 275 } 276 277 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 278 0, 0, sysctl_hw_usermem, "IU", ""); 279 280 static int 281 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 282 { 283 int error = sysctl_handle_int(oidp, 0, 284 x86_64_btop(avail_end - avail_start), req); 285 return (error); 286 } 287 288 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 289 0, 0, sysctl_hw_availpages, "I", ""); 290 291 vm_paddr_t Maxmem; 292 vm_paddr_t Realmem; 293 294 /* 295 * The number of PHYSMAP entries must be one less than the number of 296 * PHYSSEG entries because the PHYSMAP entry that spans the largest 297 * physical address that is accessible by ISA DMA is split into two 298 * PHYSSEG entries. 299 */ 300 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 301 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 302 303 /* must be 1 less so 0 0 can signal end of chunks */ 304 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 305 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 306 307 static vm_offset_t buffer_sva, buffer_eva; 308 vm_offset_t clean_sva, clean_eva; 309 static vm_offset_t pager_sva, pager_eva; 310 static struct trapframe proc0_tf; 311 312 static void 313 cpu_startup(void *dummy) 314 { 315 caddr_t v; 316 vm_size_t size = 0; 317 vm_offset_t firstaddr; 318 319 /* 320 * Good {morning,afternoon,evening,night}. 321 */ 322 kprintf("%s", version); 323 startrtclock(); 324 printcpuinfo(); 325 panicifcpuunsupported(); 326 kprintf("real memory = %ju (%ju MB)\n", 327 (intmax_t)Realmem, 328 (intmax_t)Realmem / 1024 / 1024); 329 /* 330 * Display any holes after the first chunk of extended memory. 331 */ 332 if (bootverbose) { 333 int indx; 334 335 kprintf("Physical memory chunk(s):\n"); 336 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 337 vm_paddr_t size1; 338 339 size1 = phys_avail[indx].phys_end - 340 phys_avail[indx].phys_beg; 341 342 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 343 (intmax_t)phys_avail[indx].phys_beg, 344 (intmax_t)phys_avail[indx].phys_end - 1, 345 (intmax_t)size1, 346 (intmax_t)(size1 / PAGE_SIZE)); 347 } 348 } 349 350 /* 351 * Allocate space for system data structures. 352 * The first available kernel virtual address is in "v". 353 * As pages of kernel virtual memory are allocated, "v" is incremented. 354 * As pages of memory are allocated and cleared, 355 * "firstaddr" is incremented. 356 * An index into the kernel page table corresponding to the 357 * virtual memory address maintained in "v" is kept in "mapaddr". 358 */ 359 360 /* 361 * Make two passes. The first pass calculates how much memory is 362 * needed and allocates it. The second pass assigns virtual 363 * addresses to the various data structures. 364 */ 365 firstaddr = 0; 366 again: 367 v = (caddr_t)firstaddr; 368 369 #define valloc(name, type, num) \ 370 (name) = (type *)v; v = (caddr_t)((name)+(num)) 371 #define valloclim(name, type, num, lim) \ 372 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 373 374 /* 375 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 376 * For the first 64MB of ram nominally allocate sufficient buffers to 377 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 378 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 379 * the buffer cache we limit the eventual kva reservation to 380 * maxbcache bytes. 381 * 382 * factor represents the 1/4 x ram conversion. 383 */ 384 if (nbuf == 0) { 385 long factor = 4 * NBUFCALCSIZE / 1024; 386 long kbytes = physmem * (PAGE_SIZE / 1024); 387 388 nbuf = 50; 389 if (kbytes > 4096) 390 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 391 if (kbytes > 65536) 392 nbuf += (kbytes - 65536) * 2 / (factor * 5); 393 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 394 nbuf = maxbcache / NBUFCALCSIZE; 395 } 396 397 /* 398 * Do not allow the buffer_map to be more then 1/2 the size of the 399 * kernel_map. 400 */ 401 if (nbuf > (virtual_end - virtual_start + 402 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 403 nbuf = (virtual_end - virtual_start + 404 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 405 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 406 } 407 408 /* 409 * Do not allow the buffer_map to use more than 50% of available 410 * physical-equivalent memory. Since the VM pages which back 411 * individual buffers are typically wired, having too many bufs 412 * can prevent the system from paging properly. 413 */ 414 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 415 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 416 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 417 } 418 419 /* 420 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 421 * the valloc space which is just the virtual_end - virtual_start 422 * section. We use valloc() to allocate the buf header array. 423 */ 424 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 425 nbuf = (virtual_end - virtual_start) / 426 sizeof(struct buf) / 2; 427 kprintf("Warning: nbufs capped at %ld due to valloc " 428 "considerations\n", nbuf); 429 } 430 431 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 432 #ifdef NSWBUF_MIN 433 if (nswbuf_mem < NSWBUF_MIN) 434 nswbuf_mem = NSWBUF_MIN; 435 #endif 436 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 437 #ifdef NSWBUF_MIN 438 if (nswbuf_kva < NSWBUF_MIN) 439 nswbuf_kva = NSWBUF_MIN; 440 #endif 441 442 valloc(swbuf_mem, struct buf, nswbuf_mem); 443 valloc(swbuf_kva, struct buf, nswbuf_kva); 444 valloc(buf, struct buf, nbuf); 445 446 /* 447 * End of first pass, size has been calculated so allocate memory 448 */ 449 if (firstaddr == 0) { 450 size = (vm_size_t)(v - firstaddr); 451 firstaddr = kmem_alloc(&kernel_map, round_page(size), 452 VM_SUBSYS_BUF); 453 if (firstaddr == 0) 454 panic("startup: no room for tables"); 455 goto again; 456 } 457 458 /* 459 * End of second pass, addresses have been assigned 460 * 461 * nbuf is an int, make sure we don't overflow the field. 462 * 463 * On 64-bit systems we always reserve maximal allocations for 464 * buffer cache buffers and there are no fragmentation issues, 465 * so the KVA segment does not have to be excessively oversized. 466 */ 467 if ((vm_size_t)(v - firstaddr) != size) 468 panic("startup: table size inconsistency"); 469 470 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 471 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 472 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 473 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 474 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 475 buffer_map.system_map = 1; 476 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 477 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 478 pager_map_size); 479 pager_map.system_map = 1; 480 kprintf("avail memory = %ju (%ju MB)\n", 481 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 482 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 483 1024 / 1024); 484 } 485 486 struct cpu_idle_stat { 487 int hint; 488 int reserved; 489 u_long halt; 490 u_long spin; 491 u_long repeat; 492 u_long repeat_last; 493 u_long repeat_delta; 494 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 495 } __cachealign; 496 497 #define CPU_IDLE_STAT_HALT -1 498 #define CPU_IDLE_STAT_SPIN -2 499 500 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 501 502 static int 503 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 504 { 505 int idx = arg2, cpu, error; 506 u_long val = 0; 507 508 if (idx == CPU_IDLE_STAT_HALT) { 509 for (cpu = 0; cpu < ncpus; ++cpu) 510 val += cpu_idle_stats[cpu].halt; 511 } else if (idx == CPU_IDLE_STAT_SPIN) { 512 for (cpu = 0; cpu < ncpus; ++cpu) 513 val += cpu_idle_stats[cpu].spin; 514 } else { 515 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 516 ("invalid index %d", idx)); 517 for (cpu = 0; cpu < ncpus; ++cpu) 518 val += cpu_idle_stats[cpu].mwait_cx[idx]; 519 } 520 521 error = sysctl_handle_quad(oidp, &val, 0, req); 522 if (error || req->newptr == NULL) 523 return error; 524 525 if (idx == CPU_IDLE_STAT_HALT) { 526 for (cpu = 0; cpu < ncpus; ++cpu) 527 cpu_idle_stats[cpu].halt = 0; 528 cpu_idle_stats[0].halt = val; 529 } else if (idx == CPU_IDLE_STAT_SPIN) { 530 for (cpu = 0; cpu < ncpus; ++cpu) 531 cpu_idle_stats[cpu].spin = 0; 532 cpu_idle_stats[0].spin = val; 533 } else { 534 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 535 ("invalid index %d", idx)); 536 for (cpu = 0; cpu < ncpus; ++cpu) 537 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 538 cpu_idle_stats[0].mwait_cx[idx] = val; 539 } 540 return 0; 541 } 542 543 static void 544 cpu_mwait_attach(void) 545 { 546 struct sbuf sb; 547 int hint_idx, i; 548 549 if (!CPU_MWAIT_HAS_CX) 550 return; 551 552 if (cpu_vendor_id == CPU_VENDOR_INTEL && 553 (CPUID_TO_FAMILY(cpu_id) > 0xf || 554 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 555 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 556 int bm_sts = 1; 557 558 /* 559 * Pentium dual-core, Core 2 and beyond do not need any 560 * additional activities to enter deep C-state, i.e. C3(+). 561 */ 562 cpu_mwait_cx_no_bmarb(); 563 564 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 565 if (!bm_sts) 566 cpu_mwait_cx_no_bmsts(); 567 } 568 569 sbuf_new(&sb, cpu_mwait_cx_supported, 570 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 571 572 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 573 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 574 int sub; 575 576 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 577 578 sysctl_ctx_init(&cx->sysctl_ctx); 579 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 580 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 581 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 582 if (cx->sysctl_tree == NULL) 583 continue; 584 585 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 586 SYSCTL_ADD_INT(&cx->sysctl_ctx, 587 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 588 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 589 "sub-state count"); 590 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 591 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 592 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 593 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 594 595 for (sub = 0; sub < cx->subcnt; ++sub) 596 sbuf_printf(&sb, "C%d/%d ", i, sub); 597 } 598 sbuf_trim(&sb); 599 sbuf_finish(&sb); 600 601 /* 602 * Non-deep C-states 603 */ 604 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 605 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 606 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 607 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 608 M_DEVBUF, M_WAITOK); 609 610 hint_idx = 0; 611 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 612 int j, subcnt; 613 614 subcnt = cpu_mwait_cx_info[i].subcnt; 615 for (j = 0; j < subcnt; ++j) { 616 KASSERT(hint_idx < cpu_mwait_hints_cnt, 617 ("invalid mwait hint index %d", hint_idx)); 618 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 619 ++hint_idx; 620 } 621 } 622 KASSERT(hint_idx == cpu_mwait_hints_cnt, 623 ("mwait hint count %d != index %d", 624 cpu_mwait_hints_cnt, hint_idx)); 625 626 if (bootverbose) { 627 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 628 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 629 int hint = cpu_mwait_hints[i]; 630 631 kprintf(" C%d/%d hint 0x%04x\n", 632 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 633 hint); 634 } 635 } 636 637 /* 638 * Deep C-states 639 */ 640 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 641 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 642 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 643 M_DEVBUF, M_WAITOK); 644 645 hint_idx = 0; 646 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 647 int j, subcnt; 648 649 subcnt = cpu_mwait_cx_info[i].subcnt; 650 for (j = 0; j < subcnt; ++j) { 651 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 652 ("invalid mwait deep hint index %d", hint_idx)); 653 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 654 ++hint_idx; 655 } 656 } 657 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 658 ("mwait deep hint count %d != index %d", 659 cpu_mwait_deep_hints_cnt, hint_idx)); 660 661 if (bootverbose) { 662 kprintf("MWAIT deep hints:\n"); 663 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 664 int hint = cpu_mwait_deep_hints[i]; 665 666 kprintf(" C%d/%d hint 0x%04x\n", 667 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 668 hint); 669 } 670 } 671 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 672 673 for (i = 0; i < ncpus; ++i) { 674 char name[16]; 675 676 ksnprintf(name, sizeof(name), "idle%d", i); 677 SYSCTL_ADD_PROC(NULL, 678 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 679 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 680 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 681 } 682 } 683 684 static void 685 cpu_finish(void *dummy __unused) 686 { 687 cpu_setregs(); 688 cpu_mwait_attach(); 689 } 690 691 static void 692 pic_finish(void *dummy __unused) 693 { 694 /* Log ELCR information */ 695 elcr_dump(); 696 697 /* Log MPTABLE information */ 698 mptable_pci_int_dump(); 699 700 /* Finalize PCI */ 701 MachIntrABI.finalize(); 702 } 703 704 /* 705 * Send an interrupt to process. 706 * 707 * Stack is set up to allow sigcode stored 708 * at top to call routine, followed by kcall 709 * to sigreturn routine below. After sigreturn 710 * resets the signal mask, the stack, and the 711 * frame pointer, it returns to the user 712 * specified pc, psl. 713 */ 714 void 715 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 716 { 717 struct lwp *lp = curthread->td_lwp; 718 struct proc *p = lp->lwp_proc; 719 struct trapframe *regs; 720 struct sigacts *psp = p->p_sigacts; 721 struct sigframe sf, *sfp; 722 int oonstack; 723 char *sp; 724 725 regs = lp->lwp_md.md_regs; 726 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 727 728 /* Save user context */ 729 bzero(&sf, sizeof(struct sigframe)); 730 sf.sf_uc.uc_sigmask = *mask; 731 sf.sf_uc.uc_stack = lp->lwp_sigstk; 732 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 733 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 734 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 735 736 /* Make the size of the saved context visible to userland */ 737 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 738 739 /* Allocate and validate space for the signal handler context. */ 740 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 741 SIGISMEMBER(psp->ps_sigonstack, sig)) { 742 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 743 sizeof(struct sigframe)); 744 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 745 } else { 746 /* We take red zone into account */ 747 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 748 } 749 750 /* 751 * XXX AVX needs 64-byte alignment but sigframe has other fields and 752 * the embedded ucontext is not at the front, so aligning this won't 753 * help us. Fortunately we bcopy in/out of the sigframe, so the 754 * kernel is ok. 755 * 756 * The problem though is if userland winds up trying to use the 757 * context directly. 758 */ 759 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 760 761 /* Translate the signal is appropriate */ 762 if (p->p_sysent->sv_sigtbl) { 763 if (sig <= p->p_sysent->sv_sigsize) 764 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 765 } 766 767 /* 768 * Build the argument list for the signal handler. 769 * 770 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 771 */ 772 regs->tf_rdi = sig; /* argument 1 */ 773 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 774 775 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 776 /* 777 * Signal handler installed with SA_SIGINFO. 778 * 779 * action(signo, siginfo, ucontext) 780 */ 781 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 782 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 783 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 784 785 /* fill siginfo structure */ 786 sf.sf_si.si_signo = sig; 787 sf.sf_si.si_code = code; 788 sf.sf_si.si_addr = (void *)regs->tf_addr; 789 } else { 790 /* 791 * Old FreeBSD-style arguments. 792 * 793 * handler (signo, code, [uc], addr) 794 */ 795 regs->tf_rsi = (register_t)code; /* argument 2 */ 796 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 797 sf.sf_ahu.sf_handler = catcher; 798 } 799 800 /* 801 * If we're a vm86 process, we want to save the segment registers. 802 * We also change eflags to be our emulated eflags, not the actual 803 * eflags. 804 */ 805 #if 0 /* JG */ 806 if (regs->tf_eflags & PSL_VM) { 807 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 808 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 809 810 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 811 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 812 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 813 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 814 815 if (vm86->vm86_has_vme == 0) 816 sf.sf_uc.uc_mcontext.mc_eflags = 817 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 818 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 819 820 /* 821 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 822 * syscalls made by the signal handler. This just avoids 823 * wasting time for our lazy fixup of such faults. PSL_NT 824 * does nothing in vm86 mode, but vm86 programs can set it 825 * almost legitimately in probes for old cpu types. 826 */ 827 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 828 } 829 #endif 830 831 /* 832 * Save the FPU state and reinit the FP unit 833 */ 834 npxpush(&sf.sf_uc.uc_mcontext); 835 836 /* 837 * Copy the sigframe out to the user's stack. 838 */ 839 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 840 /* 841 * Something is wrong with the stack pointer. 842 * ...Kill the process. 843 */ 844 sigexit(lp, SIGILL); 845 } 846 847 regs->tf_rsp = (register_t)sfp; 848 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 849 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 850 851 /* 852 * i386 abi specifies that the direction flag must be cleared 853 * on function entry 854 */ 855 regs->tf_rflags &= ~(PSL_T | PSL_D); 856 857 /* 858 * 64 bit mode has a code and stack selector but 859 * no data or extra selector. %fs and %gs are not 860 * stored in-context. 861 */ 862 regs->tf_cs = _ucodesel; 863 regs->tf_ss = _udatasel; 864 clear_quickret(); 865 } 866 867 /* 868 * Sanitize the trapframe for a virtual kernel passing control to a custom 869 * VM context. Remove any items that would otherwise create a privilage 870 * issue. 871 * 872 * XXX at the moment we allow userland to set the resume flag. Is this a 873 * bad idea? 874 */ 875 int 876 cpu_sanitize_frame(struct trapframe *frame) 877 { 878 frame->tf_cs = _ucodesel; 879 frame->tf_ss = _udatasel; 880 /* XXX VM (8086) mode not supported? */ 881 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 882 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 883 884 return(0); 885 } 886 887 /* 888 * Sanitize the tls so loading the descriptor does not blow up 889 * on us. For x86_64 we don't have to do anything. 890 */ 891 int 892 cpu_sanitize_tls(struct savetls *tls) 893 { 894 return(0); 895 } 896 897 /* 898 * sigreturn(ucontext_t *sigcntxp) 899 * 900 * System call to cleanup state after a signal 901 * has been taken. Reset signal mask and 902 * stack state from context left by sendsig (above). 903 * Return to previous pc and psl as specified by 904 * context left by sendsig. Check carefully to 905 * make sure that the user has not modified the 906 * state to gain improper privileges. 907 * 908 * MPSAFE 909 */ 910 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 911 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 912 913 int 914 sys_sigreturn(struct sigreturn_args *uap) 915 { 916 struct lwp *lp = curthread->td_lwp; 917 struct trapframe *regs; 918 ucontext_t uc; 919 ucontext_t *ucp; 920 register_t rflags; 921 int cs; 922 int error; 923 924 /* 925 * We have to copy the information into kernel space so userland 926 * can't modify it while we are sniffing it. 927 */ 928 regs = lp->lwp_md.md_regs; 929 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 930 if (error) 931 return (error); 932 ucp = &uc; 933 rflags = ucp->uc_mcontext.mc_rflags; 934 935 /* VM (8086) mode not supported */ 936 rflags &= ~PSL_VM_UNSUPP; 937 938 #if 0 /* JG */ 939 if (eflags & PSL_VM) { 940 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 941 struct vm86_kernel *vm86; 942 943 /* 944 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 945 * set up the vm86 area, and we can't enter vm86 mode. 946 */ 947 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 948 return (EINVAL); 949 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 950 if (vm86->vm86_inited == 0) 951 return (EINVAL); 952 953 /* go back to user mode if both flags are set */ 954 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 955 trapsignal(lp, SIGBUS, 0); 956 957 if (vm86->vm86_has_vme) { 958 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 959 (eflags & VME_USERCHANGE) | PSL_VM; 960 } else { 961 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 962 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 963 (eflags & VM_USERCHANGE) | PSL_VM; 964 } 965 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 966 tf->tf_eflags = eflags; 967 tf->tf_vm86_ds = tf->tf_ds; 968 tf->tf_vm86_es = tf->tf_es; 969 tf->tf_vm86_fs = tf->tf_fs; 970 tf->tf_vm86_gs = tf->tf_gs; 971 tf->tf_ds = _udatasel; 972 tf->tf_es = _udatasel; 973 tf->tf_fs = _udatasel; 974 tf->tf_gs = _udatasel; 975 } else 976 #endif 977 { 978 /* 979 * Don't allow users to change privileged or reserved flags. 980 */ 981 /* 982 * XXX do allow users to change the privileged flag PSL_RF. 983 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 984 * should sometimes set it there too. tf_eflags is kept in 985 * the signal context during signal handling and there is no 986 * other place to remember it, so the PSL_RF bit may be 987 * corrupted by the signal handler without us knowing. 988 * Corruption of the PSL_RF bit at worst causes one more or 989 * one less debugger trap, so allowing it is fairly harmless. 990 */ 991 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 992 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 993 return(EINVAL); 994 } 995 996 /* 997 * Don't allow users to load a valid privileged %cs. Let the 998 * hardware check for invalid selectors, excess privilege in 999 * other selectors, invalid %eip's and invalid %esp's. 1000 */ 1001 cs = ucp->uc_mcontext.mc_cs; 1002 if (!CS_SECURE(cs)) { 1003 kprintf("sigreturn: cs = 0x%x\n", cs); 1004 trapsignal(lp, SIGBUS, T_PROTFLT); 1005 return(EINVAL); 1006 } 1007 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1008 } 1009 1010 /* 1011 * Restore the FPU state from the frame 1012 */ 1013 crit_enter(); 1014 npxpop(&ucp->uc_mcontext); 1015 1016 if (ucp->uc_mcontext.mc_onstack & 1) 1017 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1018 else 1019 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1020 1021 lp->lwp_sigmask = ucp->uc_sigmask; 1022 SIG_CANTMASK(lp->lwp_sigmask); 1023 clear_quickret(); 1024 crit_exit(); 1025 return(EJUSTRETURN); 1026 } 1027 1028 /* 1029 * Machine dependent boot() routine 1030 * 1031 * I haven't seen anything to put here yet 1032 * Possibly some stuff might be grafted back here from boot() 1033 */ 1034 void 1035 cpu_boot(int howto) 1036 { 1037 } 1038 1039 /* 1040 * Shutdown the CPU as much as possible 1041 */ 1042 void 1043 cpu_halt(void) 1044 { 1045 for (;;) 1046 __asm__ __volatile("hlt"); 1047 } 1048 1049 /* 1050 * cpu_idle() represents the idle LWKT. You cannot return from this function 1051 * (unless you want to blow things up!). Instead we look for runnable threads 1052 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1053 * 1054 * The main loop is entered with a critical section held, we must release 1055 * the critical section before doing anything else. lwkt_switch() will 1056 * check for pending interrupts due to entering and exiting its own 1057 * critical section. 1058 * 1059 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1060 * However, there are cases where the idlethread will be entered with 1061 * the possibility that no IPI will occur and in such cases 1062 * lwkt_switch() sets TDF_IDLE_NOHLT. 1063 * 1064 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1065 * must occur before it starts using ACPI halt. 1066 * 1067 * NOTE: Value overridden in hammer_time(). 1068 */ 1069 static int cpu_idle_hlt = 2; 1070 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1071 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1072 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1073 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1074 1075 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1076 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1077 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1078 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1079 1080 static void 1081 cpu_idle_default_hook(void) 1082 { 1083 /* 1084 * We must guarentee that hlt is exactly the instruction 1085 * following the sti. 1086 */ 1087 __asm __volatile("sti; hlt"); 1088 } 1089 1090 /* Other subsystems (e.g., ACPI) can hook this later. */ 1091 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1092 1093 static __inline int 1094 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1095 { 1096 int hint, cx_idx; 1097 u_int idx; 1098 1099 hint = stat->hint; 1100 if (hint >= 0) 1101 goto done; 1102 1103 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1104 cpu_mwait_repeat_shift; 1105 if (idx >= cpu_mwait_c1_hints_cnt) { 1106 /* Step up faster, once we walked through all C1 states */ 1107 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1108 } 1109 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1110 if (idx >= cpu_mwait_deep_hints_cnt) 1111 idx = cpu_mwait_deep_hints_cnt - 1; 1112 hint = cpu_mwait_deep_hints[idx]; 1113 } else { 1114 if (idx >= cpu_mwait_hints_cnt) 1115 idx = cpu_mwait_hints_cnt - 1; 1116 hint = cpu_mwait_hints[idx]; 1117 } 1118 done: 1119 cx_idx = MWAIT_EAX_TO_CX(hint); 1120 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1121 stat->mwait_cx[cx_idx]++; 1122 return hint; 1123 } 1124 1125 void 1126 cpu_idle(void) 1127 { 1128 globaldata_t gd = mycpu; 1129 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1130 struct thread *td __debugvar = gd->gd_curthread; 1131 int reqflags; 1132 int quick; 1133 1134 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1135 1136 crit_exit(); 1137 KKASSERT(td->td_critcount == 0); 1138 1139 for (;;) { 1140 /* 1141 * See if there are any LWKTs ready to go. 1142 */ 1143 lwkt_switch(); 1144 1145 /* 1146 * When halting inside a cli we must check for reqflags 1147 * races, particularly [re]schedule requests. Running 1148 * splz() does the job. 1149 * 1150 * cpu_idle_hlt: 1151 * 0 Never halt, just spin 1152 * 1153 * 1 Always use MONITOR/MWAIT if avail, HLT 1154 * otherwise. 1155 * 1156 * Better default for modern (Haswell+) Intel 1157 * cpus. 1158 * 1159 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1160 * use the ACPI halt (default). This is a hybrid 1161 * approach. See machdep.cpu_idle_repeat. 1162 * 1163 * Better default for modern AMD cpus and older 1164 * Intel cpus. 1165 * 1166 * 3 Always use the ACPI halt. This typically 1167 * eats the least amount of power but the cpu 1168 * will be slow waking up. Slows down e.g. 1169 * compiles and other pipe/event oriented stuff. 1170 * 1171 * Usually the best default for AMD cpus. 1172 * 1173 * 4 Always use HLT. 1174 * 1175 * 5 Always spin. 1176 * 1177 * NOTE: Interrupts are enabled and we are not in a critical 1178 * section. 1179 * 1180 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1181 * don't bother capping gd_idle_repeat, it is ok if 1182 * it overflows. 1183 * 1184 * Implement optimized invltlb operations when halted 1185 * in idle. By setting the bit in smp_idleinvl_mask 1186 * we inform other cpus that they can set _reqs to 1187 * request an invltlb. Current the code to do that 1188 * sets the bits in _reqs anyway, but then check _mask 1189 * to determine if they can assume the invltlb will execute. 1190 * 1191 * A critical section is required to ensure that interrupts 1192 * do not fully run until after we've had a chance to execute 1193 * the request. 1194 */ 1195 if (gd->gd_idle_repeat == 0) { 1196 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1197 if (stat->repeat > cpu_idle_repeat_max) 1198 stat->repeat = cpu_idle_repeat_max; 1199 stat->repeat_last = 0; 1200 stat->repeat_delta = 0; 1201 } 1202 ++stat->repeat_last; 1203 1204 ++gd->gd_idle_repeat; 1205 reqflags = gd->gd_reqflags; 1206 quick = (cpu_idle_hlt == 1) || 1207 (cpu_idle_hlt == 2 && 1208 gd->gd_idle_repeat < cpu_idle_repeat); 1209 1210 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1211 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1212 splz(); /* XXX */ 1213 crit_enter_gd(gd); 1214 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1215 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1216 cpu_mwait_cx_hint(stat), 0); 1217 stat->halt++; 1218 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1219 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1220 gd->gd_cpuid)) { 1221 cpu_invltlb(); 1222 cpu_mfence(); 1223 } 1224 crit_exit_gd(gd); 1225 } else if (cpu_idle_hlt) { 1226 __asm __volatile("cli"); 1227 splz(); 1228 crit_enter_gd(gd); 1229 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1230 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1231 if (cpu_idle_hlt == 5) { 1232 __asm __volatile("sti"); 1233 } else if (quick || cpu_idle_hlt == 4) { 1234 cpu_idle_default_hook(); 1235 } else { 1236 cpu_idle_hook(); 1237 } 1238 } 1239 __asm __volatile("sti"); 1240 stat->halt++; 1241 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1242 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1243 gd->gd_cpuid)) { 1244 cpu_invltlb(); 1245 cpu_mfence(); 1246 } 1247 crit_exit_gd(gd); 1248 } else { 1249 splz(); 1250 __asm __volatile("sti"); 1251 stat->spin++; 1252 crit_enter_gd(gd); 1253 crit_exit_gd(gd); 1254 } 1255 } 1256 } 1257 1258 /* 1259 * Called in a loop indirectly via Xcpustop 1260 */ 1261 void 1262 cpu_smp_stopped(void) 1263 { 1264 globaldata_t gd = mycpu; 1265 volatile __uint64_t *ptr; 1266 __uint64_t ovalue; 1267 1268 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1269 ovalue = *ptr; 1270 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1271 if (cpu_mi_feature & CPU_MI_MONITOR) { 1272 if (cpu_mwait_hints) { 1273 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1274 ovalue, 1275 cpu_mwait_hints[CPU_MWAIT_C1], 0); 1276 } else { 1277 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1278 ovalue, 0, 0); 1279 } 1280 } else { 1281 cpu_halt(); /* depend on lapic timer */ 1282 } 1283 } 1284 } 1285 1286 /* 1287 * This routine is called if a spinlock has been held through the 1288 * exponential backoff period and is seriously contested. On a real cpu 1289 * we let it spin. 1290 */ 1291 void 1292 cpu_spinlock_contested(void) 1293 { 1294 cpu_pause(); 1295 } 1296 1297 /* 1298 * Clear registers on exec 1299 */ 1300 void 1301 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1302 { 1303 struct thread *td = curthread; 1304 struct lwp *lp = td->td_lwp; 1305 struct pcb *pcb = td->td_pcb; 1306 struct trapframe *regs = lp->lwp_md.md_regs; 1307 1308 /* was i386_user_cleanup() in NetBSD */ 1309 user_ldt_free(pcb); 1310 1311 clear_quickret(); 1312 bzero((char *)regs, sizeof(struct trapframe)); 1313 regs->tf_rip = entry; 1314 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1315 regs->tf_rdi = stack; /* argv */ 1316 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1317 regs->tf_ss = _udatasel; 1318 regs->tf_cs = _ucodesel; 1319 regs->tf_rbx = ps_strings; 1320 1321 /* 1322 * Reset the hardware debug registers if they were in use. 1323 * They won't have any meaning for the newly exec'd process. 1324 */ 1325 if (pcb->pcb_flags & PCB_DBREGS) { 1326 pcb->pcb_dr0 = 0; 1327 pcb->pcb_dr1 = 0; 1328 pcb->pcb_dr2 = 0; 1329 pcb->pcb_dr3 = 0; 1330 pcb->pcb_dr6 = 0; 1331 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1332 if (pcb == td->td_pcb) { 1333 /* 1334 * Clear the debug registers on the running 1335 * CPU, otherwise they will end up affecting 1336 * the next process we switch to. 1337 */ 1338 reset_dbregs(); 1339 } 1340 pcb->pcb_flags &= ~PCB_DBREGS; 1341 } 1342 1343 /* 1344 * Initialize the math emulator (if any) for the current process. 1345 * Actually, just clear the bit that says that the emulator has 1346 * been initialized. Initialization is delayed until the process 1347 * traps to the emulator (if it is done at all) mainly because 1348 * emulators don't provide an entry point for initialization. 1349 */ 1350 pcb->pcb_flags &= ~FP_SOFTFP; 1351 1352 /* 1353 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1354 * gd_npxthread. Otherwise a preemptive interrupt thread 1355 * may panic in npxdna(). 1356 */ 1357 crit_enter(); 1358 load_cr0(rcr0() | CR0_MP); 1359 1360 /* 1361 * NOTE: The MSR values must be correct so we can return to 1362 * userland. gd_user_fs/gs must be correct so the switch 1363 * code knows what the current MSR values are. 1364 */ 1365 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1366 pcb->pcb_gsbase = 0; 1367 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1368 mdcpu->gd_user_gs = 0; 1369 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1370 wrmsr(MSR_KGSBASE, 0); 1371 1372 /* Initialize the npx (if any) for the current process. */ 1373 npxinit(); 1374 crit_exit(); 1375 1376 pcb->pcb_ds = _udatasel; 1377 pcb->pcb_es = _udatasel; 1378 pcb->pcb_fs = _udatasel; 1379 pcb->pcb_gs = _udatasel; 1380 } 1381 1382 void 1383 cpu_setregs(void) 1384 { 1385 register_t cr0; 1386 1387 cr0 = rcr0(); 1388 cr0 |= CR0_NE; /* Done by npxinit() */ 1389 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1390 cr0 |= CR0_WP | CR0_AM; 1391 load_cr0(cr0); 1392 load_gs(_udatasel); 1393 } 1394 1395 static int 1396 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1397 { 1398 int error; 1399 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1400 req); 1401 if (!error && req->newptr) 1402 resettodr(); 1403 return (error); 1404 } 1405 1406 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1407 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1408 1409 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1410 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1411 1412 #if 0 /* JG */ 1413 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1414 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1415 #endif 1416 1417 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1418 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1419 1420 static int 1421 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1422 { 1423 struct efi_map_header *efihdr; 1424 caddr_t kmdp; 1425 uint32_t efisize; 1426 1427 kmdp = preload_search_by_type("elf kernel"); 1428 if (kmdp == NULL) 1429 kmdp = preload_search_by_type("elf64 kernel"); 1430 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1431 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1432 if (efihdr == NULL) 1433 return (0); 1434 efisize = *((uint32_t *)efihdr - 1); 1435 return (SYSCTL_OUT(req, efihdr, efisize)); 1436 } 1437 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1438 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1439 1440 /* 1441 * Initialize 386 and configure to run kernel 1442 */ 1443 1444 /* 1445 * Initialize segments & interrupt table 1446 */ 1447 1448 int _default_ldt; 1449 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1450 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1451 #if 0 /* JG */ 1452 union descriptor ldt[NLDT]; /* local descriptor table */ 1453 #endif 1454 1455 /* table descriptors - used to load tables by cpu */ 1456 struct region_descriptor r_gdt; 1457 struct region_descriptor r_idt_arr[MAXCPU]; 1458 1459 /* JG proc0paddr is a virtual address */ 1460 void *proc0paddr; 1461 /* JG alignment? */ 1462 char proc0paddr_buff[LWKT_THREAD_STACK]; 1463 1464 1465 /* software prototypes -- in more palatable form */ 1466 struct soft_segment_descriptor gdt_segs[] = { 1467 /* GNULL_SEL 0 Null Descriptor */ 1468 { 0x0, /* segment base address */ 1469 0x0, /* length */ 1470 0, /* segment type */ 1471 0, /* segment descriptor priority level */ 1472 0, /* segment descriptor present */ 1473 0, /* long */ 1474 0, /* default 32 vs 16 bit size */ 1475 0 /* limit granularity (byte/page units)*/ }, 1476 /* GCODE_SEL 1 Code Descriptor for kernel */ 1477 { 0x0, /* segment base address */ 1478 0xfffff, /* length - all address space */ 1479 SDT_MEMERA, /* segment type */ 1480 SEL_KPL, /* segment descriptor priority level */ 1481 1, /* segment descriptor present */ 1482 1, /* long */ 1483 0, /* default 32 vs 16 bit size */ 1484 1 /* limit granularity (byte/page units)*/ }, 1485 /* GDATA_SEL 2 Data Descriptor for kernel */ 1486 { 0x0, /* segment base address */ 1487 0xfffff, /* length - all address space */ 1488 SDT_MEMRWA, /* segment type */ 1489 SEL_KPL, /* segment descriptor priority level */ 1490 1, /* segment descriptor present */ 1491 1, /* long */ 1492 0, /* default 32 vs 16 bit size */ 1493 1 /* limit granularity (byte/page units)*/ }, 1494 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1495 { 0x0, /* segment base address */ 1496 0xfffff, /* length - all address space */ 1497 SDT_MEMERA, /* segment type */ 1498 SEL_UPL, /* segment descriptor priority level */ 1499 1, /* segment descriptor present */ 1500 0, /* long */ 1501 1, /* default 32 vs 16 bit size */ 1502 1 /* limit granularity (byte/page units)*/ }, 1503 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1504 { 0x0, /* segment base address */ 1505 0xfffff, /* length - all address space */ 1506 SDT_MEMRWA, /* segment type */ 1507 SEL_UPL, /* segment descriptor priority level */ 1508 1, /* segment descriptor present */ 1509 0, /* long */ 1510 1, /* default 32 vs 16 bit size */ 1511 1 /* limit granularity (byte/page units)*/ }, 1512 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1513 { 0x0, /* segment base address */ 1514 0xfffff, /* length - all address space */ 1515 SDT_MEMERA, /* segment type */ 1516 SEL_UPL, /* segment descriptor priority level */ 1517 1, /* segment descriptor present */ 1518 1, /* long */ 1519 0, /* default 32 vs 16 bit size */ 1520 1 /* limit granularity (byte/page units)*/ }, 1521 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1522 { 1523 0x0, /* segment base address */ 1524 sizeof(struct x86_64tss)-1,/* length - all address space */ 1525 SDT_SYSTSS, /* segment type */ 1526 SEL_KPL, /* segment descriptor priority level */ 1527 1, /* segment descriptor present */ 1528 0, /* long */ 1529 0, /* unused - default 32 vs 16 bit size */ 1530 0 /* limit granularity (byte/page units)*/ }, 1531 /* Actually, the TSS is a system descriptor which is double size */ 1532 { 0x0, /* segment base address */ 1533 0x0, /* length */ 1534 0, /* segment type */ 1535 0, /* segment descriptor priority level */ 1536 0, /* segment descriptor present */ 1537 0, /* long */ 1538 0, /* default 32 vs 16 bit size */ 1539 0 /* limit granularity (byte/page units)*/ }, 1540 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1541 { 0x0, /* segment base address */ 1542 0xfffff, /* length - all address space */ 1543 SDT_MEMRWA, /* segment type */ 1544 SEL_UPL, /* segment descriptor priority level */ 1545 1, /* segment descriptor present */ 1546 0, /* long */ 1547 1, /* default 32 vs 16 bit size */ 1548 1 /* limit granularity (byte/page units)*/ }, 1549 }; 1550 1551 void 1552 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1553 { 1554 int cpu; 1555 1556 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1557 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1558 1559 ip->gd_looffset = (uintptr_t)func; 1560 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1561 ip->gd_ist = ist; 1562 ip->gd_xx = 0; 1563 ip->gd_type = typ; 1564 ip->gd_dpl = dpl; 1565 ip->gd_p = 1; 1566 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1567 } 1568 } 1569 1570 void 1571 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1572 { 1573 struct gate_descriptor *ip; 1574 1575 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1576 1577 ip = &idt_arr[cpu][idx]; 1578 ip->gd_looffset = (uintptr_t)func; 1579 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1580 ip->gd_ist = ist; 1581 ip->gd_xx = 0; 1582 ip->gd_type = typ; 1583 ip->gd_dpl = dpl; 1584 ip->gd_p = 1; 1585 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1586 } 1587 1588 #define IDTVEC(name) __CONCAT(X,name) 1589 1590 extern inthand_t 1591 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1592 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1593 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1594 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1595 IDTVEC(xmm), IDTVEC(dblfault), 1596 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1597 1598 void 1599 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1600 { 1601 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1602 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1603 ssd->ssd_type = sd->sd_type; 1604 ssd->ssd_dpl = sd->sd_dpl; 1605 ssd->ssd_p = sd->sd_p; 1606 ssd->ssd_def32 = sd->sd_def32; 1607 ssd->ssd_gran = sd->sd_gran; 1608 } 1609 1610 void 1611 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1612 { 1613 1614 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1615 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1616 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1617 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1618 sd->sd_type = ssd->ssd_type; 1619 sd->sd_dpl = ssd->ssd_dpl; 1620 sd->sd_p = ssd->ssd_p; 1621 sd->sd_long = ssd->ssd_long; 1622 sd->sd_def32 = ssd->ssd_def32; 1623 sd->sd_gran = ssd->ssd_gran; 1624 } 1625 1626 void 1627 ssdtosyssd(struct soft_segment_descriptor *ssd, 1628 struct system_segment_descriptor *sd) 1629 { 1630 1631 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1632 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1633 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1634 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1635 sd->sd_type = ssd->ssd_type; 1636 sd->sd_dpl = ssd->ssd_dpl; 1637 sd->sd_p = ssd->ssd_p; 1638 sd->sd_gran = ssd->ssd_gran; 1639 } 1640 1641 /* 1642 * Populate the (physmap) array with base/bound pairs describing the 1643 * available physical memory in the system, then test this memory and 1644 * build the phys_avail array describing the actually-available memory. 1645 * 1646 * If we cannot accurately determine the physical memory map, then use 1647 * value from the 0xE801 call, and failing that, the RTC. 1648 * 1649 * Total memory size may be set by the kernel environment variable 1650 * hw.physmem or the compile-time define MAXMEM. 1651 * 1652 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1653 * of PAGE_SIZE. This also greatly reduces the memory test time 1654 * which would otherwise be excessive on machines with > 8G of ram. 1655 * 1656 * XXX first should be vm_paddr_t. 1657 */ 1658 1659 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1660 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1661 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1662 1663 vm_paddr_t physmap[PHYSMAP_SIZE]; 1664 struct bios_smap *smapbase, *smap, *smapend; 1665 struct efi_map_header *efihdrbase; 1666 u_int32_t smapsize; 1667 1668 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1669 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1670 1671 static void 1672 add_smap_entries(int *physmap_idx) 1673 { 1674 int i; 1675 1676 smapsize = *((u_int32_t *)smapbase - 1); 1677 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1678 1679 for (smap = smapbase; smap < smapend; smap++) { 1680 if (boothowto & RB_VERBOSE) 1681 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1682 smap->type, smap->base, smap->length); 1683 1684 if (smap->type != SMAP_TYPE_MEMORY) 1685 continue; 1686 1687 if (smap->length == 0) 1688 continue; 1689 1690 for (i = 0; i <= *physmap_idx; i += 2) { 1691 if (smap->base < physmap[i + 1]) { 1692 if (boothowto & RB_VERBOSE) { 1693 kprintf("Overlapping or non-monotonic " 1694 "memory region, ignoring " 1695 "second region\n"); 1696 } 1697 break; 1698 } 1699 } 1700 if (i <= *physmap_idx) 1701 continue; 1702 1703 Realmem += smap->length; 1704 1705 if (smap->base == physmap[*physmap_idx + 1]) { 1706 physmap[*physmap_idx + 1] += smap->length; 1707 continue; 1708 } 1709 1710 *physmap_idx += 2; 1711 if (*physmap_idx == PHYSMAP_SIZE) { 1712 kprintf("Too many segments in the physical " 1713 "address map, giving up\n"); 1714 break; 1715 } 1716 physmap[*physmap_idx] = smap->base; 1717 physmap[*physmap_idx + 1] = smap->base + smap->length; 1718 } 1719 } 1720 1721 static void 1722 add_efi_map_entries(int *physmap_idx) 1723 { 1724 struct efi_md *map, *p; 1725 const char *type; 1726 size_t efisz; 1727 int i, ndesc; 1728 1729 static const char *types[] = { 1730 "Reserved", 1731 "LoaderCode", 1732 "LoaderData", 1733 "BootServicesCode", 1734 "BootServicesData", 1735 "RuntimeServicesCode", 1736 "RuntimeServicesData", 1737 "ConventionalMemory", 1738 "UnusableMemory", 1739 "ACPIReclaimMemory", 1740 "ACPIMemoryNVS", 1741 "MemoryMappedIO", 1742 "MemoryMappedIOPortSpace", 1743 "PalCode" 1744 }; 1745 1746 /* 1747 * Memory map data provided by UEFI via the GetMemoryMap 1748 * Boot Services API. 1749 */ 1750 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1751 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1752 1753 if (efihdrbase->descriptor_size == 0) 1754 return; 1755 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1756 1757 if (boothowto & RB_VERBOSE) 1758 kprintf("%23s %12s %12s %8s %4s\n", 1759 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1760 1761 for (i = 0, p = map; i < ndesc; i++, 1762 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1763 if (boothowto & RB_VERBOSE) { 1764 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1765 type = types[p->md_type]; 1766 else 1767 type = "<INVALID>"; 1768 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1769 p->md_virt, p->md_pages); 1770 if (p->md_attr & EFI_MD_ATTR_UC) 1771 kprintf("UC "); 1772 if (p->md_attr & EFI_MD_ATTR_WC) 1773 kprintf("WC "); 1774 if (p->md_attr & EFI_MD_ATTR_WT) 1775 kprintf("WT "); 1776 if (p->md_attr & EFI_MD_ATTR_WB) 1777 kprintf("WB "); 1778 if (p->md_attr & EFI_MD_ATTR_UCE) 1779 kprintf("UCE "); 1780 if (p->md_attr & EFI_MD_ATTR_WP) 1781 kprintf("WP "); 1782 if (p->md_attr & EFI_MD_ATTR_RP) 1783 kprintf("RP "); 1784 if (p->md_attr & EFI_MD_ATTR_XP) 1785 kprintf("XP "); 1786 if (p->md_attr & EFI_MD_ATTR_RT) 1787 kprintf("RUNTIME"); 1788 kprintf("\n"); 1789 } 1790 1791 switch (p->md_type) { 1792 case EFI_MD_TYPE_CODE: 1793 case EFI_MD_TYPE_DATA: 1794 case EFI_MD_TYPE_BS_CODE: 1795 case EFI_MD_TYPE_BS_DATA: 1796 case EFI_MD_TYPE_FREE: 1797 /* 1798 * We're allowed to use any entry with these types. 1799 */ 1800 break; 1801 default: 1802 continue; 1803 } 1804 1805 Realmem += p->md_pages * PAGE_SIZE; 1806 1807 if (p->md_phys == physmap[*physmap_idx + 1]) { 1808 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1809 continue; 1810 } 1811 1812 *physmap_idx += 2; 1813 if (*physmap_idx == PHYSMAP_SIZE) { 1814 kprintf("Too many segments in the physical " 1815 "address map, giving up\n"); 1816 break; 1817 } 1818 physmap[*physmap_idx] = p->md_phys; 1819 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1820 } 1821 } 1822 1823 struct fb_info efi_fb_info; 1824 static int have_efi_framebuffer = 0; 1825 1826 static void 1827 efi_fb_init_vaddr(int direct_map) 1828 { 1829 uint64_t sz; 1830 vm_offset_t addr, v; 1831 1832 v = efi_fb_info.vaddr; 1833 sz = efi_fb_info.stride * efi_fb_info.height; 1834 1835 if (direct_map) { 1836 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1837 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1838 efi_fb_info.vaddr = addr; 1839 } else { 1840 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1841 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1842 } 1843 } 1844 1845 static u_int 1846 efifb_color_depth(struct efi_fb *efifb) 1847 { 1848 uint32_t mask; 1849 u_int depth; 1850 1851 mask = efifb->fb_mask_red | efifb->fb_mask_green | 1852 efifb->fb_mask_blue | efifb->fb_mask_reserved; 1853 if (mask == 0) 1854 return (0); 1855 for (depth = 1; mask != 1; depth++) 1856 mask >>= 1; 1857 return (depth); 1858 } 1859 1860 int 1861 probe_efi_fb(int early) 1862 { 1863 struct efi_fb *efifb; 1864 caddr_t kmdp; 1865 u_int depth; 1866 1867 if (have_efi_framebuffer) { 1868 if (!early && 1869 (efi_fb_info.vaddr == 0 || 1870 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 1871 efi_fb_init_vaddr(0); 1872 return 0; 1873 } 1874 1875 kmdp = preload_search_by_type("elf kernel"); 1876 if (kmdp == NULL) 1877 kmdp = preload_search_by_type("elf64 kernel"); 1878 efifb = (struct efi_fb *)preload_search_info(kmdp, 1879 MODINFO_METADATA | MODINFOMD_EFI_FB); 1880 if (efifb == NULL) 1881 return 1; 1882 1883 depth = efifb_color_depth(efifb); 1884 /* 1885 * Our bootloader should already notice, when we won't be able to 1886 * use the UEFI framebuffer. 1887 */ 1888 if (depth != 24 && depth != 32) 1889 return 1; 1890 1891 have_efi_framebuffer = 1; 1892 1893 efi_fb_info.is_vga_boot_display = 1; 1894 efi_fb_info.width = efifb->fb_width; 1895 efi_fb_info.height = efifb->fb_height; 1896 efi_fb_info.depth = depth; 1897 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 1898 efi_fb_info.paddr = efifb->fb_addr; 1899 if (early) { 1900 efi_fb_info.vaddr = 0; 1901 } else { 1902 efi_fb_init_vaddr(0); 1903 } 1904 efi_fb_info.fbops.fb_set_par = NULL; 1905 efi_fb_info.fbops.fb_blank = NULL; 1906 efi_fb_info.fbops.fb_debug_enter = NULL; 1907 efi_fb_info.device = NULL; 1908 1909 return 0; 1910 } 1911 1912 static void 1913 efifb_startup(void *arg) 1914 { 1915 probe_efi_fb(0); 1916 } 1917 1918 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 1919 1920 static void 1921 getmemsize(caddr_t kmdp, u_int64_t first) 1922 { 1923 int off, physmap_idx, pa_indx, da_indx; 1924 int i, j; 1925 vm_paddr_t pa; 1926 vm_paddr_t msgbuf_size; 1927 u_long physmem_tunable; 1928 pt_entry_t *pte; 1929 quad_t dcons_addr, dcons_size; 1930 1931 bzero(physmap, sizeof(physmap)); 1932 physmap_idx = 0; 1933 1934 /* 1935 * get memory map from INT 15:E820, kindly supplied by the loader. 1936 * 1937 * subr_module.c says: 1938 * "Consumer may safely assume that size value precedes data." 1939 * ie: an int32_t immediately precedes smap. 1940 */ 1941 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 1942 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1943 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1944 MODINFO_METADATA | MODINFOMD_SMAP); 1945 if (smapbase == NULL && efihdrbase == NULL) 1946 panic("No BIOS smap or EFI map info from loader!"); 1947 1948 if (efihdrbase == NULL) 1949 add_smap_entries(&physmap_idx); 1950 else 1951 add_efi_map_entries(&physmap_idx); 1952 1953 base_memory = physmap[1] / 1024; 1954 /* make hole for AP bootstrap code */ 1955 physmap[1] = mp_bootaddress(base_memory); 1956 1957 /* Save EBDA address, if any */ 1958 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1959 ebda_addr <<= 4; 1960 1961 /* 1962 * Maxmem isn't the "maximum memory", it's one larger than the 1963 * highest page of the physical address space. It should be 1964 * called something like "Maxphyspage". We may adjust this 1965 * based on ``hw.physmem'' and the results of the memory test. 1966 */ 1967 Maxmem = atop(physmap[physmap_idx + 1]); 1968 1969 #ifdef MAXMEM 1970 Maxmem = MAXMEM / 4; 1971 #endif 1972 1973 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1974 Maxmem = atop(physmem_tunable); 1975 1976 /* 1977 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1978 * in the system. 1979 */ 1980 if (Maxmem > atop(physmap[physmap_idx + 1])) 1981 Maxmem = atop(physmap[physmap_idx + 1]); 1982 1983 /* 1984 * Blowing out the DMAP will blow up the system. 1985 */ 1986 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1987 kprintf("Limiting Maxmem due to DMAP size\n"); 1988 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1989 } 1990 1991 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1992 (boothowto & RB_VERBOSE)) { 1993 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1994 } 1995 1996 /* 1997 * Call pmap initialization to make new kernel address space 1998 * 1999 * Mask off page 0. 2000 */ 2001 pmap_bootstrap(&first); 2002 physmap[0] = PAGE_SIZE; 2003 2004 /* 2005 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2006 * exceeding Maxmem. 2007 */ 2008 for (i = j = 0; i <= physmap_idx; i += 2) { 2009 if (physmap[i+1] > ptoa(Maxmem)) 2010 physmap[i+1] = ptoa(Maxmem); 2011 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2012 ~PHYSMAP_ALIGN_MASK; 2013 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2014 2015 physmap[j] = physmap[i]; 2016 physmap[j+1] = physmap[i+1]; 2017 2018 if (physmap[i] < physmap[i+1]) 2019 j += 2; 2020 } 2021 physmap_idx = j - 2; 2022 2023 /* 2024 * Align anything else used in the validation loop. 2025 */ 2026 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2027 2028 /* 2029 * Size up each available chunk of physical memory. 2030 */ 2031 pa_indx = 0; 2032 da_indx = 0; 2033 phys_avail[pa_indx].phys_beg = physmap[0]; 2034 phys_avail[pa_indx].phys_end = physmap[0]; 2035 dump_avail[da_indx].phys_beg = 0; 2036 dump_avail[da_indx].phys_end = physmap[0]; 2037 pte = CMAP1; 2038 2039 /* 2040 * Get dcons buffer address 2041 */ 2042 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2043 kgetenv_quad("dcons.size", &dcons_size) == 0) 2044 dcons_addr = 0; 2045 2046 /* 2047 * Validate the physical memory. The physical memory segments 2048 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2049 * of PAGE_SIZE. 2050 */ 2051 for (i = 0; i <= physmap_idx; i += 2) { 2052 vm_paddr_t end; 2053 vm_paddr_t incr = PHYSMAP_ALIGN; 2054 2055 end = physmap[i + 1]; 2056 2057 for (pa = physmap[i]; pa < end; pa += incr) { 2058 int page_bad, full; 2059 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2060 uint64_t tmp; 2061 2062 incr = PHYSMAP_ALIGN; 2063 full = FALSE; 2064 2065 /* 2066 * block out kernel memory as not available. 2067 */ 2068 if (pa >= 0x200000 && pa < first) 2069 goto do_dump_avail; 2070 2071 /* 2072 * block out dcons buffer 2073 */ 2074 if (dcons_addr > 0 2075 && pa >= trunc_page(dcons_addr) 2076 && pa < dcons_addr + dcons_size) { 2077 goto do_dump_avail; 2078 } 2079 2080 page_bad = FALSE; 2081 2082 /* 2083 * Always test the first and last block supplied in 2084 * the map entry, but it just takes too long to run 2085 * the test these days and we already have to skip 2086 * pages. Handwave it on PHYSMAP_HANDWAVE boundaries. 2087 */ 2088 if (pa != physmap[i]) { 2089 vm_paddr_t bytes = end - pa; 2090 if ((pa & PHYSMAP_HANDWAVE_MASK) == 0 && 2091 bytes >= PHYSMAP_HANDWAVE + PHYSMAP_ALIGN) { 2092 incr = PHYSMAP_HANDWAVE; 2093 goto handwaved; 2094 } 2095 } 2096 2097 /* 2098 * map page into kernel: valid, read/write,non-cacheable 2099 */ 2100 *pte = pa | 2101 kernel_pmap.pmap_bits[PG_V_IDX] | 2102 kernel_pmap.pmap_bits[PG_RW_IDX] | 2103 kernel_pmap.pmap_bits[PG_N_IDX]; 2104 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2105 cpu_mfence(); 2106 2107 tmp = *ptr; 2108 /* 2109 * Test for alternating 1's and 0's 2110 */ 2111 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2112 cpu_mfence(); 2113 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2114 page_bad = TRUE; 2115 /* 2116 * Test for alternating 0's and 1's 2117 */ 2118 *ptr = 0x5555555555555555LLU; 2119 cpu_mfence(); 2120 if (*ptr != 0x5555555555555555LLU) 2121 page_bad = TRUE; 2122 /* 2123 * Test for all 1's 2124 */ 2125 *ptr = 0xffffffffffffffffLLU; 2126 cpu_mfence(); 2127 if (*ptr != 0xffffffffffffffffLLU) 2128 page_bad = TRUE; 2129 /* 2130 * Test for all 0's 2131 */ 2132 *ptr = 0x0; 2133 cpu_mfence(); 2134 if (*ptr != 0x0) 2135 page_bad = TRUE; 2136 /* 2137 * Restore original value. 2138 */ 2139 *ptr = tmp; 2140 handwaved: 2141 2142 /* 2143 * Adjust array of valid/good pages. 2144 */ 2145 if (page_bad == TRUE) 2146 continue; 2147 2148 /* 2149 * If this good page is a continuation of the 2150 * previous set of good pages, then just increase 2151 * the end pointer. Otherwise start a new chunk. 2152 * Note that "end" points one higher than end, 2153 * making the range >= start and < end. 2154 * If we're also doing a speculative memory 2155 * test and we at or past the end, bump up Maxmem 2156 * so that we keep going. The first bad page 2157 * will terminate the loop. 2158 */ 2159 if (phys_avail[pa_indx].phys_end == pa) { 2160 phys_avail[pa_indx].phys_end += incr; 2161 } else { 2162 ++pa_indx; 2163 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2164 kprintf( 2165 "Too many holes in the physical address space, giving up\n"); 2166 --pa_indx; 2167 full = TRUE; 2168 goto do_dump_avail; 2169 } 2170 phys_avail[pa_indx].phys_beg = pa; 2171 phys_avail[pa_indx].phys_end = pa + incr; 2172 } 2173 physmem += incr / PAGE_SIZE; 2174 do_dump_avail: 2175 if (dump_avail[da_indx].phys_end == pa) { 2176 dump_avail[da_indx].phys_end += incr; 2177 } else { 2178 ++da_indx; 2179 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2180 --da_indx; 2181 goto do_next; 2182 } 2183 dump_avail[da_indx].phys_beg = pa; 2184 dump_avail[da_indx].phys_end = pa + incr; 2185 } 2186 do_next: 2187 if (full) 2188 break; 2189 } 2190 } 2191 *pte = 0; 2192 cpu_invltlb(); 2193 cpu_mfence(); 2194 2195 /* 2196 * The last chunk must contain at least one page plus the message 2197 * buffer to avoid complicating other code (message buffer address 2198 * calculation, etc.). 2199 */ 2200 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2201 2202 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2203 phys_avail[pa_indx].phys_end) { 2204 physmem -= atop(phys_avail[pa_indx].phys_end - 2205 phys_avail[pa_indx].phys_beg); 2206 phys_avail[pa_indx].phys_beg = 0; 2207 phys_avail[pa_indx].phys_end = 0; 2208 --pa_indx; 2209 } 2210 2211 Maxmem = atop(phys_avail[pa_indx].phys_end); 2212 2213 /* Trim off space for the message buffer. */ 2214 phys_avail[pa_indx].phys_end -= msgbuf_size; 2215 2216 avail_end = phys_avail[pa_indx].phys_end; 2217 2218 /* Map the message buffer. */ 2219 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2220 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2221 } 2222 /* Try to get EFI framebuffer working as early as possible */ 2223 if (have_efi_framebuffer) 2224 efi_fb_init_vaddr(1); 2225 } 2226 2227 struct machintr_abi MachIntrABI; 2228 2229 /* 2230 * IDT VECTORS: 2231 * 0 Divide by zero 2232 * 1 Debug 2233 * 2 NMI 2234 * 3 BreakPoint 2235 * 4 OverFlow 2236 * 5 Bound-Range 2237 * 6 Invalid OpCode 2238 * 7 Device Not Available (x87) 2239 * 8 Double-Fault 2240 * 9 Coprocessor Segment overrun (unsupported, reserved) 2241 * 10 Invalid-TSS 2242 * 11 Segment not present 2243 * 12 Stack 2244 * 13 General Protection 2245 * 14 Page Fault 2246 * 15 Reserved 2247 * 16 x87 FP Exception pending 2248 * 17 Alignment Check 2249 * 18 Machine Check 2250 * 19 SIMD floating point 2251 * 20-31 reserved 2252 * 32-255 INTn/external sources 2253 */ 2254 u_int64_t 2255 hammer_time(u_int64_t modulep, u_int64_t physfree) 2256 { 2257 caddr_t kmdp; 2258 int gsel_tss, x, cpu; 2259 #if 0 /* JG */ 2260 int metadata_missing, off; 2261 #endif 2262 struct mdglobaldata *gd; 2263 u_int64_t msr; 2264 2265 /* 2266 * Prevent lowering of the ipl if we call tsleep() early. 2267 */ 2268 gd = &CPU_prvspace[0]->mdglobaldata; 2269 bzero(gd, sizeof(*gd)); 2270 2271 /* 2272 * Note: on both UP and SMP curthread must be set non-NULL 2273 * early in the boot sequence because the system assumes 2274 * that 'curthread' is never NULL. 2275 */ 2276 2277 gd->mi.gd_curthread = &thread0; 2278 thread0.td_gd = &gd->mi; 2279 2280 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2281 2282 #if 0 /* JG */ 2283 metadata_missing = 0; 2284 if (bootinfo.bi_modulep) { 2285 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2286 preload_bootstrap_relocate(KERNBASE); 2287 } else { 2288 metadata_missing = 1; 2289 } 2290 if (bootinfo.bi_envp) 2291 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2292 #endif 2293 2294 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2295 preload_bootstrap_relocate(PTOV_OFFSET); 2296 kmdp = preload_search_by_type("elf kernel"); 2297 if (kmdp == NULL) 2298 kmdp = preload_search_by_type("elf64 kernel"); 2299 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2300 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2301 #ifdef DDB 2302 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2303 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2304 #endif 2305 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2306 2307 if (boothowto & RB_VERBOSE) 2308 bootverbose++; 2309 2310 /* 2311 * Default MachIntrABI to ICU 2312 */ 2313 MachIntrABI = MachIntrABI_ICU; 2314 2315 /* 2316 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2317 */ 2318 ncpus = 1; 2319 ncpus_fit = 1; 2320 /* Init basic tunables, hz etc */ 2321 init_param1(); 2322 2323 /* 2324 * make gdt memory segments 2325 */ 2326 gdt_segs[GPROC0_SEL].ssd_base = 2327 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss; 2328 2329 gd->mi.gd_prvspace = CPU_prvspace[0]; 2330 2331 for (x = 0; x < NGDT; x++) { 2332 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2333 ssdtosd(&gdt_segs[x], &gdt[x]); 2334 } 2335 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2336 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2337 2338 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2339 r_gdt.rd_base = (long) gdt; 2340 lgdt(&r_gdt); 2341 2342 wrmsr(MSR_FSBASE, 0); /* User value */ 2343 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2344 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2345 2346 mi_gdinit(&gd->mi, 0); 2347 cpu_gdinit(gd, 0); 2348 proc0paddr = proc0paddr_buff; 2349 mi_proc0init(&gd->mi, proc0paddr); 2350 safepri = TDPRI_MAX; 2351 2352 /* spinlocks and the BGL */ 2353 init_locks(); 2354 2355 /* exceptions */ 2356 for (x = 0; x < NIDT; x++) 2357 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2358 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2359 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2360 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2361 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2362 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2363 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2364 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2365 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2366 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2367 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2368 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2369 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2370 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2371 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2372 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2373 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2374 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2375 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2376 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2377 2378 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2379 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2380 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2381 } 2382 2383 lidt(&r_idt_arr[0]); 2384 2385 /* 2386 * Initialize the console before we print anything out. 2387 */ 2388 cninit(); 2389 2390 #if 0 /* JG */ 2391 if (metadata_missing) 2392 kprintf("WARNING: loader(8) metadata is missing!\n"); 2393 #endif 2394 2395 #if NISA >0 2396 elcr_probe(); 2397 isa_defaultirq(); 2398 #endif 2399 rand_initialize(); 2400 2401 /* 2402 * Initialize IRQ mapping 2403 * 2404 * NOTE: 2405 * SHOULD be after elcr_probe() 2406 */ 2407 MachIntrABI_ICU.initmap(); 2408 MachIntrABI_IOAPIC.initmap(); 2409 2410 #ifdef DDB 2411 kdb_init(); 2412 if (boothowto & RB_KDB) 2413 Debugger("Boot flags requested debugger"); 2414 #endif 2415 2416 #if 0 /* JG */ 2417 finishidentcpu(); /* Final stage of CPU initialization */ 2418 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2419 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2420 #endif 2421 identify_cpu(); /* Final stage of CPU initialization */ 2422 initializecpu(0); /* Initialize CPU registers */ 2423 2424 /* 2425 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2426 * because the cpu does significant power management in MWAIT 2427 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2428 * 2429 * On modern AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2430 * significant power management only when using ACPI halt mode. 2431 * 2432 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2433 * is needed to reduce power consumption, but wakeup times are often 2434 * too long longer. 2435 */ 2436 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2437 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2438 cpu_idle_hlt = 1; 2439 } 2440 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2441 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2442 /* Ryzen or later */ 2443 cpu_idle_hlt = 3; 2444 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2445 /* Bobcat or later */ 2446 cpu_idle_hlt = 3; 2447 } 2448 } 2449 2450 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2451 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2452 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2453 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2454 2455 /* 2456 * Some of the virtual machines do not work w/ I/O APIC 2457 * enabled. If the user does not explicitly enable or 2458 * disable the I/O APIC (ioapic_enable < 0), then we 2459 * disable I/O APIC on all virtual machines. 2460 * 2461 * NOTE: 2462 * This must be done after identify_cpu(), which sets 2463 * 'cpu_feature2' 2464 */ 2465 if (ioapic_enable < 0) { 2466 if (cpu_feature2 & CPUID2_VMM) 2467 ioapic_enable = 0; 2468 else 2469 ioapic_enable = 1; 2470 } 2471 2472 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2473 gd->gd_common_tss.tss_rsp0 = 2474 (register_t)(thread0.td_kstack + 2475 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 2476 /* Ensure the stack is aligned to 16 bytes */ 2477 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 2478 2479 /* double fault stack */ 2480 gd->gd_common_tss.tss_ist1 = 2481 (long)&gd->mi.gd_prvspace->idlestack[ 2482 sizeof(gd->mi.gd_prvspace->idlestack)]; 2483 2484 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2485 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 2486 2487 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2488 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2489 gd->gd_common_tssd = *gd->gd_tss_gdt; 2490 ltr(gsel_tss); 2491 2492 /* Set up the fast syscall stuff */ 2493 msr = rdmsr(MSR_EFER) | EFER_SCE; 2494 wrmsr(MSR_EFER, msr); 2495 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2496 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2497 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2498 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2499 wrmsr(MSR_STAR, msr); 2500 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2501 2502 getmemsize(kmdp, physfree); 2503 init_param2(physmem); 2504 2505 /* now running on new page tables, configured,and u/iom is accessible */ 2506 2507 /* Map the message buffer. */ 2508 #if 0 /* JG */ 2509 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2510 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2511 #endif 2512 2513 msgbufinit(msgbufp, MSGBUF_SIZE); 2514 2515 2516 /* transfer to user mode */ 2517 2518 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2519 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2520 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2521 2522 load_ds(_udatasel); 2523 load_es(_udatasel); 2524 load_fs(_udatasel); 2525 2526 /* setup proc 0's pcb */ 2527 thread0.td_pcb->pcb_flags = 0; 2528 thread0.td_pcb->pcb_cr3 = KPML4phys; 2529 thread0.td_pcb->pcb_ext = NULL; 2530 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2531 2532 /* Location of kernel stack for locore */ 2533 return ((u_int64_t)thread0.td_pcb); 2534 } 2535 2536 /* 2537 * Initialize machine-dependant portions of the global data structure. 2538 * Note that the global data area and cpu0's idlestack in the private 2539 * data space were allocated in locore. 2540 * 2541 * Note: the idlethread's cpl is 0 2542 * 2543 * WARNING! Called from early boot, 'mycpu' may not work yet. 2544 */ 2545 void 2546 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2547 { 2548 if (cpu) 2549 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2550 2551 lwkt_init_thread(&gd->mi.gd_idlethread, 2552 gd->mi.gd_prvspace->idlestack, 2553 sizeof(gd->mi.gd_prvspace->idlestack), 2554 0, &gd->mi); 2555 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2556 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2557 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2558 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2559 } 2560 2561 /* 2562 * We only have to check for DMAP bounds, the globaldata space is 2563 * actually part of the kernel_map so we don't have to waste time 2564 * checking CPU_prvspace[*]. 2565 */ 2566 int 2567 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2568 { 2569 #if 0 2570 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2571 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2572 return (TRUE); 2573 } 2574 #endif 2575 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2576 return (TRUE); 2577 return (FALSE); 2578 } 2579 2580 struct globaldata * 2581 globaldata_find(int cpu) 2582 { 2583 KKASSERT(cpu >= 0 && cpu < ncpus); 2584 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2585 } 2586 2587 /* 2588 * This path should be safe from the SYSRET issue because only stopped threads 2589 * can have their %rip adjusted this way (and all heavy weight thread switches 2590 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2591 * convoluted so add a safety by forcing %rip to be cannonical. 2592 */ 2593 int 2594 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2595 { 2596 if (addr & 0x0000800000000000LLU) 2597 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2598 else 2599 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2600 return (0); 2601 } 2602 2603 int 2604 ptrace_single_step(struct lwp *lp) 2605 { 2606 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2607 return (0); 2608 } 2609 2610 int 2611 fill_regs(struct lwp *lp, struct reg *regs) 2612 { 2613 struct trapframe *tp; 2614 2615 if ((tp = lp->lwp_md.md_regs) == NULL) 2616 return EINVAL; 2617 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2618 return (0); 2619 } 2620 2621 int 2622 set_regs(struct lwp *lp, struct reg *regs) 2623 { 2624 struct trapframe *tp; 2625 2626 tp = lp->lwp_md.md_regs; 2627 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2628 !CS_SECURE(regs->r_cs)) 2629 return (EINVAL); 2630 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2631 clear_quickret(); 2632 return (0); 2633 } 2634 2635 static void 2636 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2637 { 2638 struct env87 *penv_87 = &sv_87->sv_env; 2639 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2640 int i; 2641 2642 /* FPU control/status */ 2643 penv_87->en_cw = penv_xmm->en_cw; 2644 penv_87->en_sw = penv_xmm->en_sw; 2645 penv_87->en_tw = penv_xmm->en_tw; 2646 penv_87->en_fip = penv_xmm->en_fip; 2647 penv_87->en_fcs = penv_xmm->en_fcs; 2648 penv_87->en_opcode = penv_xmm->en_opcode; 2649 penv_87->en_foo = penv_xmm->en_foo; 2650 penv_87->en_fos = penv_xmm->en_fos; 2651 2652 /* FPU registers */ 2653 for (i = 0; i < 8; ++i) 2654 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2655 } 2656 2657 static void 2658 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2659 { 2660 struct env87 *penv_87 = &sv_87->sv_env; 2661 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2662 int i; 2663 2664 /* FPU control/status */ 2665 penv_xmm->en_cw = penv_87->en_cw; 2666 penv_xmm->en_sw = penv_87->en_sw; 2667 penv_xmm->en_tw = penv_87->en_tw; 2668 penv_xmm->en_fip = penv_87->en_fip; 2669 penv_xmm->en_fcs = penv_87->en_fcs; 2670 penv_xmm->en_opcode = penv_87->en_opcode; 2671 penv_xmm->en_foo = penv_87->en_foo; 2672 penv_xmm->en_fos = penv_87->en_fos; 2673 2674 /* FPU registers */ 2675 for (i = 0; i < 8; ++i) 2676 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2677 } 2678 2679 int 2680 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2681 { 2682 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2683 return EINVAL; 2684 if (cpu_fxsr) { 2685 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2686 (struct save87 *)fpregs); 2687 return (0); 2688 } 2689 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2690 return (0); 2691 } 2692 2693 int 2694 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2695 { 2696 if (cpu_fxsr) { 2697 set_fpregs_xmm((struct save87 *)fpregs, 2698 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2699 return (0); 2700 } 2701 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2702 return (0); 2703 } 2704 2705 int 2706 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2707 { 2708 struct pcb *pcb; 2709 2710 if (lp == NULL) { 2711 dbregs->dr[0] = rdr0(); 2712 dbregs->dr[1] = rdr1(); 2713 dbregs->dr[2] = rdr2(); 2714 dbregs->dr[3] = rdr3(); 2715 dbregs->dr[4] = rdr4(); 2716 dbregs->dr[5] = rdr5(); 2717 dbregs->dr[6] = rdr6(); 2718 dbregs->dr[7] = rdr7(); 2719 return (0); 2720 } 2721 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2722 return EINVAL; 2723 dbregs->dr[0] = pcb->pcb_dr0; 2724 dbregs->dr[1] = pcb->pcb_dr1; 2725 dbregs->dr[2] = pcb->pcb_dr2; 2726 dbregs->dr[3] = pcb->pcb_dr3; 2727 dbregs->dr[4] = 0; 2728 dbregs->dr[5] = 0; 2729 dbregs->dr[6] = pcb->pcb_dr6; 2730 dbregs->dr[7] = pcb->pcb_dr7; 2731 return (0); 2732 } 2733 2734 int 2735 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2736 { 2737 if (lp == NULL) { 2738 load_dr0(dbregs->dr[0]); 2739 load_dr1(dbregs->dr[1]); 2740 load_dr2(dbregs->dr[2]); 2741 load_dr3(dbregs->dr[3]); 2742 load_dr4(dbregs->dr[4]); 2743 load_dr5(dbregs->dr[5]); 2744 load_dr6(dbregs->dr[6]); 2745 load_dr7(dbregs->dr[7]); 2746 } else { 2747 struct pcb *pcb; 2748 struct ucred *ucred; 2749 int i; 2750 uint64_t mask1, mask2; 2751 2752 /* 2753 * Don't let an illegal value for dr7 get set. Specifically, 2754 * check for undefined settings. Setting these bit patterns 2755 * result in undefined behaviour and can lead to an unexpected 2756 * TRCTRAP. 2757 */ 2758 /* JG this loop looks unreadable */ 2759 /* Check 4 2-bit fields for invalid patterns. 2760 * These fields are R/Wi, for i = 0..3 2761 */ 2762 /* Is 10 in LENi allowed when running in compatibility mode? */ 2763 /* Pattern 10 in R/Wi might be used to indicate 2764 * breakpoint on I/O. Further analysis should be 2765 * carried to decide if it is safe and useful to 2766 * provide access to that capability 2767 */ 2768 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2769 i++, mask1 <<= 4, mask2 <<= 4) 2770 if ((dbregs->dr[7] & mask1) == mask2) 2771 return (EINVAL); 2772 2773 pcb = lp->lwp_thread->td_pcb; 2774 ucred = lp->lwp_proc->p_ucred; 2775 2776 /* 2777 * Don't let a process set a breakpoint that is not within the 2778 * process's address space. If a process could do this, it 2779 * could halt the system by setting a breakpoint in the kernel 2780 * (if ddb was enabled). Thus, we need to check to make sure 2781 * that no breakpoints are being enabled for addresses outside 2782 * process's address space, unless, perhaps, we were called by 2783 * uid 0. 2784 * 2785 * XXX - what about when the watched area of the user's 2786 * address space is written into from within the kernel 2787 * ... wouldn't that still cause a breakpoint to be generated 2788 * from within kernel mode? 2789 */ 2790 2791 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2792 if (dbregs->dr[7] & 0x3) { 2793 /* dr0 is enabled */ 2794 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2795 return (EINVAL); 2796 } 2797 2798 if (dbregs->dr[7] & (0x3<<2)) { 2799 /* dr1 is enabled */ 2800 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2801 return (EINVAL); 2802 } 2803 2804 if (dbregs->dr[7] & (0x3<<4)) { 2805 /* dr2 is enabled */ 2806 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2807 return (EINVAL); 2808 } 2809 2810 if (dbregs->dr[7] & (0x3<<6)) { 2811 /* dr3 is enabled */ 2812 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2813 return (EINVAL); 2814 } 2815 } 2816 2817 pcb->pcb_dr0 = dbregs->dr[0]; 2818 pcb->pcb_dr1 = dbregs->dr[1]; 2819 pcb->pcb_dr2 = dbregs->dr[2]; 2820 pcb->pcb_dr3 = dbregs->dr[3]; 2821 pcb->pcb_dr6 = dbregs->dr[6]; 2822 pcb->pcb_dr7 = dbregs->dr[7]; 2823 2824 pcb->pcb_flags |= PCB_DBREGS; 2825 } 2826 2827 return (0); 2828 } 2829 2830 /* 2831 * Return > 0 if a hardware breakpoint has been hit, and the 2832 * breakpoint was in user space. Return 0, otherwise. 2833 */ 2834 int 2835 user_dbreg_trap(void) 2836 { 2837 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2838 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2839 int nbp; /* number of breakpoints that triggered */ 2840 caddr_t addr[4]; /* breakpoint addresses */ 2841 int i; 2842 2843 dr7 = rdr7(); 2844 if ((dr7 & 0xff) == 0) { 2845 /* 2846 * all GE and LE bits in the dr7 register are zero, 2847 * thus the trap couldn't have been caused by the 2848 * hardware debug registers 2849 */ 2850 return 0; 2851 } 2852 2853 nbp = 0; 2854 dr6 = rdr6(); 2855 bp = dr6 & 0xf; 2856 2857 if (bp == 0) { 2858 /* 2859 * None of the breakpoint bits are set meaning this 2860 * trap was not caused by any of the debug registers 2861 */ 2862 return 0; 2863 } 2864 2865 /* 2866 * at least one of the breakpoints were hit, check to see 2867 * which ones and if any of them are user space addresses 2868 */ 2869 2870 if (bp & 0x01) { 2871 addr[nbp++] = (caddr_t)rdr0(); 2872 } 2873 if (bp & 0x02) { 2874 addr[nbp++] = (caddr_t)rdr1(); 2875 } 2876 if (bp & 0x04) { 2877 addr[nbp++] = (caddr_t)rdr2(); 2878 } 2879 if (bp & 0x08) { 2880 addr[nbp++] = (caddr_t)rdr3(); 2881 } 2882 2883 for (i=0; i<nbp; i++) { 2884 if (addr[i] < 2885 (caddr_t)VM_MAX_USER_ADDRESS) { 2886 /* 2887 * addr[i] is in user space 2888 */ 2889 return nbp; 2890 } 2891 } 2892 2893 /* 2894 * None of the breakpoints are in user space. 2895 */ 2896 return 0; 2897 } 2898 2899 2900 #ifndef DDB 2901 void 2902 Debugger(const char *msg) 2903 { 2904 kprintf("Debugger(\"%s\") called.\n", msg); 2905 } 2906 #endif /* no DDB */ 2907 2908 #ifdef DDB 2909 2910 /* 2911 * Provide inb() and outb() as functions. They are normally only 2912 * available as macros calling inlined functions, thus cannot be 2913 * called inside DDB. 2914 * 2915 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2916 */ 2917 2918 #undef inb 2919 #undef outb 2920 2921 /* silence compiler warnings */ 2922 u_char inb(u_int); 2923 void outb(u_int, u_char); 2924 2925 u_char 2926 inb(u_int port) 2927 { 2928 u_char data; 2929 /* 2930 * We use %%dx and not %1 here because i/o is done at %dx and not at 2931 * %edx, while gcc generates inferior code (movw instead of movl) 2932 * if we tell it to load (u_short) port. 2933 */ 2934 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2935 return (data); 2936 } 2937 2938 void 2939 outb(u_int port, u_char data) 2940 { 2941 u_char al; 2942 /* 2943 * Use an unnecessary assignment to help gcc's register allocator. 2944 * This make a large difference for gcc-1.40 and a tiny difference 2945 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2946 * best results. gcc-2.6.0 can't handle this. 2947 */ 2948 al = data; 2949 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2950 } 2951 2952 #endif /* DDB */ 2953 2954 2955 2956 /* 2957 * initialize all the SMP locks 2958 */ 2959 2960 /* critical region when masking or unmasking interupts */ 2961 struct spinlock_deprecated imen_spinlock; 2962 2963 /* lock region used by kernel profiling */ 2964 struct spinlock_deprecated mcount_spinlock; 2965 2966 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2967 struct spinlock_deprecated com_spinlock; 2968 2969 /* lock regions around the clock hardware */ 2970 struct spinlock_deprecated clock_spinlock; 2971 2972 static void 2973 init_locks(void) 2974 { 2975 /* 2976 * Get the initial mplock with a count of 1 for the BSP. 2977 * This uses a LOGICAL cpu ID, ie BSP == 0. 2978 */ 2979 cpu_get_initial_mplock(); 2980 /* DEPRECATED */ 2981 spin_init_deprecated(&mcount_spinlock); 2982 spin_init_deprecated(&imen_spinlock); 2983 spin_init_deprecated(&com_spinlock); 2984 spin_init_deprecated(&clock_spinlock); 2985 2986 /* our token pool needs to work early */ 2987 lwkt_token_pool_init(); 2988 } 2989 2990 boolean_t 2991 cpu_mwait_hint_valid(uint32_t hint) 2992 { 2993 int cx_idx, sub; 2994 2995 cx_idx = MWAIT_EAX_TO_CX(hint); 2996 if (cx_idx >= CPU_MWAIT_CX_MAX) 2997 return FALSE; 2998 2999 sub = MWAIT_EAX_TO_CX_SUB(hint); 3000 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3001 return FALSE; 3002 3003 return TRUE; 3004 } 3005 3006 void 3007 cpu_mwait_cx_no_bmsts(void) 3008 { 3009 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3010 } 3011 3012 void 3013 cpu_mwait_cx_no_bmarb(void) 3014 { 3015 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3016 } 3017 3018 static int 3019 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3020 { 3021 int old_cx_idx, sub = 0; 3022 3023 if (hint >= 0) { 3024 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3025 sub = MWAIT_EAX_TO_CX_SUB(hint); 3026 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3027 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3028 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3029 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3030 } else { 3031 old_cx_idx = CPU_MWAIT_CX_MAX; 3032 } 3033 3034 if (!CPU_MWAIT_HAS_CX) 3035 strlcpy(name, "NONE", namelen); 3036 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3037 strlcpy(name, "AUTO", namelen); 3038 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3039 strlcpy(name, "AUTODEEP", namelen); 3040 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3041 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3042 strlcpy(name, "INVALID", namelen); 3043 else 3044 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3045 3046 return old_cx_idx; 3047 } 3048 3049 static int 3050 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3051 { 3052 int cx_idx, sub, hint; 3053 char *ptr, *start; 3054 3055 if (allow_auto && strcmp(name, "AUTO") == 0) { 3056 hint = CPU_MWAIT_HINT_AUTO; 3057 cx_idx = CPU_MWAIT_C2; 3058 goto done; 3059 } 3060 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3061 hint = CPU_MWAIT_HINT_AUTODEEP; 3062 cx_idx = CPU_MWAIT_C3; 3063 goto done; 3064 } 3065 3066 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3067 return -1; 3068 start = &name[1]; 3069 ptr = NULL; 3070 3071 cx_idx = strtol(start, &ptr, 10); 3072 if (ptr == start || *ptr != '/') 3073 return -1; 3074 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3075 return -1; 3076 3077 start = ptr + 1; 3078 ptr = NULL; 3079 3080 sub = strtol(start, &ptr, 10); 3081 if (*ptr != '\0') 3082 return -1; 3083 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3084 return -1; 3085 3086 hint = MWAIT_EAX_HINT(cx_idx, sub); 3087 done: 3088 *hint0 = hint; 3089 return cx_idx; 3090 } 3091 3092 static int 3093 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3094 { 3095 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3096 return EOPNOTSUPP; 3097 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3098 int error; 3099 3100 error = cputimer_intr_powersave_addreq(); 3101 if (error) 3102 return error; 3103 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3104 cputimer_intr_powersave_remreq(); 3105 } 3106 return 0; 3107 } 3108 3109 static int 3110 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3111 boolean_t allow_auto) 3112 { 3113 int error, cx_idx, old_cx_idx, hint; 3114 char name[CPU_MWAIT_CX_NAMELEN]; 3115 3116 hint = *hint0; 3117 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3118 allow_auto); 3119 3120 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3121 if (error != 0 || req->newptr == NULL) 3122 return error; 3123 3124 if (!CPU_MWAIT_HAS_CX) 3125 return EOPNOTSUPP; 3126 3127 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3128 if (cx_idx < 0) 3129 return EINVAL; 3130 3131 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3132 if (error) 3133 return error; 3134 3135 *hint0 = hint; 3136 return 0; 3137 } 3138 3139 static int 3140 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3141 { 3142 int error, cx_idx, old_cx_idx, hint; 3143 char name[CPU_MWAIT_CX_NAMELEN]; 3144 3145 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3146 3147 hint = stat->hint; 3148 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3149 3150 strlcpy(name, cx_name, sizeof(name)); 3151 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3152 if (cx_idx < 0) 3153 return EINVAL; 3154 3155 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3156 if (error) 3157 return error; 3158 3159 stat->hint = hint; 3160 return 0; 3161 } 3162 3163 static int 3164 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3165 { 3166 int hint = cpu_mwait_halt_global; 3167 int error, cx_idx, cpu; 3168 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3169 3170 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3171 3172 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3173 if (error != 0 || req->newptr == NULL) 3174 return error; 3175 3176 if (!CPU_MWAIT_HAS_CX) 3177 return EOPNOTSUPP; 3178 3179 /* Save name for later per-cpu CX configuration */ 3180 strlcpy(cx_name, name, sizeof(cx_name)); 3181 3182 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3183 if (cx_idx < 0) 3184 return EINVAL; 3185 3186 /* Change per-cpu CX configuration */ 3187 for (cpu = 0; cpu < ncpus; ++cpu) { 3188 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3189 if (error) 3190 return error; 3191 } 3192 3193 cpu_mwait_halt_global = hint; 3194 return 0; 3195 } 3196 3197 static int 3198 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3199 { 3200 struct cpu_idle_stat *stat = arg1; 3201 int error; 3202 3203 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3204 &stat->hint, TRUE); 3205 return error; 3206 } 3207 3208 static int 3209 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3210 { 3211 int error; 3212 3213 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3214 &cpu_mwait_spin, FALSE); 3215 return error; 3216 } 3217 3218 /* 3219 * This manual debugging code is called unconditionally from Xtimer 3220 * (the per-cpu timer interrupt) whether the current thread is in a 3221 * critical section or not) and can be useful in tracking down lockups. 3222 * 3223 * NOTE: MANUAL DEBUG CODE 3224 */ 3225 #if 0 3226 static int saveticks[SMP_MAXCPU]; 3227 static int savecounts[SMP_MAXCPU]; 3228 #endif 3229 3230 void 3231 pcpu_timer_always(struct intrframe *frame) 3232 { 3233 #if 0 3234 globaldata_t gd = mycpu; 3235 int cpu = gd->gd_cpuid; 3236 char buf[64]; 3237 short *gptr; 3238 int i; 3239 3240 if (cpu <= 20) { 3241 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3242 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3243 ++gptr; 3244 3245 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3246 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3247 gd->gd_infomsg); 3248 for (i = 0; buf[i]; ++i) { 3249 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3250 } 3251 } 3252 #if 0 3253 if (saveticks[gd->gd_cpuid] != ticks) { 3254 saveticks[gd->gd_cpuid] = ticks; 3255 savecounts[gd->gd_cpuid] = 0; 3256 } 3257 ++savecounts[gd->gd_cpuid]; 3258 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3259 panic("cpud %d panicing on ticks failure", 3260 gd->gd_cpuid); 3261 } 3262 for (i = 0; i < ncpus; ++i) { 3263 int delta; 3264 if (saveticks[i] && panicstr == NULL) { 3265 delta = saveticks[i] - ticks; 3266 if (delta < -10 || delta > 10) { 3267 panic("cpu %d panicing on cpu %d watchdog", 3268 gd->gd_cpuid, i); 3269 } 3270 } 3271 } 3272 #endif 3273 #endif 3274 } 3275