1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_compat.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_directio.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_msgbuf.h" 52 #include "opt_swap.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysproto.h> 57 #include <sys/signalvar.h> 58 #include <sys/kernel.h> 59 #include <sys/linker.h> 60 #include <sys/malloc.h> 61 #include <sys/proc.h> 62 #include <sys/priv.h> 63 #include <sys/buf.h> 64 #include <sys/reboot.h> 65 #include <sys/mbuf.h> 66 #include <sys/msgbuf.h> 67 #include <sys/sysent.h> 68 #include <sys/sysctl.h> 69 #include <sys/vmmeter.h> 70 #include <sys/bus.h> 71 #include <sys/usched.h> 72 #include <sys/reg.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <sys/lock.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_page.h> 80 #include <vm/vm_map.h> 81 #include <vm/vm_pager.h> 82 #include <vm/vm_extern.h> 83 84 #include <sys/thread2.h> 85 #include <sys/mplock2.h> 86 #include <sys/mutex2.h> 87 88 #include <sys/user.h> 89 #include <sys/exec.h> 90 #include <sys/cons.h> 91 92 #include <ddb/ddb.h> 93 94 #include <machine/cpu.h> 95 #include <machine/clock.h> 96 #include <machine/specialreg.h> 97 #if JG 98 #include <machine/bootinfo.h> 99 #endif 100 #include <machine/md_var.h> 101 #include <machine/metadata.h> 102 #include <machine/pc/bios.h> 103 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 104 #include <machine/globaldata.h> /* CPU_prvspace */ 105 #include <machine/smp.h> 106 #ifdef PERFMON 107 #include <machine/perfmon.h> 108 #endif 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 112 #ifdef OLD_BUS_ARCH 113 #include <bus/isa/isa_device.h> 114 #endif 115 #include <machine_base/isa/isa_intr.h> 116 #include <bus/isa/rtc.h> 117 #include <sys/random.h> 118 #include <sys/ptrace.h> 119 #include <machine/sigframe.h> 120 121 #include <sys/machintr.h> 122 #include <machine_base/icu/icu_abi.h> 123 #include <machine_base/icu/elcr_var.h> 124 #include <machine_base/apic/lapic.h> 125 #include <machine_base/apic/ioapic.h> 126 #include <machine_base/apic/ioapic_abi.h> 127 #include <machine/mptable.h> 128 129 #define PHYSMAP_ENTRIES 10 130 131 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 132 133 extern void printcpuinfo(void); /* XXX header file */ 134 extern void identify_cpu(void); 135 #if JG 136 extern void finishidentcpu(void); 137 #endif 138 extern void panicifcpuunsupported(void); 139 140 static void cpu_startup(void *); 141 static void pic_finish(void *); 142 static void cpu_finish(void *); 143 144 #ifndef CPU_DISABLE_SSE 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 #endif /* CPU_DISABLE_SSE */ 148 #ifdef DIRECTIO 149 extern void ffs_rawread_setup(void); 150 #endif /* DIRECTIO */ 151 static void init_locks(void); 152 153 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL) 154 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL) 155 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL) 156 157 #ifdef DDB 158 extern vm_offset_t ksym_start, ksym_end; 159 #endif 160 161 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */ 162 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 int cpu_mwait_halt; 167 168 #if defined(SWTCH_OPTIM_STATS) 169 extern int swtch_optim_stats; 170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 171 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 173 CTLFLAG_RD, &tlb_flush_count, 0, ""); 174 #endif 175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 176 CTLFLAG_RW, &cpu_mwait_halt, 0, ""); 177 178 long physmem = 0; 179 180 u_long ebda_addr = 0; 181 182 int imcr_present = 0; 183 184 int naps = 0; /* # of Applications processors */ 185 186 u_int base_memory; 187 struct mtx dt_lock; /* lock for GDT and LDT */ 188 189 static int 190 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 191 { 192 u_long pmem = ctob(physmem); 193 194 int error = sysctl_handle_long(oidp, &pmem, 0, req); 195 return (error); 196 } 197 198 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 199 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 200 201 static int 202 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 203 { 204 int error = sysctl_handle_int(oidp, 0, 205 ctob(physmem - vmstats.v_wire_count), req); 206 return (error); 207 } 208 209 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 210 0, 0, sysctl_hw_usermem, "IU", ""); 211 212 static int 213 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 214 { 215 int error = sysctl_handle_int(oidp, 0, 216 x86_64_btop(avail_end - avail_start), req); 217 return (error); 218 } 219 220 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 221 0, 0, sysctl_hw_availpages, "I", ""); 222 223 vm_paddr_t Maxmem; 224 vm_paddr_t Realmem; 225 226 /* 227 * The number of PHYSMAP entries must be one less than the number of 228 * PHYSSEG entries because the PHYSMAP entry that spans the largest 229 * physical address that is accessible by ISA DMA is split into two 230 * PHYSSEG entries. 231 */ 232 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 233 234 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 235 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 236 237 /* must be 2 less so 0 0 can signal end of chunks */ 238 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2) 239 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2) 240 241 static vm_offset_t buffer_sva, buffer_eva; 242 vm_offset_t clean_sva, clean_eva; 243 static vm_offset_t pager_sva, pager_eva; 244 static struct trapframe proc0_tf; 245 246 static void 247 cpu_startup(void *dummy) 248 { 249 caddr_t v; 250 vm_size_t size = 0; 251 vm_offset_t firstaddr; 252 253 /* 254 * Good {morning,afternoon,evening,night}. 255 */ 256 kprintf("%s", version); 257 startrtclock(); 258 printcpuinfo(); 259 panicifcpuunsupported(); 260 #ifdef PERFMON 261 perfmon_init(); 262 #endif 263 kprintf("real memory = %ju (%ju MB)\n", 264 (intmax_t)Realmem, 265 (intmax_t)Realmem / 1024 / 1024); 266 /* 267 * Display any holes after the first chunk of extended memory. 268 */ 269 if (bootverbose) { 270 int indx; 271 272 kprintf("Physical memory chunk(s):\n"); 273 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 274 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx]; 275 276 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 277 (intmax_t)phys_avail[indx], 278 (intmax_t)phys_avail[indx + 1] - 1, 279 (intmax_t)size1, 280 (intmax_t)(size1 / PAGE_SIZE)); 281 } 282 } 283 284 /* 285 * Allocate space for system data structures. 286 * The first available kernel virtual address is in "v". 287 * As pages of kernel virtual memory are allocated, "v" is incremented. 288 * As pages of memory are allocated and cleared, 289 * "firstaddr" is incremented. 290 * An index into the kernel page table corresponding to the 291 * virtual memory address maintained in "v" is kept in "mapaddr". 292 */ 293 294 /* 295 * Make two passes. The first pass calculates how much memory is 296 * needed and allocates it. The second pass assigns virtual 297 * addresses to the various data structures. 298 */ 299 firstaddr = 0; 300 again: 301 v = (caddr_t)firstaddr; 302 303 #define valloc(name, type, num) \ 304 (name) = (type *)v; v = (caddr_t)((name)+(num)) 305 #define valloclim(name, type, num, lim) \ 306 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 307 308 /* 309 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE. 310 * For the first 64MB of ram nominally allocate sufficient buffers to 311 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 312 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 313 * the buffer cache we limit the eventual kva reservation to 314 * maxbcache bytes. 315 * 316 * factor represents the 1/4 x ram conversion. 317 */ 318 if (nbuf == 0) { 319 long factor = 4 * BKVASIZE / 1024; 320 long kbytes = physmem * (PAGE_SIZE / 1024); 321 322 nbuf = 50; 323 if (kbytes > 4096) 324 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 325 if (kbytes > 65536) 326 nbuf += (kbytes - 65536) * 2 / (factor * 5); 327 if (maxbcache && nbuf > maxbcache / BKVASIZE) 328 nbuf = maxbcache / BKVASIZE; 329 } 330 331 /* 332 * Do not allow the buffer_map to be more then 1/2 the size of the 333 * kernel_map. 334 */ 335 if (nbuf > (virtual_end - virtual_start + 336 virtual2_end - virtual2_start) / (BKVASIZE * 2)) { 337 nbuf = (virtual_end - virtual_start + 338 virtual2_end - virtual2_start) / (BKVASIZE * 2); 339 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 340 } 341 342 /* 343 * Do not allow the buffer_map to use more than 50% of available 344 * physical-equivalent memory. Since the VM pages which back 345 * individual buffers are typically wired, having too many bufs 346 * can prevent the system from paging properly. 347 */ 348 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) { 349 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2); 350 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 351 } 352 353 /* 354 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 355 * the valloc space which is just the virtual_end - virtual_start 356 * section. We use valloc() to allocate the buf header array. 357 */ 358 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 359 nbuf = (virtual_end - virtual_start) / 360 sizeof(struct buf) / 2; 361 kprintf("Warning: nbufs capped at %ld due to valloc " 362 "considerations", nbuf); 363 } 364 365 nswbuf = lmax(lmin(nbuf / 4, 256), 16); 366 #ifdef NSWBUF_MIN 367 if (nswbuf < NSWBUF_MIN) 368 nswbuf = NSWBUF_MIN; 369 #endif 370 #ifdef DIRECTIO 371 ffs_rawread_setup(); 372 #endif 373 374 valloc(swbuf, struct buf, nswbuf); 375 valloc(buf, struct buf, nbuf); 376 377 /* 378 * End of first pass, size has been calculated so allocate memory 379 */ 380 if (firstaddr == 0) { 381 size = (vm_size_t)(v - firstaddr); 382 firstaddr = kmem_alloc(&kernel_map, round_page(size)); 383 if (firstaddr == 0) 384 panic("startup: no room for tables"); 385 goto again; 386 } 387 388 /* 389 * End of second pass, addresses have been assigned 390 * 391 * nbuf is an int, make sure we don't overflow the field. 392 * 393 * On 64-bit systems fragmentation can create serious performance 394 * loss due to the large number of buffers the system is likely 395 * going to maintain. The easiest solution is to create a KVA 396 * section that is twice as big as the nominal buffer cache size, 397 * hence the multiplication by 2 below. 398 */ 399 if ((vm_size_t)(v - firstaddr) != size) 400 panic("startup: table size inconsistency"); 401 402 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 403 ((vm_offset_t)nbuf * BKVASIZE * 2) + 404 (nswbuf * MAXPHYS) + pager_map_size); 405 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 406 ((vm_offset_t)nbuf * BKVASIZE * 2)); 407 buffer_map.system_map = 1; 408 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 409 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size); 410 pager_map.system_map = 1; 411 412 #if defined(USERCONFIG) 413 userconfig(); 414 cninit(); /* the preferred console may have changed */ 415 #endif 416 417 kprintf("avail memory = %ju (%ju MB)\n", 418 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 419 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 420 1024 / 1024); 421 422 /* 423 * Set up buffers, so they can be used to read disk labels. 424 */ 425 bufinit(); 426 vm_pager_bufferinit(); 427 } 428 429 static void 430 cpu_finish(void *dummy __unused) 431 { 432 cpu_setregs(); 433 } 434 435 static void 436 pic_finish(void *dummy __unused) 437 { 438 /* Log ELCR information */ 439 elcr_dump(); 440 441 /* Log MPTABLE information */ 442 mptable_pci_int_dump(); 443 444 /* Finalize PCI */ 445 MachIntrABI.finalize(); 446 } 447 448 /* 449 * Send an interrupt to process. 450 * 451 * Stack is set up to allow sigcode stored 452 * at top to call routine, followed by kcall 453 * to sigreturn routine below. After sigreturn 454 * resets the signal mask, the stack, and the 455 * frame pointer, it returns to the user 456 * specified pc, psl. 457 */ 458 void 459 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 460 { 461 struct lwp *lp = curthread->td_lwp; 462 struct proc *p = lp->lwp_proc; 463 struct trapframe *regs; 464 struct sigacts *psp = p->p_sigacts; 465 struct sigframe sf, *sfp; 466 int oonstack; 467 char *sp; 468 469 regs = lp->lwp_md.md_regs; 470 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 471 472 /* Save user context */ 473 bzero(&sf, sizeof(struct sigframe)); 474 sf.sf_uc.uc_sigmask = *mask; 475 sf.sf_uc.uc_stack = lp->lwp_sigstk; 476 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 477 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 478 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 479 480 /* Make the size of the saved context visible to userland */ 481 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 482 483 /* Allocate and validate space for the signal handler context. */ 484 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 485 SIGISMEMBER(psp->ps_sigonstack, sig)) { 486 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 487 sizeof(struct sigframe)); 488 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 489 } else { 490 /* We take red zone into account */ 491 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 492 } 493 494 /* 495 * XXX AVX needs 64-byte alignment but sigframe has other fields and 496 * the embedded ucontext is not at the front, so aligning this won't 497 * help us. Fortunately we bcopy in/out of the sigframe, so the 498 * kernel is ok. 499 * 500 * The problem though is if userland winds up trying to use the 501 * context directly. 502 */ 503 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 504 505 /* Translate the signal is appropriate */ 506 if (p->p_sysent->sv_sigtbl) { 507 if (sig <= p->p_sysent->sv_sigsize) 508 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 509 } 510 511 /* 512 * Build the argument list for the signal handler. 513 * 514 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 515 */ 516 regs->tf_rdi = sig; /* argument 1 */ 517 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 518 519 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 520 /* 521 * Signal handler installed with SA_SIGINFO. 522 * 523 * action(signo, siginfo, ucontext) 524 */ 525 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 526 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 527 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 528 529 /* fill siginfo structure */ 530 sf.sf_si.si_signo = sig; 531 sf.sf_si.si_code = code; 532 sf.sf_si.si_addr = (void *)regs->tf_addr; 533 } else { 534 /* 535 * Old FreeBSD-style arguments. 536 * 537 * handler (signo, code, [uc], addr) 538 */ 539 regs->tf_rsi = (register_t)code; /* argument 2 */ 540 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 541 sf.sf_ahu.sf_handler = catcher; 542 } 543 544 /* 545 * If we're a vm86 process, we want to save the segment registers. 546 * We also change eflags to be our emulated eflags, not the actual 547 * eflags. 548 */ 549 #if JG 550 if (regs->tf_eflags & PSL_VM) { 551 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 552 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 553 554 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 555 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 556 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 557 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 558 559 if (vm86->vm86_has_vme == 0) 560 sf.sf_uc.uc_mcontext.mc_eflags = 561 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 562 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 563 564 /* 565 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 566 * syscalls made by the signal handler. This just avoids 567 * wasting time for our lazy fixup of such faults. PSL_NT 568 * does nothing in vm86 mode, but vm86 programs can set it 569 * almost legitimately in probes for old cpu types. 570 */ 571 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 572 } 573 #endif 574 575 /* 576 * Save the FPU state and reinit the FP unit 577 */ 578 npxpush(&sf.sf_uc.uc_mcontext); 579 580 /* 581 * Copy the sigframe out to the user's stack. 582 */ 583 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 584 /* 585 * Something is wrong with the stack pointer. 586 * ...Kill the process. 587 */ 588 sigexit(lp, SIGILL); 589 } 590 591 regs->tf_rsp = (register_t)sfp; 592 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 593 594 /* 595 * i386 abi specifies that the direction flag must be cleared 596 * on function entry 597 */ 598 regs->tf_rflags &= ~(PSL_T|PSL_D); 599 600 /* 601 * 64 bit mode has a code and stack selector but 602 * no data or extra selector. %fs and %gs are not 603 * stored in-context. 604 */ 605 regs->tf_cs = _ucodesel; 606 regs->tf_ss = _udatasel; 607 clear_quickret(); 608 } 609 610 /* 611 * Sanitize the trapframe for a virtual kernel passing control to a custom 612 * VM context. Remove any items that would otherwise create a privilage 613 * issue. 614 * 615 * XXX at the moment we allow userland to set the resume flag. Is this a 616 * bad idea? 617 */ 618 int 619 cpu_sanitize_frame(struct trapframe *frame) 620 { 621 frame->tf_cs = _ucodesel; 622 frame->tf_ss = _udatasel; 623 /* XXX VM (8086) mode not supported? */ 624 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 625 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 626 627 return(0); 628 } 629 630 /* 631 * Sanitize the tls so loading the descriptor does not blow up 632 * on us. For x86_64 we don't have to do anything. 633 */ 634 int 635 cpu_sanitize_tls(struct savetls *tls) 636 { 637 return(0); 638 } 639 640 /* 641 * sigreturn(ucontext_t *sigcntxp) 642 * 643 * System call to cleanup state after a signal 644 * has been taken. Reset signal mask and 645 * stack state from context left by sendsig (above). 646 * Return to previous pc and psl as specified by 647 * context left by sendsig. Check carefully to 648 * make sure that the user has not modified the 649 * state to gain improper privileges. 650 * 651 * MPSAFE 652 */ 653 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 654 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 655 656 int 657 sys_sigreturn(struct sigreturn_args *uap) 658 { 659 struct lwp *lp = curthread->td_lwp; 660 struct trapframe *regs; 661 ucontext_t uc; 662 ucontext_t *ucp; 663 register_t rflags; 664 int cs; 665 int error; 666 667 /* 668 * We have to copy the information into kernel space so userland 669 * can't modify it while we are sniffing it. 670 */ 671 regs = lp->lwp_md.md_regs; 672 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 673 if (error) 674 return (error); 675 ucp = &uc; 676 rflags = ucp->uc_mcontext.mc_rflags; 677 678 /* VM (8086) mode not supported */ 679 rflags &= ~PSL_VM_UNSUPP; 680 681 #if JG 682 if (eflags & PSL_VM) { 683 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 684 struct vm86_kernel *vm86; 685 686 /* 687 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 688 * set up the vm86 area, and we can't enter vm86 mode. 689 */ 690 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 691 return (EINVAL); 692 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 693 if (vm86->vm86_inited == 0) 694 return (EINVAL); 695 696 /* go back to user mode if both flags are set */ 697 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 698 trapsignal(lp, SIGBUS, 0); 699 700 if (vm86->vm86_has_vme) { 701 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 702 (eflags & VME_USERCHANGE) | PSL_VM; 703 } else { 704 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 705 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 706 (eflags & VM_USERCHANGE) | PSL_VM; 707 } 708 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 709 tf->tf_eflags = eflags; 710 tf->tf_vm86_ds = tf->tf_ds; 711 tf->tf_vm86_es = tf->tf_es; 712 tf->tf_vm86_fs = tf->tf_fs; 713 tf->tf_vm86_gs = tf->tf_gs; 714 tf->tf_ds = _udatasel; 715 tf->tf_es = _udatasel; 716 tf->tf_fs = _udatasel; 717 tf->tf_gs = _udatasel; 718 } else 719 #endif 720 { 721 /* 722 * Don't allow users to change privileged or reserved flags. 723 */ 724 /* 725 * XXX do allow users to change the privileged flag PSL_RF. 726 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 727 * should sometimes set it there too. tf_eflags is kept in 728 * the signal context during signal handling and there is no 729 * other place to remember it, so the PSL_RF bit may be 730 * corrupted by the signal handler without us knowing. 731 * Corruption of the PSL_RF bit at worst causes one more or 732 * one less debugger trap, so allowing it is fairly harmless. 733 */ 734 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 735 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 736 return(EINVAL); 737 } 738 739 /* 740 * Don't allow users to load a valid privileged %cs. Let the 741 * hardware check for invalid selectors, excess privilege in 742 * other selectors, invalid %eip's and invalid %esp's. 743 */ 744 cs = ucp->uc_mcontext.mc_cs; 745 if (!CS_SECURE(cs)) { 746 kprintf("sigreturn: cs = 0x%x\n", cs); 747 trapsignal(lp, SIGBUS, T_PROTFLT); 748 return(EINVAL); 749 } 750 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 751 } 752 753 /* 754 * Restore the FPU state from the frame 755 */ 756 crit_enter(); 757 npxpop(&ucp->uc_mcontext); 758 759 if (ucp->uc_mcontext.mc_onstack & 1) 760 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 761 else 762 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 763 764 lp->lwp_sigmask = ucp->uc_sigmask; 765 SIG_CANTMASK(lp->lwp_sigmask); 766 clear_quickret(); 767 crit_exit(); 768 return(EJUSTRETURN); 769 } 770 771 /* 772 * Machine dependent boot() routine 773 * 774 * I haven't seen anything to put here yet 775 * Possibly some stuff might be grafted back here from boot() 776 */ 777 void 778 cpu_boot(int howto) 779 { 780 } 781 782 /* 783 * Shutdown the CPU as much as possible 784 */ 785 void 786 cpu_halt(void) 787 { 788 for (;;) 789 __asm__ __volatile("hlt"); 790 } 791 792 /* 793 * cpu_idle() represents the idle LWKT. You cannot return from this function 794 * (unless you want to blow things up!). Instead we look for runnable threads 795 * and loop or halt as appropriate. Giant is not held on entry to the thread. 796 * 797 * The main loop is entered with a critical section held, we must release 798 * the critical section before doing anything else. lwkt_switch() will 799 * check for pending interrupts due to entering and exiting its own 800 * critical section. 801 * 802 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 803 * However, there are cases where the idlethread will be entered with 804 * the possibility that no IPI will occur and in such cases 805 * lwkt_switch() sets TDF_IDLE_NOHLT. 806 * 807 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to 808 * 1 to just use hlt and for debugging purposes. 809 * 810 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 811 * must occur before it starts using ACPI halt. 812 */ 813 static int cpu_idle_hlt = 2; 814 static int cpu_idle_hltcnt; 815 static int cpu_idle_spincnt; 816 static u_int cpu_idle_repeat = 750; 817 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 818 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 819 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW, 820 &cpu_idle_hltcnt, 0, "Idle loop entry halts"); 821 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW, 822 &cpu_idle_spincnt, 0, "Idle loop entry spins"); 823 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 824 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 825 826 static void 827 cpu_idle_default_hook(void) 828 { 829 /* 830 * We must guarentee that hlt is exactly the instruction 831 * following the sti. 832 */ 833 __asm __volatile("sti; hlt"); 834 } 835 836 /* Other subsystems (e.g., ACPI) can hook this later. */ 837 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 838 839 void 840 cpu_idle(void) 841 { 842 globaldata_t gd = mycpu; 843 struct thread *td __debugvar = gd->gd_curthread; 844 int reqflags; 845 int quick; 846 847 crit_exit(); 848 KKASSERT(td->td_critcount == 0); 849 for (;;) { 850 /* 851 * See if there are any LWKTs ready to go. 852 */ 853 lwkt_switch(); 854 855 /* 856 * When halting inside a cli we must check for reqflags 857 * races, particularly [re]schedule requests. Running 858 * splz() does the job. 859 * 860 * cpu_idle_hlt: 861 * 0 Never halt, just spin 862 * 863 * 1 Always use HLT (or MONITOR/MWAIT if avail). 864 * This typically eats more power than the 865 * ACPI halt. 866 * 867 * 2 Use HLT/MONITOR/MWAIT up to a point and then 868 * use the ACPI halt (default). This is a hybrid 869 * approach. See machdep.cpu_idle_repeat. 870 * 871 * 3 Always use the ACPI halt. This typically 872 * eats the least amount of power but the cpu 873 * will be slow waking up. Slows down e.g. 874 * compiles and other pipe/event oriented stuff. 875 * 876 * NOTE: Interrupts are enabled and we are not in a critical 877 * section. 878 * 879 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 880 * don't bother capping gd_idle_repeat, it is ok if 881 * it overflows. 882 */ 883 ++gd->gd_idle_repeat; 884 reqflags = gd->gd_reqflags; 885 quick = (cpu_idle_hlt == 1) || 886 (cpu_idle_hlt < 3 && 887 gd->gd_idle_repeat < cpu_idle_repeat); 888 889 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 890 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 891 splz(); /* XXX */ 892 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 893 cpu_mwait_halt); 894 ++cpu_idle_hltcnt; 895 } else if (cpu_idle_hlt) { 896 __asm __volatile("cli"); 897 splz(); 898 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 899 if (quick) 900 cpu_idle_default_hook(); 901 else 902 cpu_idle_hook(); 903 } 904 __asm __volatile("sti"); 905 ++cpu_idle_hltcnt; 906 } else { 907 splz(); 908 __asm __volatile("sti"); 909 ++cpu_idle_spincnt; 910 } 911 } 912 } 913 914 /* 915 * This routine is called if a spinlock has been held through the 916 * exponential backoff period and is seriously contested. On a real cpu 917 * we let it spin. 918 */ 919 void 920 cpu_spinlock_contested(void) 921 { 922 cpu_pause(); 923 } 924 925 /* 926 * Clear registers on exec 927 */ 928 void 929 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 930 { 931 struct thread *td = curthread; 932 struct lwp *lp = td->td_lwp; 933 struct pcb *pcb = td->td_pcb; 934 struct trapframe *regs = lp->lwp_md.md_regs; 935 936 /* was i386_user_cleanup() in NetBSD */ 937 user_ldt_free(pcb); 938 939 clear_quickret(); 940 bzero((char *)regs, sizeof(struct trapframe)); 941 regs->tf_rip = entry; 942 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 943 regs->tf_rdi = stack; /* argv */ 944 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 945 regs->tf_ss = _udatasel; 946 regs->tf_cs = _ucodesel; 947 regs->tf_rbx = ps_strings; 948 949 /* 950 * Reset the hardware debug registers if they were in use. 951 * They won't have any meaning for the newly exec'd process. 952 */ 953 if (pcb->pcb_flags & PCB_DBREGS) { 954 pcb->pcb_dr0 = 0; 955 pcb->pcb_dr1 = 0; 956 pcb->pcb_dr2 = 0; 957 pcb->pcb_dr3 = 0; 958 pcb->pcb_dr6 = 0; 959 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 960 if (pcb == td->td_pcb) { 961 /* 962 * Clear the debug registers on the running 963 * CPU, otherwise they will end up affecting 964 * the next process we switch to. 965 */ 966 reset_dbregs(); 967 } 968 pcb->pcb_flags &= ~PCB_DBREGS; 969 } 970 971 /* 972 * Initialize the math emulator (if any) for the current process. 973 * Actually, just clear the bit that says that the emulator has 974 * been initialized. Initialization is delayed until the process 975 * traps to the emulator (if it is done at all) mainly because 976 * emulators don't provide an entry point for initialization. 977 */ 978 pcb->pcb_flags &= ~FP_SOFTFP; 979 980 /* 981 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 982 * gd_npxthread. Otherwise a preemptive interrupt thread 983 * may panic in npxdna(). 984 */ 985 crit_enter(); 986 load_cr0(rcr0() | CR0_MP); 987 988 /* 989 * NOTE: The MSR values must be correct so we can return to 990 * userland. gd_user_fs/gs must be correct so the switch 991 * code knows what the current MSR values are. 992 */ 993 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 994 pcb->pcb_gsbase = 0; 995 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 996 mdcpu->gd_user_gs = 0; 997 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 998 wrmsr(MSR_KGSBASE, 0); 999 1000 /* Initialize the npx (if any) for the current process. */ 1001 npxinit(__INITIAL_FPUCW__); 1002 crit_exit(); 1003 1004 pcb->pcb_ds = _udatasel; 1005 pcb->pcb_es = _udatasel; 1006 pcb->pcb_fs = _udatasel; 1007 pcb->pcb_gs = _udatasel; 1008 } 1009 1010 void 1011 cpu_setregs(void) 1012 { 1013 register_t cr0; 1014 1015 cr0 = rcr0(); 1016 cr0 |= CR0_NE; /* Done by npxinit() */ 1017 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1018 cr0 |= CR0_WP | CR0_AM; 1019 load_cr0(cr0); 1020 load_gs(_udatasel); 1021 } 1022 1023 static int 1024 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1025 { 1026 int error; 1027 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1028 req); 1029 if (!error && req->newptr) 1030 resettodr(); 1031 return (error); 1032 } 1033 1034 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1035 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1036 1037 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1038 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1039 1040 #if JG 1041 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1042 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1043 #endif 1044 1045 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1046 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1047 1048 extern u_long bootdev; /* not a cdev_t - encoding is different */ 1049 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 1050 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)"); 1051 1052 /* 1053 * Initialize 386 and configure to run kernel 1054 */ 1055 1056 /* 1057 * Initialize segments & interrupt table 1058 */ 1059 1060 int _default_ldt; 1061 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1062 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1063 #if JG 1064 union descriptor ldt[NLDT]; /* local descriptor table */ 1065 #endif 1066 1067 /* table descriptors - used to load tables by cpu */ 1068 struct region_descriptor r_gdt; 1069 struct region_descriptor r_idt_arr[MAXCPU]; 1070 1071 /* JG proc0paddr is a virtual address */ 1072 void *proc0paddr; 1073 /* JG alignment? */ 1074 char proc0paddr_buff[LWKT_THREAD_STACK]; 1075 1076 1077 /* software prototypes -- in more palatable form */ 1078 struct soft_segment_descriptor gdt_segs[] = { 1079 /* GNULL_SEL 0 Null Descriptor */ 1080 { 0x0, /* segment base address */ 1081 0x0, /* length */ 1082 0, /* segment type */ 1083 0, /* segment descriptor priority level */ 1084 0, /* segment descriptor present */ 1085 0, /* long */ 1086 0, /* default 32 vs 16 bit size */ 1087 0 /* limit granularity (byte/page units)*/ }, 1088 /* GCODE_SEL 1 Code Descriptor for kernel */ 1089 { 0x0, /* segment base address */ 1090 0xfffff, /* length - all address space */ 1091 SDT_MEMERA, /* segment type */ 1092 SEL_KPL, /* segment descriptor priority level */ 1093 1, /* segment descriptor present */ 1094 1, /* long */ 1095 0, /* default 32 vs 16 bit size */ 1096 1 /* limit granularity (byte/page units)*/ }, 1097 /* GDATA_SEL 2 Data Descriptor for kernel */ 1098 { 0x0, /* segment base address */ 1099 0xfffff, /* length - all address space */ 1100 SDT_MEMRWA, /* segment type */ 1101 SEL_KPL, /* segment descriptor priority level */ 1102 1, /* segment descriptor present */ 1103 1, /* long */ 1104 0, /* default 32 vs 16 bit size */ 1105 1 /* limit granularity (byte/page units)*/ }, 1106 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1107 { 0x0, /* segment base address */ 1108 0xfffff, /* length - all address space */ 1109 SDT_MEMERA, /* segment type */ 1110 SEL_UPL, /* segment descriptor priority level */ 1111 1, /* segment descriptor present */ 1112 0, /* long */ 1113 1, /* default 32 vs 16 bit size */ 1114 1 /* limit granularity (byte/page units)*/ }, 1115 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1116 { 0x0, /* segment base address */ 1117 0xfffff, /* length - all address space */ 1118 SDT_MEMRWA, /* segment type */ 1119 SEL_UPL, /* segment descriptor priority level */ 1120 1, /* segment descriptor present */ 1121 0, /* long */ 1122 1, /* default 32 vs 16 bit size */ 1123 1 /* limit granularity (byte/page units)*/ }, 1124 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1125 { 0x0, /* segment base address */ 1126 0xfffff, /* length - all address space */ 1127 SDT_MEMERA, /* segment type */ 1128 SEL_UPL, /* segment descriptor priority level */ 1129 1, /* segment descriptor present */ 1130 1, /* long */ 1131 0, /* default 32 vs 16 bit size */ 1132 1 /* limit granularity (byte/page units)*/ }, 1133 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1134 { 1135 0x0, /* segment base address */ 1136 sizeof(struct x86_64tss)-1,/* length - all address space */ 1137 SDT_SYSTSS, /* segment type */ 1138 SEL_KPL, /* segment descriptor priority level */ 1139 1, /* segment descriptor present */ 1140 0, /* long */ 1141 0, /* unused - default 32 vs 16 bit size */ 1142 0 /* limit granularity (byte/page units)*/ }, 1143 /* Actually, the TSS is a system descriptor which is double size */ 1144 { 0x0, /* segment base address */ 1145 0x0, /* length */ 1146 0, /* segment type */ 1147 0, /* segment descriptor priority level */ 1148 0, /* segment descriptor present */ 1149 0, /* long */ 1150 0, /* default 32 vs 16 bit size */ 1151 0 /* limit granularity (byte/page units)*/ }, 1152 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1153 { 0x0, /* segment base address */ 1154 0xfffff, /* length - all address space */ 1155 SDT_MEMRWA, /* segment type */ 1156 SEL_UPL, /* segment descriptor priority level */ 1157 1, /* segment descriptor present */ 1158 0, /* long */ 1159 1, /* default 32 vs 16 bit size */ 1160 1 /* limit granularity (byte/page units)*/ }, 1161 }; 1162 1163 void 1164 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1165 { 1166 int cpu; 1167 1168 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1169 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1170 1171 ip->gd_looffset = (uintptr_t)func; 1172 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1173 ip->gd_ist = ist; 1174 ip->gd_xx = 0; 1175 ip->gd_type = typ; 1176 ip->gd_dpl = dpl; 1177 ip->gd_p = 1; 1178 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1179 } 1180 } 1181 1182 void 1183 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1184 { 1185 struct gate_descriptor *ip; 1186 1187 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1188 1189 ip = &idt_arr[cpu][idx]; 1190 ip->gd_looffset = (uintptr_t)func; 1191 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1192 ip->gd_ist = ist; 1193 ip->gd_xx = 0; 1194 ip->gd_type = typ; 1195 ip->gd_dpl = dpl; 1196 ip->gd_p = 1; 1197 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1198 } 1199 1200 #define IDTVEC(name) __CONCAT(X,name) 1201 1202 extern inthand_t 1203 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1204 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1205 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1206 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1207 IDTVEC(xmm), IDTVEC(dblfault), 1208 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1209 1210 #ifdef DEBUG_INTERRUPTS 1211 extern inthand_t *Xrsvdary[256]; 1212 #endif 1213 1214 void 1215 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1216 { 1217 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1218 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1219 ssd->ssd_type = sd->sd_type; 1220 ssd->ssd_dpl = sd->sd_dpl; 1221 ssd->ssd_p = sd->sd_p; 1222 ssd->ssd_def32 = sd->sd_def32; 1223 ssd->ssd_gran = sd->sd_gran; 1224 } 1225 1226 void 1227 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1228 { 1229 1230 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1231 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1232 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1233 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1234 sd->sd_type = ssd->ssd_type; 1235 sd->sd_dpl = ssd->ssd_dpl; 1236 sd->sd_p = ssd->ssd_p; 1237 sd->sd_long = ssd->ssd_long; 1238 sd->sd_def32 = ssd->ssd_def32; 1239 sd->sd_gran = ssd->ssd_gran; 1240 } 1241 1242 void 1243 ssdtosyssd(struct soft_segment_descriptor *ssd, 1244 struct system_segment_descriptor *sd) 1245 { 1246 1247 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1248 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1249 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1250 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1251 sd->sd_type = ssd->ssd_type; 1252 sd->sd_dpl = ssd->ssd_dpl; 1253 sd->sd_p = ssd->ssd_p; 1254 sd->sd_gran = ssd->ssd_gran; 1255 } 1256 1257 /* 1258 * Populate the (physmap) array with base/bound pairs describing the 1259 * available physical memory in the system, then test this memory and 1260 * build the phys_avail array describing the actually-available memory. 1261 * 1262 * If we cannot accurately determine the physical memory map, then use 1263 * value from the 0xE801 call, and failing that, the RTC. 1264 * 1265 * Total memory size may be set by the kernel environment variable 1266 * hw.physmem or the compile-time define MAXMEM. 1267 * 1268 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1269 * of PAGE_SIZE. This also greatly reduces the memory test time 1270 * which would otherwise be excessive on machines with > 8G of ram. 1271 * 1272 * XXX first should be vm_paddr_t. 1273 */ 1274 1275 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1276 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1277 1278 static void 1279 getmemsize(caddr_t kmdp, u_int64_t first) 1280 { 1281 int off, physmap_idx, pa_indx, da_indx; 1282 int i, j; 1283 vm_paddr_t physmap[PHYSMAP_SIZE]; 1284 vm_paddr_t pa; 1285 vm_paddr_t msgbuf_size; 1286 u_long physmem_tunable; 1287 pt_entry_t *pte; 1288 struct bios_smap *smapbase, *smap, *smapend; 1289 u_int32_t smapsize; 1290 quad_t dcons_addr, dcons_size; 1291 1292 bzero(physmap, sizeof(physmap)); 1293 physmap_idx = 0; 1294 1295 /* 1296 * get memory map from INT 15:E820, kindly supplied by the loader. 1297 * 1298 * subr_module.c says: 1299 * "Consumer may safely assume that size value precedes data." 1300 * ie: an int32_t immediately precedes smap. 1301 */ 1302 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1303 MODINFO_METADATA | MODINFOMD_SMAP); 1304 if (smapbase == NULL) 1305 panic("No BIOS smap info from loader!"); 1306 1307 smapsize = *((u_int32_t *)smapbase - 1); 1308 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1309 1310 for (smap = smapbase; smap < smapend; smap++) { 1311 if (boothowto & RB_VERBOSE) 1312 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1313 smap->type, smap->base, smap->length); 1314 1315 if (smap->type != SMAP_TYPE_MEMORY) 1316 continue; 1317 1318 if (smap->length == 0) 1319 continue; 1320 1321 for (i = 0; i <= physmap_idx; i += 2) { 1322 if (smap->base < physmap[i + 1]) { 1323 if (boothowto & RB_VERBOSE) { 1324 kprintf("Overlapping or non-monotonic " 1325 "memory region, ignoring " 1326 "second region\n"); 1327 } 1328 break; 1329 } 1330 } 1331 if (i <= physmap_idx) 1332 continue; 1333 1334 Realmem += smap->length; 1335 1336 if (smap->base == physmap[physmap_idx + 1]) { 1337 physmap[physmap_idx + 1] += smap->length; 1338 continue; 1339 } 1340 1341 physmap_idx += 2; 1342 if (physmap_idx == PHYSMAP_SIZE) { 1343 kprintf("Too many segments in the physical " 1344 "address map, giving up\n"); 1345 break; 1346 } 1347 physmap[physmap_idx] = smap->base; 1348 physmap[physmap_idx + 1] = smap->base + smap->length; 1349 } 1350 1351 base_memory = physmap[1] / 1024; 1352 /* make hole for AP bootstrap code */ 1353 physmap[1] = mp_bootaddress(base_memory); 1354 1355 /* Save EBDA address, if any */ 1356 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1357 ebda_addr <<= 4; 1358 1359 /* 1360 * Maxmem isn't the "maximum memory", it's one larger than the 1361 * highest page of the physical address space. It should be 1362 * called something like "Maxphyspage". We may adjust this 1363 * based on ``hw.physmem'' and the results of the memory test. 1364 */ 1365 Maxmem = atop(physmap[physmap_idx + 1]); 1366 1367 #ifdef MAXMEM 1368 Maxmem = MAXMEM / 4; 1369 #endif 1370 1371 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1372 Maxmem = atop(physmem_tunable); 1373 1374 /* 1375 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1376 * in the system. 1377 */ 1378 if (Maxmem > atop(physmap[physmap_idx + 1])) 1379 Maxmem = atop(physmap[physmap_idx + 1]); 1380 1381 /* 1382 * Blowing out the DMAP will blow up the system. 1383 */ 1384 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1385 kprintf("Limiting Maxmem due to DMAP size\n"); 1386 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1387 } 1388 1389 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1390 (boothowto & RB_VERBOSE)) { 1391 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1392 } 1393 1394 /* 1395 * Call pmap initialization to make new kernel address space 1396 * 1397 * Mask off page 0. 1398 */ 1399 pmap_bootstrap(&first); 1400 physmap[0] = PAGE_SIZE; 1401 1402 /* 1403 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1404 * exceeding Maxmem. 1405 */ 1406 for (i = j = 0; i <= physmap_idx; i += 2) { 1407 if (physmap[i+1] > ptoa(Maxmem)) 1408 physmap[i+1] = ptoa(Maxmem); 1409 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1410 ~PHYSMAP_ALIGN_MASK; 1411 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1412 1413 physmap[j] = physmap[i]; 1414 physmap[j+1] = physmap[i+1]; 1415 1416 if (physmap[i] < physmap[i+1]) 1417 j += 2; 1418 } 1419 physmap_idx = j - 2; 1420 1421 /* 1422 * Align anything else used in the validation loop. 1423 */ 1424 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1425 1426 /* 1427 * Size up each available chunk of physical memory. 1428 */ 1429 pa_indx = 0; 1430 da_indx = 1; 1431 phys_avail[pa_indx++] = physmap[0]; 1432 phys_avail[pa_indx] = physmap[0]; 1433 dump_avail[da_indx] = physmap[0]; 1434 pte = CMAP1; 1435 1436 /* 1437 * Get dcons buffer address 1438 */ 1439 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 1440 kgetenv_quad("dcons.size", &dcons_size) == 0) 1441 dcons_addr = 0; 1442 1443 /* 1444 * Validate the physical memory. The physical memory segments 1445 * have already been aligned to PHYSMAP_ALIGN which is a multiple 1446 * of PAGE_SIZE. 1447 */ 1448 for (i = 0; i <= physmap_idx; i += 2) { 1449 vm_paddr_t end; 1450 1451 end = physmap[i + 1]; 1452 1453 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) { 1454 int tmp, page_bad, full; 1455 int *ptr = (int *)CADDR1; 1456 1457 full = FALSE; 1458 /* 1459 * block out kernel memory as not available. 1460 */ 1461 if (pa >= 0x200000 && pa < first) 1462 goto do_dump_avail; 1463 1464 /* 1465 * block out dcons buffer 1466 */ 1467 if (dcons_addr > 0 1468 && pa >= trunc_page(dcons_addr) 1469 && pa < dcons_addr + dcons_size) { 1470 goto do_dump_avail; 1471 } 1472 1473 page_bad = FALSE; 1474 1475 /* 1476 * map page into kernel: valid, read/write,non-cacheable 1477 */ 1478 *pte = pa | 1479 kernel_pmap.pmap_bits[PG_V_IDX] | 1480 kernel_pmap.pmap_bits[PG_RW_IDX] | 1481 kernel_pmap.pmap_bits[PG_N_IDX]; 1482 cpu_invltlb(); 1483 1484 tmp = *ptr; 1485 /* 1486 * Test for alternating 1's and 0's 1487 */ 1488 *(volatile int *)ptr = 0xaaaaaaaa; 1489 cpu_mfence(); 1490 if (*(volatile int *)ptr != 0xaaaaaaaa) 1491 page_bad = TRUE; 1492 /* 1493 * Test for alternating 0's and 1's 1494 */ 1495 *(volatile int *)ptr = 0x55555555; 1496 cpu_mfence(); 1497 if (*(volatile int *)ptr != 0x55555555) 1498 page_bad = TRUE; 1499 /* 1500 * Test for all 1's 1501 */ 1502 *(volatile int *)ptr = 0xffffffff; 1503 cpu_mfence(); 1504 if (*(volatile int *)ptr != 0xffffffff) 1505 page_bad = TRUE; 1506 /* 1507 * Test for all 0's 1508 */ 1509 *(volatile int *)ptr = 0x0; 1510 cpu_mfence(); 1511 if (*(volatile int *)ptr != 0x0) 1512 page_bad = TRUE; 1513 /* 1514 * Restore original value. 1515 */ 1516 *ptr = tmp; 1517 1518 /* 1519 * Adjust array of valid/good pages. 1520 */ 1521 if (page_bad == TRUE) 1522 continue; 1523 /* 1524 * If this good page is a continuation of the 1525 * previous set of good pages, then just increase 1526 * the end pointer. Otherwise start a new chunk. 1527 * Note that "end" points one higher than end, 1528 * making the range >= start and < end. 1529 * If we're also doing a speculative memory 1530 * test and we at or past the end, bump up Maxmem 1531 * so that we keep going. The first bad page 1532 * will terminate the loop. 1533 */ 1534 if (phys_avail[pa_indx] == pa) { 1535 phys_avail[pa_indx] += PHYSMAP_ALIGN; 1536 } else { 1537 pa_indx++; 1538 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1539 kprintf( 1540 "Too many holes in the physical address space, giving up\n"); 1541 pa_indx--; 1542 full = TRUE; 1543 goto do_dump_avail; 1544 } 1545 phys_avail[pa_indx++] = pa; 1546 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN; 1547 } 1548 physmem += PHYSMAP_ALIGN / PAGE_SIZE; 1549 do_dump_avail: 1550 if (dump_avail[da_indx] == pa) { 1551 dump_avail[da_indx] += PHYSMAP_ALIGN; 1552 } else { 1553 da_indx++; 1554 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1555 da_indx--; 1556 goto do_next; 1557 } 1558 dump_avail[da_indx++] = pa; 1559 dump_avail[da_indx] = pa + PHYSMAP_ALIGN; 1560 } 1561 do_next: 1562 if (full) 1563 break; 1564 } 1565 } 1566 *pte = 0; 1567 cpu_invltlb(); 1568 1569 /* 1570 * The last chunk must contain at least one page plus the message 1571 * buffer to avoid complicating other code (message buffer address 1572 * calculation, etc.). 1573 */ 1574 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1575 1576 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN + 1577 msgbuf_size >= phys_avail[pa_indx]) { 1578 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1579 phys_avail[pa_indx--] = 0; 1580 phys_avail[pa_indx--] = 0; 1581 } 1582 1583 Maxmem = atop(phys_avail[pa_indx]); 1584 1585 /* Trim off space for the message buffer. */ 1586 phys_avail[pa_indx] -= msgbuf_size; 1587 1588 avail_end = phys_avail[pa_indx]; 1589 1590 /* Map the message buffer. */ 1591 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 1592 pmap_kenter((vm_offset_t)msgbufp + off, 1593 phys_avail[pa_indx] + off); 1594 } 1595 } 1596 1597 struct machintr_abi MachIntrABI; 1598 1599 /* 1600 * IDT VECTORS: 1601 * 0 Divide by zero 1602 * 1 Debug 1603 * 2 NMI 1604 * 3 BreakPoint 1605 * 4 OverFlow 1606 * 5 Bound-Range 1607 * 6 Invalid OpCode 1608 * 7 Device Not Available (x87) 1609 * 8 Double-Fault 1610 * 9 Coprocessor Segment overrun (unsupported, reserved) 1611 * 10 Invalid-TSS 1612 * 11 Segment not present 1613 * 12 Stack 1614 * 13 General Protection 1615 * 14 Page Fault 1616 * 15 Reserved 1617 * 16 x87 FP Exception pending 1618 * 17 Alignment Check 1619 * 18 Machine Check 1620 * 19 SIMD floating point 1621 * 20-31 reserved 1622 * 32-255 INTn/external sources 1623 */ 1624 u_int64_t 1625 hammer_time(u_int64_t modulep, u_int64_t physfree) 1626 { 1627 caddr_t kmdp; 1628 int gsel_tss, x, cpu; 1629 #if JG 1630 int metadata_missing, off; 1631 #endif 1632 struct mdglobaldata *gd; 1633 u_int64_t msr; 1634 1635 /* 1636 * Prevent lowering of the ipl if we call tsleep() early. 1637 */ 1638 gd = &CPU_prvspace[0].mdglobaldata; 1639 bzero(gd, sizeof(*gd)); 1640 1641 /* 1642 * Note: on both UP and SMP curthread must be set non-NULL 1643 * early in the boot sequence because the system assumes 1644 * that 'curthread' is never NULL. 1645 */ 1646 1647 gd->mi.gd_curthread = &thread0; 1648 thread0.td_gd = &gd->mi; 1649 1650 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 1651 1652 #if JG 1653 metadata_missing = 0; 1654 if (bootinfo.bi_modulep) { 1655 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 1656 preload_bootstrap_relocate(KERNBASE); 1657 } else { 1658 metadata_missing = 1; 1659 } 1660 if (bootinfo.bi_envp) 1661 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 1662 #endif 1663 1664 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 1665 preload_bootstrap_relocate(PTOV_OFFSET); 1666 kmdp = preload_search_by_type("elf kernel"); 1667 if (kmdp == NULL) 1668 kmdp = preload_search_by_type("elf64 kernel"); 1669 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1670 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 1671 #ifdef DDB 1672 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1673 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1674 #endif 1675 1676 if (boothowto & RB_VERBOSE) 1677 bootverbose++; 1678 1679 /* 1680 * Default MachIntrABI to ICU 1681 */ 1682 MachIntrABI = MachIntrABI_ICU; 1683 1684 /* 1685 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask, 1686 * and ncpus_fit_mask remain 0. 1687 */ 1688 ncpus = 1; 1689 ncpus2 = 1; 1690 ncpus_fit = 1; 1691 /* Init basic tunables, hz etc */ 1692 init_param1(); 1693 1694 /* 1695 * make gdt memory segments 1696 */ 1697 gdt_segs[GPROC0_SEL].ssd_base = 1698 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss; 1699 1700 gd->mi.gd_prvspace = &CPU_prvspace[0]; 1701 1702 for (x = 0; x < NGDT; x++) { 1703 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 1704 ssdtosd(&gdt_segs[x], &gdt[x]); 1705 } 1706 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1707 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1708 1709 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1710 r_gdt.rd_base = (long) gdt; 1711 lgdt(&r_gdt); 1712 1713 wrmsr(MSR_FSBASE, 0); /* User value */ 1714 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 1715 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1716 1717 mi_gdinit(&gd->mi, 0); 1718 cpu_gdinit(gd, 0); 1719 proc0paddr = proc0paddr_buff; 1720 mi_proc0init(&gd->mi, proc0paddr); 1721 safepri = TDPRI_MAX; 1722 1723 /* spinlocks and the BGL */ 1724 init_locks(); 1725 1726 /* exceptions */ 1727 for (x = 0; x < NIDT; x++) 1728 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1729 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1730 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1731 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 1732 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1733 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1734 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1735 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1736 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1737 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1738 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1739 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1740 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1741 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1742 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1743 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1744 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1745 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1746 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1747 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1748 1749 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1750 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 1751 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 1752 } 1753 1754 lidt(&r_idt_arr[0]); 1755 1756 /* 1757 * Initialize the console before we print anything out. 1758 */ 1759 cninit(); 1760 1761 #if JG 1762 if (metadata_missing) 1763 kprintf("WARNING: loader(8) metadata is missing!\n"); 1764 #endif 1765 1766 #if NISA >0 1767 elcr_probe(); 1768 isa_defaultirq(); 1769 #endif 1770 rand_initialize(); 1771 1772 /* 1773 * Initialize IRQ mapping 1774 * 1775 * NOTE: 1776 * SHOULD be after elcr_probe() 1777 */ 1778 MachIntrABI_ICU.initmap(); 1779 MachIntrABI_IOAPIC.initmap(); 1780 1781 #ifdef DDB 1782 kdb_init(); 1783 if (boothowto & RB_KDB) 1784 Debugger("Boot flags requested debugger"); 1785 #endif 1786 1787 #if JG 1788 finishidentcpu(); /* Final stage of CPU initialization */ 1789 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1790 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1791 #endif 1792 identify_cpu(); /* Final stage of CPU initialization */ 1793 initializecpu(0); /* Initialize CPU registers */ 1794 1795 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 1796 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 1797 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 1798 1799 /* 1800 * Some of the virtual machines do not work w/ I/O APIC 1801 * enabled. If the user does not explicitly enable or 1802 * disable the I/O APIC (ioapic_enable < 0), then we 1803 * disable I/O APIC on all virtual machines. 1804 * 1805 * NOTE: 1806 * This must be done after identify_cpu(), which sets 1807 * 'cpu_feature2' 1808 */ 1809 if (ioapic_enable < 0) { 1810 if (cpu_feature2 & CPUID2_VMM) 1811 ioapic_enable = 0; 1812 else 1813 ioapic_enable = 1; 1814 } 1815 1816 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1817 gd->gd_common_tss.tss_rsp0 = 1818 (register_t)(thread0.td_kstack + 1819 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 1820 /* Ensure the stack is aligned to 16 bytes */ 1821 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 1822 1823 /* double fault stack */ 1824 gd->gd_common_tss.tss_ist1 = 1825 (long)&gd->mi.gd_prvspace->idlestack[ 1826 sizeof(gd->mi.gd_prvspace->idlestack)]; 1827 1828 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1829 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 1830 1831 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1832 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 1833 gd->gd_common_tssd = *gd->gd_tss_gdt; 1834 ltr(gsel_tss); 1835 1836 /* Set up the fast syscall stuff */ 1837 msr = rdmsr(MSR_EFER) | EFER_SCE; 1838 wrmsr(MSR_EFER, msr); 1839 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1840 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1841 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1842 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1843 wrmsr(MSR_STAR, msr); 1844 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 1845 1846 getmemsize(kmdp, physfree); 1847 init_param2(physmem); 1848 1849 /* now running on new page tables, configured,and u/iom is accessible */ 1850 1851 /* Map the message buffer. */ 1852 #if JG 1853 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1854 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 1855 #endif 1856 1857 msgbufinit(msgbufp, MSGBUF_SIZE); 1858 1859 1860 /* transfer to user mode */ 1861 1862 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1863 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1864 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1865 1866 load_ds(_udatasel); 1867 load_es(_udatasel); 1868 load_fs(_udatasel); 1869 1870 /* setup proc 0's pcb */ 1871 thread0.td_pcb->pcb_flags = 0; 1872 thread0.td_pcb->pcb_cr3 = KPML4phys; 1873 thread0.td_pcb->pcb_ext = NULL; 1874 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 1875 1876 /* Location of kernel stack for locore */ 1877 return ((u_int64_t)thread0.td_pcb); 1878 } 1879 1880 /* 1881 * Initialize machine-dependant portions of the global data structure. 1882 * Note that the global data area and cpu0's idlestack in the private 1883 * data space were allocated in locore. 1884 * 1885 * Note: the idlethread's cpl is 0 1886 * 1887 * WARNING! Called from early boot, 'mycpu' may not work yet. 1888 */ 1889 void 1890 cpu_gdinit(struct mdglobaldata *gd, int cpu) 1891 { 1892 if (cpu) 1893 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 1894 1895 lwkt_init_thread(&gd->mi.gd_idlethread, 1896 gd->mi.gd_prvspace->idlestack, 1897 sizeof(gd->mi.gd_prvspace->idlestack), 1898 0, &gd->mi); 1899 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 1900 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 1901 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 1902 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 1903 } 1904 1905 int 1906 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 1907 { 1908 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 1909 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 1910 return (TRUE); 1911 } 1912 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 1913 return (TRUE); 1914 return (FALSE); 1915 } 1916 1917 struct globaldata * 1918 globaldata_find(int cpu) 1919 { 1920 KKASSERT(cpu >= 0 && cpu < ncpus); 1921 return(&CPU_prvspace[cpu].mdglobaldata.mi); 1922 } 1923 1924 int 1925 ptrace_set_pc(struct lwp *lp, unsigned long addr) 1926 { 1927 lp->lwp_md.md_regs->tf_rip = addr; 1928 return (0); 1929 } 1930 1931 int 1932 ptrace_single_step(struct lwp *lp) 1933 { 1934 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 1935 return (0); 1936 } 1937 1938 int 1939 fill_regs(struct lwp *lp, struct reg *regs) 1940 { 1941 struct trapframe *tp; 1942 1943 if ((tp = lp->lwp_md.md_regs) == NULL) 1944 return EINVAL; 1945 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 1946 return (0); 1947 } 1948 1949 int 1950 set_regs(struct lwp *lp, struct reg *regs) 1951 { 1952 struct trapframe *tp; 1953 1954 tp = lp->lwp_md.md_regs; 1955 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 1956 !CS_SECURE(regs->r_cs)) 1957 return (EINVAL); 1958 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 1959 clear_quickret(); 1960 return (0); 1961 } 1962 1963 #ifndef CPU_DISABLE_SSE 1964 static void 1965 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 1966 { 1967 struct env87 *penv_87 = &sv_87->sv_env; 1968 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1969 int i; 1970 1971 /* FPU control/status */ 1972 penv_87->en_cw = penv_xmm->en_cw; 1973 penv_87->en_sw = penv_xmm->en_sw; 1974 penv_87->en_tw = penv_xmm->en_tw; 1975 penv_87->en_fip = penv_xmm->en_fip; 1976 penv_87->en_fcs = penv_xmm->en_fcs; 1977 penv_87->en_opcode = penv_xmm->en_opcode; 1978 penv_87->en_foo = penv_xmm->en_foo; 1979 penv_87->en_fos = penv_xmm->en_fos; 1980 1981 /* FPU registers */ 1982 for (i = 0; i < 8; ++i) 1983 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 1984 } 1985 1986 static void 1987 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 1988 { 1989 struct env87 *penv_87 = &sv_87->sv_env; 1990 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1991 int i; 1992 1993 /* FPU control/status */ 1994 penv_xmm->en_cw = penv_87->en_cw; 1995 penv_xmm->en_sw = penv_87->en_sw; 1996 penv_xmm->en_tw = penv_87->en_tw; 1997 penv_xmm->en_fip = penv_87->en_fip; 1998 penv_xmm->en_fcs = penv_87->en_fcs; 1999 penv_xmm->en_opcode = penv_87->en_opcode; 2000 penv_xmm->en_foo = penv_87->en_foo; 2001 penv_xmm->en_fos = penv_87->en_fos; 2002 2003 /* FPU registers */ 2004 for (i = 0; i < 8; ++i) 2005 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2006 } 2007 #endif /* CPU_DISABLE_SSE */ 2008 2009 int 2010 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2011 { 2012 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2013 return EINVAL; 2014 #ifndef CPU_DISABLE_SSE 2015 if (cpu_fxsr) { 2016 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2017 (struct save87 *)fpregs); 2018 return (0); 2019 } 2020 #endif /* CPU_DISABLE_SSE */ 2021 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2022 return (0); 2023 } 2024 2025 int 2026 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2027 { 2028 #ifndef CPU_DISABLE_SSE 2029 if (cpu_fxsr) { 2030 set_fpregs_xmm((struct save87 *)fpregs, 2031 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2032 return (0); 2033 } 2034 #endif /* CPU_DISABLE_SSE */ 2035 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2036 return (0); 2037 } 2038 2039 int 2040 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2041 { 2042 struct pcb *pcb; 2043 2044 if (lp == NULL) { 2045 dbregs->dr[0] = rdr0(); 2046 dbregs->dr[1] = rdr1(); 2047 dbregs->dr[2] = rdr2(); 2048 dbregs->dr[3] = rdr3(); 2049 dbregs->dr[4] = rdr4(); 2050 dbregs->dr[5] = rdr5(); 2051 dbregs->dr[6] = rdr6(); 2052 dbregs->dr[7] = rdr7(); 2053 return (0); 2054 } 2055 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2056 return EINVAL; 2057 dbregs->dr[0] = pcb->pcb_dr0; 2058 dbregs->dr[1] = pcb->pcb_dr1; 2059 dbregs->dr[2] = pcb->pcb_dr2; 2060 dbregs->dr[3] = pcb->pcb_dr3; 2061 dbregs->dr[4] = 0; 2062 dbregs->dr[5] = 0; 2063 dbregs->dr[6] = pcb->pcb_dr6; 2064 dbregs->dr[7] = pcb->pcb_dr7; 2065 return (0); 2066 } 2067 2068 int 2069 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2070 { 2071 if (lp == NULL) { 2072 load_dr0(dbregs->dr[0]); 2073 load_dr1(dbregs->dr[1]); 2074 load_dr2(dbregs->dr[2]); 2075 load_dr3(dbregs->dr[3]); 2076 load_dr4(dbregs->dr[4]); 2077 load_dr5(dbregs->dr[5]); 2078 load_dr6(dbregs->dr[6]); 2079 load_dr7(dbregs->dr[7]); 2080 } else { 2081 struct pcb *pcb; 2082 struct ucred *ucred; 2083 int i; 2084 uint64_t mask1, mask2; 2085 2086 /* 2087 * Don't let an illegal value for dr7 get set. Specifically, 2088 * check for undefined settings. Setting these bit patterns 2089 * result in undefined behaviour and can lead to an unexpected 2090 * TRCTRAP. 2091 */ 2092 /* JG this loop looks unreadable */ 2093 /* Check 4 2-bit fields for invalid patterns. 2094 * These fields are R/Wi, for i = 0..3 2095 */ 2096 /* Is 10 in LENi allowed when running in compatibility mode? */ 2097 /* Pattern 10 in R/Wi might be used to indicate 2098 * breakpoint on I/O. Further analysis should be 2099 * carried to decide if it is safe and useful to 2100 * provide access to that capability 2101 */ 2102 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2103 i++, mask1 <<= 4, mask2 <<= 4) 2104 if ((dbregs->dr[7] & mask1) == mask2) 2105 return (EINVAL); 2106 2107 pcb = lp->lwp_thread->td_pcb; 2108 ucred = lp->lwp_proc->p_ucred; 2109 2110 /* 2111 * Don't let a process set a breakpoint that is not within the 2112 * process's address space. If a process could do this, it 2113 * could halt the system by setting a breakpoint in the kernel 2114 * (if ddb was enabled). Thus, we need to check to make sure 2115 * that no breakpoints are being enabled for addresses outside 2116 * process's address space, unless, perhaps, we were called by 2117 * uid 0. 2118 * 2119 * XXX - what about when the watched area of the user's 2120 * address space is written into from within the kernel 2121 * ... wouldn't that still cause a breakpoint to be generated 2122 * from within kernel mode? 2123 */ 2124 2125 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2126 if (dbregs->dr[7] & 0x3) { 2127 /* dr0 is enabled */ 2128 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2129 return (EINVAL); 2130 } 2131 2132 if (dbregs->dr[7] & (0x3<<2)) { 2133 /* dr1 is enabled */ 2134 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2135 return (EINVAL); 2136 } 2137 2138 if (dbregs->dr[7] & (0x3<<4)) { 2139 /* dr2 is enabled */ 2140 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2141 return (EINVAL); 2142 } 2143 2144 if (dbregs->dr[7] & (0x3<<6)) { 2145 /* dr3 is enabled */ 2146 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2147 return (EINVAL); 2148 } 2149 } 2150 2151 pcb->pcb_dr0 = dbregs->dr[0]; 2152 pcb->pcb_dr1 = dbregs->dr[1]; 2153 pcb->pcb_dr2 = dbregs->dr[2]; 2154 pcb->pcb_dr3 = dbregs->dr[3]; 2155 pcb->pcb_dr6 = dbregs->dr[6]; 2156 pcb->pcb_dr7 = dbregs->dr[7]; 2157 2158 pcb->pcb_flags |= PCB_DBREGS; 2159 } 2160 2161 return (0); 2162 } 2163 2164 /* 2165 * Return > 0 if a hardware breakpoint has been hit, and the 2166 * breakpoint was in user space. Return 0, otherwise. 2167 */ 2168 int 2169 user_dbreg_trap(void) 2170 { 2171 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2172 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2173 int nbp; /* number of breakpoints that triggered */ 2174 caddr_t addr[4]; /* breakpoint addresses */ 2175 int i; 2176 2177 dr7 = rdr7(); 2178 if ((dr7 & 0xff) == 0) { 2179 /* 2180 * all GE and LE bits in the dr7 register are zero, 2181 * thus the trap couldn't have been caused by the 2182 * hardware debug registers 2183 */ 2184 return 0; 2185 } 2186 2187 nbp = 0; 2188 dr6 = rdr6(); 2189 bp = dr6 & 0xf; 2190 2191 if (bp == 0) { 2192 /* 2193 * None of the breakpoint bits are set meaning this 2194 * trap was not caused by any of the debug registers 2195 */ 2196 return 0; 2197 } 2198 2199 /* 2200 * at least one of the breakpoints were hit, check to see 2201 * which ones and if any of them are user space addresses 2202 */ 2203 2204 if (bp & 0x01) { 2205 addr[nbp++] = (caddr_t)rdr0(); 2206 } 2207 if (bp & 0x02) { 2208 addr[nbp++] = (caddr_t)rdr1(); 2209 } 2210 if (bp & 0x04) { 2211 addr[nbp++] = (caddr_t)rdr2(); 2212 } 2213 if (bp & 0x08) { 2214 addr[nbp++] = (caddr_t)rdr3(); 2215 } 2216 2217 for (i=0; i<nbp; i++) { 2218 if (addr[i] < 2219 (caddr_t)VM_MAX_USER_ADDRESS) { 2220 /* 2221 * addr[i] is in user space 2222 */ 2223 return nbp; 2224 } 2225 } 2226 2227 /* 2228 * None of the breakpoints are in user space. 2229 */ 2230 return 0; 2231 } 2232 2233 2234 #ifndef DDB 2235 void 2236 Debugger(const char *msg) 2237 { 2238 kprintf("Debugger(\"%s\") called.\n", msg); 2239 } 2240 #endif /* no DDB */ 2241 2242 #ifdef DDB 2243 2244 /* 2245 * Provide inb() and outb() as functions. They are normally only 2246 * available as macros calling inlined functions, thus cannot be 2247 * called inside DDB. 2248 * 2249 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2250 */ 2251 2252 #undef inb 2253 #undef outb 2254 2255 /* silence compiler warnings */ 2256 u_char inb(u_int); 2257 void outb(u_int, u_char); 2258 2259 u_char 2260 inb(u_int port) 2261 { 2262 u_char data; 2263 /* 2264 * We use %%dx and not %1 here because i/o is done at %dx and not at 2265 * %edx, while gcc generates inferior code (movw instead of movl) 2266 * if we tell it to load (u_short) port. 2267 */ 2268 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2269 return (data); 2270 } 2271 2272 void 2273 outb(u_int port, u_char data) 2274 { 2275 u_char al; 2276 /* 2277 * Use an unnecessary assignment to help gcc's register allocator. 2278 * This make a large difference for gcc-1.40 and a tiny difference 2279 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2280 * best results. gcc-2.6.0 can't handle this. 2281 */ 2282 al = data; 2283 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2284 } 2285 2286 #endif /* DDB */ 2287 2288 2289 2290 /* 2291 * initialize all the SMP locks 2292 */ 2293 2294 /* critical region when masking or unmasking interupts */ 2295 struct spinlock_deprecated imen_spinlock; 2296 2297 /* critical region for old style disable_intr/enable_intr */ 2298 struct spinlock_deprecated mpintr_spinlock; 2299 2300 /* critical region around INTR() routines */ 2301 struct spinlock_deprecated intr_spinlock; 2302 2303 /* lock region used by kernel profiling */ 2304 struct spinlock_deprecated mcount_spinlock; 2305 2306 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2307 struct spinlock_deprecated com_spinlock; 2308 2309 /* lock regions around the clock hardware */ 2310 struct spinlock_deprecated clock_spinlock; 2311 2312 static void 2313 init_locks(void) 2314 { 2315 /* 2316 * Get the initial mplock with a count of 1 for the BSP. 2317 * This uses a LOGICAL cpu ID, ie BSP == 0. 2318 */ 2319 cpu_get_initial_mplock(); 2320 /* DEPRECATED */ 2321 spin_lock_init(&mcount_spinlock); 2322 spin_lock_init(&intr_spinlock); 2323 spin_lock_init(&mpintr_spinlock); 2324 spin_lock_init(&imen_spinlock); 2325 spin_lock_init(&com_spinlock); 2326 spin_lock_init(&clock_spinlock); 2327 2328 /* our token pool needs to work early */ 2329 lwkt_token_pool_init(); 2330 } 2331 2332