1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008-2017 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 #if 0 /* JG */ 137 extern void finishidentcpu(void); 138 #endif 139 extern void panicifcpuunsupported(void); 140 141 static void cpu_startup(void *); 142 static void pic_finish(void *); 143 static void cpu_finish(void *); 144 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 static void init_locks(void); 148 149 extern void pcpu_timer_always(struct intrframe *); 150 151 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 152 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 153 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 154 155 #ifdef DDB 156 extern vm_offset_t ksym_start, ksym_end; 157 #endif 158 159 struct privatespace CPU_prvspace_bsp __aligned(4096); 160 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 161 162 vm_paddr_t efi_systbl_phys; 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 cpumask_t smp_idleinvl_mask; 167 cpumask_t smp_idleinvl_reqs; 168 169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 170 171 #if defined(SWTCH_OPTIM_STATS) 172 extern int swtch_optim_stats; 173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 174 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 176 CTLFLAG_RD, &tlb_flush_count, 0, ""); 177 #endif 178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, 181 CTLFLAG_RD, &cpu_mwait_spin, 0, "monitor/mwait target state"); 182 183 #define CPU_MWAIT_HAS_CX \ 184 ((cpu_feature2 & CPUID2_MON) && \ 185 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 186 187 #define CPU_MWAIT_CX_NAMELEN 16 188 189 #define CPU_MWAIT_C1 1 190 #define CPU_MWAIT_C2 2 191 #define CPU_MWAIT_C3 3 192 #define CPU_MWAIT_CX_MAX 8 193 194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 196 197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 199 200 struct cpu_mwait_cx { 201 int subcnt; 202 char name[4]; 203 struct sysctl_ctx_list sysctl_ctx; 204 struct sysctl_oid *sysctl_tree; 205 }; 206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 207 static char cpu_mwait_cx_supported[256]; 208 209 static int cpu_mwait_c1_hints_cnt; 210 static int cpu_mwait_hints_cnt; 211 static int *cpu_mwait_hints; 212 213 static int cpu_mwait_deep_hints_cnt; 214 static int *cpu_mwait_deep_hints; 215 216 #define CPU_IDLE_REPEAT_DEFAULT 750 217 218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 220 static u_int cpu_mwait_repeat_shift = 1; 221 222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 224 225 static int cpu_mwait_c3_preamble = 226 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 227 CPU_MWAIT_C3_PREAMBLE_BM_STS; 228 229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 230 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 233 234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 235 int *, boolean_t); 236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 239 240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 245 &cpu_mwait_repeat_shift, 0, ""); 246 247 long physmem = 0; 248 249 u_long ebda_addr = 0; 250 251 int imcr_present = 0; 252 253 int naps = 0; /* # of Applications processors */ 254 255 u_int base_memory; 256 257 static int 258 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 259 { 260 u_long pmem = ctob(physmem); 261 int error; 262 263 error = sysctl_handle_long(oidp, &pmem, 0, req); 264 265 return (error); 266 } 267 268 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 269 0, 0, sysctl_hw_physmem, "LU", 270 "Total system memory in bytes (number of pages * page size)"); 271 272 static int 273 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 274 { 275 u_long usermem = ctob(physmem - vmstats.v_wire_count); 276 int error; 277 278 error = sysctl_handle_long(oidp, &usermem, 0, req); 279 280 return (error); 281 } 282 283 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_ULONG|CTLFLAG_RD, 284 0, 0, sysctl_hw_usermem, "LU", ""); 285 286 static int 287 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 288 { 289 int error; 290 u_long availpages; 291 292 availpages = x86_64_btop(avail_end - avail_start); 293 error = sysctl_handle_long(oidp, &availpages, 0, req); 294 295 return (error); 296 } 297 298 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_ULONG|CTLFLAG_RD, 299 0, 0, sysctl_hw_availpages, "LU", ""); 300 301 vm_paddr_t Maxmem; 302 vm_paddr_t Realmem; 303 304 /* 305 * The number of PHYSMAP entries must be one less than the number of 306 * PHYSSEG entries because the PHYSMAP entry that spans the largest 307 * physical address that is accessible by ISA DMA is split into two 308 * PHYSSEG entries. 309 */ 310 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 311 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 312 313 /* must be 1 less so 0 0 can signal end of chunks */ 314 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 315 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 316 317 static vm_offset_t buffer_sva, buffer_eva; 318 vm_offset_t clean_sva, clean_eva; 319 static vm_offset_t pager_sva, pager_eva; 320 static struct trapframe proc0_tf; 321 322 static void 323 cpu_startup(void *dummy) 324 { 325 caddr_t v; 326 vm_size_t size = 0; 327 vm_offset_t firstaddr; 328 329 /* 330 * Good {morning,afternoon,evening,night}. 331 */ 332 kprintf("%s", version); 333 startrtclock(); 334 printcpuinfo(); 335 panicifcpuunsupported(); 336 kprintf("real memory = %ju (%ju MB)\n", 337 (intmax_t)Realmem, 338 (intmax_t)Realmem / 1024 / 1024); 339 /* 340 * Display any holes after the first chunk of extended memory. 341 */ 342 if (bootverbose) { 343 int indx; 344 345 kprintf("Physical memory chunk(s):\n"); 346 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 347 vm_paddr_t size1; 348 349 size1 = phys_avail[indx].phys_end - 350 phys_avail[indx].phys_beg; 351 352 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 353 (intmax_t)phys_avail[indx].phys_beg, 354 (intmax_t)phys_avail[indx].phys_end - 1, 355 (intmax_t)size1, 356 (intmax_t)(size1 / PAGE_SIZE)); 357 } 358 } 359 360 /* 361 * Allocate space for system data structures. 362 * The first available kernel virtual address is in "v". 363 * As pages of kernel virtual memory are allocated, "v" is incremented. 364 * As pages of memory are allocated and cleared, 365 * "firstaddr" is incremented. 366 * An index into the kernel page table corresponding to the 367 * virtual memory address maintained in "v" is kept in "mapaddr". 368 */ 369 370 /* 371 * Make two passes. The first pass calculates how much memory is 372 * needed and allocates it. The second pass assigns virtual 373 * addresses to the various data structures. 374 */ 375 firstaddr = 0; 376 again: 377 v = (caddr_t)firstaddr; 378 379 #define valloc(name, type, num) \ 380 (name) = (type *)v; v = (caddr_t)((name)+(num)) 381 #define valloclim(name, type, num, lim) \ 382 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 383 384 /* 385 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 386 * For the first 64MB of ram nominally allocate sufficient buffers to 387 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 388 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 389 * the buffer cache we limit the eventual kva reservation to 390 * maxbcache bytes. 391 * 392 * factor represents the 1/4 x ram conversion. 393 */ 394 if (nbuf == 0) { 395 long factor = 4 * NBUFCALCSIZE / 1024; 396 long kbytes = physmem * (PAGE_SIZE / 1024); 397 398 nbuf = 50; 399 if (kbytes > 4096) 400 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 401 if (kbytes > 65536) 402 nbuf += (kbytes - 65536) * 2 / (factor * 5); 403 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 404 nbuf = maxbcache / NBUFCALCSIZE; 405 } 406 407 /* 408 * Do not allow the buffer_map to be more then 1/2 the size of the 409 * kernel_map. 410 */ 411 if (nbuf > (virtual_end - virtual_start + 412 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 413 nbuf = (virtual_end - virtual_start + 414 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 415 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 416 } 417 418 /* 419 * Do not allow the buffer_map to use more than 50% of available 420 * physical-equivalent memory. Since the VM pages which back 421 * individual buffers are typically wired, having too many bufs 422 * can prevent the system from paging properly. 423 */ 424 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 425 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 426 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 427 } 428 429 /* 430 * Do not allow the sizeof(struct buf) * nbuf to exceed 1/4 of 431 * the valloc space which is just the virtual_end - virtual_start 432 * section. This is typically ~2GB regardless of the amount of 433 * memory, so we use 500MB as a metric. 434 * 435 * This is because we use valloc() to allocate the buf header array. 436 * 437 * NOTE: buffer space in bytes is limited by vfs.*bufspace sysctls. 438 */ 439 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 4) { 440 nbuf = (virtual_end - virtual_start) / 441 sizeof(struct buf) / 2; 442 kprintf("Warning: nbufs capped at %ld due to " 443 "valloc considerations\n", 444 nbuf); 445 } 446 447 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 448 #ifdef NSWBUF_MIN 449 if (nswbuf_mem < NSWBUF_MIN) 450 nswbuf_mem = NSWBUF_MIN; 451 #endif 452 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 453 #ifdef NSWBUF_MIN 454 if (nswbuf_kva < NSWBUF_MIN) 455 nswbuf_kva = NSWBUF_MIN; 456 #endif 457 458 valloc(swbuf_mem, struct buf, nswbuf_mem); 459 valloc(swbuf_kva, struct buf, nswbuf_kva); 460 valloc(buf, struct buf, nbuf); 461 462 /* 463 * End of first pass, size has been calculated so allocate memory 464 */ 465 if (firstaddr == 0) { 466 size = (vm_size_t)(v - firstaddr); 467 firstaddr = kmem_alloc(&kernel_map, round_page(size), 468 VM_SUBSYS_BUF); 469 if (firstaddr == 0) 470 panic("startup: no room for tables"); 471 goto again; 472 } 473 474 /* 475 * End of second pass, addresses have been assigned 476 * 477 * nbuf is an int, make sure we don't overflow the field. 478 * 479 * On 64-bit systems we always reserve maximal allocations for 480 * buffer cache buffers and there are no fragmentation issues, 481 * so the KVA segment does not have to be excessively oversized. 482 */ 483 if ((vm_size_t)(v - firstaddr) != size) 484 panic("startup: table size inconsistency"); 485 486 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 487 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 488 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 489 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 490 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 491 buffer_map.system_map = 1; 492 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 493 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 494 pager_map_size); 495 pager_map.system_map = 1; 496 kprintf("avail memory = %ju (%ju MB)\n", 497 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 498 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 499 1024 / 1024); 500 } 501 502 struct cpu_idle_stat { 503 int hint; 504 int reserved; 505 u_long halt; 506 u_long spin; 507 u_long repeat; 508 u_long repeat_last; 509 u_long repeat_delta; 510 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 511 } __cachealign; 512 513 #define CPU_IDLE_STAT_HALT -1 514 #define CPU_IDLE_STAT_SPIN -2 515 516 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 517 518 static int 519 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 520 { 521 int idx = arg2, cpu, error; 522 u_long val = 0; 523 524 if (idx == CPU_IDLE_STAT_HALT) { 525 for (cpu = 0; cpu < ncpus; ++cpu) 526 val += cpu_idle_stats[cpu].halt; 527 } else if (idx == CPU_IDLE_STAT_SPIN) { 528 for (cpu = 0; cpu < ncpus; ++cpu) 529 val += cpu_idle_stats[cpu].spin; 530 } else { 531 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 532 ("invalid index %d", idx)); 533 for (cpu = 0; cpu < ncpus; ++cpu) 534 val += cpu_idle_stats[cpu].mwait_cx[idx]; 535 } 536 537 error = sysctl_handle_quad(oidp, &val, 0, req); 538 if (error || req->newptr == NULL) 539 return error; 540 541 if (idx == CPU_IDLE_STAT_HALT) { 542 for (cpu = 0; cpu < ncpus; ++cpu) 543 cpu_idle_stats[cpu].halt = 0; 544 cpu_idle_stats[0].halt = val; 545 } else if (idx == CPU_IDLE_STAT_SPIN) { 546 for (cpu = 0; cpu < ncpus; ++cpu) 547 cpu_idle_stats[cpu].spin = 0; 548 cpu_idle_stats[0].spin = val; 549 } else { 550 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 551 ("invalid index %d", idx)); 552 for (cpu = 0; cpu < ncpus; ++cpu) 553 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 554 cpu_idle_stats[0].mwait_cx[idx] = val; 555 } 556 return 0; 557 } 558 559 static void 560 cpu_mwait_attach(void) 561 { 562 struct sbuf sb; 563 int hint_idx, i; 564 565 if (!CPU_MWAIT_HAS_CX) 566 return; 567 568 if (cpu_vendor_id == CPU_VENDOR_INTEL && 569 (CPUID_TO_FAMILY(cpu_id) > 0xf || 570 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 571 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 572 int bm_sts = 1; 573 574 /* 575 * Pentium dual-core, Core 2 and beyond do not need any 576 * additional activities to enter deep C-state, i.e. C3(+). 577 */ 578 cpu_mwait_cx_no_bmarb(); 579 580 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 581 if (!bm_sts) 582 cpu_mwait_cx_no_bmsts(); 583 } 584 585 sbuf_new(&sb, cpu_mwait_cx_supported, 586 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 587 588 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 589 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 590 int sub; 591 592 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 593 594 sysctl_ctx_init(&cx->sysctl_ctx); 595 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 596 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 597 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 598 if (cx->sysctl_tree == NULL) 599 continue; 600 601 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 602 SYSCTL_ADD_INT(&cx->sysctl_ctx, 603 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 604 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 605 "sub-state count"); 606 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 607 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 608 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 609 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 610 611 for (sub = 0; sub < cx->subcnt; ++sub) 612 sbuf_printf(&sb, "C%d/%d ", i, sub); 613 } 614 sbuf_trim(&sb); 615 sbuf_finish(&sb); 616 617 /* 618 * Non-deep C-states 619 */ 620 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 621 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 622 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 623 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 624 M_DEVBUF, M_WAITOK); 625 626 hint_idx = 0; 627 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 628 int j, subcnt; 629 630 subcnt = cpu_mwait_cx_info[i].subcnt; 631 for (j = 0; j < subcnt; ++j) { 632 KASSERT(hint_idx < cpu_mwait_hints_cnt, 633 ("invalid mwait hint index %d", hint_idx)); 634 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 635 ++hint_idx; 636 } 637 } 638 KASSERT(hint_idx == cpu_mwait_hints_cnt, 639 ("mwait hint count %d != index %d", 640 cpu_mwait_hints_cnt, hint_idx)); 641 642 if (bootverbose) { 643 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 644 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 645 int hint = cpu_mwait_hints[i]; 646 647 kprintf(" C%d/%d hint 0x%04x\n", 648 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 649 hint); 650 } 651 } 652 653 /* 654 * Deep C-states 655 */ 656 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 657 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 658 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 659 M_DEVBUF, M_WAITOK); 660 661 hint_idx = 0; 662 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 663 int j, subcnt; 664 665 subcnt = cpu_mwait_cx_info[i].subcnt; 666 for (j = 0; j < subcnt; ++j) { 667 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 668 ("invalid mwait deep hint index %d", hint_idx)); 669 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 670 ++hint_idx; 671 } 672 } 673 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 674 ("mwait deep hint count %d != index %d", 675 cpu_mwait_deep_hints_cnt, hint_idx)); 676 677 if (bootverbose) { 678 kprintf("MWAIT deep hints:\n"); 679 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 680 int hint = cpu_mwait_deep_hints[i]; 681 682 kprintf(" C%d/%d hint 0x%04x\n", 683 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 684 hint); 685 } 686 } 687 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 688 689 for (i = 0; i < ncpus; ++i) { 690 char name[16]; 691 692 ksnprintf(name, sizeof(name), "idle%d", i); 693 SYSCTL_ADD_PROC(NULL, 694 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 695 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 696 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 697 } 698 } 699 700 static void 701 cpu_finish(void *dummy __unused) 702 { 703 cpu_setregs(); 704 cpu_mwait_attach(); 705 } 706 707 static void 708 pic_finish(void *dummy __unused) 709 { 710 /* Log ELCR information */ 711 elcr_dump(); 712 713 /* Log MPTABLE information */ 714 mptable_pci_int_dump(); 715 716 /* Finalize PCI */ 717 MachIntrABI.finalize(); 718 } 719 720 /* 721 * Send an interrupt to process. 722 * 723 * Stack is set up to allow sigcode stored 724 * at top to call routine, followed by kcall 725 * to sigreturn routine below. After sigreturn 726 * resets the signal mask, the stack, and the 727 * frame pointer, it returns to the user 728 * specified pc, psl. 729 */ 730 void 731 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 732 { 733 struct lwp *lp = curthread->td_lwp; 734 struct proc *p = lp->lwp_proc; 735 struct trapframe *regs; 736 struct sigacts *psp = p->p_sigacts; 737 struct sigframe sf, *sfp; 738 int oonstack; 739 char *sp; 740 741 regs = lp->lwp_md.md_regs; 742 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 743 744 /* Save user context */ 745 bzero(&sf, sizeof(struct sigframe)); 746 sf.sf_uc.uc_sigmask = *mask; 747 sf.sf_uc.uc_stack = lp->lwp_sigstk; 748 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 749 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 750 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 751 752 /* Make the size of the saved context visible to userland */ 753 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 754 755 /* Allocate and validate space for the signal handler context. */ 756 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 757 SIGISMEMBER(psp->ps_sigonstack, sig)) { 758 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 759 sizeof(struct sigframe)); 760 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 761 } else { 762 /* We take red zone into account */ 763 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 764 } 765 766 /* 767 * XXX AVX needs 64-byte alignment but sigframe has other fields and 768 * the embedded ucontext is not at the front, so aligning this won't 769 * help us. Fortunately we bcopy in/out of the sigframe, so the 770 * kernel is ok. 771 * 772 * The problem though is if userland winds up trying to use the 773 * context directly. 774 */ 775 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 776 777 /* Translate the signal is appropriate */ 778 if (p->p_sysent->sv_sigtbl) { 779 if (sig <= p->p_sysent->sv_sigsize) 780 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 781 } 782 783 /* 784 * Build the argument list for the signal handler. 785 * 786 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 787 */ 788 regs->tf_rdi = sig; /* argument 1 */ 789 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 790 791 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 792 /* 793 * Signal handler installed with SA_SIGINFO. 794 * 795 * action(signo, siginfo, ucontext) 796 */ 797 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 798 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 799 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 800 801 /* fill siginfo structure */ 802 sf.sf_si.si_signo = sig; 803 sf.sf_si.si_code = code; 804 sf.sf_si.si_addr = (void *)regs->tf_addr; 805 } else { 806 /* 807 * Old FreeBSD-style arguments. 808 * 809 * handler (signo, code, [uc], addr) 810 */ 811 regs->tf_rsi = (register_t)code; /* argument 2 */ 812 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 813 sf.sf_ahu.sf_handler = catcher; 814 } 815 816 /* 817 * If we're a vm86 process, we want to save the segment registers. 818 * We also change eflags to be our emulated eflags, not the actual 819 * eflags. 820 */ 821 #if 0 /* JG */ 822 if (regs->tf_eflags & PSL_VM) { 823 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 824 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 825 826 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 827 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 828 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 829 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 830 831 if (vm86->vm86_has_vme == 0) 832 sf.sf_uc.uc_mcontext.mc_eflags = 833 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 834 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 835 836 /* 837 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 838 * syscalls made by the signal handler. This just avoids 839 * wasting time for our lazy fixup of such faults. PSL_NT 840 * does nothing in vm86 mode, but vm86 programs can set it 841 * almost legitimately in probes for old cpu types. 842 */ 843 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 844 } 845 #endif 846 847 /* 848 * Save the FPU state and reinit the FP unit 849 */ 850 npxpush(&sf.sf_uc.uc_mcontext); 851 852 /* 853 * Copy the sigframe out to the user's stack. 854 */ 855 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 856 /* 857 * Something is wrong with the stack pointer. 858 * ...Kill the process. 859 */ 860 sigexit(lp, SIGILL); 861 } 862 863 regs->tf_rsp = (register_t)sfp; 864 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 865 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 866 867 /* 868 * x86 abi specifies that the direction flag must be cleared 869 * on function entry 870 */ 871 regs->tf_rflags &= ~(PSL_T | PSL_D); 872 873 /* 874 * 64 bit mode has a code and stack selector but 875 * no data or extra selector. %fs and %gs are not 876 * stored in-context. 877 */ 878 regs->tf_cs = _ucodesel; 879 regs->tf_ss = _udatasel; 880 clear_quickret(); 881 } 882 883 /* 884 * Sanitize the trapframe for a virtual kernel passing control to a custom 885 * VM context. Remove any items that would otherwise create a privilage 886 * issue. 887 * 888 * XXX at the moment we allow userland to set the resume flag. Is this a 889 * bad idea? 890 */ 891 int 892 cpu_sanitize_frame(struct trapframe *frame) 893 { 894 frame->tf_cs = _ucodesel; 895 frame->tf_ss = _udatasel; 896 /* XXX VM (8086) mode not supported? */ 897 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 898 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 899 900 return(0); 901 } 902 903 /* 904 * Sanitize the tls so loading the descriptor does not blow up 905 * on us. For x86_64 we don't have to do anything. 906 */ 907 int 908 cpu_sanitize_tls(struct savetls *tls) 909 { 910 return(0); 911 } 912 913 /* 914 * sigreturn(ucontext_t *sigcntxp) 915 * 916 * System call to cleanup state after a signal 917 * has been taken. Reset signal mask and 918 * stack state from context left by sendsig (above). 919 * Return to previous pc and psl as specified by 920 * context left by sendsig. Check carefully to 921 * make sure that the user has not modified the 922 * state to gain improper privileges. 923 * 924 * MPSAFE 925 */ 926 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 927 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 928 929 int 930 sys_sigreturn(struct sigreturn_args *uap) 931 { 932 struct lwp *lp = curthread->td_lwp; 933 struct trapframe *regs; 934 ucontext_t uc; 935 ucontext_t *ucp; 936 register_t rflags; 937 int cs; 938 int error; 939 940 /* 941 * We have to copy the information into kernel space so userland 942 * can't modify it while we are sniffing it. 943 */ 944 regs = lp->lwp_md.md_regs; 945 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 946 if (error) 947 return (error); 948 ucp = &uc; 949 rflags = ucp->uc_mcontext.mc_rflags; 950 951 /* VM (8086) mode not supported */ 952 rflags &= ~PSL_VM_UNSUPP; 953 954 #if 0 /* JG */ 955 if (eflags & PSL_VM) { 956 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 957 struct vm86_kernel *vm86; 958 959 /* 960 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 961 * set up the vm86 area, and we can't enter vm86 mode. 962 */ 963 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 964 return (EINVAL); 965 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 966 if (vm86->vm86_inited == 0) 967 return (EINVAL); 968 969 /* go back to user mode if both flags are set */ 970 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 971 trapsignal(lp, SIGBUS, 0); 972 973 if (vm86->vm86_has_vme) { 974 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 975 (eflags & VME_USERCHANGE) | PSL_VM; 976 } else { 977 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 978 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 979 (eflags & VM_USERCHANGE) | PSL_VM; 980 } 981 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 982 tf->tf_eflags = eflags; 983 tf->tf_vm86_ds = tf->tf_ds; 984 tf->tf_vm86_es = tf->tf_es; 985 tf->tf_vm86_fs = tf->tf_fs; 986 tf->tf_vm86_gs = tf->tf_gs; 987 tf->tf_ds = _udatasel; 988 tf->tf_es = _udatasel; 989 tf->tf_fs = _udatasel; 990 tf->tf_gs = _udatasel; 991 } else 992 #endif 993 { 994 /* 995 * Don't allow users to change privileged or reserved flags. 996 */ 997 /* 998 * XXX do allow users to change the privileged flag PSL_RF. 999 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 1000 * should sometimes set it there too. tf_eflags is kept in 1001 * the signal context during signal handling and there is no 1002 * other place to remember it, so the PSL_RF bit may be 1003 * corrupted by the signal handler without us knowing. 1004 * Corruption of the PSL_RF bit at worst causes one more or 1005 * one less debugger trap, so allowing it is fairly harmless. 1006 */ 1007 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 1008 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 1009 return(EINVAL); 1010 } 1011 1012 /* 1013 * Don't allow users to load a valid privileged %cs. Let the 1014 * hardware check for invalid selectors, excess privilege in 1015 * other selectors, invalid %eip's and invalid %esp's. 1016 */ 1017 cs = ucp->uc_mcontext.mc_cs; 1018 if (!CS_SECURE(cs)) { 1019 kprintf("sigreturn: cs = 0x%x\n", cs); 1020 trapsignal(lp, SIGBUS, T_PROTFLT); 1021 return(EINVAL); 1022 } 1023 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1024 } 1025 1026 /* 1027 * Restore the FPU state from the frame 1028 */ 1029 crit_enter(); 1030 npxpop(&ucp->uc_mcontext); 1031 1032 if (ucp->uc_mcontext.mc_onstack & 1) 1033 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1034 else 1035 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1036 1037 lp->lwp_sigmask = ucp->uc_sigmask; 1038 SIG_CANTMASK(lp->lwp_sigmask); 1039 clear_quickret(); 1040 crit_exit(); 1041 return(EJUSTRETURN); 1042 } 1043 1044 /* 1045 * Machine dependent boot() routine 1046 * 1047 * I haven't seen anything to put here yet 1048 * Possibly some stuff might be grafted back here from boot() 1049 */ 1050 void 1051 cpu_boot(int howto) 1052 { 1053 } 1054 1055 /* 1056 * Shutdown the CPU as much as possible 1057 */ 1058 void 1059 cpu_halt(void) 1060 { 1061 for (;;) 1062 __asm__ __volatile("hlt"); 1063 } 1064 1065 /* 1066 * cpu_idle() represents the idle LWKT. You cannot return from this function 1067 * (unless you want to blow things up!). Instead we look for runnable threads 1068 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1069 * 1070 * The main loop is entered with a critical section held, we must release 1071 * the critical section before doing anything else. lwkt_switch() will 1072 * check for pending interrupts due to entering and exiting its own 1073 * critical section. 1074 * 1075 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1076 * However, there are cases where the idlethread will be entered with 1077 * the possibility that no IPI will occur and in such cases 1078 * lwkt_switch() sets TDF_IDLE_NOHLT. 1079 * 1080 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1081 * must occur before it starts using ACPI halt. 1082 * 1083 * NOTE: Value overridden in hammer_time(). 1084 */ 1085 static int cpu_idle_hlt = 2; 1086 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1087 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1088 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1089 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1090 1091 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1092 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1093 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1094 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1095 1096 static void 1097 cpu_idle_default_hook(void) 1098 { 1099 /* 1100 * We must guarentee that hlt is exactly the instruction 1101 * following the sti. 1102 */ 1103 __asm __volatile("sti; hlt"); 1104 } 1105 1106 /* Other subsystems (e.g., ACPI) can hook this later. */ 1107 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1108 1109 static __inline int 1110 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1111 { 1112 int hint, cx_idx; 1113 u_int idx; 1114 1115 hint = stat->hint; 1116 if (hint >= 0) 1117 goto done; 1118 1119 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1120 cpu_mwait_repeat_shift; 1121 if (idx >= cpu_mwait_c1_hints_cnt) { 1122 /* Step up faster, once we walked through all C1 states */ 1123 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1124 } 1125 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1126 if (idx >= cpu_mwait_deep_hints_cnt) 1127 idx = cpu_mwait_deep_hints_cnt - 1; 1128 hint = cpu_mwait_deep_hints[idx]; 1129 } else { 1130 if (idx >= cpu_mwait_hints_cnt) 1131 idx = cpu_mwait_hints_cnt - 1; 1132 hint = cpu_mwait_hints[idx]; 1133 } 1134 done: 1135 cx_idx = MWAIT_EAX_TO_CX(hint); 1136 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1137 stat->mwait_cx[cx_idx]++; 1138 return hint; 1139 } 1140 1141 void 1142 cpu_idle(void) 1143 { 1144 globaldata_t gd = mycpu; 1145 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1146 struct thread *td __debugvar = gd->gd_curthread; 1147 int reqflags; 1148 int quick; 1149 1150 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1151 1152 crit_exit(); 1153 KKASSERT(td->td_critcount == 0); 1154 1155 for (;;) { 1156 /* 1157 * See if there are any LWKTs ready to go. 1158 */ 1159 lwkt_switch(); 1160 1161 /* 1162 * When halting inside a cli we must check for reqflags 1163 * races, particularly [re]schedule requests. Running 1164 * splz() does the job. 1165 * 1166 * cpu_idle_hlt: 1167 * 0 Never halt, just spin 1168 * 1169 * 1 Always use MONITOR/MWAIT if avail, HLT 1170 * otherwise. 1171 * 1172 * Better default for modern (Haswell+) Intel 1173 * cpus. 1174 * 1175 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1176 * use the ACPI halt (default). This is a hybrid 1177 * approach. See machdep.cpu_idle_repeat. 1178 * 1179 * Better default for modern AMD cpus and older 1180 * Intel cpus. 1181 * 1182 * 3 Always use the ACPI halt. This typically 1183 * eats the least amount of power but the cpu 1184 * will be slow waking up. Slows down e.g. 1185 * compiles and other pipe/event oriented stuff. 1186 * 1187 * Usually the best default for AMD cpus. 1188 * 1189 * 4 Always use HLT. 1190 * 1191 * 5 Always spin. 1192 * 1193 * NOTE: Interrupts are enabled and we are not in a critical 1194 * section. 1195 * 1196 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1197 * don't bother capping gd_idle_repeat, it is ok if 1198 * it overflows. 1199 * 1200 * Implement optimized invltlb operations when halted 1201 * in idle. By setting the bit in smp_idleinvl_mask 1202 * we inform other cpus that they can set _reqs to 1203 * request an invltlb. Current the code to do that 1204 * sets the bits in _reqs anyway, but then check _mask 1205 * to determine if they can assume the invltlb will execute. 1206 * 1207 * A critical section is required to ensure that interrupts 1208 * do not fully run until after we've had a chance to execute 1209 * the request. 1210 */ 1211 if (gd->gd_idle_repeat == 0) { 1212 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1213 if (stat->repeat > cpu_idle_repeat_max) 1214 stat->repeat = cpu_idle_repeat_max; 1215 stat->repeat_last = 0; 1216 stat->repeat_delta = 0; 1217 } 1218 ++stat->repeat_last; 1219 1220 /* 1221 * General idle thread halt code 1222 * 1223 * IBRS NOTES - IBRS is a SPECTRE mitigation. When going 1224 * idle, IBRS 1225 */ 1226 ++gd->gd_idle_repeat; 1227 reqflags = gd->gd_reqflags; 1228 quick = (cpu_idle_hlt == 1) || 1229 (cpu_idle_hlt == 2 && 1230 gd->gd_idle_repeat < cpu_idle_repeat); 1231 1232 1233 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1234 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1235 /* 1236 * MWAIT halt 1237 */ 1238 splz(); /* XXX */ 1239 crit_enter_gd(gd); 1240 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1241 if (pscpu->trampoline.tr_pcb_gflags & 1242 (PCB_IBRS1 | PCB_IBRS2)) { 1243 wrmsr(0x48, 0); /* IBRS (spectre) */ 1244 } 1245 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1246 cpu_mwait_cx_hint(stat), 0); 1247 if (pscpu->trampoline.tr_pcb_gflags & 1248 (PCB_IBRS1 | PCB_IBRS2)) { 1249 wrmsr(0x48, 1); /* IBRS (spectre) */ 1250 } 1251 stat->halt++; 1252 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1253 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1254 gd->gd_cpuid)) { 1255 cpu_invltlb(); 1256 cpu_mfence(); 1257 } 1258 crit_exit_gd(gd); 1259 } else if (cpu_idle_hlt) { 1260 /* 1261 * Idle halt 1262 */ 1263 __asm __volatile("cli"); 1264 splz(); 1265 crit_enter_gd(gd); 1266 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1267 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1268 if (cpu_idle_hlt == 5) { 1269 __asm __volatile("sti"); 1270 } else if (quick || cpu_idle_hlt == 4) { 1271 if (pscpu->trampoline.tr_pcb_gflags & 1272 (PCB_IBRS1 | PCB_IBRS2)) { 1273 /* IBRS (spectre) */ 1274 wrmsr(0x48, 0); 1275 } 1276 cpu_idle_default_hook(); 1277 if (pscpu->trampoline.tr_pcb_gflags & 1278 (PCB_IBRS1 | PCB_IBRS2)) { 1279 /* IBRS (spectre) */ 1280 wrmsr(0x48, 1); 1281 } 1282 } else { 1283 if (pscpu->trampoline.tr_pcb_gflags & 1284 (PCB_IBRS1 | PCB_IBRS2)) { 1285 wrmsr(0x48, 0); 1286 } 1287 cpu_idle_hook(); 1288 if (pscpu->trampoline.tr_pcb_gflags & 1289 (PCB_IBRS1 | PCB_IBRS2)) { 1290 wrmsr(0x48, 1); 1291 } 1292 } 1293 } 1294 __asm __volatile("sti"); 1295 stat->halt++; 1296 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1297 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1298 gd->gd_cpuid)) { 1299 cpu_invltlb(); 1300 cpu_mfence(); 1301 } 1302 crit_exit_gd(gd); 1303 } else { 1304 splz(); 1305 __asm __volatile("sti"); 1306 stat->spin++; 1307 crit_enter_gd(gd); 1308 crit_exit_gd(gd); 1309 } 1310 } 1311 } 1312 1313 /* 1314 * Called in a loop indirectly via Xcpustop 1315 */ 1316 void 1317 cpu_smp_stopped(void) 1318 { 1319 globaldata_t gd = mycpu; 1320 volatile __uint64_t *ptr; 1321 __uint64_t ovalue; 1322 1323 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1324 ovalue = *ptr; 1325 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1326 if (cpu_mi_feature & CPU_MI_MONITOR) { 1327 if (cpu_mwait_hints) { 1328 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1329 ovalue, 1330 cpu_mwait_hints[CPU_MWAIT_C1], 0); 1331 } else { 1332 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1333 ovalue, 0, 0); 1334 } 1335 } else { 1336 cpu_halt(); /* depend on lapic timer */ 1337 } 1338 } 1339 } 1340 1341 /* 1342 * This routine is called if a spinlock has been held through the 1343 * exponential backoff period and is seriously contested. On a real cpu 1344 * we let it spin. 1345 */ 1346 void 1347 cpu_spinlock_contested(void) 1348 { 1349 cpu_pause(); 1350 } 1351 1352 /* 1353 * Clear registers on exec 1354 */ 1355 void 1356 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1357 { 1358 struct thread *td = curthread; 1359 struct lwp *lp = td->td_lwp; 1360 struct pcb *pcb = td->td_pcb; 1361 struct trapframe *regs = lp->lwp_md.md_regs; 1362 1363 user_ldt_free(pcb); 1364 1365 clear_quickret(); 1366 bzero((char *)regs, sizeof(struct trapframe)); 1367 regs->tf_rip = entry; 1368 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1369 regs->tf_rdi = stack; /* argv */ 1370 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1371 regs->tf_ss = _udatasel; 1372 regs->tf_cs = _ucodesel; 1373 regs->tf_rbx = ps_strings; 1374 1375 /* 1376 * Reset the hardware debug registers if they were in use. 1377 * They won't have any meaning for the newly exec'd process. 1378 */ 1379 if (pcb->pcb_flags & PCB_DBREGS) { 1380 pcb->pcb_dr0 = 0; 1381 pcb->pcb_dr1 = 0; 1382 pcb->pcb_dr2 = 0; 1383 pcb->pcb_dr3 = 0; 1384 pcb->pcb_dr6 = 0; 1385 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1386 if (pcb == td->td_pcb) { 1387 /* 1388 * Clear the debug registers on the running 1389 * CPU, otherwise they will end up affecting 1390 * the next process we switch to. 1391 */ 1392 reset_dbregs(); 1393 } 1394 pcb->pcb_flags &= ~PCB_DBREGS; 1395 } 1396 1397 /* 1398 * Initialize the math emulator (if any) for the current process. 1399 * Actually, just clear the bit that says that the emulator has 1400 * been initialized. Initialization is delayed until the process 1401 * traps to the emulator (if it is done at all) mainly because 1402 * emulators don't provide an entry point for initialization. 1403 */ 1404 pcb->pcb_flags &= ~FP_SOFTFP; 1405 1406 /* 1407 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1408 * gd_npxthread. Otherwise a preemptive interrupt thread 1409 * may panic in npxdna(). 1410 */ 1411 crit_enter(); 1412 load_cr0(rcr0() | CR0_MP); 1413 1414 /* 1415 * NOTE: The MSR values must be correct so we can return to 1416 * userland. gd_user_fs/gs must be correct so the switch 1417 * code knows what the current MSR values are. 1418 */ 1419 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1420 pcb->pcb_gsbase = 0; 1421 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1422 mdcpu->gd_user_gs = 0; 1423 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1424 wrmsr(MSR_KGSBASE, 0); 1425 1426 /* Initialize the npx (if any) for the current process. */ 1427 npxinit(); 1428 crit_exit(); 1429 1430 pcb->pcb_ds = _udatasel; 1431 pcb->pcb_es = _udatasel; 1432 pcb->pcb_fs = _udatasel; 1433 pcb->pcb_gs = _udatasel; 1434 } 1435 1436 void 1437 cpu_setregs(void) 1438 { 1439 register_t cr0; 1440 1441 cr0 = rcr0(); 1442 cr0 |= CR0_NE; /* Done by npxinit() */ 1443 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1444 cr0 |= CR0_WP | CR0_AM; 1445 load_cr0(cr0); 1446 load_gs(_udatasel); 1447 } 1448 1449 static int 1450 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1451 { 1452 int error; 1453 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1454 req); 1455 if (!error && req->newptr) 1456 resettodr(); 1457 return (error); 1458 } 1459 1460 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1461 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1462 1463 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1464 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1465 1466 #if 0 /* JG */ 1467 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1468 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1469 #endif 1470 1471 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1472 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1473 1474 static int 1475 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1476 { 1477 struct efi_map_header *efihdr; 1478 caddr_t kmdp; 1479 uint32_t efisize; 1480 1481 kmdp = preload_search_by_type("elf kernel"); 1482 if (kmdp == NULL) 1483 kmdp = preload_search_by_type("elf64 kernel"); 1484 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1485 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1486 if (efihdr == NULL) 1487 return (0); 1488 efisize = *((uint32_t *)efihdr - 1); 1489 return (SYSCTL_OUT(req, efihdr, efisize)); 1490 } 1491 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1492 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1493 1494 /* 1495 * Initialize x86 and configure to run kernel 1496 */ 1497 1498 /* 1499 * Initialize segments & interrupt table 1500 */ 1501 1502 int _default_ldt; 1503 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1504 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1505 #if 0 /* JG */ 1506 union descriptor ldt[NLDT]; /* local descriptor table */ 1507 #endif 1508 1509 /* table descriptors - used to load tables by cpu */ 1510 struct region_descriptor r_gdt; 1511 struct region_descriptor r_idt_arr[MAXCPU]; 1512 1513 /* JG proc0paddr is a virtual address */ 1514 void *proc0paddr; 1515 /* JG alignment? */ 1516 char proc0paddr_buff[LWKT_THREAD_STACK]; 1517 1518 1519 /* software prototypes -- in more palatable form */ 1520 struct soft_segment_descriptor gdt_segs[] = { 1521 /* GNULL_SEL 0 Null Descriptor */ 1522 { 0x0, /* segment base address */ 1523 0x0, /* length */ 1524 0, /* segment type */ 1525 0, /* segment descriptor priority level */ 1526 0, /* segment descriptor present */ 1527 0, /* long */ 1528 0, /* default 32 vs 16 bit size */ 1529 0 /* limit granularity (byte/page units)*/ }, 1530 /* GCODE_SEL 1 Code Descriptor for kernel */ 1531 { 0x0, /* segment base address */ 1532 0xfffff, /* length - all address space */ 1533 SDT_MEMERA, /* segment type */ 1534 SEL_KPL, /* segment descriptor priority level */ 1535 1, /* segment descriptor present */ 1536 1, /* long */ 1537 0, /* default 32 vs 16 bit size */ 1538 1 /* limit granularity (byte/page units)*/ }, 1539 /* GDATA_SEL 2 Data Descriptor for kernel */ 1540 { 0x0, /* segment base address */ 1541 0xfffff, /* length - all address space */ 1542 SDT_MEMRWA, /* segment type */ 1543 SEL_KPL, /* segment descriptor priority level */ 1544 1, /* segment descriptor present */ 1545 1, /* long */ 1546 0, /* default 32 vs 16 bit size */ 1547 1 /* limit granularity (byte/page units)*/ }, 1548 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1549 { 0x0, /* segment base address */ 1550 0xfffff, /* length - all address space */ 1551 SDT_MEMERA, /* segment type */ 1552 SEL_UPL, /* segment descriptor priority level */ 1553 1, /* segment descriptor present */ 1554 0, /* long */ 1555 1, /* default 32 vs 16 bit size */ 1556 1 /* limit granularity (byte/page units)*/ }, 1557 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1558 { 0x0, /* segment base address */ 1559 0xfffff, /* length - all address space */ 1560 SDT_MEMRWA, /* segment type */ 1561 SEL_UPL, /* segment descriptor priority level */ 1562 1, /* segment descriptor present */ 1563 0, /* long */ 1564 1, /* default 32 vs 16 bit size */ 1565 1 /* limit granularity (byte/page units)*/ }, 1566 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1567 { 0x0, /* segment base address */ 1568 0xfffff, /* length - all address space */ 1569 SDT_MEMERA, /* segment type */ 1570 SEL_UPL, /* segment descriptor priority level */ 1571 1, /* segment descriptor present */ 1572 1, /* long */ 1573 0, /* default 32 vs 16 bit size */ 1574 1 /* limit granularity (byte/page units)*/ }, 1575 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1576 { 1577 0x0, /* segment base address */ 1578 sizeof(struct x86_64tss)-1,/* length - all address space */ 1579 SDT_SYSTSS, /* segment type */ 1580 SEL_KPL, /* segment descriptor priority level */ 1581 1, /* segment descriptor present */ 1582 0, /* long */ 1583 0, /* unused - default 32 vs 16 bit size */ 1584 0 /* limit granularity (byte/page units)*/ }, 1585 /* Actually, the TSS is a system descriptor which is double size */ 1586 { 0x0, /* segment base address */ 1587 0x0, /* length */ 1588 0, /* segment type */ 1589 0, /* segment descriptor priority level */ 1590 0, /* segment descriptor present */ 1591 0, /* long */ 1592 0, /* default 32 vs 16 bit size */ 1593 0 /* limit granularity (byte/page units)*/ }, 1594 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1595 { 0x0, /* segment base address */ 1596 0xfffff, /* length - all address space */ 1597 SDT_MEMRWA, /* segment type */ 1598 SEL_UPL, /* segment descriptor priority level */ 1599 1, /* segment descriptor present */ 1600 0, /* long */ 1601 1, /* default 32 vs 16 bit size */ 1602 1 /* limit granularity (byte/page units)*/ }, 1603 }; 1604 1605 void 1606 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1607 { 1608 int cpu; 1609 1610 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1611 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1612 1613 ip->gd_looffset = (uintptr_t)func; 1614 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1615 ip->gd_ist = ist; 1616 ip->gd_xx = 0; 1617 ip->gd_type = typ; 1618 ip->gd_dpl = dpl; 1619 ip->gd_p = 1; 1620 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1621 } 1622 } 1623 1624 void 1625 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1626 { 1627 struct gate_descriptor *ip; 1628 1629 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1630 1631 ip = &idt_arr[cpu][idx]; 1632 ip->gd_looffset = (uintptr_t)func; 1633 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1634 ip->gd_ist = ist; 1635 ip->gd_xx = 0; 1636 ip->gd_type = typ; 1637 ip->gd_dpl = dpl; 1638 ip->gd_p = 1; 1639 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1640 } 1641 1642 #define IDTVEC(name) __CONCAT(X,name) 1643 1644 extern inthand_t 1645 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1646 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1647 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1648 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1649 IDTVEC(xmm), IDTVEC(dblfault), 1650 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1651 1652 void 1653 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1654 { 1655 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1656 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1657 ssd->ssd_type = sd->sd_type; 1658 ssd->ssd_dpl = sd->sd_dpl; 1659 ssd->ssd_p = sd->sd_p; 1660 ssd->ssd_def32 = sd->sd_def32; 1661 ssd->ssd_gran = sd->sd_gran; 1662 } 1663 1664 void 1665 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1666 { 1667 1668 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1669 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1670 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1671 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1672 sd->sd_type = ssd->ssd_type; 1673 sd->sd_dpl = ssd->ssd_dpl; 1674 sd->sd_p = ssd->ssd_p; 1675 sd->sd_long = ssd->ssd_long; 1676 sd->sd_def32 = ssd->ssd_def32; 1677 sd->sd_gran = ssd->ssd_gran; 1678 } 1679 1680 void 1681 ssdtosyssd(struct soft_segment_descriptor *ssd, 1682 struct system_segment_descriptor *sd) 1683 { 1684 1685 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1686 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1687 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1688 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1689 sd->sd_type = ssd->ssd_type; 1690 sd->sd_dpl = ssd->ssd_dpl; 1691 sd->sd_p = ssd->ssd_p; 1692 sd->sd_gran = ssd->ssd_gran; 1693 } 1694 1695 /* 1696 * Populate the (physmap) array with base/bound pairs describing the 1697 * available physical memory in the system, then test this memory and 1698 * build the phys_avail array describing the actually-available memory. 1699 * 1700 * If we cannot accurately determine the physical memory map, then use 1701 * value from the 0xE801 call, and failing that, the RTC. 1702 * 1703 * Total memory size may be set by the kernel environment variable 1704 * hw.physmem or the compile-time define MAXMEM. 1705 * 1706 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1707 * of PAGE_SIZE. This also greatly reduces the memory test time 1708 * which would otherwise be excessive on machines with > 8G of ram. 1709 * 1710 * XXX first should be vm_paddr_t. 1711 */ 1712 1713 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1714 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1715 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1716 1717 vm_paddr_t physmap[PHYSMAP_SIZE]; 1718 struct bios_smap *smapbase, *smap, *smapend; 1719 struct efi_map_header *efihdrbase; 1720 u_int32_t smapsize; 1721 1722 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1723 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1724 1725 static void 1726 add_smap_entries(int *physmap_idx) 1727 { 1728 int i; 1729 1730 smapsize = *((u_int32_t *)smapbase - 1); 1731 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1732 1733 for (smap = smapbase; smap < smapend; smap++) { 1734 if (boothowto & RB_VERBOSE) 1735 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1736 smap->type, smap->base, smap->length); 1737 1738 if (smap->type != SMAP_TYPE_MEMORY) 1739 continue; 1740 1741 if (smap->length == 0) 1742 continue; 1743 1744 for (i = 0; i <= *physmap_idx; i += 2) { 1745 if (smap->base < physmap[i + 1]) { 1746 if (boothowto & RB_VERBOSE) { 1747 kprintf("Overlapping or non-monotonic " 1748 "memory region, ignoring " 1749 "second region\n"); 1750 } 1751 break; 1752 } 1753 } 1754 if (i <= *physmap_idx) 1755 continue; 1756 1757 Realmem += smap->length; 1758 1759 if (smap->base == physmap[*physmap_idx + 1]) { 1760 physmap[*physmap_idx + 1] += smap->length; 1761 continue; 1762 } 1763 1764 *physmap_idx += 2; 1765 if (*physmap_idx == PHYSMAP_SIZE) { 1766 kprintf("Too many segments in the physical " 1767 "address map, giving up\n"); 1768 break; 1769 } 1770 physmap[*physmap_idx] = smap->base; 1771 physmap[*physmap_idx + 1] = smap->base + smap->length; 1772 } 1773 } 1774 1775 static void 1776 add_efi_map_entries(int *physmap_idx) 1777 { 1778 struct efi_md *map, *p; 1779 const char *type; 1780 size_t efisz; 1781 int i, ndesc; 1782 1783 static const char *types[] = { 1784 "Reserved", 1785 "LoaderCode", 1786 "LoaderData", 1787 "BootServicesCode", 1788 "BootServicesData", 1789 "RuntimeServicesCode", 1790 "RuntimeServicesData", 1791 "ConventionalMemory", 1792 "UnusableMemory", 1793 "ACPIReclaimMemory", 1794 "ACPIMemoryNVS", 1795 "MemoryMappedIO", 1796 "MemoryMappedIOPortSpace", 1797 "PalCode" 1798 }; 1799 1800 /* 1801 * Memory map data provided by UEFI via the GetMemoryMap 1802 * Boot Services API. 1803 */ 1804 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1805 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1806 1807 if (efihdrbase->descriptor_size == 0) 1808 return; 1809 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1810 1811 if (boothowto & RB_VERBOSE) 1812 kprintf("%23s %12s %12s %8s %4s\n", 1813 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1814 1815 for (i = 0, p = map; i < ndesc; i++, 1816 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1817 if (boothowto & RB_VERBOSE) { 1818 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1819 type = types[p->md_type]; 1820 else 1821 type = "<INVALID>"; 1822 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1823 p->md_virt, p->md_pages); 1824 if (p->md_attr & EFI_MD_ATTR_UC) 1825 kprintf("UC "); 1826 if (p->md_attr & EFI_MD_ATTR_WC) 1827 kprintf("WC "); 1828 if (p->md_attr & EFI_MD_ATTR_WT) 1829 kprintf("WT "); 1830 if (p->md_attr & EFI_MD_ATTR_WB) 1831 kprintf("WB "); 1832 if (p->md_attr & EFI_MD_ATTR_UCE) 1833 kprintf("UCE "); 1834 if (p->md_attr & EFI_MD_ATTR_WP) 1835 kprintf("WP "); 1836 if (p->md_attr & EFI_MD_ATTR_RP) 1837 kprintf("RP "); 1838 if (p->md_attr & EFI_MD_ATTR_XP) 1839 kprintf("XP "); 1840 if (p->md_attr & EFI_MD_ATTR_RT) 1841 kprintf("RUNTIME"); 1842 kprintf("\n"); 1843 } 1844 1845 switch (p->md_type) { 1846 case EFI_MD_TYPE_CODE: 1847 case EFI_MD_TYPE_DATA: 1848 case EFI_MD_TYPE_BS_CODE: 1849 case EFI_MD_TYPE_BS_DATA: 1850 case EFI_MD_TYPE_FREE: 1851 /* 1852 * We're allowed to use any entry with these types. 1853 */ 1854 break; 1855 default: 1856 continue; 1857 } 1858 1859 Realmem += p->md_pages * PAGE_SIZE; 1860 1861 if (p->md_phys == physmap[*physmap_idx + 1]) { 1862 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1863 continue; 1864 } 1865 1866 *physmap_idx += 2; 1867 if (*physmap_idx == PHYSMAP_SIZE) { 1868 kprintf("Too many segments in the physical " 1869 "address map, giving up\n"); 1870 break; 1871 } 1872 physmap[*physmap_idx] = p->md_phys; 1873 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1874 } 1875 } 1876 1877 struct fb_info efi_fb_info; 1878 static int have_efi_framebuffer = 0; 1879 1880 static void 1881 efi_fb_init_vaddr(int direct_map) 1882 { 1883 uint64_t sz; 1884 vm_offset_t addr, v; 1885 1886 v = efi_fb_info.vaddr; 1887 sz = efi_fb_info.stride * efi_fb_info.height; 1888 1889 if (direct_map) { 1890 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1891 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1892 efi_fb_info.vaddr = addr; 1893 } else { 1894 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1895 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1896 } 1897 } 1898 1899 static u_int 1900 efifb_color_depth(struct efi_fb *efifb) 1901 { 1902 uint32_t mask; 1903 u_int depth; 1904 1905 mask = efifb->fb_mask_red | efifb->fb_mask_green | 1906 efifb->fb_mask_blue | efifb->fb_mask_reserved; 1907 if (mask == 0) 1908 return (0); 1909 for (depth = 1; mask != 1; depth++) 1910 mask >>= 1; 1911 return (depth); 1912 } 1913 1914 int 1915 probe_efi_fb(int early) 1916 { 1917 struct efi_fb *efifb; 1918 caddr_t kmdp; 1919 u_int depth; 1920 1921 if (have_efi_framebuffer) { 1922 if (!early && 1923 (efi_fb_info.vaddr == 0 || 1924 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 1925 efi_fb_init_vaddr(0); 1926 return 0; 1927 } 1928 1929 kmdp = preload_search_by_type("elf kernel"); 1930 if (kmdp == NULL) 1931 kmdp = preload_search_by_type("elf64 kernel"); 1932 efifb = (struct efi_fb *)preload_search_info(kmdp, 1933 MODINFO_METADATA | MODINFOMD_EFI_FB); 1934 if (efifb == NULL) 1935 return 1; 1936 1937 depth = efifb_color_depth(efifb); 1938 /* 1939 * Our bootloader should already notice, when we won't be able to 1940 * use the UEFI framebuffer. 1941 */ 1942 if (depth != 24 && depth != 32) 1943 return 1; 1944 1945 have_efi_framebuffer = 1; 1946 1947 efi_fb_info.is_vga_boot_display = 1; 1948 efi_fb_info.width = efifb->fb_width; 1949 efi_fb_info.height = efifb->fb_height; 1950 efi_fb_info.depth = depth; 1951 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 1952 efi_fb_info.paddr = efifb->fb_addr; 1953 if (early) { 1954 efi_fb_info.vaddr = 0; 1955 } else { 1956 efi_fb_init_vaddr(0); 1957 } 1958 efi_fb_info.fbops.fb_set_par = NULL; 1959 efi_fb_info.fbops.fb_blank = NULL; 1960 efi_fb_info.fbops.fb_debug_enter = NULL; 1961 efi_fb_info.device = NULL; 1962 1963 return 0; 1964 } 1965 1966 static void 1967 efifb_startup(void *arg) 1968 { 1969 probe_efi_fb(0); 1970 } 1971 1972 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 1973 1974 static void 1975 getmemsize(caddr_t kmdp, u_int64_t first) 1976 { 1977 int off, physmap_idx, pa_indx, da_indx; 1978 int i, j; 1979 vm_paddr_t pa; 1980 vm_paddr_t msgbuf_size; 1981 u_long physmem_tunable; 1982 pt_entry_t *pte; 1983 quad_t dcons_addr, dcons_size; 1984 1985 bzero(physmap, sizeof(physmap)); 1986 physmap_idx = 0; 1987 1988 /* 1989 * get memory map from INT 15:E820, kindly supplied by the loader. 1990 * 1991 * subr_module.c says: 1992 * "Consumer may safely assume that size value precedes data." 1993 * ie: an int32_t immediately precedes smap. 1994 */ 1995 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 1996 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1997 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1998 MODINFO_METADATA | MODINFOMD_SMAP); 1999 if (smapbase == NULL && efihdrbase == NULL) 2000 panic("No BIOS smap or EFI map info from loader!"); 2001 2002 if (efihdrbase == NULL) 2003 add_smap_entries(&physmap_idx); 2004 else 2005 add_efi_map_entries(&physmap_idx); 2006 2007 base_memory = physmap[1] / 1024; 2008 /* make hole for AP bootstrap code */ 2009 physmap[1] = mp_bootaddress(base_memory); 2010 2011 /* Save EBDA address, if any */ 2012 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 2013 ebda_addr <<= 4; 2014 2015 /* 2016 * Maxmem isn't the "maximum memory", it's one larger than the 2017 * highest page of the physical address space. It should be 2018 * called something like "Maxphyspage". We may adjust this 2019 * based on ``hw.physmem'' and the results of the memory test. 2020 */ 2021 Maxmem = atop(physmap[physmap_idx + 1]); 2022 2023 #ifdef MAXMEM 2024 Maxmem = MAXMEM / 4; 2025 #endif 2026 2027 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 2028 Maxmem = atop(physmem_tunable); 2029 2030 /* 2031 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 2032 * in the system. 2033 */ 2034 if (Maxmem > atop(physmap[physmap_idx + 1])) 2035 Maxmem = atop(physmap[physmap_idx + 1]); 2036 2037 /* 2038 * Blowing out the DMAP will blow up the system. 2039 */ 2040 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 2041 kprintf("Limiting Maxmem due to DMAP size\n"); 2042 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 2043 } 2044 2045 if (atop(physmap[physmap_idx + 1]) != Maxmem && 2046 (boothowto & RB_VERBOSE)) { 2047 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 2048 } 2049 2050 /* 2051 * Call pmap initialization to make new kernel address space 2052 * 2053 * Mask off page 0. 2054 */ 2055 pmap_bootstrap(&first); 2056 physmap[0] = PAGE_SIZE; 2057 2058 /* 2059 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2060 * exceeding Maxmem. 2061 */ 2062 for (i = j = 0; i <= physmap_idx; i += 2) { 2063 if (physmap[i+1] > ptoa(Maxmem)) 2064 physmap[i+1] = ptoa(Maxmem); 2065 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2066 ~PHYSMAP_ALIGN_MASK; 2067 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2068 2069 physmap[j] = physmap[i]; 2070 physmap[j+1] = physmap[i+1]; 2071 2072 if (physmap[i] < physmap[i+1]) 2073 j += 2; 2074 } 2075 physmap_idx = j - 2; 2076 2077 /* 2078 * Align anything else used in the validation loop. 2079 * 2080 * Also make sure that our 2MB kernel text+data+bss mappings 2081 * do not overlap potentially allocatable space. 2082 */ 2083 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2084 2085 /* 2086 * Size up each available chunk of physical memory. 2087 */ 2088 pa_indx = 0; 2089 da_indx = 0; 2090 phys_avail[pa_indx].phys_beg = physmap[0]; 2091 phys_avail[pa_indx].phys_end = physmap[0]; 2092 dump_avail[da_indx].phys_beg = 0; 2093 dump_avail[da_indx].phys_end = physmap[0]; 2094 pte = CMAP1; 2095 2096 /* 2097 * Get dcons buffer address 2098 */ 2099 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2100 kgetenv_quad("dcons.size", &dcons_size) == 0) 2101 dcons_addr = 0; 2102 2103 /* 2104 * Validate the physical memory. The physical memory segments 2105 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2106 * of PAGE_SIZE. 2107 * 2108 * We no longer perform an exhaustive memory test. Instead we 2109 * simply test the first and last word in each physmap[] 2110 * segment. 2111 */ 2112 for (i = 0; i <= physmap_idx; i += 2) { 2113 vm_paddr_t end; 2114 vm_paddr_t incr; 2115 2116 end = physmap[i + 1]; 2117 2118 for (pa = physmap[i]; pa < end; pa += incr) { 2119 int page_bad, full; 2120 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2121 uint64_t tmp; 2122 2123 full = FALSE; 2124 2125 /* 2126 * Calculate incr. Just test the first and 2127 * last page in each physmap[] segment. 2128 */ 2129 if (pa == end - PAGE_SIZE) 2130 incr = PAGE_SIZE; 2131 else 2132 incr = end - pa - PAGE_SIZE; 2133 2134 /* 2135 * Make sure we don't skip blacked out areas. 2136 */ 2137 if (pa < 0x200000 && 0x200000 < end) { 2138 incr = 0x200000 - pa; 2139 } 2140 if (dcons_addr > 0 && 2141 pa < dcons_addr && 2142 dcons_addr < end) { 2143 incr = dcons_addr - pa; 2144 } 2145 2146 /* 2147 * Block out kernel memory as not available. 2148 */ 2149 if (pa >= 0x200000 && pa < first) { 2150 incr = first - pa; 2151 if (pa + incr > end) 2152 incr = end - pa; 2153 goto do_dump_avail; 2154 } 2155 2156 /* 2157 * Block out the dcons buffer if it exists. 2158 */ 2159 if (dcons_addr > 0 && 2160 pa >= trunc_page(dcons_addr) && 2161 pa < dcons_addr + dcons_size) { 2162 incr = dcons_addr + dcons_size - pa; 2163 incr = (incr + PAGE_MASK) & 2164 ~(vm_paddr_t)PAGE_MASK; 2165 if (pa + incr > end) 2166 incr = end - pa; 2167 goto do_dump_avail; 2168 } 2169 2170 page_bad = FALSE; 2171 2172 /* 2173 * Map the page non-cacheable for the memory 2174 * test. 2175 */ 2176 *pte = pa | 2177 kernel_pmap.pmap_bits[PG_V_IDX] | 2178 kernel_pmap.pmap_bits[PG_RW_IDX] | 2179 kernel_pmap.pmap_bits[PG_N_IDX]; 2180 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2181 cpu_mfence(); 2182 2183 /* 2184 * Save original value for restoration later. 2185 */ 2186 tmp = *ptr; 2187 2188 /* 2189 * Test for alternating 1's and 0's 2190 */ 2191 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2192 cpu_mfence(); 2193 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2194 page_bad = TRUE; 2195 /* 2196 * Test for alternating 0's and 1's 2197 */ 2198 *ptr = 0x5555555555555555LLU; 2199 cpu_mfence(); 2200 if (*ptr != 0x5555555555555555LLU) 2201 page_bad = TRUE; 2202 /* 2203 * Test for all 1's 2204 */ 2205 *ptr = 0xffffffffffffffffLLU; 2206 cpu_mfence(); 2207 if (*ptr != 0xffffffffffffffffLLU) 2208 page_bad = TRUE; 2209 /* 2210 * Test for all 0's 2211 */ 2212 *ptr = 0x0; 2213 cpu_mfence(); 2214 if (*ptr != 0x0) 2215 page_bad = TRUE; 2216 2217 /* 2218 * Restore original value. 2219 */ 2220 *ptr = tmp; 2221 2222 /* 2223 * Adjust array of valid/good pages. 2224 */ 2225 if (page_bad == TRUE) { 2226 incr = PAGE_SIZE; 2227 continue; 2228 } 2229 2230 /* 2231 * Collapse page address into phys_avail[]. Do a 2232 * continuation of the current phys_avail[] index 2233 * when possible. 2234 */ 2235 if (phys_avail[pa_indx].phys_end == pa) { 2236 /* 2237 * Continuation 2238 */ 2239 phys_avail[pa_indx].phys_end += incr; 2240 } else if (phys_avail[pa_indx].phys_beg == 2241 phys_avail[pa_indx].phys_end) { 2242 /* 2243 * Current phys_avail is completely empty, 2244 * reuse the index. 2245 */ 2246 phys_avail[pa_indx].phys_beg = pa; 2247 phys_avail[pa_indx].phys_end = pa + incr; 2248 } else { 2249 /* 2250 * Allocate next phys_avail index. 2251 */ 2252 ++pa_indx; 2253 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2254 kprintf( 2255 "Too many holes in the physical address space, giving up\n"); 2256 --pa_indx; 2257 full = TRUE; 2258 goto do_dump_avail; 2259 } 2260 phys_avail[pa_indx].phys_beg = pa; 2261 phys_avail[pa_indx].phys_end = pa + incr; 2262 } 2263 physmem += incr / PAGE_SIZE; 2264 2265 /* 2266 * pa available for dumping 2267 */ 2268 do_dump_avail: 2269 if (dump_avail[da_indx].phys_end == pa) { 2270 dump_avail[da_indx].phys_end += incr; 2271 } else { 2272 ++da_indx; 2273 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2274 --da_indx; 2275 goto do_next; 2276 } 2277 dump_avail[da_indx].phys_beg = pa; 2278 dump_avail[da_indx].phys_end = pa + incr; 2279 } 2280 do_next: 2281 if (full) 2282 break; 2283 } 2284 } 2285 *pte = 0; 2286 cpu_invltlb(); 2287 cpu_mfence(); 2288 2289 /* 2290 * The last chunk must contain at least one page plus the message 2291 * buffer to avoid complicating other code (message buffer address 2292 * calculation, etc.). 2293 */ 2294 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2295 2296 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2297 phys_avail[pa_indx].phys_end) { 2298 physmem -= atop(phys_avail[pa_indx].phys_end - 2299 phys_avail[pa_indx].phys_beg); 2300 phys_avail[pa_indx].phys_beg = 0; 2301 phys_avail[pa_indx].phys_end = 0; 2302 --pa_indx; 2303 } 2304 2305 Maxmem = atop(phys_avail[pa_indx].phys_end); 2306 2307 /* Trim off space for the message buffer. */ 2308 phys_avail[pa_indx].phys_end -= msgbuf_size; 2309 2310 avail_end = phys_avail[pa_indx].phys_end; 2311 2312 /* Map the message buffer. */ 2313 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2314 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2315 } 2316 /* Try to get EFI framebuffer working as early as possible */ 2317 if (have_efi_framebuffer) 2318 efi_fb_init_vaddr(1); 2319 } 2320 2321 struct machintr_abi MachIntrABI; 2322 2323 /* 2324 * IDT VECTORS: 2325 * 0 Divide by zero 2326 * 1 Debug 2327 * 2 NMI 2328 * 3 BreakPoint 2329 * 4 OverFlow 2330 * 5 Bound-Range 2331 * 6 Invalid OpCode 2332 * 7 Device Not Available (x87) 2333 * 8 Double-Fault 2334 * 9 Coprocessor Segment overrun (unsupported, reserved) 2335 * 10 Invalid-TSS 2336 * 11 Segment not present 2337 * 12 Stack 2338 * 13 General Protection 2339 * 14 Page Fault 2340 * 15 Reserved 2341 * 16 x87 FP Exception pending 2342 * 17 Alignment Check 2343 * 18 Machine Check 2344 * 19 SIMD floating point 2345 * 20-31 reserved 2346 * 32-255 INTn/external sources 2347 */ 2348 u_int64_t 2349 hammer_time(u_int64_t modulep, u_int64_t physfree) 2350 { 2351 caddr_t kmdp; 2352 int gsel_tss, x, cpu; 2353 #if 0 /* JG */ 2354 int metadata_missing, off; 2355 #endif 2356 struct mdglobaldata *gd; 2357 struct privatespace *ps; 2358 u_int64_t msr; 2359 2360 /* 2361 * Prevent lowering of the ipl if we call tsleep() early. 2362 */ 2363 gd = &CPU_prvspace[0]->mdglobaldata; 2364 ps = (struct privatespace *)gd; 2365 bzero(gd, sizeof(*gd)); 2366 bzero(&ps->common_tss, sizeof(ps->common_tss)); 2367 2368 /* 2369 * Note: on both UP and SMP curthread must be set non-NULL 2370 * early in the boot sequence because the system assumes 2371 * that 'curthread' is never NULL. 2372 */ 2373 2374 gd->mi.gd_curthread = &thread0; 2375 thread0.td_gd = &gd->mi; 2376 2377 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2378 2379 #if 0 /* JG */ 2380 metadata_missing = 0; 2381 if (bootinfo.bi_modulep) { 2382 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2383 preload_bootstrap_relocate(KERNBASE); 2384 } else { 2385 metadata_missing = 1; 2386 } 2387 if (bootinfo.bi_envp) 2388 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2389 #endif 2390 2391 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2392 preload_bootstrap_relocate(PTOV_OFFSET); 2393 kmdp = preload_search_by_type("elf kernel"); 2394 if (kmdp == NULL) 2395 kmdp = preload_search_by_type("elf64 kernel"); 2396 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2397 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2398 #ifdef DDB 2399 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2400 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2401 #endif 2402 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2403 2404 if (boothowto & RB_VERBOSE) 2405 bootverbose++; 2406 2407 /* 2408 * Default MachIntrABI to ICU 2409 */ 2410 MachIntrABI = MachIntrABI_ICU; 2411 2412 /* 2413 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2414 */ 2415 ncpus = 1; 2416 ncpus_fit = 1; 2417 /* Init basic tunables, hz etc */ 2418 init_param1(); 2419 2420 /* 2421 * make gdt memory segments 2422 */ 2423 gdt_segs[GPROC0_SEL].ssd_base = 2424 (uintptr_t) &CPU_prvspace[0]->common_tss; 2425 2426 gd->mi.gd_prvspace = CPU_prvspace[0]; 2427 2428 for (x = 0; x < NGDT; x++) { 2429 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2430 ssdtosd(&gdt_segs[x], &gdt[x]); 2431 } 2432 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2433 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2434 2435 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2436 r_gdt.rd_base = (long) gdt; 2437 lgdt(&r_gdt); 2438 2439 wrmsr(MSR_FSBASE, 0); /* User value */ 2440 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2441 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2442 2443 mi_gdinit(&gd->mi, 0); 2444 cpu_gdinit(gd, 0); 2445 proc0paddr = proc0paddr_buff; 2446 mi_proc0init(&gd->mi, proc0paddr); 2447 safepri = TDPRI_MAX; 2448 2449 /* spinlocks and the BGL */ 2450 init_locks(); 2451 2452 /* exceptions */ 2453 for (x = 0; x < NIDT; x++) 2454 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2455 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2456 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2457 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2458 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2459 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2460 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2461 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2462 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2463 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2464 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2465 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2466 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2467 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2468 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2469 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2470 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2471 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2472 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2473 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2474 2475 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2476 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2477 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2478 } 2479 2480 lidt(&r_idt_arr[0]); 2481 2482 /* 2483 * Initialize the console before we print anything out. 2484 */ 2485 cninit(); 2486 2487 #if 0 /* JG */ 2488 if (metadata_missing) 2489 kprintf("WARNING: loader(8) metadata is missing!\n"); 2490 #endif 2491 2492 #if NISA >0 2493 elcr_probe(); 2494 isa_defaultirq(); 2495 #endif 2496 rand_initialize(); 2497 2498 /* 2499 * Initialize IRQ mapping 2500 * 2501 * NOTE: 2502 * SHOULD be after elcr_probe() 2503 */ 2504 MachIntrABI_ICU.initmap(); 2505 MachIntrABI_IOAPIC.initmap(); 2506 2507 #ifdef DDB 2508 kdb_init(); 2509 if (boothowto & RB_KDB) 2510 Debugger("Boot flags requested debugger"); 2511 #endif 2512 2513 identify_cpu(); /* Final stage of CPU initialization */ 2514 initializecpu(0); /* Initialize CPU registers */ 2515 2516 /* 2517 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2518 * because the cpu does significant power management in MWAIT 2519 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2520 * 2521 * On modern AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2522 * significant power management only when using ACPI halt mode. 2523 * 2524 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2525 * is needed to reduce power consumption, but wakeup times are often 2526 * too long longer. 2527 */ 2528 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2529 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2530 cpu_idle_hlt = 1; 2531 } 2532 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2533 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2534 /* Ryzen or later */ 2535 cpu_idle_hlt = 3; 2536 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2537 /* Bobcat or later */ 2538 cpu_idle_hlt = 3; 2539 } 2540 } 2541 2542 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2543 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2544 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2545 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2546 2547 /* 2548 * Some of the virtual machines do not work w/ I/O APIC 2549 * enabled. If the user does not explicitly enable or 2550 * disable the I/O APIC (ioapic_enable < 0), then we 2551 * disable I/O APIC on all virtual machines. 2552 * 2553 * NOTE: 2554 * This must be done after identify_cpu(), which sets 2555 * 'cpu_feature2' 2556 */ 2557 if (ioapic_enable < 0) { 2558 if (cpu_feature2 & CPUID2_VMM) 2559 ioapic_enable = 0; 2560 else 2561 ioapic_enable = 1; 2562 } 2563 2564 /* 2565 * TSS entry point for interrupts, traps, and exceptions 2566 * (sans NMI). This will always go to near the top of the pcpu 2567 * trampoline area. Hardware-pushed data will be copied into 2568 * the trap-frame on entry, and (if necessary) returned to the 2569 * trampoline on exit. 2570 * 2571 * We store some pcb data for the trampoline code above the 2572 * stack the cpu hw pushes into, and arrange things so the 2573 * address of tr_pcb_rsp is the same as the desired top of 2574 * stack. 2575 */ 2576 ps->common_tss.tss_rsp0 = (register_t)&ps->trampoline.tr_pcb_rsp; 2577 ps->trampoline.tr_pcb_rsp = ps->common_tss.tss_rsp0; 2578 2579 /* double fault stack */ 2580 ps->common_tss.tss_ist1 = (register_t)ps->dblstack + 2581 sizeof(ps->dblstack); 2582 2583 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2584 ps->common_tss.tss_iobase = sizeof(struct x86_64tss); 2585 2586 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2587 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2588 gd->gd_common_tssd = *gd->gd_tss_gdt; 2589 ltr(gsel_tss); 2590 2591 /* Set up the fast syscall stuff */ 2592 msr = rdmsr(MSR_EFER) | EFER_SCE; 2593 wrmsr(MSR_EFER, msr); 2594 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2595 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2596 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2597 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2598 wrmsr(MSR_STAR, msr); 2599 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2600 2601 getmemsize(kmdp, physfree); 2602 init_param2(physmem); 2603 2604 /* now running on new page tables, configured,and u/iom is accessible */ 2605 2606 /* Map the message buffer. */ 2607 #if 0 /* JG */ 2608 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2609 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2610 #endif 2611 2612 msgbufinit(msgbufp, MSGBUF_SIZE); 2613 2614 2615 /* transfer to user mode */ 2616 2617 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2618 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2619 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2620 2621 load_ds(_udatasel); 2622 load_es(_udatasel); 2623 load_fs(_udatasel); 2624 2625 /* setup proc 0's pcb */ 2626 thread0.td_pcb->pcb_flags = 0; 2627 thread0.td_pcb->pcb_cr3 = KPML4phys; 2628 thread0.td_pcb->pcb_cr3_iso = 0; 2629 thread0.td_pcb->pcb_ext = NULL; 2630 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2631 2632 /* Location of kernel stack for locore */ 2633 return ((u_int64_t)thread0.td_pcb); 2634 } 2635 2636 /* 2637 * Initialize machine-dependant portions of the global data structure. 2638 * Note that the global data area and cpu0's idlestack in the private 2639 * data space were allocated in locore. 2640 * 2641 * Note: the idlethread's cpl is 0 2642 * 2643 * WARNING! Called from early boot, 'mycpu' may not work yet. 2644 */ 2645 void 2646 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2647 { 2648 if (cpu) 2649 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2650 2651 lwkt_init_thread(&gd->mi.gd_idlethread, 2652 gd->mi.gd_prvspace->idlestack, 2653 sizeof(gd->mi.gd_prvspace->idlestack), 2654 0, &gd->mi); 2655 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2656 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2657 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2658 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2659 } 2660 2661 /* 2662 * We only have to check for DMAP bounds, the globaldata space is 2663 * actually part of the kernel_map so we don't have to waste time 2664 * checking CPU_prvspace[*]. 2665 */ 2666 int 2667 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2668 { 2669 #if 0 2670 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2671 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2672 return (TRUE); 2673 } 2674 #endif 2675 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2676 return (TRUE); 2677 return (FALSE); 2678 } 2679 2680 struct globaldata * 2681 globaldata_find(int cpu) 2682 { 2683 KKASSERT(cpu >= 0 && cpu < ncpus); 2684 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2685 } 2686 2687 /* 2688 * This path should be safe from the SYSRET issue because only stopped threads 2689 * can have their %rip adjusted this way (and all heavy weight thread switches 2690 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2691 * convoluted so add a safety by forcing %rip to be cannonical. 2692 */ 2693 int 2694 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2695 { 2696 if (addr & 0x0000800000000000LLU) 2697 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2698 else 2699 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2700 return (0); 2701 } 2702 2703 int 2704 ptrace_single_step(struct lwp *lp) 2705 { 2706 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2707 return (0); 2708 } 2709 2710 int 2711 fill_regs(struct lwp *lp, struct reg *regs) 2712 { 2713 struct trapframe *tp; 2714 2715 if ((tp = lp->lwp_md.md_regs) == NULL) 2716 return EINVAL; 2717 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2718 return (0); 2719 } 2720 2721 int 2722 set_regs(struct lwp *lp, struct reg *regs) 2723 { 2724 struct trapframe *tp; 2725 2726 tp = lp->lwp_md.md_regs; 2727 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2728 !CS_SECURE(regs->r_cs)) 2729 return (EINVAL); 2730 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2731 clear_quickret(); 2732 return (0); 2733 } 2734 2735 static void 2736 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2737 { 2738 struct env87 *penv_87 = &sv_87->sv_env; 2739 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2740 int i; 2741 2742 /* FPU control/status */ 2743 penv_87->en_cw = penv_xmm->en_cw; 2744 penv_87->en_sw = penv_xmm->en_sw; 2745 penv_87->en_tw = penv_xmm->en_tw; 2746 penv_87->en_fip = penv_xmm->en_fip; 2747 penv_87->en_fcs = penv_xmm->en_fcs; 2748 penv_87->en_opcode = penv_xmm->en_opcode; 2749 penv_87->en_foo = penv_xmm->en_foo; 2750 penv_87->en_fos = penv_xmm->en_fos; 2751 2752 /* FPU registers */ 2753 for (i = 0; i < 8; ++i) 2754 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2755 } 2756 2757 static void 2758 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2759 { 2760 struct env87 *penv_87 = &sv_87->sv_env; 2761 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2762 int i; 2763 2764 /* FPU control/status */ 2765 penv_xmm->en_cw = penv_87->en_cw; 2766 penv_xmm->en_sw = penv_87->en_sw; 2767 penv_xmm->en_tw = penv_87->en_tw; 2768 penv_xmm->en_fip = penv_87->en_fip; 2769 penv_xmm->en_fcs = penv_87->en_fcs; 2770 penv_xmm->en_opcode = penv_87->en_opcode; 2771 penv_xmm->en_foo = penv_87->en_foo; 2772 penv_xmm->en_fos = penv_87->en_fos; 2773 2774 /* FPU registers */ 2775 for (i = 0; i < 8; ++i) 2776 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2777 } 2778 2779 int 2780 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2781 { 2782 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2783 return EINVAL; 2784 if (cpu_fxsr) { 2785 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2786 (struct save87 *)fpregs); 2787 return (0); 2788 } 2789 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2790 return (0); 2791 } 2792 2793 int 2794 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2795 { 2796 if (cpu_fxsr) { 2797 set_fpregs_xmm((struct save87 *)fpregs, 2798 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2799 return (0); 2800 } 2801 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2802 return (0); 2803 } 2804 2805 int 2806 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2807 { 2808 struct pcb *pcb; 2809 2810 if (lp == NULL) { 2811 dbregs->dr[0] = rdr0(); 2812 dbregs->dr[1] = rdr1(); 2813 dbregs->dr[2] = rdr2(); 2814 dbregs->dr[3] = rdr3(); 2815 dbregs->dr[4] = rdr4(); 2816 dbregs->dr[5] = rdr5(); 2817 dbregs->dr[6] = rdr6(); 2818 dbregs->dr[7] = rdr7(); 2819 return (0); 2820 } 2821 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2822 return EINVAL; 2823 dbregs->dr[0] = pcb->pcb_dr0; 2824 dbregs->dr[1] = pcb->pcb_dr1; 2825 dbregs->dr[2] = pcb->pcb_dr2; 2826 dbregs->dr[3] = pcb->pcb_dr3; 2827 dbregs->dr[4] = 0; 2828 dbregs->dr[5] = 0; 2829 dbregs->dr[6] = pcb->pcb_dr6; 2830 dbregs->dr[7] = pcb->pcb_dr7; 2831 return (0); 2832 } 2833 2834 int 2835 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2836 { 2837 if (lp == NULL) { 2838 load_dr0(dbregs->dr[0]); 2839 load_dr1(dbregs->dr[1]); 2840 load_dr2(dbregs->dr[2]); 2841 load_dr3(dbregs->dr[3]); 2842 load_dr4(dbregs->dr[4]); 2843 load_dr5(dbregs->dr[5]); 2844 load_dr6(dbregs->dr[6]); 2845 load_dr7(dbregs->dr[7]); 2846 } else { 2847 struct pcb *pcb; 2848 struct ucred *ucred; 2849 int i; 2850 uint64_t mask1, mask2; 2851 2852 /* 2853 * Don't let an illegal value for dr7 get set. Specifically, 2854 * check for undefined settings. Setting these bit patterns 2855 * result in undefined behaviour and can lead to an unexpected 2856 * TRCTRAP. 2857 */ 2858 /* JG this loop looks unreadable */ 2859 /* Check 4 2-bit fields for invalid patterns. 2860 * These fields are R/Wi, for i = 0..3 2861 */ 2862 /* Is 10 in LENi allowed when running in compatibility mode? */ 2863 /* Pattern 10 in R/Wi might be used to indicate 2864 * breakpoint on I/O. Further analysis should be 2865 * carried to decide if it is safe and useful to 2866 * provide access to that capability 2867 */ 2868 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2869 i++, mask1 <<= 4, mask2 <<= 4) 2870 if ((dbregs->dr[7] & mask1) == mask2) 2871 return (EINVAL); 2872 2873 pcb = lp->lwp_thread->td_pcb; 2874 ucred = lp->lwp_proc->p_ucred; 2875 2876 /* 2877 * Don't let a process set a breakpoint that is not within the 2878 * process's address space. If a process could do this, it 2879 * could halt the system by setting a breakpoint in the kernel 2880 * (if ddb was enabled). Thus, we need to check to make sure 2881 * that no breakpoints are being enabled for addresses outside 2882 * process's address space, unless, perhaps, we were called by 2883 * uid 0. 2884 * 2885 * XXX - what about when the watched area of the user's 2886 * address space is written into from within the kernel 2887 * ... wouldn't that still cause a breakpoint to be generated 2888 * from within kernel mode? 2889 */ 2890 2891 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2892 if (dbregs->dr[7] & 0x3) { 2893 /* dr0 is enabled */ 2894 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2895 return (EINVAL); 2896 } 2897 2898 if (dbregs->dr[7] & (0x3<<2)) { 2899 /* dr1 is enabled */ 2900 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2901 return (EINVAL); 2902 } 2903 2904 if (dbregs->dr[7] & (0x3<<4)) { 2905 /* dr2 is enabled */ 2906 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2907 return (EINVAL); 2908 } 2909 2910 if (dbregs->dr[7] & (0x3<<6)) { 2911 /* dr3 is enabled */ 2912 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2913 return (EINVAL); 2914 } 2915 } 2916 2917 pcb->pcb_dr0 = dbregs->dr[0]; 2918 pcb->pcb_dr1 = dbregs->dr[1]; 2919 pcb->pcb_dr2 = dbregs->dr[2]; 2920 pcb->pcb_dr3 = dbregs->dr[3]; 2921 pcb->pcb_dr6 = dbregs->dr[6]; 2922 pcb->pcb_dr7 = dbregs->dr[7]; 2923 2924 pcb->pcb_flags |= PCB_DBREGS; 2925 } 2926 2927 return (0); 2928 } 2929 2930 /* 2931 * Return > 0 if a hardware breakpoint has been hit, and the 2932 * breakpoint was in user space. Return 0, otherwise. 2933 */ 2934 int 2935 user_dbreg_trap(void) 2936 { 2937 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2938 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2939 int nbp; /* number of breakpoints that triggered */ 2940 caddr_t addr[4]; /* breakpoint addresses */ 2941 int i; 2942 2943 dr7 = rdr7(); 2944 if ((dr7 & 0xff) == 0) { 2945 /* 2946 * all GE and LE bits in the dr7 register are zero, 2947 * thus the trap couldn't have been caused by the 2948 * hardware debug registers 2949 */ 2950 return 0; 2951 } 2952 2953 nbp = 0; 2954 dr6 = rdr6(); 2955 bp = dr6 & 0xf; 2956 2957 if (bp == 0) { 2958 /* 2959 * None of the breakpoint bits are set meaning this 2960 * trap was not caused by any of the debug registers 2961 */ 2962 return 0; 2963 } 2964 2965 /* 2966 * at least one of the breakpoints were hit, check to see 2967 * which ones and if any of them are user space addresses 2968 */ 2969 2970 if (bp & 0x01) { 2971 addr[nbp++] = (caddr_t)rdr0(); 2972 } 2973 if (bp & 0x02) { 2974 addr[nbp++] = (caddr_t)rdr1(); 2975 } 2976 if (bp & 0x04) { 2977 addr[nbp++] = (caddr_t)rdr2(); 2978 } 2979 if (bp & 0x08) { 2980 addr[nbp++] = (caddr_t)rdr3(); 2981 } 2982 2983 for (i=0; i<nbp; i++) { 2984 if (addr[i] < 2985 (caddr_t)VM_MAX_USER_ADDRESS) { 2986 /* 2987 * addr[i] is in user space 2988 */ 2989 return nbp; 2990 } 2991 } 2992 2993 /* 2994 * None of the breakpoints are in user space. 2995 */ 2996 return 0; 2997 } 2998 2999 3000 #ifndef DDB 3001 void 3002 Debugger(const char *msg) 3003 { 3004 kprintf("Debugger(\"%s\") called.\n", msg); 3005 } 3006 #endif /* no DDB */ 3007 3008 #ifdef DDB 3009 3010 /* 3011 * Provide inb() and outb() as functions. They are normally only 3012 * available as macros calling inlined functions, thus cannot be 3013 * called inside DDB. 3014 * 3015 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 3016 */ 3017 3018 #undef inb 3019 #undef outb 3020 3021 /* silence compiler warnings */ 3022 u_char inb(u_int); 3023 void outb(u_int, u_char); 3024 3025 u_char 3026 inb(u_int port) 3027 { 3028 u_char data; 3029 /* 3030 * We use %%dx and not %1 here because i/o is done at %dx and not at 3031 * %edx, while gcc generates inferior code (movw instead of movl) 3032 * if we tell it to load (u_short) port. 3033 */ 3034 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 3035 return (data); 3036 } 3037 3038 void 3039 outb(u_int port, u_char data) 3040 { 3041 u_char al; 3042 /* 3043 * Use an unnecessary assignment to help gcc's register allocator. 3044 * This make a large difference for gcc-1.40 and a tiny difference 3045 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 3046 * best results. gcc-2.6.0 can't handle this. 3047 */ 3048 al = data; 3049 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 3050 } 3051 3052 #endif /* DDB */ 3053 3054 3055 3056 /* 3057 * initialize all the SMP locks 3058 */ 3059 3060 /* critical region when masking or unmasking interupts */ 3061 struct spinlock_deprecated imen_spinlock; 3062 3063 /* lock region used by kernel profiling */ 3064 struct spinlock_deprecated mcount_spinlock; 3065 3066 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 3067 struct spinlock_deprecated com_spinlock; 3068 3069 /* lock regions around the clock hardware */ 3070 struct spinlock_deprecated clock_spinlock; 3071 3072 static void 3073 init_locks(void) 3074 { 3075 /* 3076 * Get the initial mplock with a count of 1 for the BSP. 3077 * This uses a LOGICAL cpu ID, ie BSP == 0. 3078 */ 3079 cpu_get_initial_mplock(); 3080 /* DEPRECATED */ 3081 spin_init_deprecated(&mcount_spinlock); 3082 spin_init_deprecated(&imen_spinlock); 3083 spin_init_deprecated(&com_spinlock); 3084 spin_init_deprecated(&clock_spinlock); 3085 3086 /* our token pool needs to work early */ 3087 lwkt_token_pool_init(); 3088 } 3089 3090 boolean_t 3091 cpu_mwait_hint_valid(uint32_t hint) 3092 { 3093 int cx_idx, sub; 3094 3095 cx_idx = MWAIT_EAX_TO_CX(hint); 3096 if (cx_idx >= CPU_MWAIT_CX_MAX) 3097 return FALSE; 3098 3099 sub = MWAIT_EAX_TO_CX_SUB(hint); 3100 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3101 return FALSE; 3102 3103 return TRUE; 3104 } 3105 3106 void 3107 cpu_mwait_cx_no_bmsts(void) 3108 { 3109 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3110 } 3111 3112 void 3113 cpu_mwait_cx_no_bmarb(void) 3114 { 3115 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3116 } 3117 3118 static int 3119 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3120 { 3121 int old_cx_idx, sub = 0; 3122 3123 if (hint >= 0) { 3124 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3125 sub = MWAIT_EAX_TO_CX_SUB(hint); 3126 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3127 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3128 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3129 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3130 } else { 3131 old_cx_idx = CPU_MWAIT_CX_MAX; 3132 } 3133 3134 if (!CPU_MWAIT_HAS_CX) 3135 strlcpy(name, "NONE", namelen); 3136 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3137 strlcpy(name, "AUTO", namelen); 3138 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3139 strlcpy(name, "AUTODEEP", namelen); 3140 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3141 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3142 strlcpy(name, "INVALID", namelen); 3143 else 3144 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3145 3146 return old_cx_idx; 3147 } 3148 3149 static int 3150 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3151 { 3152 int cx_idx, sub, hint; 3153 char *ptr, *start; 3154 3155 if (allow_auto && strcmp(name, "AUTO") == 0) { 3156 hint = CPU_MWAIT_HINT_AUTO; 3157 cx_idx = CPU_MWAIT_C2; 3158 goto done; 3159 } 3160 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3161 hint = CPU_MWAIT_HINT_AUTODEEP; 3162 cx_idx = CPU_MWAIT_C3; 3163 goto done; 3164 } 3165 3166 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3167 return -1; 3168 start = &name[1]; 3169 ptr = NULL; 3170 3171 cx_idx = strtol(start, &ptr, 10); 3172 if (ptr == start || *ptr != '/') 3173 return -1; 3174 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3175 return -1; 3176 3177 start = ptr + 1; 3178 ptr = NULL; 3179 3180 sub = strtol(start, &ptr, 10); 3181 if (*ptr != '\0') 3182 return -1; 3183 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3184 return -1; 3185 3186 hint = MWAIT_EAX_HINT(cx_idx, sub); 3187 done: 3188 *hint0 = hint; 3189 return cx_idx; 3190 } 3191 3192 static int 3193 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3194 { 3195 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3196 return EOPNOTSUPP; 3197 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3198 int error; 3199 3200 error = cputimer_intr_powersave_addreq(); 3201 if (error) 3202 return error; 3203 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3204 cputimer_intr_powersave_remreq(); 3205 } 3206 return 0; 3207 } 3208 3209 static int 3210 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3211 boolean_t allow_auto) 3212 { 3213 int error, cx_idx, old_cx_idx, hint; 3214 char name[CPU_MWAIT_CX_NAMELEN]; 3215 3216 hint = *hint0; 3217 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3218 allow_auto); 3219 3220 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3221 if (error != 0 || req->newptr == NULL) 3222 return error; 3223 3224 if (!CPU_MWAIT_HAS_CX) 3225 return EOPNOTSUPP; 3226 3227 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3228 if (cx_idx < 0) 3229 return EINVAL; 3230 3231 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3232 if (error) 3233 return error; 3234 3235 *hint0 = hint; 3236 return 0; 3237 } 3238 3239 static int 3240 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3241 { 3242 int error, cx_idx, old_cx_idx, hint; 3243 char name[CPU_MWAIT_CX_NAMELEN]; 3244 3245 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3246 3247 hint = stat->hint; 3248 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3249 3250 strlcpy(name, cx_name, sizeof(name)); 3251 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3252 if (cx_idx < 0) 3253 return EINVAL; 3254 3255 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3256 if (error) 3257 return error; 3258 3259 stat->hint = hint; 3260 return 0; 3261 } 3262 3263 static int 3264 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3265 { 3266 int hint = cpu_mwait_halt_global; 3267 int error, cx_idx, cpu; 3268 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3269 3270 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3271 3272 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3273 if (error != 0 || req->newptr == NULL) 3274 return error; 3275 3276 if (!CPU_MWAIT_HAS_CX) 3277 return EOPNOTSUPP; 3278 3279 /* Save name for later per-cpu CX configuration */ 3280 strlcpy(cx_name, name, sizeof(cx_name)); 3281 3282 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3283 if (cx_idx < 0) 3284 return EINVAL; 3285 3286 /* Change per-cpu CX configuration */ 3287 for (cpu = 0; cpu < ncpus; ++cpu) { 3288 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3289 if (error) 3290 return error; 3291 } 3292 3293 cpu_mwait_halt_global = hint; 3294 return 0; 3295 } 3296 3297 static int 3298 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3299 { 3300 struct cpu_idle_stat *stat = arg1; 3301 int error; 3302 3303 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3304 &stat->hint, TRUE); 3305 return error; 3306 } 3307 3308 static int 3309 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3310 { 3311 int error; 3312 3313 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3314 &cpu_mwait_spin, FALSE); 3315 return error; 3316 } 3317 3318 /* 3319 * This manual debugging code is called unconditionally from Xtimer 3320 * (the per-cpu timer interrupt) whether the current thread is in a 3321 * critical section or not) and can be useful in tracking down lockups. 3322 * 3323 * NOTE: MANUAL DEBUG CODE 3324 */ 3325 #if 0 3326 static int saveticks[SMP_MAXCPU]; 3327 static int savecounts[SMP_MAXCPU]; 3328 #endif 3329 3330 void 3331 pcpu_timer_always(struct intrframe *frame) 3332 { 3333 #if 0 3334 globaldata_t gd = mycpu; 3335 int cpu = gd->gd_cpuid; 3336 char buf[64]; 3337 short *gptr; 3338 int i; 3339 3340 if (cpu <= 20) { 3341 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3342 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3343 ++gptr; 3344 3345 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3346 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3347 gd->gd_infomsg); 3348 for (i = 0; buf[i]; ++i) { 3349 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3350 } 3351 } 3352 #if 0 3353 if (saveticks[gd->gd_cpuid] != ticks) { 3354 saveticks[gd->gd_cpuid] = ticks; 3355 savecounts[gd->gd_cpuid] = 0; 3356 } 3357 ++savecounts[gd->gd_cpuid]; 3358 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3359 panic("cpud %d panicing on ticks failure", 3360 gd->gd_cpuid); 3361 } 3362 for (i = 0; i < ncpus; ++i) { 3363 int delta; 3364 if (saveticks[i] && panicstr == NULL) { 3365 delta = saveticks[i] - ticks; 3366 if (delta < -10 || delta > 10) { 3367 panic("cpu %d panicing on cpu %d watchdog", 3368 gd->gd_cpuid, i); 3369 } 3370 } 3371 } 3372 #endif 3373 #endif 3374 } 3375