1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008-2017 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 extern void panicifcpuunsupported(void); 137 138 static void cpu_startup(void *); 139 static void pic_finish(void *); 140 static void cpu_finish(void *); 141 142 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 143 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 144 static void init_locks(void); 145 146 extern void pcpu_timer_always(struct intrframe *); 147 148 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 149 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 150 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 151 152 #ifdef DDB 153 extern vm_offset_t ksym_start, ksym_end; 154 #endif 155 156 struct privatespace CPU_prvspace_bsp __aligned(4096); 157 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 158 159 vm_paddr_t efi_systbl_phys; 160 int _udatasel, _ucodesel, _ucode32sel; 161 u_long atdevbase; 162 int64_t tsc_offsets[MAXCPU]; 163 cpumask_t smp_idleinvl_mask; 164 cpumask_t smp_idleinvl_reqs; 165 166 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 167 168 #if defined(SWTCH_OPTIM_STATS) 169 extern int swtch_optim_stats; 170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 171 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 173 CTLFLAG_RD, &tlb_flush_count, 0, ""); 174 #endif 175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 176 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 177 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, 178 CTLFLAG_RD, &cpu_mwait_spin, 0, "monitor/mwait target state"); 179 180 #define CPU_MWAIT_HAS_CX \ 181 ((cpu_feature2 & CPUID2_MON) && \ 182 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 183 184 #define CPU_MWAIT_CX_NAMELEN 16 185 186 #define CPU_MWAIT_C1 1 187 #define CPU_MWAIT_C2 2 188 #define CPU_MWAIT_C3 3 189 #define CPU_MWAIT_CX_MAX 8 190 191 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 192 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 193 194 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 195 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 196 197 struct cpu_mwait_cx { 198 int subcnt; 199 char name[4]; 200 struct sysctl_ctx_list sysctl_ctx; 201 struct sysctl_oid *sysctl_tree; 202 }; 203 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 204 static char cpu_mwait_cx_supported[256]; 205 206 static int cpu_mwait_c1_hints_cnt; 207 static int cpu_mwait_hints_cnt; 208 static int *cpu_mwait_hints; 209 210 static int cpu_mwait_deep_hints_cnt; 211 static int *cpu_mwait_deep_hints; 212 213 #define CPU_IDLE_REPEAT_DEFAULT 750 214 215 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 216 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 217 static u_int cpu_mwait_repeat_shift = 1; 218 219 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 220 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 221 222 static int cpu_mwait_c3_preamble = 223 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 224 CPU_MWAIT_C3_PREAMBLE_BM_STS; 225 226 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 227 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 228 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 229 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 230 231 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 232 int *, boolean_t); 233 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 234 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 235 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 236 237 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 238 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 239 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 240 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 241 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 242 &cpu_mwait_repeat_shift, 0, ""); 243 244 long physmem = 0; 245 246 u_long ebda_addr = 0; 247 248 int imcr_present = 0; 249 250 int naps = 0; /* # of Applications processors */ 251 252 u_int base_memory; 253 254 static int 255 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 256 { 257 u_long pmem = ctob(physmem); 258 int error; 259 260 error = sysctl_handle_long(oidp, &pmem, 0, req); 261 262 return (error); 263 } 264 265 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 266 0, 0, sysctl_hw_physmem, "LU", 267 "Total system memory in bytes (number of pages * page size)"); 268 269 static int 270 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 271 { 272 u_long usermem = ctob(physmem - vmstats.v_wire_count); 273 int error; 274 275 error = sysctl_handle_long(oidp, &usermem, 0, req); 276 277 return (error); 278 } 279 280 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_ULONG|CTLFLAG_RD, 281 0, 0, sysctl_hw_usermem, "LU", ""); 282 283 static int 284 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 285 { 286 int error; 287 u_long availpages; 288 289 availpages = x86_64_btop(avail_end - avail_start); 290 error = sysctl_handle_long(oidp, &availpages, 0, req); 291 292 return (error); 293 } 294 295 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_ULONG|CTLFLAG_RD, 296 0, 0, sysctl_hw_availpages, "LU", ""); 297 298 vm_paddr_t Maxmem; 299 vm_paddr_t Realmem; 300 301 /* 302 * The number of PHYSMAP entries must be one less than the number of 303 * PHYSSEG entries because the PHYSMAP entry that spans the largest 304 * physical address that is accessible by ISA DMA is split into two 305 * PHYSSEG entries. 306 */ 307 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 308 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 309 310 /* must be 1 less so 0 0 can signal end of chunks */ 311 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 312 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 313 314 static vm_offset_t buffer_sva, buffer_eva; 315 vm_offset_t clean_sva, clean_eva; 316 static vm_offset_t pager_sva, pager_eva; 317 static struct trapframe proc0_tf; 318 319 static void 320 cpu_startup(void *dummy) 321 { 322 caddr_t v; 323 vm_size_t size = 0; 324 vm_offset_t firstaddr; 325 326 /* 327 * Good {morning,afternoon,evening,night}. 328 */ 329 kprintf("%s", version); 330 startrtclock(); 331 printcpuinfo(); 332 panicifcpuunsupported(); 333 kprintf("real memory = %ju (%ju MB)\n", 334 (intmax_t)Realmem, 335 (intmax_t)Realmem / 1024 / 1024); 336 /* 337 * Display any holes after the first chunk of extended memory. 338 */ 339 if (bootverbose) { 340 int indx; 341 342 kprintf("Physical memory chunk(s):\n"); 343 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 344 vm_paddr_t size1; 345 346 size1 = phys_avail[indx].phys_end - 347 phys_avail[indx].phys_beg; 348 349 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 350 (intmax_t)phys_avail[indx].phys_beg, 351 (intmax_t)phys_avail[indx].phys_end - 1, 352 (intmax_t)size1, 353 (intmax_t)(size1 / PAGE_SIZE)); 354 } 355 } 356 357 /* 358 * Allocate space for system data structures. 359 * The first available kernel virtual address is in "v". 360 * As pages of kernel virtual memory are allocated, "v" is incremented. 361 * As pages of memory are allocated and cleared, 362 * "firstaddr" is incremented. 363 * An index into the kernel page table corresponding to the 364 * virtual memory address maintained in "v" is kept in "mapaddr". 365 */ 366 367 /* 368 * Make two passes. The first pass calculates how much memory is 369 * needed and allocates it. The second pass assigns virtual 370 * addresses to the various data structures. 371 */ 372 firstaddr = 0; 373 again: 374 v = (caddr_t)firstaddr; 375 376 #define valloc(name, type, num) \ 377 (name) = (type *)v; v = (caddr_t)((name)+(num)) 378 #define valloclim(name, type, num, lim) \ 379 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 380 381 /* 382 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 383 * For the first 64MB of ram nominally allocate sufficient buffers to 384 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 385 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 386 * the buffer cache we limit the eventual kva reservation to 387 * maxbcache bytes. 388 * 389 * factor represents the 1/4 x ram conversion. 390 */ 391 if (nbuf == 0) { 392 long factor = 4 * NBUFCALCSIZE / 1024; 393 long kbytes = physmem * (PAGE_SIZE / 1024); 394 395 nbuf = 50; 396 if (kbytes > 4096) 397 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 398 if (kbytes > 65536) 399 nbuf += (kbytes - 65536) * 2 / (factor * 5); 400 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 401 nbuf = maxbcache / NBUFCALCSIZE; 402 } 403 404 /* 405 * Do not allow the buffer_map to be more then 1/2 the size of the 406 * kernel_map. 407 */ 408 if (nbuf > (virtual_end - virtual_start + 409 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 410 nbuf = (virtual_end - virtual_start + 411 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 412 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 413 } 414 415 /* 416 * Do not allow the buffer_map to use more than 50% of available 417 * physical-equivalent memory. Since the VM pages which back 418 * individual buffers are typically wired, having too many bufs 419 * can prevent the system from paging properly. 420 */ 421 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 422 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 423 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 424 } 425 426 /* 427 * Do not allow the sizeof(struct buf) * nbuf to exceed 1/4 of 428 * the valloc space which is just the virtual_end - virtual_start 429 * section. This is typically ~2GB regardless of the amount of 430 * memory, so we use 500MB as a metric. 431 * 432 * This is because we use valloc() to allocate the buf header array. 433 * 434 * NOTE: buffer space in bytes is limited by vfs.*bufspace sysctls. 435 */ 436 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 4) { 437 nbuf = (virtual_end - virtual_start) / 438 sizeof(struct buf) / 2; 439 kprintf("Warning: nbufs capped at %ld due to " 440 "valloc considerations\n", 441 nbuf); 442 } 443 444 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 445 #ifdef NSWBUF_MIN 446 if (nswbuf_mem < NSWBUF_MIN) 447 nswbuf_mem = NSWBUF_MIN; 448 #endif 449 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 450 #ifdef NSWBUF_MIN 451 if (nswbuf_kva < NSWBUF_MIN) 452 nswbuf_kva = NSWBUF_MIN; 453 #endif 454 455 valloc(swbuf_mem, struct buf, nswbuf_mem); 456 valloc(swbuf_kva, struct buf, nswbuf_kva); 457 valloc(buf, struct buf, nbuf); 458 459 /* 460 * End of first pass, size has been calculated so allocate memory 461 */ 462 if (firstaddr == 0) { 463 size = (vm_size_t)(v - firstaddr); 464 firstaddr = kmem_alloc(&kernel_map, round_page(size), 465 VM_SUBSYS_BUF); 466 if (firstaddr == 0) 467 panic("startup: no room for tables"); 468 goto again; 469 } 470 471 /* 472 * End of second pass, addresses have been assigned 473 * 474 * nbuf is an int, make sure we don't overflow the field. 475 * 476 * On 64-bit systems we always reserve maximal allocations for 477 * buffer cache buffers and there are no fragmentation issues, 478 * so the KVA segment does not have to be excessively oversized. 479 */ 480 if ((vm_size_t)(v - firstaddr) != size) 481 panic("startup: table size inconsistency"); 482 483 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 484 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 485 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 486 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 487 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 488 buffer_map.system_map = 1; 489 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 490 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 491 pager_map_size); 492 pager_map.system_map = 1; 493 kprintf("avail memory = %ju (%ju MB)\n", 494 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 495 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 496 1024 / 1024); 497 } 498 499 struct cpu_idle_stat { 500 int hint; 501 int reserved; 502 u_long halt; 503 u_long spin; 504 u_long repeat; 505 u_long repeat_last; 506 u_long repeat_delta; 507 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 508 } __cachealign; 509 510 #define CPU_IDLE_STAT_HALT -1 511 #define CPU_IDLE_STAT_SPIN -2 512 513 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 514 515 static int 516 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 517 { 518 int idx = arg2, cpu, error; 519 u_long val = 0; 520 521 if (idx == CPU_IDLE_STAT_HALT) { 522 for (cpu = 0; cpu < ncpus; ++cpu) 523 val += cpu_idle_stats[cpu].halt; 524 } else if (idx == CPU_IDLE_STAT_SPIN) { 525 for (cpu = 0; cpu < ncpus; ++cpu) 526 val += cpu_idle_stats[cpu].spin; 527 } else { 528 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 529 ("invalid index %d", idx)); 530 for (cpu = 0; cpu < ncpus; ++cpu) 531 val += cpu_idle_stats[cpu].mwait_cx[idx]; 532 } 533 534 error = sysctl_handle_quad(oidp, &val, 0, req); 535 if (error || req->newptr == NULL) 536 return error; 537 538 if (idx == CPU_IDLE_STAT_HALT) { 539 for (cpu = 0; cpu < ncpus; ++cpu) 540 cpu_idle_stats[cpu].halt = 0; 541 cpu_idle_stats[0].halt = val; 542 } else if (idx == CPU_IDLE_STAT_SPIN) { 543 for (cpu = 0; cpu < ncpus; ++cpu) 544 cpu_idle_stats[cpu].spin = 0; 545 cpu_idle_stats[0].spin = val; 546 } else { 547 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 548 ("invalid index %d", idx)); 549 for (cpu = 0; cpu < ncpus; ++cpu) 550 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 551 cpu_idle_stats[0].mwait_cx[idx] = val; 552 } 553 return 0; 554 } 555 556 static void 557 cpu_mwait_attach(void) 558 { 559 struct sbuf sb; 560 int hint_idx, i; 561 562 if (!CPU_MWAIT_HAS_CX) 563 return; 564 565 if (cpu_vendor_id == CPU_VENDOR_INTEL && 566 (CPUID_TO_FAMILY(cpu_id) > 0xf || 567 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 568 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 569 int bm_sts = 1; 570 571 /* 572 * Pentium dual-core, Core 2 and beyond do not need any 573 * additional activities to enter deep C-state, i.e. C3(+). 574 */ 575 cpu_mwait_cx_no_bmarb(); 576 577 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 578 if (!bm_sts) 579 cpu_mwait_cx_no_bmsts(); 580 } 581 582 sbuf_new(&sb, cpu_mwait_cx_supported, 583 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 584 585 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 586 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 587 int sub; 588 589 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 590 591 sysctl_ctx_init(&cx->sysctl_ctx); 592 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 593 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 594 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 595 if (cx->sysctl_tree == NULL) 596 continue; 597 598 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 599 SYSCTL_ADD_INT(&cx->sysctl_ctx, 600 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 601 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 602 "sub-state count"); 603 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 604 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 605 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 606 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 607 608 for (sub = 0; sub < cx->subcnt; ++sub) 609 sbuf_printf(&sb, "C%d/%d ", i, sub); 610 } 611 sbuf_trim(&sb); 612 sbuf_finish(&sb); 613 614 /* 615 * Non-deep C-states 616 */ 617 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 618 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 619 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 620 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 621 M_DEVBUF, M_WAITOK); 622 623 hint_idx = 0; 624 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 625 int j, subcnt; 626 627 subcnt = cpu_mwait_cx_info[i].subcnt; 628 for (j = 0; j < subcnt; ++j) { 629 KASSERT(hint_idx < cpu_mwait_hints_cnt, 630 ("invalid mwait hint index %d", hint_idx)); 631 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 632 ++hint_idx; 633 } 634 } 635 KASSERT(hint_idx == cpu_mwait_hints_cnt, 636 ("mwait hint count %d != index %d", 637 cpu_mwait_hints_cnt, hint_idx)); 638 639 if (bootverbose) { 640 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 641 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 642 int hint = cpu_mwait_hints[i]; 643 644 kprintf(" C%d/%d hint 0x%04x\n", 645 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 646 hint); 647 } 648 } 649 650 /* 651 * Deep C-states 652 */ 653 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 654 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 655 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 656 M_DEVBUF, M_WAITOK); 657 658 hint_idx = 0; 659 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 660 int j, subcnt; 661 662 subcnt = cpu_mwait_cx_info[i].subcnt; 663 for (j = 0; j < subcnt; ++j) { 664 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 665 ("invalid mwait deep hint index %d", hint_idx)); 666 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 667 ++hint_idx; 668 } 669 } 670 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 671 ("mwait deep hint count %d != index %d", 672 cpu_mwait_deep_hints_cnt, hint_idx)); 673 674 if (bootverbose) { 675 kprintf("MWAIT deep hints:\n"); 676 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 677 int hint = cpu_mwait_deep_hints[i]; 678 679 kprintf(" C%d/%d hint 0x%04x\n", 680 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 681 hint); 682 } 683 } 684 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 685 686 for (i = 0; i < ncpus; ++i) { 687 char name[16]; 688 689 ksnprintf(name, sizeof(name), "idle%d", i); 690 SYSCTL_ADD_PROC(NULL, 691 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 692 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 693 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 694 } 695 } 696 697 static void 698 cpu_finish(void *dummy __unused) 699 { 700 cpu_setregs(); 701 cpu_mwait_attach(); 702 } 703 704 static void 705 pic_finish(void *dummy __unused) 706 { 707 /* Log ELCR information */ 708 elcr_dump(); 709 710 /* Log MPTABLE information */ 711 mptable_pci_int_dump(); 712 713 /* Finalize PCI */ 714 MachIntrABI.finalize(); 715 } 716 717 /* 718 * Send an interrupt to process. 719 * 720 * Stack is set up to allow sigcode stored 721 * at top to call routine, followed by kcall 722 * to sigreturn routine below. After sigreturn 723 * resets the signal mask, the stack, and the 724 * frame pointer, it returns to the user 725 * specified pc, psl. 726 */ 727 void 728 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 729 { 730 struct lwp *lp = curthread->td_lwp; 731 struct proc *p = lp->lwp_proc; 732 struct trapframe *regs; 733 struct sigacts *psp = p->p_sigacts; 734 struct sigframe sf, *sfp; 735 int oonstack; 736 char *sp; 737 738 regs = lp->lwp_md.md_regs; 739 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 740 741 /* Save user context */ 742 bzero(&sf, sizeof(struct sigframe)); 743 sf.sf_uc.uc_sigmask = *mask; 744 sf.sf_uc.uc_stack = lp->lwp_sigstk; 745 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 746 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 747 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 748 749 /* Make the size of the saved context visible to userland */ 750 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 751 752 /* Allocate and validate space for the signal handler context. */ 753 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 754 SIGISMEMBER(psp->ps_sigonstack, sig)) { 755 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 756 sizeof(struct sigframe)); 757 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 758 } else { 759 /* We take red zone into account */ 760 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 761 } 762 763 /* 764 * XXX AVX needs 64-byte alignment but sigframe has other fields and 765 * the embedded ucontext is not at the front, so aligning this won't 766 * help us. Fortunately we bcopy in/out of the sigframe, so the 767 * kernel is ok. 768 * 769 * The problem though is if userland winds up trying to use the 770 * context directly. 771 */ 772 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 773 774 /* Translate the signal is appropriate */ 775 if (p->p_sysent->sv_sigtbl) { 776 if (sig <= p->p_sysent->sv_sigsize) 777 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 778 } 779 780 /* 781 * Build the argument list for the signal handler. 782 * 783 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 784 */ 785 regs->tf_rdi = sig; /* argument 1 */ 786 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 787 788 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 789 /* 790 * Signal handler installed with SA_SIGINFO. 791 * 792 * action(signo, siginfo, ucontext) 793 */ 794 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 795 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 796 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 797 798 /* fill siginfo structure */ 799 sf.sf_si.si_signo = sig; 800 sf.sf_si.si_code = code; 801 sf.sf_si.si_addr = (void *)regs->tf_addr; 802 } else { 803 /* 804 * Old FreeBSD-style arguments. 805 * 806 * handler (signo, code, [uc], addr) 807 */ 808 regs->tf_rsi = (register_t)code; /* argument 2 */ 809 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 810 sf.sf_ahu.sf_handler = catcher; 811 } 812 813 /* 814 * If we're a vm86 process, we want to save the segment registers. 815 * We also change eflags to be our emulated eflags, not the actual 816 * eflags. 817 */ 818 #if 0 /* JG */ 819 if (regs->tf_eflags & PSL_VM) { 820 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 821 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 822 823 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 824 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 825 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 826 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 827 828 if (vm86->vm86_has_vme == 0) 829 sf.sf_uc.uc_mcontext.mc_eflags = 830 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 831 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 832 833 /* 834 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 835 * syscalls made by the signal handler. This just avoids 836 * wasting time for our lazy fixup of such faults. PSL_NT 837 * does nothing in vm86 mode, but vm86 programs can set it 838 * almost legitimately in probes for old cpu types. 839 */ 840 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 841 } 842 #endif 843 844 /* 845 * Save the FPU state and reinit the FP unit 846 */ 847 npxpush(&sf.sf_uc.uc_mcontext); 848 849 /* 850 * Copy the sigframe out to the user's stack. 851 */ 852 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 853 /* 854 * Something is wrong with the stack pointer. 855 * ...Kill the process. 856 */ 857 sigexit(lp, SIGILL); 858 } 859 860 regs->tf_rsp = (register_t)sfp; 861 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 862 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 863 864 /* 865 * x86 abi specifies that the direction flag must be cleared 866 * on function entry 867 */ 868 regs->tf_rflags &= ~(PSL_T | PSL_D); 869 870 /* 871 * 64 bit mode has a code and stack selector but 872 * no data or extra selector. %fs and %gs are not 873 * stored in-context. 874 */ 875 regs->tf_cs = _ucodesel; 876 regs->tf_ss = _udatasel; 877 clear_quickret(); 878 } 879 880 /* 881 * Sanitize the trapframe for a virtual kernel passing control to a custom 882 * VM context. Remove any items that would otherwise create a privilage 883 * issue. 884 * 885 * XXX at the moment we allow userland to set the resume flag. Is this a 886 * bad idea? 887 */ 888 int 889 cpu_sanitize_frame(struct trapframe *frame) 890 { 891 frame->tf_cs = _ucodesel; 892 frame->tf_ss = _udatasel; 893 /* XXX VM (8086) mode not supported? */ 894 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 895 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 896 897 return(0); 898 } 899 900 /* 901 * Sanitize the tls so loading the descriptor does not blow up 902 * on us. For x86_64 we don't have to do anything. 903 */ 904 int 905 cpu_sanitize_tls(struct savetls *tls) 906 { 907 return(0); 908 } 909 910 /* 911 * sigreturn(ucontext_t *sigcntxp) 912 * 913 * System call to cleanup state after a signal 914 * has been taken. Reset signal mask and 915 * stack state from context left by sendsig (above). 916 * Return to previous pc and psl as specified by 917 * context left by sendsig. Check carefully to 918 * make sure that the user has not modified the 919 * state to gain improper privileges. 920 * 921 * MPSAFE 922 */ 923 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 924 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 925 926 int 927 sys_sigreturn(struct sigreturn_args *uap) 928 { 929 struct lwp *lp = curthread->td_lwp; 930 struct trapframe *regs; 931 ucontext_t uc; 932 ucontext_t *ucp; 933 register_t rflags; 934 int cs; 935 int error; 936 937 /* 938 * We have to copy the information into kernel space so userland 939 * can't modify it while we are sniffing it. 940 */ 941 regs = lp->lwp_md.md_regs; 942 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 943 if (error) 944 return (error); 945 ucp = &uc; 946 rflags = ucp->uc_mcontext.mc_rflags; 947 948 /* VM (8086) mode not supported */ 949 rflags &= ~PSL_VM_UNSUPP; 950 951 #if 0 /* JG */ 952 if (eflags & PSL_VM) { 953 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 954 struct vm86_kernel *vm86; 955 956 /* 957 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 958 * set up the vm86 area, and we can't enter vm86 mode. 959 */ 960 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 961 return (EINVAL); 962 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 963 if (vm86->vm86_inited == 0) 964 return (EINVAL); 965 966 /* go back to user mode if both flags are set */ 967 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 968 trapsignal(lp, SIGBUS, 0); 969 970 if (vm86->vm86_has_vme) { 971 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 972 (eflags & VME_USERCHANGE) | PSL_VM; 973 } else { 974 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 975 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 976 (eflags & VM_USERCHANGE) | PSL_VM; 977 } 978 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 979 tf->tf_eflags = eflags; 980 tf->tf_vm86_ds = tf->tf_ds; 981 tf->tf_vm86_es = tf->tf_es; 982 tf->tf_vm86_fs = tf->tf_fs; 983 tf->tf_vm86_gs = tf->tf_gs; 984 tf->tf_ds = _udatasel; 985 tf->tf_es = _udatasel; 986 tf->tf_fs = _udatasel; 987 tf->tf_gs = _udatasel; 988 } else 989 #endif 990 { 991 /* 992 * Don't allow users to change privileged or reserved flags. 993 */ 994 /* 995 * XXX do allow users to change the privileged flag PSL_RF. 996 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 997 * should sometimes set it there too. tf_eflags is kept in 998 * the signal context during signal handling and there is no 999 * other place to remember it, so the PSL_RF bit may be 1000 * corrupted by the signal handler without us knowing. 1001 * Corruption of the PSL_RF bit at worst causes one more or 1002 * one less debugger trap, so allowing it is fairly harmless. 1003 */ 1004 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 1005 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 1006 return(EINVAL); 1007 } 1008 1009 /* 1010 * Don't allow users to load a valid privileged %cs. Let the 1011 * hardware check for invalid selectors, excess privilege in 1012 * other selectors, invalid %eip's and invalid %esp's. 1013 */ 1014 cs = ucp->uc_mcontext.mc_cs; 1015 if (!CS_SECURE(cs)) { 1016 kprintf("sigreturn: cs = 0x%x\n", cs); 1017 trapsignal(lp, SIGBUS, T_PROTFLT); 1018 return(EINVAL); 1019 } 1020 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1021 } 1022 1023 /* 1024 * Restore the FPU state from the frame 1025 */ 1026 crit_enter(); 1027 npxpop(&ucp->uc_mcontext); 1028 1029 if (ucp->uc_mcontext.mc_onstack & 1) 1030 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1031 else 1032 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1033 1034 lp->lwp_sigmask = ucp->uc_sigmask; 1035 SIG_CANTMASK(lp->lwp_sigmask); 1036 clear_quickret(); 1037 crit_exit(); 1038 return(EJUSTRETURN); 1039 } 1040 1041 /* 1042 * Machine dependent boot() routine 1043 * 1044 * I haven't seen anything to put here yet 1045 * Possibly some stuff might be grafted back here from boot() 1046 */ 1047 void 1048 cpu_boot(int howto) 1049 { 1050 } 1051 1052 /* 1053 * Shutdown the CPU as much as possible 1054 */ 1055 void 1056 cpu_halt(void) 1057 { 1058 for (;;) 1059 __asm__ __volatile("hlt"); 1060 } 1061 1062 /* 1063 * cpu_idle() represents the idle LWKT. You cannot return from this function 1064 * (unless you want to blow things up!). Instead we look for runnable threads 1065 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1066 * 1067 * The main loop is entered with a critical section held, we must release 1068 * the critical section before doing anything else. lwkt_switch() will 1069 * check for pending interrupts due to entering and exiting its own 1070 * critical section. 1071 * 1072 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1073 * However, there are cases where the idlethread will be entered with 1074 * the possibility that no IPI will occur and in such cases 1075 * lwkt_switch() sets TDF_IDLE_NOHLT. 1076 * 1077 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1078 * must occur before it starts using ACPI halt. 1079 * 1080 * NOTE: Value overridden in hammer_time(). 1081 */ 1082 static int cpu_idle_hlt = 2; 1083 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1084 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1085 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1086 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1087 1088 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1089 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1090 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1091 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1092 1093 static void 1094 cpu_idle_default_hook(void) 1095 { 1096 /* 1097 * We must guarentee that hlt is exactly the instruction 1098 * following the sti. 1099 */ 1100 __asm __volatile("sti; hlt"); 1101 } 1102 1103 /* Other subsystems (e.g., ACPI) can hook this later. */ 1104 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1105 1106 static __inline int 1107 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1108 { 1109 int hint, cx_idx; 1110 u_int idx; 1111 1112 hint = stat->hint; 1113 if (hint >= 0) 1114 goto done; 1115 1116 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1117 cpu_mwait_repeat_shift; 1118 if (idx >= cpu_mwait_c1_hints_cnt) { 1119 /* Step up faster, once we walked through all C1 states */ 1120 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1121 } 1122 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1123 if (idx >= cpu_mwait_deep_hints_cnt) 1124 idx = cpu_mwait_deep_hints_cnt - 1; 1125 hint = cpu_mwait_deep_hints[idx]; 1126 } else { 1127 if (idx >= cpu_mwait_hints_cnt) 1128 idx = cpu_mwait_hints_cnt - 1; 1129 hint = cpu_mwait_hints[idx]; 1130 } 1131 done: 1132 cx_idx = MWAIT_EAX_TO_CX(hint); 1133 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1134 stat->mwait_cx[cx_idx]++; 1135 return hint; 1136 } 1137 1138 void 1139 cpu_idle(void) 1140 { 1141 globaldata_t gd = mycpu; 1142 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1143 struct thread *td __debugvar = gd->gd_curthread; 1144 int reqflags; 1145 1146 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1147 1148 crit_exit(); 1149 KKASSERT(td->td_critcount == 0); 1150 1151 for (;;) { 1152 /* 1153 * See if there are any LWKTs ready to go. 1154 */ 1155 lwkt_switch(); 1156 1157 /* 1158 * When halting inside a cli we must check for reqflags 1159 * races, particularly [re]schedule requests. Running 1160 * splz() does the job. 1161 * 1162 * cpu_idle_hlt: 1163 * 0 Never halt, just spin 1164 * 1165 * 1 Always use MONITOR/MWAIT if avail, HLT 1166 * otherwise. 1167 * 1168 * Better default for modern (Haswell+) Intel 1169 * cpus. 1170 * 1171 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1172 * use the ACPI halt (default). This is a hybrid 1173 * approach. See machdep.cpu_idle_repeat. 1174 * 1175 * Better default for modern AMD cpus and older 1176 * Intel cpus. 1177 * 1178 * 3 Always use the ACPI halt. This typically 1179 * eats the least amount of power but the cpu 1180 * will be slow waking up. Slows down e.g. 1181 * compiles and other pipe/event oriented stuff. 1182 * 1183 * Usually the best default for AMD cpus. 1184 * 1185 * 4 Always use HLT. 1186 * 1187 * 5 Always spin. 1188 * 1189 * NOTE: Interrupts are enabled and we are not in a critical 1190 * section. 1191 * 1192 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1193 * don't bother capping gd_idle_repeat, it is ok if 1194 * it overflows (we do make it unsigned, however). 1195 * 1196 * Implement optimized invltlb operations when halted 1197 * in idle. By setting the bit in smp_idleinvl_mask 1198 * we inform other cpus that they can set _reqs to 1199 * request an invltlb. Current the code to do that 1200 * sets the bits in _reqs anyway, but then check _mask 1201 * to determine if they can assume the invltlb will execute. 1202 * 1203 * A critical section is required to ensure that interrupts 1204 * do not fully run until after we've had a chance to execute 1205 * the request. 1206 */ 1207 if (gd->gd_idle_repeat == 0) { 1208 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1209 if (stat->repeat > cpu_idle_repeat_max) 1210 stat->repeat = cpu_idle_repeat_max; 1211 stat->repeat_last = 0; 1212 stat->repeat_delta = 0; 1213 } 1214 ++stat->repeat_last; 1215 1216 /* 1217 * General idle thread halt code 1218 * 1219 * IBRS NOTES - IBRS is a SPECTRE mitigation. When going 1220 * idle, IBRS 1221 */ 1222 ++gd->gd_idle_repeat; 1223 1224 switch(cpu_idle_hlt) { 1225 default: 1226 case 0: 1227 /* 1228 * Always spin 1229 */ 1230 ; 1231 do_spin: 1232 splz(); 1233 __asm __volatile("sti"); 1234 stat->spin++; 1235 crit_enter_gd(gd); 1236 crit_exit_gd(gd); 1237 break; 1238 case 2: 1239 /* 1240 * Use MONITOR/MWAIT (or HLT) for a few cycles, 1241 * then start using the ACPI halt code if we 1242 * continue to be idle. 1243 */ 1244 if (gd->gd_idle_repeat >= cpu_idle_repeat) 1245 goto do_acpi; 1246 /* FALL THROUGH */ 1247 case 1: 1248 /* 1249 * Always use MONITOR/MWAIT (will use HLT if 1250 * MONITOR/MWAIT not available). 1251 */ 1252 if (cpu_mi_feature & CPU_MI_MONITOR) { 1253 splz(); /* XXX */ 1254 reqflags = gd->gd_reqflags; 1255 if (reqflags & RQF_IDLECHECK_WK_MASK) 1256 goto do_spin; 1257 crit_enter_gd(gd); 1258 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1259 if (pscpu->trampoline.tr_pcb_gflags & 1260 (PCB_IBRS1 | PCB_IBRS2)) { 1261 wrmsr(0x48, 0); /* IBRS (spectre) */ 1262 } 1263 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1264 cpu_mwait_cx_hint(stat), 0); 1265 if (pscpu->trampoline.tr_pcb_gflags & 1266 (PCB_IBRS1 | PCB_IBRS2)) { 1267 wrmsr(0x48, 1); /* IBRS (spectre) */ 1268 } 1269 stat->halt++; 1270 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1271 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1272 gd->gd_cpuid)) { 1273 cpu_invltlb(); 1274 cpu_mfence(); 1275 } 1276 crit_exit_gd(gd); 1277 break; 1278 } 1279 /* FALLTHROUGH */ 1280 case 4: 1281 /* 1282 * Use HLT 1283 */ 1284 __asm __volatile("cli"); 1285 splz(); 1286 crit_enter_gd(gd); 1287 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1288 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1289 gd->gd_cpuid); 1290 if (pscpu->trampoline.tr_pcb_gflags & 1291 (PCB_IBRS1 | PCB_IBRS2)) { 1292 /* IBRS (spectre) */ 1293 wrmsr(0x48, 0); 1294 } 1295 cpu_idle_default_hook(); 1296 if (pscpu->trampoline.tr_pcb_gflags & 1297 (PCB_IBRS1 | PCB_IBRS2)) { 1298 /* IBRS (spectre) */ 1299 wrmsr(0x48, 1); 1300 } 1301 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1302 gd->gd_cpuid); 1303 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1304 gd->gd_cpuid)) { 1305 cpu_invltlb(); 1306 cpu_mfence(); 1307 } 1308 } 1309 __asm __volatile("sti"); 1310 stat->halt++; 1311 crit_exit_gd(gd); 1312 break; 1313 case 3: 1314 /* 1315 * Use ACPI halt 1316 */ 1317 ; 1318 do_acpi: 1319 __asm __volatile("cli"); 1320 splz(); 1321 crit_enter_gd(gd); 1322 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1323 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1324 gd->gd_cpuid); 1325 if (pscpu->trampoline.tr_pcb_gflags & 1326 (PCB_IBRS1 | PCB_IBRS2)) { 1327 wrmsr(0x48, 0); 1328 } 1329 cpu_idle_hook(); 1330 if (pscpu->trampoline.tr_pcb_gflags & 1331 (PCB_IBRS1 | PCB_IBRS2)) { 1332 wrmsr(0x48, 1); 1333 } 1334 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1335 gd->gd_cpuid); 1336 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1337 gd->gd_cpuid)) { 1338 cpu_invltlb(); 1339 cpu_mfence(); 1340 } 1341 } 1342 __asm __volatile("sti"); 1343 stat->halt++; 1344 crit_exit_gd(gd); 1345 break; 1346 } 1347 } 1348 } 1349 1350 /* 1351 * Called from deep ACPI via cpu_idle_hook() (see above) to actually halt 1352 * the cpu in C1. ACPI might use other halt methods for deeper states 1353 * and not reach here. 1354 * 1355 * For now we always use HLT as we are not sure what ACPI may have actually 1356 * done. MONITOR/MWAIT might not be appropriate. 1357 * 1358 * NOTE: MONITOR/MWAIT does not appear to throttle AMD cpus, while HLT 1359 * does. On Intel, MONITOR/MWAIT does appear to throttle the cpu. 1360 */ 1361 void 1362 cpu_idle_halt(void) 1363 { 1364 globaldata_t gd; 1365 1366 gd = mycpu; 1367 #if 0 1368 /* DISABLED FOR NOW */ 1369 struct cpu_idle_stat *stat; 1370 int reqflags; 1371 1372 1373 if ((cpu_idle_hlt == 1 || cpu_idle_hlt == 2) && 1374 (cpu_mi_feature & CPU_MI_MONITOR) && 1375 cpu_vendor_id != CPU_VENDOR_AMD) { 1376 /* 1377 * Use MONITOR/MWAIT 1378 * 1379 * (NOTE: On ryzen, MWAIT does not throttle clocks, so we 1380 * have to use HLT) 1381 */ 1382 stat = &cpu_idle_stats[gd->gd_cpuid]; 1383 reqflags = gd->gd_reqflags; 1384 if ((reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1385 __asm __volatile("sti"); 1386 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1387 cpu_mwait_cx_hint(stat), 0); 1388 } else { 1389 __asm __volatile("sti; pause"); 1390 } 1391 } else 1392 #endif 1393 { 1394 /* 1395 * Use HLT 1396 */ 1397 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1398 __asm __volatile("sti; hlt"); 1399 else 1400 __asm __volatile("sti; pause"); 1401 } 1402 } 1403 1404 1405 /* 1406 * Called in a loop indirectly via Xcpustop 1407 */ 1408 void 1409 cpu_smp_stopped(void) 1410 { 1411 globaldata_t gd = mycpu; 1412 volatile __uint64_t *ptr; 1413 __uint64_t ovalue; 1414 1415 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1416 ovalue = *ptr; 1417 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1418 if (cpu_mi_feature & CPU_MI_MONITOR) { 1419 if (cpu_mwait_hints) { 1420 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1421 ovalue, 1422 cpu_mwait_hints[ 1423 cpu_mwait_hints_cnt - 1], 0); 1424 } else { 1425 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1426 ovalue, 0, 0); 1427 } 1428 } else { 1429 cpu_halt(); /* depend on lapic timer */ 1430 } 1431 } 1432 } 1433 1434 /* 1435 * This routine is called if a spinlock has been held through the 1436 * exponential backoff period and is seriously contested. On a real cpu 1437 * we let it spin. 1438 */ 1439 void 1440 cpu_spinlock_contested(void) 1441 { 1442 cpu_pause(); 1443 } 1444 1445 /* 1446 * Clear registers on exec 1447 */ 1448 void 1449 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1450 { 1451 struct thread *td = curthread; 1452 struct lwp *lp = td->td_lwp; 1453 struct pcb *pcb = td->td_pcb; 1454 struct trapframe *regs = lp->lwp_md.md_regs; 1455 1456 user_ldt_free(pcb); 1457 1458 clear_quickret(); 1459 bzero((char *)regs, sizeof(struct trapframe)); 1460 regs->tf_rip = entry; 1461 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1462 regs->tf_rdi = stack; /* argv */ 1463 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1464 regs->tf_ss = _udatasel; 1465 regs->tf_cs = _ucodesel; 1466 regs->tf_rbx = ps_strings; 1467 1468 /* 1469 * Reset the hardware debug registers if they were in use. 1470 * They won't have any meaning for the newly exec'd process. 1471 */ 1472 if (pcb->pcb_flags & PCB_DBREGS) { 1473 pcb->pcb_dr0 = 0; 1474 pcb->pcb_dr1 = 0; 1475 pcb->pcb_dr2 = 0; 1476 pcb->pcb_dr3 = 0; 1477 pcb->pcb_dr6 = 0; 1478 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1479 if (pcb == td->td_pcb) { 1480 /* 1481 * Clear the debug registers on the running 1482 * CPU, otherwise they will end up affecting 1483 * the next process we switch to. 1484 */ 1485 reset_dbregs(); 1486 } 1487 pcb->pcb_flags &= ~PCB_DBREGS; 1488 } 1489 1490 /* 1491 * Initialize the math emulator (if any) for the current process. 1492 * Actually, just clear the bit that says that the emulator has 1493 * been initialized. Initialization is delayed until the process 1494 * traps to the emulator (if it is done at all) mainly because 1495 * emulators don't provide an entry point for initialization. 1496 */ 1497 pcb->pcb_flags &= ~FP_SOFTFP; 1498 1499 /* 1500 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1501 * gd_npxthread. Otherwise a preemptive interrupt thread 1502 * may panic in npxdna(). 1503 */ 1504 crit_enter(); 1505 load_cr0(rcr0() | CR0_MP); 1506 1507 /* 1508 * NOTE: The MSR values must be correct so we can return to 1509 * userland. gd_user_fs/gs must be correct so the switch 1510 * code knows what the current MSR values are. 1511 */ 1512 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1513 pcb->pcb_gsbase = 0; 1514 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1515 mdcpu->gd_user_gs = 0; 1516 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1517 wrmsr(MSR_KGSBASE, 0); 1518 1519 /* Initialize the npx (if any) for the current process. */ 1520 npxinit(); 1521 crit_exit(); 1522 1523 pcb->pcb_ds = _udatasel; 1524 pcb->pcb_es = _udatasel; 1525 pcb->pcb_fs = _udatasel; 1526 pcb->pcb_gs = _udatasel; 1527 } 1528 1529 void 1530 cpu_setregs(void) 1531 { 1532 register_t cr0; 1533 1534 cr0 = rcr0(); 1535 cr0 |= CR0_NE; /* Done by npxinit() */ 1536 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1537 cr0 |= CR0_WP | CR0_AM; 1538 load_cr0(cr0); 1539 load_gs(_udatasel); 1540 } 1541 1542 static int 1543 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1544 { 1545 int error; 1546 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1547 req); 1548 if (!error && req->newptr) 1549 resettodr(); 1550 return (error); 1551 } 1552 1553 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1554 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1555 1556 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1557 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1558 1559 #if 0 /* JG */ 1560 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1561 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1562 #endif 1563 1564 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1565 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1566 1567 static int 1568 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1569 { 1570 struct efi_map_header *efihdr; 1571 caddr_t kmdp; 1572 uint32_t efisize; 1573 1574 kmdp = preload_search_by_type("elf kernel"); 1575 if (kmdp == NULL) 1576 kmdp = preload_search_by_type("elf64 kernel"); 1577 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1578 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1579 if (efihdr == NULL) 1580 return (0); 1581 efisize = *((uint32_t *)efihdr - 1); 1582 return (SYSCTL_OUT(req, efihdr, efisize)); 1583 } 1584 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1585 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1586 1587 /* 1588 * Initialize x86 and configure to run kernel 1589 */ 1590 1591 /* 1592 * Initialize segments & interrupt table 1593 */ 1594 1595 int _default_ldt; 1596 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1597 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1598 #if 0 /* JG */ 1599 union descriptor ldt[NLDT]; /* local descriptor table */ 1600 #endif 1601 1602 /* table descriptors - used to load tables by cpu */ 1603 struct region_descriptor r_gdt; 1604 struct region_descriptor r_idt_arr[MAXCPU]; 1605 1606 /* JG proc0paddr is a virtual address */ 1607 void *proc0paddr; 1608 /* JG alignment? */ 1609 char proc0paddr_buff[LWKT_THREAD_STACK]; 1610 1611 1612 /* software prototypes -- in more palatable form */ 1613 struct soft_segment_descriptor gdt_segs[] = { 1614 /* GNULL_SEL 0 Null Descriptor */ 1615 { 0x0, /* segment base address */ 1616 0x0, /* length */ 1617 0, /* segment type */ 1618 0, /* segment descriptor priority level */ 1619 0, /* segment descriptor present */ 1620 0, /* long */ 1621 0, /* default 32 vs 16 bit size */ 1622 0 /* limit granularity (byte/page units)*/ }, 1623 /* GCODE_SEL 1 Code Descriptor for kernel */ 1624 { 0x0, /* segment base address */ 1625 0xfffff, /* length - all address space */ 1626 SDT_MEMERA, /* segment type */ 1627 SEL_KPL, /* segment descriptor priority level */ 1628 1, /* segment descriptor present */ 1629 1, /* long */ 1630 0, /* default 32 vs 16 bit size */ 1631 1 /* limit granularity (byte/page units)*/ }, 1632 /* GDATA_SEL 2 Data Descriptor for kernel */ 1633 { 0x0, /* segment base address */ 1634 0xfffff, /* length - all address space */ 1635 SDT_MEMRWA, /* segment type */ 1636 SEL_KPL, /* segment descriptor priority level */ 1637 1, /* segment descriptor present */ 1638 1, /* long */ 1639 0, /* default 32 vs 16 bit size */ 1640 1 /* limit granularity (byte/page units)*/ }, 1641 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1642 { 0x0, /* segment base address */ 1643 0xfffff, /* length - all address space */ 1644 SDT_MEMERA, /* segment type */ 1645 SEL_UPL, /* segment descriptor priority level */ 1646 1, /* segment descriptor present */ 1647 0, /* long */ 1648 1, /* default 32 vs 16 bit size */ 1649 1 /* limit granularity (byte/page units)*/ }, 1650 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1651 { 0x0, /* segment base address */ 1652 0xfffff, /* length - all address space */ 1653 SDT_MEMRWA, /* segment type */ 1654 SEL_UPL, /* segment descriptor priority level */ 1655 1, /* segment descriptor present */ 1656 0, /* long */ 1657 1, /* default 32 vs 16 bit size */ 1658 1 /* limit granularity (byte/page units)*/ }, 1659 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1660 { 0x0, /* segment base address */ 1661 0xfffff, /* length - all address space */ 1662 SDT_MEMERA, /* segment type */ 1663 SEL_UPL, /* segment descriptor priority level */ 1664 1, /* segment descriptor present */ 1665 1, /* long */ 1666 0, /* default 32 vs 16 bit size */ 1667 1 /* limit granularity (byte/page units)*/ }, 1668 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1669 { 1670 0x0, /* segment base address */ 1671 sizeof(struct x86_64tss)-1,/* length - all address space */ 1672 SDT_SYSTSS, /* segment type */ 1673 SEL_KPL, /* segment descriptor priority level */ 1674 1, /* segment descriptor present */ 1675 0, /* long */ 1676 0, /* unused - default 32 vs 16 bit size */ 1677 0 /* limit granularity (byte/page units)*/ }, 1678 /* Actually, the TSS is a system descriptor which is double size */ 1679 { 0x0, /* segment base address */ 1680 0x0, /* length */ 1681 0, /* segment type */ 1682 0, /* segment descriptor priority level */ 1683 0, /* segment descriptor present */ 1684 0, /* long */ 1685 0, /* default 32 vs 16 bit size */ 1686 0 /* limit granularity (byte/page units)*/ }, 1687 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1688 { 0x0, /* segment base address */ 1689 0xfffff, /* length - all address space */ 1690 SDT_MEMRWA, /* segment type */ 1691 SEL_UPL, /* segment descriptor priority level */ 1692 1, /* segment descriptor present */ 1693 0, /* long */ 1694 1, /* default 32 vs 16 bit size */ 1695 1 /* limit granularity (byte/page units)*/ }, 1696 }; 1697 1698 void 1699 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1700 { 1701 int cpu; 1702 1703 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1704 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1705 1706 ip->gd_looffset = (uintptr_t)func; 1707 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1708 ip->gd_ist = ist; 1709 ip->gd_xx = 0; 1710 ip->gd_type = typ; 1711 ip->gd_dpl = dpl; 1712 ip->gd_p = 1; 1713 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1714 } 1715 } 1716 1717 void 1718 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1719 { 1720 struct gate_descriptor *ip; 1721 1722 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1723 1724 ip = &idt_arr[cpu][idx]; 1725 ip->gd_looffset = (uintptr_t)func; 1726 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1727 ip->gd_ist = ist; 1728 ip->gd_xx = 0; 1729 ip->gd_type = typ; 1730 ip->gd_dpl = dpl; 1731 ip->gd_p = 1; 1732 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1733 } 1734 1735 #define IDTVEC(name) __CONCAT(X,name) 1736 1737 extern inthand_t 1738 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1739 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1740 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1741 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1742 IDTVEC(xmm), IDTVEC(dblfault), 1743 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1744 1745 void 1746 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1747 { 1748 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1749 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1750 ssd->ssd_type = sd->sd_type; 1751 ssd->ssd_dpl = sd->sd_dpl; 1752 ssd->ssd_p = sd->sd_p; 1753 ssd->ssd_def32 = sd->sd_def32; 1754 ssd->ssd_gran = sd->sd_gran; 1755 } 1756 1757 void 1758 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1759 { 1760 1761 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1762 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1763 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1764 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1765 sd->sd_type = ssd->ssd_type; 1766 sd->sd_dpl = ssd->ssd_dpl; 1767 sd->sd_p = ssd->ssd_p; 1768 sd->sd_long = ssd->ssd_long; 1769 sd->sd_def32 = ssd->ssd_def32; 1770 sd->sd_gran = ssd->ssd_gran; 1771 } 1772 1773 void 1774 ssdtosyssd(struct soft_segment_descriptor *ssd, 1775 struct system_segment_descriptor *sd) 1776 { 1777 1778 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1779 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1780 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1781 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1782 sd->sd_type = ssd->ssd_type; 1783 sd->sd_dpl = ssd->ssd_dpl; 1784 sd->sd_p = ssd->ssd_p; 1785 sd->sd_gran = ssd->ssd_gran; 1786 } 1787 1788 /* 1789 * Populate the (physmap) array with base/bound pairs describing the 1790 * available physical memory in the system, then test this memory and 1791 * build the phys_avail array describing the actually-available memory. 1792 * 1793 * If we cannot accurately determine the physical memory map, then use 1794 * value from the 0xE801 call, and failing that, the RTC. 1795 * 1796 * Total memory size may be set by the kernel environment variable 1797 * hw.physmem or the compile-time define MAXMEM. 1798 * 1799 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1800 * of PAGE_SIZE. This also greatly reduces the memory test time 1801 * which would otherwise be excessive on machines with > 8G of ram. 1802 * 1803 * XXX first should be vm_paddr_t. 1804 */ 1805 1806 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1807 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1808 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1809 1810 vm_paddr_t physmap[PHYSMAP_SIZE]; 1811 struct bios_smap *smapbase, *smap, *smapend; 1812 struct efi_map_header *efihdrbase; 1813 u_int32_t smapsize; 1814 1815 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1816 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1817 1818 static void 1819 add_smap_entries(int *physmap_idx) 1820 { 1821 int i; 1822 1823 smapsize = *((u_int32_t *)smapbase - 1); 1824 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1825 1826 for (smap = smapbase; smap < smapend; smap++) { 1827 if (boothowto & RB_VERBOSE) 1828 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1829 smap->type, smap->base, smap->length); 1830 1831 if (smap->type != SMAP_TYPE_MEMORY) 1832 continue; 1833 1834 if (smap->length == 0) 1835 continue; 1836 1837 for (i = 0; i <= *physmap_idx; i += 2) { 1838 if (smap->base < physmap[i + 1]) { 1839 if (boothowto & RB_VERBOSE) { 1840 kprintf("Overlapping or non-monotonic " 1841 "memory region, ignoring " 1842 "second region\n"); 1843 } 1844 break; 1845 } 1846 } 1847 if (i <= *physmap_idx) 1848 continue; 1849 1850 Realmem += smap->length; 1851 1852 if (smap->base == physmap[*physmap_idx + 1]) { 1853 physmap[*physmap_idx + 1] += smap->length; 1854 continue; 1855 } 1856 1857 *physmap_idx += 2; 1858 if (*physmap_idx == PHYSMAP_SIZE) { 1859 kprintf("Too many segments in the physical " 1860 "address map, giving up\n"); 1861 break; 1862 } 1863 physmap[*physmap_idx] = smap->base; 1864 physmap[*physmap_idx + 1] = smap->base + smap->length; 1865 } 1866 } 1867 1868 static void 1869 add_efi_map_entries(int *physmap_idx) 1870 { 1871 struct efi_md *map, *p; 1872 const char *type; 1873 size_t efisz; 1874 int i, ndesc; 1875 1876 static const char *types[] = { 1877 "Reserved", 1878 "LoaderCode", 1879 "LoaderData", 1880 "BootServicesCode", 1881 "BootServicesData", 1882 "RuntimeServicesCode", 1883 "RuntimeServicesData", 1884 "ConventionalMemory", 1885 "UnusableMemory", 1886 "ACPIReclaimMemory", 1887 "ACPIMemoryNVS", 1888 "MemoryMappedIO", 1889 "MemoryMappedIOPortSpace", 1890 "PalCode" 1891 }; 1892 1893 /* 1894 * Memory map data provided by UEFI via the GetMemoryMap 1895 * Boot Services API. 1896 */ 1897 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1898 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1899 1900 if (efihdrbase->descriptor_size == 0) 1901 return; 1902 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1903 1904 if (boothowto & RB_VERBOSE) 1905 kprintf("%23s %12s %12s %8s %4s\n", 1906 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1907 1908 for (i = 0, p = map; i < ndesc; i++, 1909 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1910 if (boothowto & RB_VERBOSE) { 1911 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1912 type = types[p->md_type]; 1913 else 1914 type = "<INVALID>"; 1915 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1916 p->md_virt, p->md_pages); 1917 if (p->md_attr & EFI_MD_ATTR_UC) 1918 kprintf("UC "); 1919 if (p->md_attr & EFI_MD_ATTR_WC) 1920 kprintf("WC "); 1921 if (p->md_attr & EFI_MD_ATTR_WT) 1922 kprintf("WT "); 1923 if (p->md_attr & EFI_MD_ATTR_WB) 1924 kprintf("WB "); 1925 if (p->md_attr & EFI_MD_ATTR_UCE) 1926 kprintf("UCE "); 1927 if (p->md_attr & EFI_MD_ATTR_WP) 1928 kprintf("WP "); 1929 if (p->md_attr & EFI_MD_ATTR_RP) 1930 kprintf("RP "); 1931 if (p->md_attr & EFI_MD_ATTR_XP) 1932 kprintf("XP "); 1933 if (p->md_attr & EFI_MD_ATTR_RT) 1934 kprintf("RUNTIME"); 1935 kprintf("\n"); 1936 } 1937 1938 switch (p->md_type) { 1939 case EFI_MD_TYPE_CODE: 1940 case EFI_MD_TYPE_DATA: 1941 case EFI_MD_TYPE_BS_CODE: 1942 case EFI_MD_TYPE_BS_DATA: 1943 case EFI_MD_TYPE_FREE: 1944 /* 1945 * We're allowed to use any entry with these types. 1946 */ 1947 break; 1948 default: 1949 continue; 1950 } 1951 1952 Realmem += p->md_pages * PAGE_SIZE; 1953 1954 if (p->md_phys == physmap[*physmap_idx + 1]) { 1955 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1956 continue; 1957 } 1958 1959 *physmap_idx += 2; 1960 if (*physmap_idx == PHYSMAP_SIZE) { 1961 kprintf("Too many segments in the physical " 1962 "address map, giving up\n"); 1963 break; 1964 } 1965 physmap[*physmap_idx] = p->md_phys; 1966 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1967 } 1968 } 1969 1970 struct fb_info efi_fb_info; 1971 static int have_efi_framebuffer = 0; 1972 1973 static void 1974 efi_fb_init_vaddr(int direct_map) 1975 { 1976 uint64_t sz; 1977 vm_offset_t addr, v; 1978 1979 v = efi_fb_info.vaddr; 1980 sz = efi_fb_info.stride * efi_fb_info.height; 1981 1982 if (direct_map) { 1983 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1984 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1985 efi_fb_info.vaddr = addr; 1986 } else { 1987 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1988 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1989 } 1990 } 1991 1992 static u_int 1993 efifb_color_depth(struct efi_fb *efifb) 1994 { 1995 uint32_t mask; 1996 u_int depth; 1997 1998 mask = efifb->fb_mask_red | efifb->fb_mask_green | 1999 efifb->fb_mask_blue | efifb->fb_mask_reserved; 2000 if (mask == 0) 2001 return (0); 2002 for (depth = 1; mask != 1; depth++) 2003 mask >>= 1; 2004 return (depth); 2005 } 2006 2007 int 2008 probe_efi_fb(int early) 2009 { 2010 struct efi_fb *efifb; 2011 caddr_t kmdp; 2012 u_int depth; 2013 2014 if (have_efi_framebuffer) { 2015 if (!early && 2016 (efi_fb_info.vaddr == 0 || 2017 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 2018 efi_fb_init_vaddr(0); 2019 return 0; 2020 } 2021 2022 kmdp = preload_search_by_type("elf kernel"); 2023 if (kmdp == NULL) 2024 kmdp = preload_search_by_type("elf64 kernel"); 2025 efifb = (struct efi_fb *)preload_search_info(kmdp, 2026 MODINFO_METADATA | MODINFOMD_EFI_FB); 2027 if (efifb == NULL) 2028 return 1; 2029 2030 depth = efifb_color_depth(efifb); 2031 /* 2032 * Our bootloader should already notice, when we won't be able to 2033 * use the UEFI framebuffer. 2034 */ 2035 if (depth != 24 && depth != 32) 2036 return 1; 2037 2038 have_efi_framebuffer = 1; 2039 2040 efi_fb_info.is_vga_boot_display = 1; 2041 efi_fb_info.width = efifb->fb_width; 2042 efi_fb_info.height = efifb->fb_height; 2043 efi_fb_info.depth = depth; 2044 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 2045 efi_fb_info.paddr = efifb->fb_addr; 2046 if (early) { 2047 efi_fb_info.vaddr = 0; 2048 } else { 2049 efi_fb_init_vaddr(0); 2050 } 2051 efi_fb_info.fbops.fb_set_par = NULL; 2052 efi_fb_info.fbops.fb_blank = NULL; 2053 efi_fb_info.fbops.fb_debug_enter = NULL; 2054 efi_fb_info.device = NULL; 2055 2056 return 0; 2057 } 2058 2059 static void 2060 efifb_startup(void *arg) 2061 { 2062 probe_efi_fb(0); 2063 } 2064 2065 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 2066 2067 static void 2068 getmemsize(caddr_t kmdp, u_int64_t first) 2069 { 2070 int off, physmap_idx, pa_indx, da_indx; 2071 int i, j; 2072 vm_paddr_t pa; 2073 vm_paddr_t msgbuf_size; 2074 u_long physmem_tunable; 2075 pt_entry_t *pte; 2076 quad_t dcons_addr, dcons_size; 2077 2078 bzero(physmap, sizeof(physmap)); 2079 physmap_idx = 0; 2080 2081 /* 2082 * get memory map from INT 15:E820, kindly supplied by the loader. 2083 * 2084 * subr_module.c says: 2085 * "Consumer may safely assume that size value precedes data." 2086 * ie: an int32_t immediately precedes smap. 2087 */ 2088 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 2089 MODINFO_METADATA | MODINFOMD_EFI_MAP); 2090 smapbase = (struct bios_smap *)preload_search_info(kmdp, 2091 MODINFO_METADATA | MODINFOMD_SMAP); 2092 if (smapbase == NULL && efihdrbase == NULL) 2093 panic("No BIOS smap or EFI map info from loader!"); 2094 2095 if (efihdrbase == NULL) 2096 add_smap_entries(&physmap_idx); 2097 else 2098 add_efi_map_entries(&physmap_idx); 2099 2100 base_memory = physmap[1] / 1024; 2101 /* make hole for AP bootstrap code */ 2102 physmap[1] = mp_bootaddress(base_memory); 2103 2104 /* Save EBDA address, if any */ 2105 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 2106 ebda_addr <<= 4; 2107 2108 /* 2109 * Maxmem isn't the "maximum memory", it's one larger than the 2110 * highest page of the physical address space. It should be 2111 * called something like "Maxphyspage". We may adjust this 2112 * based on ``hw.physmem'' and the results of the memory test. 2113 */ 2114 Maxmem = atop(physmap[physmap_idx + 1]); 2115 2116 #ifdef MAXMEM 2117 Maxmem = MAXMEM / 4; 2118 #endif 2119 2120 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 2121 Maxmem = atop(physmem_tunable); 2122 2123 /* 2124 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 2125 * in the system. 2126 */ 2127 if (Maxmem > atop(physmap[physmap_idx + 1])) 2128 Maxmem = atop(physmap[physmap_idx + 1]); 2129 2130 /* 2131 * Blowing out the DMAP will blow up the system. 2132 */ 2133 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 2134 kprintf("Limiting Maxmem due to DMAP size\n"); 2135 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 2136 } 2137 2138 if (atop(physmap[physmap_idx + 1]) != Maxmem && 2139 (boothowto & RB_VERBOSE)) { 2140 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 2141 } 2142 2143 /* 2144 * Call pmap initialization to make new kernel address space 2145 * 2146 * Mask off page 0. 2147 */ 2148 pmap_bootstrap(&first); 2149 physmap[0] = PAGE_SIZE; 2150 2151 /* 2152 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2153 * exceeding Maxmem. 2154 */ 2155 for (i = j = 0; i <= physmap_idx; i += 2) { 2156 if (physmap[i+1] > ptoa(Maxmem)) 2157 physmap[i+1] = ptoa(Maxmem); 2158 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2159 ~PHYSMAP_ALIGN_MASK; 2160 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2161 2162 physmap[j] = physmap[i]; 2163 physmap[j+1] = physmap[i+1]; 2164 2165 if (physmap[i] < physmap[i+1]) 2166 j += 2; 2167 } 2168 physmap_idx = j - 2; 2169 2170 /* 2171 * Align anything else used in the validation loop. 2172 * 2173 * Also make sure that our 2MB kernel text+data+bss mappings 2174 * do not overlap potentially allocatable space. 2175 */ 2176 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2177 2178 /* 2179 * Size up each available chunk of physical memory. 2180 */ 2181 pa_indx = 0; 2182 da_indx = 0; 2183 phys_avail[pa_indx].phys_beg = physmap[0]; 2184 phys_avail[pa_indx].phys_end = physmap[0]; 2185 dump_avail[da_indx].phys_beg = 0; 2186 dump_avail[da_indx].phys_end = physmap[0]; 2187 pte = CMAP1; 2188 2189 /* 2190 * Get dcons buffer address 2191 */ 2192 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2193 kgetenv_quad("dcons.size", &dcons_size) == 0) 2194 dcons_addr = 0; 2195 2196 /* 2197 * Validate the physical memory. The physical memory segments 2198 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2199 * of PAGE_SIZE. 2200 * 2201 * We no longer perform an exhaustive memory test. Instead we 2202 * simply test the first and last word in each physmap[] 2203 * segment. 2204 */ 2205 for (i = 0; i <= physmap_idx; i += 2) { 2206 vm_paddr_t end; 2207 vm_paddr_t incr; 2208 2209 end = physmap[i + 1]; 2210 2211 for (pa = physmap[i]; pa < end; pa += incr) { 2212 int page_bad, full; 2213 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2214 uint64_t tmp; 2215 2216 full = FALSE; 2217 2218 /* 2219 * Calculate incr. Just test the first and 2220 * last page in each physmap[] segment. 2221 */ 2222 if (pa == end - PAGE_SIZE) 2223 incr = PAGE_SIZE; 2224 else 2225 incr = end - pa - PAGE_SIZE; 2226 2227 /* 2228 * Make sure we don't skip blacked out areas. 2229 */ 2230 if (pa < 0x200000 && 0x200000 < end) { 2231 incr = 0x200000 - pa; 2232 } 2233 if (dcons_addr > 0 && 2234 pa < dcons_addr && 2235 dcons_addr < end) { 2236 incr = dcons_addr - pa; 2237 } 2238 2239 /* 2240 * Block out kernel memory as not available. 2241 */ 2242 if (pa >= 0x200000 && pa < first) { 2243 incr = first - pa; 2244 if (pa + incr > end) 2245 incr = end - pa; 2246 goto do_dump_avail; 2247 } 2248 2249 /* 2250 * Block out the dcons buffer if it exists. 2251 */ 2252 if (dcons_addr > 0 && 2253 pa >= trunc_page(dcons_addr) && 2254 pa < dcons_addr + dcons_size) { 2255 incr = dcons_addr + dcons_size - pa; 2256 incr = (incr + PAGE_MASK) & 2257 ~(vm_paddr_t)PAGE_MASK; 2258 if (pa + incr > end) 2259 incr = end - pa; 2260 goto do_dump_avail; 2261 } 2262 2263 page_bad = FALSE; 2264 2265 /* 2266 * Map the page non-cacheable for the memory 2267 * test. 2268 */ 2269 *pte = pa | 2270 kernel_pmap.pmap_bits[PG_V_IDX] | 2271 kernel_pmap.pmap_bits[PG_RW_IDX] | 2272 kernel_pmap.pmap_bits[PG_N_IDX]; 2273 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2274 cpu_mfence(); 2275 2276 /* 2277 * Save original value for restoration later. 2278 */ 2279 tmp = *ptr; 2280 2281 /* 2282 * Test for alternating 1's and 0's 2283 */ 2284 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2285 cpu_mfence(); 2286 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2287 page_bad = TRUE; 2288 /* 2289 * Test for alternating 0's and 1's 2290 */ 2291 *ptr = 0x5555555555555555LLU; 2292 cpu_mfence(); 2293 if (*ptr != 0x5555555555555555LLU) 2294 page_bad = TRUE; 2295 /* 2296 * Test for all 1's 2297 */ 2298 *ptr = 0xffffffffffffffffLLU; 2299 cpu_mfence(); 2300 if (*ptr != 0xffffffffffffffffLLU) 2301 page_bad = TRUE; 2302 /* 2303 * Test for all 0's 2304 */ 2305 *ptr = 0x0; 2306 cpu_mfence(); 2307 if (*ptr != 0x0) 2308 page_bad = TRUE; 2309 2310 /* 2311 * Restore original value. 2312 */ 2313 *ptr = tmp; 2314 2315 /* 2316 * Adjust array of valid/good pages. 2317 */ 2318 if (page_bad == TRUE) { 2319 incr = PAGE_SIZE; 2320 continue; 2321 } 2322 2323 /* 2324 * Collapse page address into phys_avail[]. Do a 2325 * continuation of the current phys_avail[] index 2326 * when possible. 2327 */ 2328 if (phys_avail[pa_indx].phys_end == pa) { 2329 /* 2330 * Continuation 2331 */ 2332 phys_avail[pa_indx].phys_end += incr; 2333 } else if (phys_avail[pa_indx].phys_beg == 2334 phys_avail[pa_indx].phys_end) { 2335 /* 2336 * Current phys_avail is completely empty, 2337 * reuse the index. 2338 */ 2339 phys_avail[pa_indx].phys_beg = pa; 2340 phys_avail[pa_indx].phys_end = pa + incr; 2341 } else { 2342 /* 2343 * Allocate next phys_avail index. 2344 */ 2345 ++pa_indx; 2346 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2347 kprintf( 2348 "Too many holes in the physical address space, giving up\n"); 2349 --pa_indx; 2350 full = TRUE; 2351 goto do_dump_avail; 2352 } 2353 phys_avail[pa_indx].phys_beg = pa; 2354 phys_avail[pa_indx].phys_end = pa + incr; 2355 } 2356 physmem += incr / PAGE_SIZE; 2357 2358 /* 2359 * pa available for dumping 2360 */ 2361 do_dump_avail: 2362 if (dump_avail[da_indx].phys_end == pa) { 2363 dump_avail[da_indx].phys_end += incr; 2364 } else { 2365 ++da_indx; 2366 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2367 --da_indx; 2368 goto do_next; 2369 } 2370 dump_avail[da_indx].phys_beg = pa; 2371 dump_avail[da_indx].phys_end = pa + incr; 2372 } 2373 do_next: 2374 if (full) 2375 break; 2376 } 2377 } 2378 *pte = 0; 2379 cpu_invltlb(); 2380 cpu_mfence(); 2381 2382 /* 2383 * The last chunk must contain at least one page plus the message 2384 * buffer to avoid complicating other code (message buffer address 2385 * calculation, etc.). 2386 */ 2387 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2388 2389 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2390 phys_avail[pa_indx].phys_end) { 2391 physmem -= atop(phys_avail[pa_indx].phys_end - 2392 phys_avail[pa_indx].phys_beg); 2393 phys_avail[pa_indx].phys_beg = 0; 2394 phys_avail[pa_indx].phys_end = 0; 2395 --pa_indx; 2396 } 2397 2398 Maxmem = atop(phys_avail[pa_indx].phys_end); 2399 2400 /* Trim off space for the message buffer. */ 2401 phys_avail[pa_indx].phys_end -= msgbuf_size; 2402 2403 avail_end = phys_avail[pa_indx].phys_end; 2404 2405 /* Map the message buffer. */ 2406 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2407 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2408 } 2409 /* Try to get EFI framebuffer working as early as possible */ 2410 if (have_efi_framebuffer) 2411 efi_fb_init_vaddr(1); 2412 } 2413 2414 struct machintr_abi MachIntrABI; 2415 2416 /* 2417 * IDT VECTORS: 2418 * 0 Divide by zero 2419 * 1 Debug 2420 * 2 NMI 2421 * 3 BreakPoint 2422 * 4 OverFlow 2423 * 5 Bound-Range 2424 * 6 Invalid OpCode 2425 * 7 Device Not Available (x87) 2426 * 8 Double-Fault 2427 * 9 Coprocessor Segment overrun (unsupported, reserved) 2428 * 10 Invalid-TSS 2429 * 11 Segment not present 2430 * 12 Stack 2431 * 13 General Protection 2432 * 14 Page Fault 2433 * 15 Reserved 2434 * 16 x87 FP Exception pending 2435 * 17 Alignment Check 2436 * 18 Machine Check 2437 * 19 SIMD floating point 2438 * 20-31 reserved 2439 * 32-255 INTn/external sources 2440 */ 2441 u_int64_t 2442 hammer_time(u_int64_t modulep, u_int64_t physfree) 2443 { 2444 caddr_t kmdp; 2445 int gsel_tss, x, cpu; 2446 #if 0 /* JG */ 2447 int metadata_missing, off; 2448 #endif 2449 struct mdglobaldata *gd; 2450 struct privatespace *ps; 2451 u_int64_t msr; 2452 2453 /* 2454 * Prevent lowering of the ipl if we call tsleep() early. 2455 */ 2456 gd = &CPU_prvspace[0]->mdglobaldata; 2457 ps = (struct privatespace *)gd; 2458 bzero(gd, sizeof(*gd)); 2459 bzero(&ps->common_tss, sizeof(ps->common_tss)); 2460 2461 /* 2462 * Note: on both UP and SMP curthread must be set non-NULL 2463 * early in the boot sequence because the system assumes 2464 * that 'curthread' is never NULL. 2465 */ 2466 2467 gd->mi.gd_curthread = &thread0; 2468 thread0.td_gd = &gd->mi; 2469 2470 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2471 2472 #if 0 /* JG */ 2473 metadata_missing = 0; 2474 if (bootinfo.bi_modulep) { 2475 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2476 preload_bootstrap_relocate(KERNBASE); 2477 } else { 2478 metadata_missing = 1; 2479 } 2480 if (bootinfo.bi_envp) 2481 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2482 #endif 2483 2484 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2485 preload_bootstrap_relocate(PTOV_OFFSET); 2486 kmdp = preload_search_by_type("elf kernel"); 2487 if (kmdp == NULL) 2488 kmdp = preload_search_by_type("elf64 kernel"); 2489 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2490 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2491 #ifdef DDB 2492 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2493 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2494 #endif 2495 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2496 2497 if (boothowto & RB_VERBOSE) 2498 bootverbose++; 2499 2500 /* 2501 * Default MachIntrABI to ICU 2502 */ 2503 MachIntrABI = MachIntrABI_ICU; 2504 2505 /* 2506 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2507 */ 2508 ncpus = 1; 2509 ncpus_fit = 1; 2510 /* Init basic tunables, hz etc */ 2511 init_param1(); 2512 2513 /* 2514 * make gdt memory segments 2515 */ 2516 gdt_segs[GPROC0_SEL].ssd_base = 2517 (uintptr_t) &CPU_prvspace[0]->common_tss; 2518 2519 gd->mi.gd_prvspace = CPU_prvspace[0]; 2520 2521 for (x = 0; x < NGDT; x++) { 2522 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2523 ssdtosd(&gdt_segs[x], &gdt[x]); 2524 } 2525 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2526 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2527 2528 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2529 r_gdt.rd_base = (long) gdt; 2530 lgdt(&r_gdt); 2531 2532 wrmsr(MSR_FSBASE, 0); /* User value */ 2533 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2534 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2535 2536 mi_gdinit(&gd->mi, 0); 2537 cpu_gdinit(gd, 0); 2538 proc0paddr = proc0paddr_buff; 2539 mi_proc0init(&gd->mi, proc0paddr); 2540 safepri = TDPRI_MAX; 2541 2542 /* spinlocks and the BGL */ 2543 init_locks(); 2544 2545 /* exceptions */ 2546 for (x = 0; x < NIDT; x++) 2547 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2548 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2549 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2550 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2551 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2552 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2553 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2554 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2555 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2556 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2557 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2558 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2559 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2560 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2561 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2562 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2563 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2564 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2565 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2566 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2567 2568 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2569 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2570 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2571 } 2572 2573 lidt(&r_idt_arr[0]); 2574 2575 /* 2576 * Initialize the console before we print anything out. 2577 */ 2578 cninit(); 2579 2580 #if 0 /* JG */ 2581 if (metadata_missing) 2582 kprintf("WARNING: loader(8) metadata is missing!\n"); 2583 #endif 2584 2585 #if NISA >0 2586 elcr_probe(); 2587 isa_defaultirq(); 2588 #endif 2589 rand_initialize(); 2590 2591 /* 2592 * Initialize IRQ mapping 2593 * 2594 * NOTE: 2595 * SHOULD be after elcr_probe() 2596 */ 2597 MachIntrABI_ICU.initmap(); 2598 MachIntrABI_IOAPIC.initmap(); 2599 2600 #ifdef DDB 2601 kdb_init(); 2602 if (boothowto & RB_KDB) 2603 Debugger("Boot flags requested debugger"); 2604 #endif 2605 2606 identify_cpu(); /* Final stage of CPU initialization */ 2607 initializecpu(0); /* Initialize CPU registers */ 2608 2609 /* 2610 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2611 * because the cpu does significant power management in MWAIT 2612 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2613 * 2614 * On many AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2615 * significant power management only when using ACPI halt mode. 2616 * (However, on Ryzen, mode 4 (HLT) also does power management). 2617 * 2618 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2619 * is needed to reduce power consumption, but wakeup times are often 2620 * too long. 2621 */ 2622 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2623 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2624 cpu_idle_hlt = 1; 2625 } 2626 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2627 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2628 /* Ryzen or later */ 2629 cpu_idle_hlt = 3; 2630 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2631 /* Bobcat or later */ 2632 cpu_idle_hlt = 3; 2633 } 2634 } 2635 2636 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2637 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2638 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2639 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2640 2641 /* 2642 * Some of the virtual machines do not work w/ I/O APIC 2643 * enabled. If the user does not explicitly enable or 2644 * disable the I/O APIC (ioapic_enable < 0), then we 2645 * disable I/O APIC on all virtual machines. 2646 * 2647 * NOTE: 2648 * This must be done after identify_cpu(), which sets 2649 * 'cpu_feature2' 2650 */ 2651 if (ioapic_enable < 0) { 2652 if (cpu_feature2 & CPUID2_VMM) 2653 ioapic_enable = 0; 2654 else 2655 ioapic_enable = 1; 2656 } 2657 2658 /* 2659 * TSS entry point for interrupts, traps, and exceptions 2660 * (sans NMI). This will always go to near the top of the pcpu 2661 * trampoline area. Hardware-pushed data will be copied into 2662 * the trap-frame on entry, and (if necessary) returned to the 2663 * trampoline on exit. 2664 * 2665 * We store some pcb data for the trampoline code above the 2666 * stack the cpu hw pushes into, and arrange things so the 2667 * address of tr_pcb_rsp is the same as the desired top of 2668 * stack. 2669 */ 2670 ps->common_tss.tss_rsp0 = (register_t)&ps->trampoline.tr_pcb_rsp; 2671 ps->trampoline.tr_pcb_rsp = ps->common_tss.tss_rsp0; 2672 2673 /* double fault stack */ 2674 ps->common_tss.tss_ist1 = (register_t)ps->dblstack + 2675 sizeof(ps->dblstack); 2676 2677 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2678 ps->common_tss.tss_iobase = sizeof(struct x86_64tss); 2679 2680 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2681 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2682 gd->gd_common_tssd = *gd->gd_tss_gdt; 2683 ltr(gsel_tss); 2684 2685 /* Set up the fast syscall stuff */ 2686 msr = rdmsr(MSR_EFER) | EFER_SCE; 2687 wrmsr(MSR_EFER, msr); 2688 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2689 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2690 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2691 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2692 wrmsr(MSR_STAR, msr); 2693 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2694 2695 getmemsize(kmdp, physfree); 2696 init_param2(physmem); 2697 2698 /* now running on new page tables, configured,and u/iom is accessible */ 2699 2700 /* Map the message buffer. */ 2701 #if 0 /* JG */ 2702 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2703 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2704 #endif 2705 2706 msgbufinit(msgbufp, MSGBUF_SIZE); 2707 2708 2709 /* transfer to user mode */ 2710 2711 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2712 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2713 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2714 2715 load_ds(_udatasel); 2716 load_es(_udatasel); 2717 load_fs(_udatasel); 2718 2719 /* setup proc 0's pcb */ 2720 thread0.td_pcb->pcb_flags = 0; 2721 thread0.td_pcb->pcb_cr3 = KPML4phys; 2722 thread0.td_pcb->pcb_cr3_iso = 0; 2723 thread0.td_pcb->pcb_ext = NULL; 2724 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2725 2726 /* Location of kernel stack for locore */ 2727 return ((u_int64_t)thread0.td_pcb); 2728 } 2729 2730 /* 2731 * Initialize machine-dependant portions of the global data structure. 2732 * Note that the global data area and cpu0's idlestack in the private 2733 * data space were allocated in locore. 2734 * 2735 * Note: the idlethread's cpl is 0 2736 * 2737 * WARNING! Called from early boot, 'mycpu' may not work yet. 2738 */ 2739 void 2740 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2741 { 2742 if (cpu) 2743 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2744 2745 lwkt_init_thread(&gd->mi.gd_idlethread, 2746 gd->mi.gd_prvspace->idlestack, 2747 sizeof(gd->mi.gd_prvspace->idlestack), 2748 0, &gd->mi); 2749 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2750 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2751 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2752 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2753 } 2754 2755 /* 2756 * We only have to check for DMAP bounds, the globaldata space is 2757 * actually part of the kernel_map so we don't have to waste time 2758 * checking CPU_prvspace[*]. 2759 */ 2760 int 2761 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2762 { 2763 #if 0 2764 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2765 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2766 return (TRUE); 2767 } 2768 #endif 2769 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2770 return (TRUE); 2771 return (FALSE); 2772 } 2773 2774 struct globaldata * 2775 globaldata_find(int cpu) 2776 { 2777 KKASSERT(cpu >= 0 && cpu < ncpus); 2778 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2779 } 2780 2781 /* 2782 * This path should be safe from the SYSRET issue because only stopped threads 2783 * can have their %rip adjusted this way (and all heavy weight thread switches 2784 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2785 * convoluted so add a safety by forcing %rip to be cannonical. 2786 */ 2787 int 2788 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2789 { 2790 if (addr & 0x0000800000000000LLU) 2791 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2792 else 2793 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2794 return (0); 2795 } 2796 2797 int 2798 ptrace_single_step(struct lwp *lp) 2799 { 2800 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2801 return (0); 2802 } 2803 2804 int 2805 fill_regs(struct lwp *lp, struct reg *regs) 2806 { 2807 struct trapframe *tp; 2808 2809 if ((tp = lp->lwp_md.md_regs) == NULL) 2810 return EINVAL; 2811 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2812 return (0); 2813 } 2814 2815 int 2816 set_regs(struct lwp *lp, struct reg *regs) 2817 { 2818 struct trapframe *tp; 2819 2820 tp = lp->lwp_md.md_regs; 2821 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2822 !CS_SECURE(regs->r_cs)) 2823 return (EINVAL); 2824 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2825 clear_quickret(); 2826 return (0); 2827 } 2828 2829 static void 2830 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2831 { 2832 struct env87 *penv_87 = &sv_87->sv_env; 2833 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2834 int i; 2835 2836 /* FPU control/status */ 2837 penv_87->en_cw = penv_xmm->en_cw; 2838 penv_87->en_sw = penv_xmm->en_sw; 2839 penv_87->en_tw = penv_xmm->en_tw; 2840 penv_87->en_fip = penv_xmm->en_fip; 2841 penv_87->en_fcs = penv_xmm->en_fcs; 2842 penv_87->en_opcode = penv_xmm->en_opcode; 2843 penv_87->en_foo = penv_xmm->en_foo; 2844 penv_87->en_fos = penv_xmm->en_fos; 2845 2846 /* FPU registers */ 2847 for (i = 0; i < 8; ++i) 2848 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2849 } 2850 2851 static void 2852 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2853 { 2854 struct env87 *penv_87 = &sv_87->sv_env; 2855 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2856 int i; 2857 2858 /* FPU control/status */ 2859 penv_xmm->en_cw = penv_87->en_cw; 2860 penv_xmm->en_sw = penv_87->en_sw; 2861 penv_xmm->en_tw = penv_87->en_tw; 2862 penv_xmm->en_fip = penv_87->en_fip; 2863 penv_xmm->en_fcs = penv_87->en_fcs; 2864 penv_xmm->en_opcode = penv_87->en_opcode; 2865 penv_xmm->en_foo = penv_87->en_foo; 2866 penv_xmm->en_fos = penv_87->en_fos; 2867 2868 /* FPU registers */ 2869 for (i = 0; i < 8; ++i) 2870 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2871 } 2872 2873 int 2874 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2875 { 2876 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2877 return EINVAL; 2878 if (cpu_fxsr) { 2879 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2880 (struct save87 *)fpregs); 2881 return (0); 2882 } 2883 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2884 return (0); 2885 } 2886 2887 int 2888 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2889 { 2890 if (cpu_fxsr) { 2891 set_fpregs_xmm((struct save87 *)fpregs, 2892 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2893 return (0); 2894 } 2895 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2896 return (0); 2897 } 2898 2899 int 2900 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2901 { 2902 struct pcb *pcb; 2903 2904 if (lp == NULL) { 2905 dbregs->dr[0] = rdr0(); 2906 dbregs->dr[1] = rdr1(); 2907 dbregs->dr[2] = rdr2(); 2908 dbregs->dr[3] = rdr3(); 2909 dbregs->dr[4] = rdr4(); 2910 dbregs->dr[5] = rdr5(); 2911 dbregs->dr[6] = rdr6(); 2912 dbregs->dr[7] = rdr7(); 2913 return (0); 2914 } 2915 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2916 return EINVAL; 2917 dbregs->dr[0] = pcb->pcb_dr0; 2918 dbregs->dr[1] = pcb->pcb_dr1; 2919 dbregs->dr[2] = pcb->pcb_dr2; 2920 dbregs->dr[3] = pcb->pcb_dr3; 2921 dbregs->dr[4] = 0; 2922 dbregs->dr[5] = 0; 2923 dbregs->dr[6] = pcb->pcb_dr6; 2924 dbregs->dr[7] = pcb->pcb_dr7; 2925 return (0); 2926 } 2927 2928 int 2929 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2930 { 2931 if (lp == NULL) { 2932 load_dr0(dbregs->dr[0]); 2933 load_dr1(dbregs->dr[1]); 2934 load_dr2(dbregs->dr[2]); 2935 load_dr3(dbregs->dr[3]); 2936 load_dr4(dbregs->dr[4]); 2937 load_dr5(dbregs->dr[5]); 2938 load_dr6(dbregs->dr[6]); 2939 load_dr7(dbregs->dr[7]); 2940 } else { 2941 struct pcb *pcb; 2942 struct ucred *ucred; 2943 int i; 2944 uint64_t mask1, mask2; 2945 2946 /* 2947 * Don't let an illegal value for dr7 get set. Specifically, 2948 * check for undefined settings. Setting these bit patterns 2949 * result in undefined behaviour and can lead to an unexpected 2950 * TRCTRAP. 2951 */ 2952 /* JG this loop looks unreadable */ 2953 /* Check 4 2-bit fields for invalid patterns. 2954 * These fields are R/Wi, for i = 0..3 2955 */ 2956 /* Is 10 in LENi allowed when running in compatibility mode? */ 2957 /* Pattern 10 in R/Wi might be used to indicate 2958 * breakpoint on I/O. Further analysis should be 2959 * carried to decide if it is safe and useful to 2960 * provide access to that capability 2961 */ 2962 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2963 i++, mask1 <<= 4, mask2 <<= 4) 2964 if ((dbregs->dr[7] & mask1) == mask2) 2965 return (EINVAL); 2966 2967 pcb = lp->lwp_thread->td_pcb; 2968 ucred = lp->lwp_proc->p_ucred; 2969 2970 /* 2971 * Don't let a process set a breakpoint that is not within the 2972 * process's address space. If a process could do this, it 2973 * could halt the system by setting a breakpoint in the kernel 2974 * (if ddb was enabled). Thus, we need to check to make sure 2975 * that no breakpoints are being enabled for addresses outside 2976 * process's address space, unless, perhaps, we were called by 2977 * uid 0. 2978 * 2979 * XXX - what about when the watched area of the user's 2980 * address space is written into from within the kernel 2981 * ... wouldn't that still cause a breakpoint to be generated 2982 * from within kernel mode? 2983 */ 2984 2985 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2986 if (dbregs->dr[7] & 0x3) { 2987 /* dr0 is enabled */ 2988 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2989 return (EINVAL); 2990 } 2991 2992 if (dbregs->dr[7] & (0x3<<2)) { 2993 /* dr1 is enabled */ 2994 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2995 return (EINVAL); 2996 } 2997 2998 if (dbregs->dr[7] & (0x3<<4)) { 2999 /* dr2 is enabled */ 3000 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 3001 return (EINVAL); 3002 } 3003 3004 if (dbregs->dr[7] & (0x3<<6)) { 3005 /* dr3 is enabled */ 3006 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 3007 return (EINVAL); 3008 } 3009 } 3010 3011 pcb->pcb_dr0 = dbregs->dr[0]; 3012 pcb->pcb_dr1 = dbregs->dr[1]; 3013 pcb->pcb_dr2 = dbregs->dr[2]; 3014 pcb->pcb_dr3 = dbregs->dr[3]; 3015 pcb->pcb_dr6 = dbregs->dr[6]; 3016 pcb->pcb_dr7 = dbregs->dr[7]; 3017 3018 pcb->pcb_flags |= PCB_DBREGS; 3019 } 3020 3021 return (0); 3022 } 3023 3024 /* 3025 * Return > 0 if a hardware breakpoint has been hit, and the 3026 * breakpoint was in user space. Return 0, otherwise. 3027 */ 3028 int 3029 user_dbreg_trap(void) 3030 { 3031 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 3032 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 3033 int nbp; /* number of breakpoints that triggered */ 3034 caddr_t addr[4]; /* breakpoint addresses */ 3035 int i; 3036 3037 dr7 = rdr7(); 3038 if ((dr7 & 0xff) == 0) { 3039 /* 3040 * all GE and LE bits in the dr7 register are zero, 3041 * thus the trap couldn't have been caused by the 3042 * hardware debug registers 3043 */ 3044 return 0; 3045 } 3046 3047 nbp = 0; 3048 dr6 = rdr6(); 3049 bp = dr6 & 0xf; 3050 3051 if (bp == 0) { 3052 /* 3053 * None of the breakpoint bits are set meaning this 3054 * trap was not caused by any of the debug registers 3055 */ 3056 return 0; 3057 } 3058 3059 /* 3060 * at least one of the breakpoints were hit, check to see 3061 * which ones and if any of them are user space addresses 3062 */ 3063 3064 if (bp & 0x01) { 3065 addr[nbp++] = (caddr_t)rdr0(); 3066 } 3067 if (bp & 0x02) { 3068 addr[nbp++] = (caddr_t)rdr1(); 3069 } 3070 if (bp & 0x04) { 3071 addr[nbp++] = (caddr_t)rdr2(); 3072 } 3073 if (bp & 0x08) { 3074 addr[nbp++] = (caddr_t)rdr3(); 3075 } 3076 3077 for (i=0; i<nbp; i++) { 3078 if (addr[i] < 3079 (caddr_t)VM_MAX_USER_ADDRESS) { 3080 /* 3081 * addr[i] is in user space 3082 */ 3083 return nbp; 3084 } 3085 } 3086 3087 /* 3088 * None of the breakpoints are in user space. 3089 */ 3090 return 0; 3091 } 3092 3093 3094 #ifndef DDB 3095 void 3096 Debugger(const char *msg) 3097 { 3098 kprintf("Debugger(\"%s\") called.\n", msg); 3099 } 3100 #endif /* no DDB */ 3101 3102 #ifdef DDB 3103 3104 /* 3105 * Provide inb() and outb() as functions. They are normally only 3106 * available as macros calling inlined functions, thus cannot be 3107 * called inside DDB. 3108 * 3109 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 3110 */ 3111 3112 #undef inb 3113 #undef outb 3114 3115 /* silence compiler warnings */ 3116 u_char inb(u_int); 3117 void outb(u_int, u_char); 3118 3119 u_char 3120 inb(u_int port) 3121 { 3122 u_char data; 3123 /* 3124 * We use %%dx and not %1 here because i/o is done at %dx and not at 3125 * %edx, while gcc generates inferior code (movw instead of movl) 3126 * if we tell it to load (u_short) port. 3127 */ 3128 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 3129 return (data); 3130 } 3131 3132 void 3133 outb(u_int port, u_char data) 3134 { 3135 u_char al; 3136 /* 3137 * Use an unnecessary assignment to help gcc's register allocator. 3138 * This make a large difference for gcc-1.40 and a tiny difference 3139 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 3140 * best results. gcc-2.6.0 can't handle this. 3141 */ 3142 al = data; 3143 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 3144 } 3145 3146 #endif /* DDB */ 3147 3148 3149 3150 /* 3151 * initialize all the SMP locks 3152 */ 3153 3154 /* critical region when masking or unmasking interupts */ 3155 struct spinlock_deprecated imen_spinlock; 3156 3157 /* lock region used by kernel profiling */ 3158 struct spinlock_deprecated mcount_spinlock; 3159 3160 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 3161 struct spinlock_deprecated com_spinlock; 3162 3163 /* lock regions around the clock hardware */ 3164 struct spinlock_deprecated clock_spinlock; 3165 3166 static void 3167 init_locks(void) 3168 { 3169 /* 3170 * Get the initial mplock with a count of 1 for the BSP. 3171 * This uses a LOGICAL cpu ID, ie BSP == 0. 3172 */ 3173 cpu_get_initial_mplock(); 3174 /* DEPRECATED */ 3175 spin_init_deprecated(&mcount_spinlock); 3176 spin_init_deprecated(&imen_spinlock); 3177 spin_init_deprecated(&com_spinlock); 3178 spin_init_deprecated(&clock_spinlock); 3179 3180 /* our token pool needs to work early */ 3181 lwkt_token_pool_init(); 3182 } 3183 3184 boolean_t 3185 cpu_mwait_hint_valid(uint32_t hint) 3186 { 3187 int cx_idx, sub; 3188 3189 cx_idx = MWAIT_EAX_TO_CX(hint); 3190 if (cx_idx >= CPU_MWAIT_CX_MAX) 3191 return FALSE; 3192 3193 sub = MWAIT_EAX_TO_CX_SUB(hint); 3194 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3195 return FALSE; 3196 3197 return TRUE; 3198 } 3199 3200 void 3201 cpu_mwait_cx_no_bmsts(void) 3202 { 3203 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3204 } 3205 3206 void 3207 cpu_mwait_cx_no_bmarb(void) 3208 { 3209 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3210 } 3211 3212 static int 3213 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3214 { 3215 int old_cx_idx, sub = 0; 3216 3217 if (hint >= 0) { 3218 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3219 sub = MWAIT_EAX_TO_CX_SUB(hint); 3220 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3221 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3222 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3223 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3224 } else { 3225 old_cx_idx = CPU_MWAIT_CX_MAX; 3226 } 3227 3228 if (!CPU_MWAIT_HAS_CX) 3229 strlcpy(name, "NONE", namelen); 3230 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3231 strlcpy(name, "AUTO", namelen); 3232 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3233 strlcpy(name, "AUTODEEP", namelen); 3234 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3235 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3236 strlcpy(name, "INVALID", namelen); 3237 else 3238 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3239 3240 return old_cx_idx; 3241 } 3242 3243 static int 3244 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3245 { 3246 int cx_idx, sub, hint; 3247 char *ptr, *start; 3248 3249 if (allow_auto && strcmp(name, "AUTO") == 0) { 3250 hint = CPU_MWAIT_HINT_AUTO; 3251 cx_idx = CPU_MWAIT_C2; 3252 goto done; 3253 } 3254 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3255 hint = CPU_MWAIT_HINT_AUTODEEP; 3256 cx_idx = CPU_MWAIT_C3; 3257 goto done; 3258 } 3259 3260 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3261 return -1; 3262 start = &name[1]; 3263 ptr = NULL; 3264 3265 cx_idx = strtol(start, &ptr, 10); 3266 if (ptr == start || *ptr != '/') 3267 return -1; 3268 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3269 return -1; 3270 3271 start = ptr + 1; 3272 ptr = NULL; 3273 3274 sub = strtol(start, &ptr, 10); 3275 if (*ptr != '\0') 3276 return -1; 3277 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3278 return -1; 3279 3280 hint = MWAIT_EAX_HINT(cx_idx, sub); 3281 done: 3282 *hint0 = hint; 3283 return cx_idx; 3284 } 3285 3286 static int 3287 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3288 { 3289 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3290 return EOPNOTSUPP; 3291 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3292 int error; 3293 3294 error = cputimer_intr_powersave_addreq(); 3295 if (error) 3296 return error; 3297 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3298 cputimer_intr_powersave_remreq(); 3299 } 3300 return 0; 3301 } 3302 3303 static int 3304 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3305 boolean_t allow_auto) 3306 { 3307 int error, cx_idx, old_cx_idx, hint; 3308 char name[CPU_MWAIT_CX_NAMELEN]; 3309 3310 hint = *hint0; 3311 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3312 allow_auto); 3313 3314 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3315 if (error != 0 || req->newptr == NULL) 3316 return error; 3317 3318 if (!CPU_MWAIT_HAS_CX) 3319 return EOPNOTSUPP; 3320 3321 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3322 if (cx_idx < 0) 3323 return EINVAL; 3324 3325 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3326 if (error) 3327 return error; 3328 3329 *hint0 = hint; 3330 return 0; 3331 } 3332 3333 static int 3334 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3335 { 3336 int error, cx_idx, old_cx_idx, hint; 3337 char name[CPU_MWAIT_CX_NAMELEN]; 3338 3339 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3340 3341 hint = stat->hint; 3342 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3343 3344 strlcpy(name, cx_name, sizeof(name)); 3345 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3346 if (cx_idx < 0) 3347 return EINVAL; 3348 3349 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3350 if (error) 3351 return error; 3352 3353 stat->hint = hint; 3354 return 0; 3355 } 3356 3357 static int 3358 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3359 { 3360 int hint = cpu_mwait_halt_global; 3361 int error, cx_idx, cpu; 3362 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3363 3364 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3365 3366 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3367 if (error != 0 || req->newptr == NULL) 3368 return error; 3369 3370 if (!CPU_MWAIT_HAS_CX) 3371 return EOPNOTSUPP; 3372 3373 /* Save name for later per-cpu CX configuration */ 3374 strlcpy(cx_name, name, sizeof(cx_name)); 3375 3376 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3377 if (cx_idx < 0) 3378 return EINVAL; 3379 3380 /* Change per-cpu CX configuration */ 3381 for (cpu = 0; cpu < ncpus; ++cpu) { 3382 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3383 if (error) 3384 return error; 3385 } 3386 3387 cpu_mwait_halt_global = hint; 3388 return 0; 3389 } 3390 3391 static int 3392 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3393 { 3394 struct cpu_idle_stat *stat = arg1; 3395 int error; 3396 3397 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3398 &stat->hint, TRUE); 3399 return error; 3400 } 3401 3402 static int 3403 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3404 { 3405 int error; 3406 3407 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3408 &cpu_mwait_spin, FALSE); 3409 return error; 3410 } 3411 3412 /* 3413 * This manual debugging code is called unconditionally from Xtimer 3414 * (the per-cpu timer interrupt) whether the current thread is in a 3415 * critical section or not) and can be useful in tracking down lockups. 3416 * 3417 * NOTE: MANUAL DEBUG CODE 3418 */ 3419 #if 0 3420 static int saveticks[SMP_MAXCPU]; 3421 static int savecounts[SMP_MAXCPU]; 3422 #endif 3423 3424 void 3425 pcpu_timer_always(struct intrframe *frame) 3426 { 3427 #if 0 3428 globaldata_t gd = mycpu; 3429 int cpu = gd->gd_cpuid; 3430 char buf[64]; 3431 short *gptr; 3432 int i; 3433 3434 if (cpu <= 20) { 3435 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3436 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3437 ++gptr; 3438 3439 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3440 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3441 gd->gd_infomsg); 3442 for (i = 0; buf[i]; ++i) { 3443 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3444 } 3445 } 3446 #if 0 3447 if (saveticks[gd->gd_cpuid] != ticks) { 3448 saveticks[gd->gd_cpuid] = ticks; 3449 savecounts[gd->gd_cpuid] = 0; 3450 } 3451 ++savecounts[gd->gd_cpuid]; 3452 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3453 panic("cpud %d panicing on ticks failure", 3454 gd->gd_cpuid); 3455 } 3456 for (i = 0; i < ncpus; ++i) { 3457 int delta; 3458 if (saveticks[i] && panicstr == NULL) { 3459 delta = saveticks[i] - ticks; 3460 if (delta < -10 || delta > 10) { 3461 panic("cpu %d panicing on cpu %d watchdog", 3462 gd->gd_cpuid, i); 3463 } 3464 } 3465 } 3466 #endif 3467 #endif 3468 } 3469