1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_directio.h" 48 #include "opt_inet.h" 49 #include "opt_msgbuf.h" 50 #include "opt_swap.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysproto.h> 55 #include <sys/signalvar.h> 56 #include <sys/kernel.h> 57 #include <sys/linker.h> 58 #include <sys/malloc.h> 59 #include <sys/proc.h> 60 #include <sys/priv.h> 61 #include <sys/buf.h> 62 #include <sys/reboot.h> 63 #include <sys/mbuf.h> 64 #include <sys/msgbuf.h> 65 #include <sys/sysent.h> 66 #include <sys/sysctl.h> 67 #include <sys/vmmeter.h> 68 #include <sys/bus.h> 69 #include <sys/usched.h> 70 #include <sys/reg.h> 71 #include <sys/sbuf.h> 72 #include <sys/ctype.h> 73 #include <sys/serialize.h> 74 #include <sys/systimer.h> 75 76 #include <vm/vm.h> 77 #include <vm/vm_param.h> 78 #include <sys/lock.h> 79 #include <vm/vm_kern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_page.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/vm_extern.h> 85 86 #include <sys/thread2.h> 87 #include <sys/mplock2.h> 88 #include <sys/mutex2.h> 89 90 #include <sys/user.h> 91 #include <sys/exec.h> 92 #include <sys/cons.h> 93 94 #include <sys/efi.h> 95 96 #include <ddb/ddb.h> 97 98 #include <machine/cpu.h> 99 #include <machine/clock.h> 100 #include <machine/specialreg.h> 101 #if 0 /* JG */ 102 #include <machine/bootinfo.h> 103 #endif 104 #include <machine/md_var.h> 105 #include <machine/metadata.h> 106 #include <machine/pc/bios.h> 107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 108 #include <machine/globaldata.h> /* CPU_prvspace */ 109 #include <machine/smp.h> 110 #include <machine/cputypes.h> 111 #include <machine/intr_machdep.h> 112 #include <machine/framebuffer.h> 113 114 #ifdef OLD_BUS_ARCH 115 #include <bus/isa/isa_device.h> 116 #endif 117 #include <machine_base/isa/isa_intr.h> 118 #include <bus/isa/rtc.h> 119 #include <sys/random.h> 120 #include <sys/ptrace.h> 121 #include <machine/sigframe.h> 122 123 #include <sys/machintr.h> 124 #include <machine_base/icu/icu_abi.h> 125 #include <machine_base/icu/elcr_var.h> 126 #include <machine_base/apic/lapic.h> 127 #include <machine_base/apic/ioapic.h> 128 #include <machine_base/apic/ioapic_abi.h> 129 #include <machine/mptable.h> 130 131 #define PHYSMAP_ENTRIES 10 132 133 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 134 135 extern void printcpuinfo(void); /* XXX header file */ 136 extern void identify_cpu(void); 137 #if 0 /* JG */ 138 extern void finishidentcpu(void); 139 #endif 140 extern void panicifcpuunsupported(void); 141 142 static void cpu_startup(void *); 143 static void pic_finish(void *); 144 static void cpu_finish(void *); 145 146 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 147 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 148 #ifdef DIRECTIO 149 extern void ffs_rawread_setup(void); 150 #endif /* DIRECTIO */ 151 static void init_locks(void); 152 153 extern void pcpu_timer_always(struct intrframe *); 154 155 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 156 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 157 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 158 159 #ifdef DDB 160 extern vm_offset_t ksym_start, ksym_end; 161 #endif 162 163 struct privatespace CPU_prvspace_bsp __aligned(4096); 164 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 165 166 vm_paddr_t efi_systbl_phys; 167 int _udatasel, _ucodesel, _ucode32sel; 168 u_long atdevbase; 169 int64_t tsc_offsets[MAXCPU]; 170 cpumask_t smp_idleinvl_mask; 171 cpumask_t smp_idleinvl_reqs; 172 173 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 174 175 #if defined(SWTCH_OPTIM_STATS) 176 extern int swtch_optim_stats; 177 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 178 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 179 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 180 CTLFLAG_RD, &tlb_flush_count, 0, ""); 181 #endif 182 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 183 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 184 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0, 185 "monitor/mwait target state"); 186 187 #define CPU_MWAIT_HAS_CX \ 188 ((cpu_feature2 & CPUID2_MON) && \ 189 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 190 191 #define CPU_MWAIT_CX_NAMELEN 16 192 193 #define CPU_MWAIT_C1 1 194 #define CPU_MWAIT_C2 2 195 #define CPU_MWAIT_C3 3 196 #define CPU_MWAIT_CX_MAX 8 197 198 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 199 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 200 201 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 202 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 203 204 struct cpu_mwait_cx { 205 int subcnt; 206 char name[4]; 207 struct sysctl_ctx_list sysctl_ctx; 208 struct sysctl_oid *sysctl_tree; 209 }; 210 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 211 static char cpu_mwait_cx_supported[256]; 212 213 static int cpu_mwait_c1_hints_cnt; 214 static int cpu_mwait_hints_cnt; 215 static int *cpu_mwait_hints; 216 217 static int cpu_mwait_deep_hints_cnt; 218 static int *cpu_mwait_deep_hints; 219 220 #define CPU_IDLE_REPEAT_DEFAULT 750 221 222 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 223 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 224 static u_int cpu_mwait_repeat_shift = 1; 225 226 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 227 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 228 229 static int cpu_mwait_c3_preamble = 230 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 231 CPU_MWAIT_C3_PREAMBLE_BM_STS; 232 233 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 234 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 235 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 236 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 237 238 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 239 int *, boolean_t); 240 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 241 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 242 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 243 244 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 245 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 246 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 247 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 248 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 249 &cpu_mwait_repeat_shift, 0, ""); 250 251 long physmem = 0; 252 253 u_long ebda_addr = 0; 254 255 int imcr_present = 0; 256 257 int naps = 0; /* # of Applications processors */ 258 259 u_int base_memory; 260 struct mtx dt_lock; /* lock for GDT and LDT */ 261 262 static int 263 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 264 { 265 u_long pmem = ctob(physmem); 266 267 int error = sysctl_handle_long(oidp, &pmem, 0, req); 268 return (error); 269 } 270 271 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 272 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 273 274 static int 275 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 276 { 277 int error = sysctl_handle_int(oidp, 0, 278 ctob(physmem - vmstats.v_wire_count), req); 279 return (error); 280 } 281 282 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 283 0, 0, sysctl_hw_usermem, "IU", ""); 284 285 static int 286 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 287 { 288 int error = sysctl_handle_int(oidp, 0, 289 x86_64_btop(avail_end - avail_start), req); 290 return (error); 291 } 292 293 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 294 0, 0, sysctl_hw_availpages, "I", ""); 295 296 vm_paddr_t Maxmem; 297 vm_paddr_t Realmem; 298 299 /* 300 * The number of PHYSMAP entries must be one less than the number of 301 * PHYSSEG entries because the PHYSMAP entry that spans the largest 302 * physical address that is accessible by ISA DMA is split into two 303 * PHYSSEG entries. 304 */ 305 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 306 307 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 308 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 309 310 /* must be 2 less so 0 0 can signal end of chunks */ 311 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2) 312 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2) 313 314 static vm_offset_t buffer_sva, buffer_eva; 315 vm_offset_t clean_sva, clean_eva; 316 static vm_offset_t pager_sva, pager_eva; 317 static struct trapframe proc0_tf; 318 319 static void 320 cpu_startup(void *dummy) 321 { 322 caddr_t v; 323 vm_size_t size = 0; 324 vm_offset_t firstaddr; 325 326 /* 327 * Good {morning,afternoon,evening,night}. 328 */ 329 kprintf("%s", version); 330 startrtclock(); 331 printcpuinfo(); 332 panicifcpuunsupported(); 333 kprintf("real memory = %ju (%ju MB)\n", 334 (intmax_t)Realmem, 335 (intmax_t)Realmem / 1024 / 1024); 336 /* 337 * Display any holes after the first chunk of extended memory. 338 */ 339 if (bootverbose) { 340 int indx; 341 342 kprintf("Physical memory chunk(s):\n"); 343 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 344 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx]; 345 346 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 347 (intmax_t)phys_avail[indx], 348 (intmax_t)phys_avail[indx + 1] - 1, 349 (intmax_t)size1, 350 (intmax_t)(size1 / PAGE_SIZE)); 351 } 352 } 353 354 /* 355 * Allocate space for system data structures. 356 * The first available kernel virtual address is in "v". 357 * As pages of kernel virtual memory are allocated, "v" is incremented. 358 * As pages of memory are allocated and cleared, 359 * "firstaddr" is incremented. 360 * An index into the kernel page table corresponding to the 361 * virtual memory address maintained in "v" is kept in "mapaddr". 362 */ 363 364 /* 365 * Make two passes. The first pass calculates how much memory is 366 * needed and allocates it. The second pass assigns virtual 367 * addresses to the various data structures. 368 */ 369 firstaddr = 0; 370 again: 371 v = (caddr_t)firstaddr; 372 373 #define valloc(name, type, num) \ 374 (name) = (type *)v; v = (caddr_t)((name)+(num)) 375 #define valloclim(name, type, num, lim) \ 376 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 377 378 /* 379 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 380 * For the first 64MB of ram nominally allocate sufficient buffers to 381 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 382 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 383 * the buffer cache we limit the eventual kva reservation to 384 * maxbcache bytes. 385 * 386 * factor represents the 1/4 x ram conversion. 387 */ 388 if (nbuf == 0) { 389 long factor = 4 * NBUFCALCSIZE / 1024; 390 long kbytes = physmem * (PAGE_SIZE / 1024); 391 392 nbuf = 50; 393 if (kbytes > 4096) 394 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 395 if (kbytes > 65536) 396 nbuf += (kbytes - 65536) * 2 / (factor * 5); 397 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 398 nbuf = maxbcache / NBUFCALCSIZE; 399 } 400 401 /* 402 * Do not allow the buffer_map to be more then 1/2 the size of the 403 * kernel_map. 404 */ 405 if (nbuf > (virtual_end - virtual_start + 406 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 407 nbuf = (virtual_end - virtual_start + 408 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 409 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 410 } 411 412 /* 413 * Do not allow the buffer_map to use more than 50% of available 414 * physical-equivalent memory. Since the VM pages which back 415 * individual buffers are typically wired, having too many bufs 416 * can prevent the system from paging properly. 417 */ 418 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 419 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 420 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 421 } 422 423 /* 424 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 425 * the valloc space which is just the virtual_end - virtual_start 426 * section. We use valloc() to allocate the buf header array. 427 */ 428 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 429 nbuf = (virtual_end - virtual_start) / 430 sizeof(struct buf) / 2; 431 kprintf("Warning: nbufs capped at %ld due to valloc " 432 "considerations\n", nbuf); 433 } 434 435 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 436 #ifdef NSWBUF_MIN 437 if (nswbuf_mem < NSWBUF_MIN) 438 nswbuf_mem = NSWBUF_MIN; 439 #endif 440 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 441 #ifdef NSWBUF_MIN 442 if (nswbuf_kva < NSWBUF_MIN) 443 nswbuf_kva = NSWBUF_MIN; 444 #endif 445 #ifdef DIRECTIO 446 ffs_rawread_setup(); 447 #endif 448 449 valloc(swbuf_mem, struct buf, nswbuf_mem); 450 valloc(swbuf_kva, struct buf, nswbuf_kva); 451 valloc(buf, struct buf, nbuf); 452 453 /* 454 * End of first pass, size has been calculated so allocate memory 455 */ 456 if (firstaddr == 0) { 457 size = (vm_size_t)(v - firstaddr); 458 firstaddr = kmem_alloc(&kernel_map, round_page(size)); 459 if (firstaddr == 0) 460 panic("startup: no room for tables"); 461 goto again; 462 } 463 464 /* 465 * End of second pass, addresses have been assigned 466 * 467 * nbuf is an int, make sure we don't overflow the field. 468 * 469 * On 64-bit systems we always reserve maximal allocations for 470 * buffer cache buffers and there are no fragmentation issues, 471 * so the KVA segment does not have to be excessively oversized. 472 */ 473 if ((vm_size_t)(v - firstaddr) != size) 474 panic("startup: table size inconsistency"); 475 476 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 477 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 478 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 479 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 480 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 481 buffer_map.system_map = 1; 482 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 483 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 484 pager_map_size); 485 pager_map.system_map = 1; 486 kprintf("avail memory = %ju (%ju MB)\n", 487 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 488 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 489 1024 / 1024); 490 } 491 492 struct cpu_idle_stat { 493 int hint; 494 int reserved; 495 u_long halt; 496 u_long spin; 497 u_long repeat; 498 u_long repeat_last; 499 u_long repeat_delta; 500 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 501 } __cachealign; 502 503 #define CPU_IDLE_STAT_HALT -1 504 #define CPU_IDLE_STAT_SPIN -2 505 506 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 507 508 static int 509 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 510 { 511 int idx = arg2, cpu, error; 512 u_long val = 0; 513 514 if (idx == CPU_IDLE_STAT_HALT) { 515 for (cpu = 0; cpu < ncpus; ++cpu) 516 val += cpu_idle_stats[cpu].halt; 517 } else if (idx == CPU_IDLE_STAT_SPIN) { 518 for (cpu = 0; cpu < ncpus; ++cpu) 519 val += cpu_idle_stats[cpu].spin; 520 } else { 521 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 522 ("invalid index %d", idx)); 523 for (cpu = 0; cpu < ncpus; ++cpu) 524 val += cpu_idle_stats[cpu].mwait_cx[idx]; 525 } 526 527 error = sysctl_handle_quad(oidp, &val, 0, req); 528 if (error || req->newptr == NULL) 529 return error; 530 531 if (idx == CPU_IDLE_STAT_HALT) { 532 for (cpu = 0; cpu < ncpus; ++cpu) 533 cpu_idle_stats[cpu].halt = 0; 534 cpu_idle_stats[0].halt = val; 535 } else if (idx == CPU_IDLE_STAT_SPIN) { 536 for (cpu = 0; cpu < ncpus; ++cpu) 537 cpu_idle_stats[cpu].spin = 0; 538 cpu_idle_stats[0].spin = val; 539 } else { 540 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 541 ("invalid index %d", idx)); 542 for (cpu = 0; cpu < ncpus; ++cpu) 543 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 544 cpu_idle_stats[0].mwait_cx[idx] = val; 545 } 546 return 0; 547 } 548 549 static void 550 cpu_mwait_attach(void) 551 { 552 struct sbuf sb; 553 int hint_idx, i; 554 555 if (!CPU_MWAIT_HAS_CX) 556 return; 557 558 if (cpu_vendor_id == CPU_VENDOR_INTEL && 559 (CPUID_TO_FAMILY(cpu_id) > 0xf || 560 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 561 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 562 int bm_sts = 1; 563 564 /* 565 * Pentium dual-core, Core 2 and beyond do not need any 566 * additional activities to enter deep C-state, i.e. C3(+). 567 */ 568 cpu_mwait_cx_no_bmarb(); 569 570 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 571 if (!bm_sts) 572 cpu_mwait_cx_no_bmsts(); 573 } 574 575 sbuf_new(&sb, cpu_mwait_cx_supported, 576 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 577 578 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 579 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 580 int sub; 581 582 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 583 584 sysctl_ctx_init(&cx->sysctl_ctx); 585 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 586 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 587 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 588 if (cx->sysctl_tree == NULL) 589 continue; 590 591 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 592 SYSCTL_ADD_INT(&cx->sysctl_ctx, 593 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 594 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 595 "sub-state count"); 596 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 597 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 598 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 599 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 600 601 for (sub = 0; sub < cx->subcnt; ++sub) 602 sbuf_printf(&sb, "C%d/%d ", i, sub); 603 } 604 sbuf_trim(&sb); 605 sbuf_finish(&sb); 606 607 /* 608 * Non-deep C-states 609 */ 610 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 611 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 612 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 613 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 614 M_DEVBUF, M_WAITOK); 615 616 hint_idx = 0; 617 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 618 int j, subcnt; 619 620 subcnt = cpu_mwait_cx_info[i].subcnt; 621 for (j = 0; j < subcnt; ++j) { 622 KASSERT(hint_idx < cpu_mwait_hints_cnt, 623 ("invalid mwait hint index %d", hint_idx)); 624 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 625 ++hint_idx; 626 } 627 } 628 KASSERT(hint_idx == cpu_mwait_hints_cnt, 629 ("mwait hint count %d != index %d", 630 cpu_mwait_hints_cnt, hint_idx)); 631 632 if (bootverbose) { 633 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 634 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 635 int hint = cpu_mwait_hints[i]; 636 637 kprintf(" C%d/%d hint 0x%04x\n", 638 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 639 hint); 640 } 641 } 642 643 /* 644 * Deep C-states 645 */ 646 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 647 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 648 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 649 M_DEVBUF, M_WAITOK); 650 651 hint_idx = 0; 652 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 653 int j, subcnt; 654 655 subcnt = cpu_mwait_cx_info[i].subcnt; 656 for (j = 0; j < subcnt; ++j) { 657 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 658 ("invalid mwait deep hint index %d", hint_idx)); 659 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 660 ++hint_idx; 661 } 662 } 663 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 664 ("mwait deep hint count %d != index %d", 665 cpu_mwait_deep_hints_cnt, hint_idx)); 666 667 if (bootverbose) { 668 kprintf("MWAIT deep hints:\n"); 669 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 670 int hint = cpu_mwait_deep_hints[i]; 671 672 kprintf(" C%d/%d hint 0x%04x\n", 673 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 674 hint); 675 } 676 } 677 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 678 679 for (i = 0; i < ncpus; ++i) { 680 char name[16]; 681 682 ksnprintf(name, sizeof(name), "idle%d", i); 683 SYSCTL_ADD_PROC(NULL, 684 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 685 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 686 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 687 } 688 } 689 690 static void 691 cpu_finish(void *dummy __unused) 692 { 693 cpu_setregs(); 694 cpu_mwait_attach(); 695 } 696 697 static void 698 pic_finish(void *dummy __unused) 699 { 700 /* Log ELCR information */ 701 elcr_dump(); 702 703 /* Log MPTABLE information */ 704 mptable_pci_int_dump(); 705 706 /* Finalize PCI */ 707 MachIntrABI.finalize(); 708 } 709 710 /* 711 * Send an interrupt to process. 712 * 713 * Stack is set up to allow sigcode stored 714 * at top to call routine, followed by kcall 715 * to sigreturn routine below. After sigreturn 716 * resets the signal mask, the stack, and the 717 * frame pointer, it returns to the user 718 * specified pc, psl. 719 */ 720 void 721 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 722 { 723 struct lwp *lp = curthread->td_lwp; 724 struct proc *p = lp->lwp_proc; 725 struct trapframe *regs; 726 struct sigacts *psp = p->p_sigacts; 727 struct sigframe sf, *sfp; 728 int oonstack; 729 char *sp; 730 731 regs = lp->lwp_md.md_regs; 732 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 733 734 /* Save user context */ 735 bzero(&sf, sizeof(struct sigframe)); 736 sf.sf_uc.uc_sigmask = *mask; 737 sf.sf_uc.uc_stack = lp->lwp_sigstk; 738 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 739 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 740 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 741 742 /* Make the size of the saved context visible to userland */ 743 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 744 745 /* Allocate and validate space for the signal handler context. */ 746 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 747 SIGISMEMBER(psp->ps_sigonstack, sig)) { 748 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 749 sizeof(struct sigframe)); 750 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 751 } else { 752 /* We take red zone into account */ 753 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 754 } 755 756 /* 757 * XXX AVX needs 64-byte alignment but sigframe has other fields and 758 * the embedded ucontext is not at the front, so aligning this won't 759 * help us. Fortunately we bcopy in/out of the sigframe, so the 760 * kernel is ok. 761 * 762 * The problem though is if userland winds up trying to use the 763 * context directly. 764 */ 765 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 766 767 /* Translate the signal is appropriate */ 768 if (p->p_sysent->sv_sigtbl) { 769 if (sig <= p->p_sysent->sv_sigsize) 770 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 771 } 772 773 /* 774 * Build the argument list for the signal handler. 775 * 776 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 777 */ 778 regs->tf_rdi = sig; /* argument 1 */ 779 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 780 781 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 782 /* 783 * Signal handler installed with SA_SIGINFO. 784 * 785 * action(signo, siginfo, ucontext) 786 */ 787 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 788 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 789 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 790 791 /* fill siginfo structure */ 792 sf.sf_si.si_signo = sig; 793 sf.sf_si.si_code = code; 794 sf.sf_si.si_addr = (void *)regs->tf_addr; 795 } else { 796 /* 797 * Old FreeBSD-style arguments. 798 * 799 * handler (signo, code, [uc], addr) 800 */ 801 regs->tf_rsi = (register_t)code; /* argument 2 */ 802 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 803 sf.sf_ahu.sf_handler = catcher; 804 } 805 806 /* 807 * If we're a vm86 process, we want to save the segment registers. 808 * We also change eflags to be our emulated eflags, not the actual 809 * eflags. 810 */ 811 #if 0 /* JG */ 812 if (regs->tf_eflags & PSL_VM) { 813 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 814 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 815 816 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 817 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 818 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 819 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 820 821 if (vm86->vm86_has_vme == 0) 822 sf.sf_uc.uc_mcontext.mc_eflags = 823 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 824 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 825 826 /* 827 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 828 * syscalls made by the signal handler. This just avoids 829 * wasting time for our lazy fixup of such faults. PSL_NT 830 * does nothing in vm86 mode, but vm86 programs can set it 831 * almost legitimately in probes for old cpu types. 832 */ 833 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 834 } 835 #endif 836 837 /* 838 * Save the FPU state and reinit the FP unit 839 */ 840 npxpush(&sf.sf_uc.uc_mcontext); 841 842 /* 843 * Copy the sigframe out to the user's stack. 844 */ 845 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 846 /* 847 * Something is wrong with the stack pointer. 848 * ...Kill the process. 849 */ 850 sigexit(lp, SIGILL); 851 } 852 853 regs->tf_rsp = (register_t)sfp; 854 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 855 856 /* 857 * i386 abi specifies that the direction flag must be cleared 858 * on function entry 859 */ 860 regs->tf_rflags &= ~(PSL_T|PSL_D); 861 862 /* 863 * 64 bit mode has a code and stack selector but 864 * no data or extra selector. %fs and %gs are not 865 * stored in-context. 866 */ 867 regs->tf_cs = _ucodesel; 868 regs->tf_ss = _udatasel; 869 clear_quickret(); 870 } 871 872 /* 873 * Sanitize the trapframe for a virtual kernel passing control to a custom 874 * VM context. Remove any items that would otherwise create a privilage 875 * issue. 876 * 877 * XXX at the moment we allow userland to set the resume flag. Is this a 878 * bad idea? 879 */ 880 int 881 cpu_sanitize_frame(struct trapframe *frame) 882 { 883 frame->tf_cs = _ucodesel; 884 frame->tf_ss = _udatasel; 885 /* XXX VM (8086) mode not supported? */ 886 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 887 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 888 889 return(0); 890 } 891 892 /* 893 * Sanitize the tls so loading the descriptor does not blow up 894 * on us. For x86_64 we don't have to do anything. 895 */ 896 int 897 cpu_sanitize_tls(struct savetls *tls) 898 { 899 return(0); 900 } 901 902 /* 903 * sigreturn(ucontext_t *sigcntxp) 904 * 905 * System call to cleanup state after a signal 906 * has been taken. Reset signal mask and 907 * stack state from context left by sendsig (above). 908 * Return to previous pc and psl as specified by 909 * context left by sendsig. Check carefully to 910 * make sure that the user has not modified the 911 * state to gain improper privileges. 912 * 913 * MPSAFE 914 */ 915 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 916 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 917 918 int 919 sys_sigreturn(struct sigreturn_args *uap) 920 { 921 struct lwp *lp = curthread->td_lwp; 922 struct trapframe *regs; 923 ucontext_t uc; 924 ucontext_t *ucp; 925 register_t rflags; 926 int cs; 927 int error; 928 929 /* 930 * We have to copy the information into kernel space so userland 931 * can't modify it while we are sniffing it. 932 */ 933 regs = lp->lwp_md.md_regs; 934 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 935 if (error) 936 return (error); 937 ucp = &uc; 938 rflags = ucp->uc_mcontext.mc_rflags; 939 940 /* VM (8086) mode not supported */ 941 rflags &= ~PSL_VM_UNSUPP; 942 943 #if 0 /* JG */ 944 if (eflags & PSL_VM) { 945 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 946 struct vm86_kernel *vm86; 947 948 /* 949 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 950 * set up the vm86 area, and we can't enter vm86 mode. 951 */ 952 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 953 return (EINVAL); 954 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 955 if (vm86->vm86_inited == 0) 956 return (EINVAL); 957 958 /* go back to user mode if both flags are set */ 959 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 960 trapsignal(lp, SIGBUS, 0); 961 962 if (vm86->vm86_has_vme) { 963 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 964 (eflags & VME_USERCHANGE) | PSL_VM; 965 } else { 966 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 967 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 968 (eflags & VM_USERCHANGE) | PSL_VM; 969 } 970 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 971 tf->tf_eflags = eflags; 972 tf->tf_vm86_ds = tf->tf_ds; 973 tf->tf_vm86_es = tf->tf_es; 974 tf->tf_vm86_fs = tf->tf_fs; 975 tf->tf_vm86_gs = tf->tf_gs; 976 tf->tf_ds = _udatasel; 977 tf->tf_es = _udatasel; 978 tf->tf_fs = _udatasel; 979 tf->tf_gs = _udatasel; 980 } else 981 #endif 982 { 983 /* 984 * Don't allow users to change privileged or reserved flags. 985 */ 986 /* 987 * XXX do allow users to change the privileged flag PSL_RF. 988 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 989 * should sometimes set it there too. tf_eflags is kept in 990 * the signal context during signal handling and there is no 991 * other place to remember it, so the PSL_RF bit may be 992 * corrupted by the signal handler without us knowing. 993 * Corruption of the PSL_RF bit at worst causes one more or 994 * one less debugger trap, so allowing it is fairly harmless. 995 */ 996 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 997 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 998 return(EINVAL); 999 } 1000 1001 /* 1002 * Don't allow users to load a valid privileged %cs. Let the 1003 * hardware check for invalid selectors, excess privilege in 1004 * other selectors, invalid %eip's and invalid %esp's. 1005 */ 1006 cs = ucp->uc_mcontext.mc_cs; 1007 if (!CS_SECURE(cs)) { 1008 kprintf("sigreturn: cs = 0x%x\n", cs); 1009 trapsignal(lp, SIGBUS, T_PROTFLT); 1010 return(EINVAL); 1011 } 1012 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1013 } 1014 1015 /* 1016 * Restore the FPU state from the frame 1017 */ 1018 crit_enter(); 1019 npxpop(&ucp->uc_mcontext); 1020 1021 if (ucp->uc_mcontext.mc_onstack & 1) 1022 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1023 else 1024 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1025 1026 lp->lwp_sigmask = ucp->uc_sigmask; 1027 SIG_CANTMASK(lp->lwp_sigmask); 1028 clear_quickret(); 1029 crit_exit(); 1030 return(EJUSTRETURN); 1031 } 1032 1033 /* 1034 * Machine dependent boot() routine 1035 * 1036 * I haven't seen anything to put here yet 1037 * Possibly some stuff might be grafted back here from boot() 1038 */ 1039 void 1040 cpu_boot(int howto) 1041 { 1042 } 1043 1044 /* 1045 * Shutdown the CPU as much as possible 1046 */ 1047 void 1048 cpu_halt(void) 1049 { 1050 for (;;) 1051 __asm__ __volatile("hlt"); 1052 } 1053 1054 /* 1055 * cpu_idle() represents the idle LWKT. You cannot return from this function 1056 * (unless you want to blow things up!). Instead we look for runnable threads 1057 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1058 * 1059 * The main loop is entered with a critical section held, we must release 1060 * the critical section before doing anything else. lwkt_switch() will 1061 * check for pending interrupts due to entering and exiting its own 1062 * critical section. 1063 * 1064 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1065 * However, there are cases where the idlethread will be entered with 1066 * the possibility that no IPI will occur and in such cases 1067 * lwkt_switch() sets TDF_IDLE_NOHLT. 1068 * 1069 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1070 * must occur before it starts using ACPI halt. 1071 * 1072 * NOTE: Value overridden in hammer_time(). 1073 */ 1074 static int cpu_idle_hlt = 2; 1075 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1076 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1077 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1078 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1079 1080 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1081 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1082 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1083 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1084 1085 static void 1086 cpu_idle_default_hook(void) 1087 { 1088 /* 1089 * We must guarentee that hlt is exactly the instruction 1090 * following the sti. 1091 */ 1092 __asm __volatile("sti; hlt"); 1093 } 1094 1095 /* Other subsystems (e.g., ACPI) can hook this later. */ 1096 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1097 1098 static __inline int 1099 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1100 { 1101 int hint, cx_idx; 1102 u_int idx; 1103 1104 hint = stat->hint; 1105 if (hint >= 0) 1106 goto done; 1107 1108 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1109 cpu_mwait_repeat_shift; 1110 if (idx >= cpu_mwait_c1_hints_cnt) { 1111 /* Step up faster, once we walked through all C1 states */ 1112 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1113 } 1114 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1115 if (idx >= cpu_mwait_deep_hints_cnt) 1116 idx = cpu_mwait_deep_hints_cnt - 1; 1117 hint = cpu_mwait_deep_hints[idx]; 1118 } else { 1119 if (idx >= cpu_mwait_hints_cnt) 1120 idx = cpu_mwait_hints_cnt - 1; 1121 hint = cpu_mwait_hints[idx]; 1122 } 1123 done: 1124 cx_idx = MWAIT_EAX_TO_CX(hint); 1125 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1126 stat->mwait_cx[cx_idx]++; 1127 return hint; 1128 } 1129 1130 void 1131 cpu_idle(void) 1132 { 1133 globaldata_t gd = mycpu; 1134 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1135 struct thread *td __debugvar = gd->gd_curthread; 1136 int reqflags; 1137 int quick; 1138 1139 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1140 1141 crit_exit(); 1142 KKASSERT(td->td_critcount == 0); 1143 1144 for (;;) { 1145 /* 1146 * See if there are any LWKTs ready to go. 1147 */ 1148 lwkt_switch(); 1149 1150 /* 1151 * When halting inside a cli we must check for reqflags 1152 * races, particularly [re]schedule requests. Running 1153 * splz() does the job. 1154 * 1155 * cpu_idle_hlt: 1156 * 0 Never halt, just spin 1157 * 1158 * 1 Always use HLT (or MONITOR/MWAIT if avail). 1159 * 1160 * Better default for modern (Haswell+) Intel 1161 * cpus. 1162 * 1163 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1164 * use the ACPI halt (default). This is a hybrid 1165 * approach. See machdep.cpu_idle_repeat. 1166 * 1167 * Better default for modern AMD cpus and older 1168 * Intel cpus. 1169 * 1170 * 3 Always use the ACPI halt. This typically 1171 * eats the least amount of power but the cpu 1172 * will be slow waking up. Slows down e.g. 1173 * compiles and other pipe/event oriented stuff. 1174 * 1175 * 4 Always use HLT. 1176 * 1177 * NOTE: Interrupts are enabled and we are not in a critical 1178 * section. 1179 * 1180 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1181 * don't bother capping gd_idle_repeat, it is ok if 1182 * it overflows. 1183 * 1184 * Implement optimized invltlb operations when halted 1185 * in idle. By setting the bit in smp_idleinvl_mask 1186 * we inform other cpus that they can set _reqs to 1187 * request an invltlb. Current the code to do that 1188 * sets the bits in _reqs anyway, but then check _mask 1189 * to determine if they can assume the invltlb will execute. 1190 * 1191 * A critical section is required to ensure that interrupts 1192 * do not fully run until after we've had a chance to execute 1193 * the request. 1194 */ 1195 if (gd->gd_idle_repeat == 0) { 1196 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1197 if (stat->repeat > cpu_idle_repeat_max) 1198 stat->repeat = cpu_idle_repeat_max; 1199 stat->repeat_last = 0; 1200 stat->repeat_delta = 0; 1201 } 1202 ++stat->repeat_last; 1203 1204 ++gd->gd_idle_repeat; 1205 reqflags = gd->gd_reqflags; 1206 quick = (cpu_idle_hlt == 1) || 1207 (cpu_idle_hlt < 3 && 1208 gd->gd_idle_repeat < cpu_idle_repeat); 1209 1210 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1211 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1212 splz(); /* XXX */ 1213 crit_enter_gd(gd); 1214 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1215 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1216 cpu_mwait_cx_hint(stat), 0); 1217 stat->halt++; 1218 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1219 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1220 gd->gd_cpuid)) { 1221 cpu_invltlb(); 1222 cpu_mfence(); 1223 } 1224 crit_exit_gd(gd); 1225 } else if (cpu_idle_hlt) { 1226 __asm __volatile("cli"); 1227 splz(); 1228 crit_enter_gd(gd); 1229 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1230 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1231 if (quick) 1232 cpu_idle_default_hook(); 1233 else 1234 cpu_idle_hook(); 1235 } 1236 __asm __volatile("sti"); 1237 stat->halt++; 1238 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1239 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1240 gd->gd_cpuid)) { 1241 cpu_invltlb(); 1242 cpu_mfence(); 1243 } 1244 crit_exit_gd(gd); 1245 } else { 1246 splz(); 1247 __asm __volatile("sti"); 1248 stat->spin++; 1249 } 1250 } 1251 } 1252 1253 /* 1254 * Called in a loop indirectly via Xcpustop 1255 */ 1256 void 1257 cpu_smp_stopped(void) 1258 { 1259 globaldata_t gd = mycpu; 1260 volatile __uint64_t *ptr; 1261 __uint64_t ovalue; 1262 1263 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1264 ovalue = *ptr; 1265 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1266 if (cpu_mi_feature & CPU_MI_MONITOR) { 1267 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), ovalue, 1268 cpu_mwait_hints[CPU_MWAIT_C1], 0); 1269 } else { 1270 cpu_halt(); /* depend on lapic timer */ 1271 } 1272 } 1273 } 1274 1275 /* 1276 * This routine is called if a spinlock has been held through the 1277 * exponential backoff period and is seriously contested. On a real cpu 1278 * we let it spin. 1279 */ 1280 void 1281 cpu_spinlock_contested(void) 1282 { 1283 cpu_pause(); 1284 } 1285 1286 /* 1287 * Clear registers on exec 1288 */ 1289 void 1290 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1291 { 1292 struct thread *td = curthread; 1293 struct lwp *lp = td->td_lwp; 1294 struct pcb *pcb = td->td_pcb; 1295 struct trapframe *regs = lp->lwp_md.md_regs; 1296 1297 /* was i386_user_cleanup() in NetBSD */ 1298 user_ldt_free(pcb); 1299 1300 clear_quickret(); 1301 bzero((char *)regs, sizeof(struct trapframe)); 1302 regs->tf_rip = entry; 1303 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1304 regs->tf_rdi = stack; /* argv */ 1305 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1306 regs->tf_ss = _udatasel; 1307 regs->tf_cs = _ucodesel; 1308 regs->tf_rbx = ps_strings; 1309 1310 /* 1311 * Reset the hardware debug registers if they were in use. 1312 * They won't have any meaning for the newly exec'd process. 1313 */ 1314 if (pcb->pcb_flags & PCB_DBREGS) { 1315 pcb->pcb_dr0 = 0; 1316 pcb->pcb_dr1 = 0; 1317 pcb->pcb_dr2 = 0; 1318 pcb->pcb_dr3 = 0; 1319 pcb->pcb_dr6 = 0; 1320 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1321 if (pcb == td->td_pcb) { 1322 /* 1323 * Clear the debug registers on the running 1324 * CPU, otherwise they will end up affecting 1325 * the next process we switch to. 1326 */ 1327 reset_dbregs(); 1328 } 1329 pcb->pcb_flags &= ~PCB_DBREGS; 1330 } 1331 1332 /* 1333 * Initialize the math emulator (if any) for the current process. 1334 * Actually, just clear the bit that says that the emulator has 1335 * been initialized. Initialization is delayed until the process 1336 * traps to the emulator (if it is done at all) mainly because 1337 * emulators don't provide an entry point for initialization. 1338 */ 1339 pcb->pcb_flags &= ~FP_SOFTFP; 1340 1341 /* 1342 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1343 * gd_npxthread. Otherwise a preemptive interrupt thread 1344 * may panic in npxdna(). 1345 */ 1346 crit_enter(); 1347 load_cr0(rcr0() | CR0_MP); 1348 1349 /* 1350 * NOTE: The MSR values must be correct so we can return to 1351 * userland. gd_user_fs/gs must be correct so the switch 1352 * code knows what the current MSR values are. 1353 */ 1354 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1355 pcb->pcb_gsbase = 0; 1356 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1357 mdcpu->gd_user_gs = 0; 1358 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1359 wrmsr(MSR_KGSBASE, 0); 1360 1361 /* Initialize the npx (if any) for the current process. */ 1362 npxinit(); 1363 crit_exit(); 1364 1365 pcb->pcb_ds = _udatasel; 1366 pcb->pcb_es = _udatasel; 1367 pcb->pcb_fs = _udatasel; 1368 pcb->pcb_gs = _udatasel; 1369 } 1370 1371 void 1372 cpu_setregs(void) 1373 { 1374 register_t cr0; 1375 1376 cr0 = rcr0(); 1377 cr0 |= CR0_NE; /* Done by npxinit() */ 1378 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1379 cr0 |= CR0_WP | CR0_AM; 1380 load_cr0(cr0); 1381 load_gs(_udatasel); 1382 } 1383 1384 static int 1385 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1386 { 1387 int error; 1388 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1389 req); 1390 if (!error && req->newptr) 1391 resettodr(); 1392 return (error); 1393 } 1394 1395 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1396 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1397 1398 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1399 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1400 1401 #if 0 /* JG */ 1402 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1403 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1404 #endif 1405 1406 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1407 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1408 1409 extern u_long bootdev; /* not a cdev_t - encoding is different */ 1410 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 1411 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)"); 1412 1413 static int 1414 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1415 { 1416 struct efi_map_header *efihdr; 1417 caddr_t kmdp; 1418 uint32_t efisize; 1419 1420 kmdp = preload_search_by_type("elf kernel"); 1421 if (kmdp == NULL) 1422 kmdp = preload_search_by_type("elf64 kernel"); 1423 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1424 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1425 if (efihdr == NULL) 1426 return (0); 1427 efisize = *((uint32_t *)efihdr - 1); 1428 return (SYSCTL_OUT(req, efihdr, efisize)); 1429 } 1430 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1431 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1432 1433 /* 1434 * Initialize 386 and configure to run kernel 1435 */ 1436 1437 /* 1438 * Initialize segments & interrupt table 1439 */ 1440 1441 int _default_ldt; 1442 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1443 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1444 #if 0 /* JG */ 1445 union descriptor ldt[NLDT]; /* local descriptor table */ 1446 #endif 1447 1448 /* table descriptors - used to load tables by cpu */ 1449 struct region_descriptor r_gdt; 1450 struct region_descriptor r_idt_arr[MAXCPU]; 1451 1452 /* JG proc0paddr is a virtual address */ 1453 void *proc0paddr; 1454 /* JG alignment? */ 1455 char proc0paddr_buff[LWKT_THREAD_STACK]; 1456 1457 1458 /* software prototypes -- in more palatable form */ 1459 struct soft_segment_descriptor gdt_segs[] = { 1460 /* GNULL_SEL 0 Null Descriptor */ 1461 { 0x0, /* segment base address */ 1462 0x0, /* length */ 1463 0, /* segment type */ 1464 0, /* segment descriptor priority level */ 1465 0, /* segment descriptor present */ 1466 0, /* long */ 1467 0, /* default 32 vs 16 bit size */ 1468 0 /* limit granularity (byte/page units)*/ }, 1469 /* GCODE_SEL 1 Code Descriptor for kernel */ 1470 { 0x0, /* segment base address */ 1471 0xfffff, /* length - all address space */ 1472 SDT_MEMERA, /* segment type */ 1473 SEL_KPL, /* segment descriptor priority level */ 1474 1, /* segment descriptor present */ 1475 1, /* long */ 1476 0, /* default 32 vs 16 bit size */ 1477 1 /* limit granularity (byte/page units)*/ }, 1478 /* GDATA_SEL 2 Data Descriptor for kernel */ 1479 { 0x0, /* segment base address */ 1480 0xfffff, /* length - all address space */ 1481 SDT_MEMRWA, /* segment type */ 1482 SEL_KPL, /* segment descriptor priority level */ 1483 1, /* segment descriptor present */ 1484 1, /* long */ 1485 0, /* default 32 vs 16 bit size */ 1486 1 /* limit granularity (byte/page units)*/ }, 1487 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1488 { 0x0, /* segment base address */ 1489 0xfffff, /* length - all address space */ 1490 SDT_MEMERA, /* segment type */ 1491 SEL_UPL, /* segment descriptor priority level */ 1492 1, /* segment descriptor present */ 1493 0, /* long */ 1494 1, /* default 32 vs 16 bit size */ 1495 1 /* limit granularity (byte/page units)*/ }, 1496 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1497 { 0x0, /* segment base address */ 1498 0xfffff, /* length - all address space */ 1499 SDT_MEMRWA, /* segment type */ 1500 SEL_UPL, /* segment descriptor priority level */ 1501 1, /* segment descriptor present */ 1502 0, /* long */ 1503 1, /* default 32 vs 16 bit size */ 1504 1 /* limit granularity (byte/page units)*/ }, 1505 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1506 { 0x0, /* segment base address */ 1507 0xfffff, /* length - all address space */ 1508 SDT_MEMERA, /* segment type */ 1509 SEL_UPL, /* segment descriptor priority level */ 1510 1, /* segment descriptor present */ 1511 1, /* long */ 1512 0, /* default 32 vs 16 bit size */ 1513 1 /* limit granularity (byte/page units)*/ }, 1514 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1515 { 1516 0x0, /* segment base address */ 1517 sizeof(struct x86_64tss)-1,/* length - all address space */ 1518 SDT_SYSTSS, /* segment type */ 1519 SEL_KPL, /* segment descriptor priority level */ 1520 1, /* segment descriptor present */ 1521 0, /* long */ 1522 0, /* unused - default 32 vs 16 bit size */ 1523 0 /* limit granularity (byte/page units)*/ }, 1524 /* Actually, the TSS is a system descriptor which is double size */ 1525 { 0x0, /* segment base address */ 1526 0x0, /* length */ 1527 0, /* segment type */ 1528 0, /* segment descriptor priority level */ 1529 0, /* segment descriptor present */ 1530 0, /* long */ 1531 0, /* default 32 vs 16 bit size */ 1532 0 /* limit granularity (byte/page units)*/ }, 1533 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1534 { 0x0, /* segment base address */ 1535 0xfffff, /* length - all address space */ 1536 SDT_MEMRWA, /* segment type */ 1537 SEL_UPL, /* segment descriptor priority level */ 1538 1, /* segment descriptor present */ 1539 0, /* long */ 1540 1, /* default 32 vs 16 bit size */ 1541 1 /* limit granularity (byte/page units)*/ }, 1542 }; 1543 1544 void 1545 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1546 { 1547 int cpu; 1548 1549 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1550 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1551 1552 ip->gd_looffset = (uintptr_t)func; 1553 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1554 ip->gd_ist = ist; 1555 ip->gd_xx = 0; 1556 ip->gd_type = typ; 1557 ip->gd_dpl = dpl; 1558 ip->gd_p = 1; 1559 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1560 } 1561 } 1562 1563 void 1564 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1565 { 1566 struct gate_descriptor *ip; 1567 1568 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1569 1570 ip = &idt_arr[cpu][idx]; 1571 ip->gd_looffset = (uintptr_t)func; 1572 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1573 ip->gd_ist = ist; 1574 ip->gd_xx = 0; 1575 ip->gd_type = typ; 1576 ip->gd_dpl = dpl; 1577 ip->gd_p = 1; 1578 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1579 } 1580 1581 #define IDTVEC(name) __CONCAT(X,name) 1582 1583 extern inthand_t 1584 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1585 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1586 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1587 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1588 IDTVEC(xmm), IDTVEC(dblfault), 1589 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1590 1591 void 1592 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1593 { 1594 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1595 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1596 ssd->ssd_type = sd->sd_type; 1597 ssd->ssd_dpl = sd->sd_dpl; 1598 ssd->ssd_p = sd->sd_p; 1599 ssd->ssd_def32 = sd->sd_def32; 1600 ssd->ssd_gran = sd->sd_gran; 1601 } 1602 1603 void 1604 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1605 { 1606 1607 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1608 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1609 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1610 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1611 sd->sd_type = ssd->ssd_type; 1612 sd->sd_dpl = ssd->ssd_dpl; 1613 sd->sd_p = ssd->ssd_p; 1614 sd->sd_long = ssd->ssd_long; 1615 sd->sd_def32 = ssd->ssd_def32; 1616 sd->sd_gran = ssd->ssd_gran; 1617 } 1618 1619 void 1620 ssdtosyssd(struct soft_segment_descriptor *ssd, 1621 struct system_segment_descriptor *sd) 1622 { 1623 1624 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1625 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1626 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1627 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1628 sd->sd_type = ssd->ssd_type; 1629 sd->sd_dpl = ssd->ssd_dpl; 1630 sd->sd_p = ssd->ssd_p; 1631 sd->sd_gran = ssd->ssd_gran; 1632 } 1633 1634 /* 1635 * Populate the (physmap) array with base/bound pairs describing the 1636 * available physical memory in the system, then test this memory and 1637 * build the phys_avail array describing the actually-available memory. 1638 * 1639 * If we cannot accurately determine the physical memory map, then use 1640 * value from the 0xE801 call, and failing that, the RTC. 1641 * 1642 * Total memory size may be set by the kernel environment variable 1643 * hw.physmem or the compile-time define MAXMEM. 1644 * 1645 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1646 * of PAGE_SIZE. This also greatly reduces the memory test time 1647 * which would otherwise be excessive on machines with > 8G of ram. 1648 * 1649 * XXX first should be vm_paddr_t. 1650 */ 1651 1652 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1653 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1654 vm_paddr_t physmap[PHYSMAP_SIZE]; 1655 struct bios_smap *smapbase, *smap, *smapend; 1656 struct efi_map_header *efihdrbase; 1657 u_int32_t smapsize; 1658 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1659 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1660 1661 static void 1662 add_smap_entries(int *physmap_idx) 1663 { 1664 int i; 1665 1666 smapsize = *((u_int32_t *)smapbase - 1); 1667 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1668 1669 for (smap = smapbase; smap < smapend; smap++) { 1670 if (boothowto & RB_VERBOSE) 1671 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1672 smap->type, smap->base, smap->length); 1673 1674 if (smap->type != SMAP_TYPE_MEMORY) 1675 continue; 1676 1677 if (smap->length == 0) 1678 continue; 1679 1680 for (i = 0; i <= *physmap_idx; i += 2) { 1681 if (smap->base < physmap[i + 1]) { 1682 if (boothowto & RB_VERBOSE) { 1683 kprintf("Overlapping or non-monotonic " 1684 "memory region, ignoring " 1685 "second region\n"); 1686 } 1687 break; 1688 } 1689 } 1690 if (i <= *physmap_idx) 1691 continue; 1692 1693 Realmem += smap->length; 1694 1695 if (smap->base == physmap[*physmap_idx + 1]) { 1696 physmap[*physmap_idx + 1] += smap->length; 1697 continue; 1698 } 1699 1700 *physmap_idx += 2; 1701 if (*physmap_idx == PHYSMAP_SIZE) { 1702 kprintf("Too many segments in the physical " 1703 "address map, giving up\n"); 1704 break; 1705 } 1706 physmap[*physmap_idx] = smap->base; 1707 physmap[*physmap_idx + 1] = smap->base + smap->length; 1708 } 1709 } 1710 1711 static void 1712 add_efi_map_entries(int *physmap_idx) 1713 { 1714 struct efi_md *map, *p; 1715 const char *type; 1716 size_t efisz; 1717 int i, ndesc; 1718 1719 static const char *types[] = { 1720 "Reserved", 1721 "LoaderCode", 1722 "LoaderData", 1723 "BootServicesCode", 1724 "BootServicesData", 1725 "RuntimeServicesCode", 1726 "RuntimeServicesData", 1727 "ConventionalMemory", 1728 "UnusableMemory", 1729 "ACPIReclaimMemory", 1730 "ACPIMemoryNVS", 1731 "MemoryMappedIO", 1732 "MemoryMappedIOPortSpace", 1733 "PalCode" 1734 }; 1735 1736 /* 1737 * Memory map data provided by UEFI via the GetMemoryMap 1738 * Boot Services API. 1739 */ 1740 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1741 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1742 1743 if (efihdrbase->descriptor_size == 0) 1744 return; 1745 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1746 1747 if (boothowto & RB_VERBOSE) 1748 kprintf("%23s %12s %12s %8s %4s\n", 1749 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1750 1751 for (i = 0, p = map; i < ndesc; i++, 1752 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1753 if (boothowto & RB_VERBOSE) { 1754 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1755 type = types[p->md_type]; 1756 else 1757 type = "<INVALID>"; 1758 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1759 p->md_virt, p->md_pages); 1760 if (p->md_attr & EFI_MD_ATTR_UC) 1761 kprintf("UC "); 1762 if (p->md_attr & EFI_MD_ATTR_WC) 1763 kprintf("WC "); 1764 if (p->md_attr & EFI_MD_ATTR_WT) 1765 kprintf("WT "); 1766 if (p->md_attr & EFI_MD_ATTR_WB) 1767 kprintf("WB "); 1768 if (p->md_attr & EFI_MD_ATTR_UCE) 1769 kprintf("UCE "); 1770 if (p->md_attr & EFI_MD_ATTR_WP) 1771 kprintf("WP "); 1772 if (p->md_attr & EFI_MD_ATTR_RP) 1773 kprintf("RP "); 1774 if (p->md_attr & EFI_MD_ATTR_XP) 1775 kprintf("XP "); 1776 if (p->md_attr & EFI_MD_ATTR_RT) 1777 kprintf("RUNTIME"); 1778 kprintf("\n"); 1779 } 1780 1781 switch (p->md_type) { 1782 case EFI_MD_TYPE_CODE: 1783 case EFI_MD_TYPE_DATA: 1784 case EFI_MD_TYPE_BS_CODE: 1785 case EFI_MD_TYPE_BS_DATA: 1786 case EFI_MD_TYPE_FREE: 1787 /* 1788 * We're allowed to use any entry with these types. 1789 */ 1790 break; 1791 default: 1792 continue; 1793 } 1794 1795 Realmem += p->md_pages * PAGE_SIZE; 1796 1797 if (p->md_phys == physmap[*physmap_idx + 1]) { 1798 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1799 continue; 1800 } 1801 1802 *physmap_idx += 2; 1803 if (*physmap_idx == PHYSMAP_SIZE) { 1804 kprintf("Too many segments in the physical " 1805 "address map, giving up\n"); 1806 break; 1807 } 1808 physmap[*physmap_idx] = p->md_phys; 1809 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1810 } 1811 } 1812 1813 struct fb_info efi_fb_info; 1814 static int have_efi_framebuffer = 0; 1815 1816 static void 1817 efi_fb_init_vaddr(int direct_map) 1818 { 1819 uint64_t sz; 1820 vm_offset_t addr, v; 1821 1822 v = efi_fb_info.vaddr; 1823 sz = efi_fb_info.stride * efi_fb_info.height; 1824 1825 if (direct_map) { 1826 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1827 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1828 efi_fb_info.vaddr = addr; 1829 } else { 1830 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1831 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1832 } 1833 } 1834 1835 int 1836 probe_efi_fb(int early) 1837 { 1838 struct efi_fb *efifb; 1839 caddr_t kmdp; 1840 1841 if (have_efi_framebuffer) { 1842 if (!early && 1843 (efi_fb_info.vaddr == 0 || 1844 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 1845 efi_fb_init_vaddr(0); 1846 return 0; 1847 } 1848 1849 kmdp = preload_search_by_type("elf kernel"); 1850 if (kmdp == NULL) 1851 kmdp = preload_search_by_type("elf64 kernel"); 1852 efifb = (struct efi_fb *)preload_search_info(kmdp, 1853 MODINFO_METADATA | MODINFOMD_EFI_FB); 1854 if (efifb == NULL) 1855 return 1; 1856 1857 have_efi_framebuffer = 1; 1858 1859 efi_fb_info.is_vga_boot_display = 1; 1860 efi_fb_info.width = efifb->fb_width; 1861 efi_fb_info.height = efifb->fb_height; 1862 efi_fb_info.stride = efifb->fb_stride * 4; 1863 efi_fb_info.depth = 32; 1864 efi_fb_info.paddr = efifb->fb_addr; 1865 if (early) { 1866 efi_fb_info.vaddr = 0; 1867 } else { 1868 efi_fb_init_vaddr(0); 1869 } 1870 efi_fb_info.fbops.fb_set_par = NULL; 1871 efi_fb_info.fbops.fb_blank = NULL; 1872 efi_fb_info.fbops.fb_debug_enter = NULL; 1873 efi_fb_info.device = NULL; 1874 1875 return 0; 1876 } 1877 1878 static void 1879 efifb_startup(void *arg) 1880 { 1881 probe_efi_fb(0); 1882 } 1883 1884 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 1885 1886 static void 1887 getmemsize(caddr_t kmdp, u_int64_t first) 1888 { 1889 int off, physmap_idx, pa_indx, da_indx; 1890 int i, j; 1891 vm_paddr_t pa; 1892 vm_paddr_t msgbuf_size; 1893 u_long physmem_tunable; 1894 pt_entry_t *pte; 1895 quad_t dcons_addr, dcons_size; 1896 1897 bzero(physmap, sizeof(physmap)); 1898 physmap_idx = 0; 1899 1900 /* 1901 * get memory map from INT 15:E820, kindly supplied by the loader. 1902 * 1903 * subr_module.c says: 1904 * "Consumer may safely assume that size value precedes data." 1905 * ie: an int32_t immediately precedes smap. 1906 */ 1907 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 1908 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1909 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1910 MODINFO_METADATA | MODINFOMD_SMAP); 1911 if (smapbase == NULL && efihdrbase == NULL) 1912 panic("No BIOS smap or EFI map info from loader!"); 1913 1914 if (efihdrbase == NULL) 1915 add_smap_entries(&physmap_idx); 1916 else 1917 add_efi_map_entries(&physmap_idx); 1918 1919 base_memory = physmap[1] / 1024; 1920 /* make hole for AP bootstrap code */ 1921 physmap[1] = mp_bootaddress(base_memory); 1922 1923 /* Save EBDA address, if any */ 1924 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1925 ebda_addr <<= 4; 1926 1927 /* 1928 * Maxmem isn't the "maximum memory", it's one larger than the 1929 * highest page of the physical address space. It should be 1930 * called something like "Maxphyspage". We may adjust this 1931 * based on ``hw.physmem'' and the results of the memory test. 1932 */ 1933 Maxmem = atop(physmap[physmap_idx + 1]); 1934 1935 #ifdef MAXMEM 1936 Maxmem = MAXMEM / 4; 1937 #endif 1938 1939 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1940 Maxmem = atop(physmem_tunable); 1941 1942 /* 1943 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1944 * in the system. 1945 */ 1946 if (Maxmem > atop(physmap[physmap_idx + 1])) 1947 Maxmem = atop(physmap[physmap_idx + 1]); 1948 1949 /* 1950 * Blowing out the DMAP will blow up the system. 1951 */ 1952 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1953 kprintf("Limiting Maxmem due to DMAP size\n"); 1954 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1955 } 1956 1957 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1958 (boothowto & RB_VERBOSE)) { 1959 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1960 } 1961 1962 /* 1963 * Call pmap initialization to make new kernel address space 1964 * 1965 * Mask off page 0. 1966 */ 1967 pmap_bootstrap(&first); 1968 physmap[0] = PAGE_SIZE; 1969 1970 /* 1971 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1972 * exceeding Maxmem. 1973 */ 1974 for (i = j = 0; i <= physmap_idx; i += 2) { 1975 if (physmap[i+1] > ptoa(Maxmem)) 1976 physmap[i+1] = ptoa(Maxmem); 1977 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1978 ~PHYSMAP_ALIGN_MASK; 1979 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1980 1981 physmap[j] = physmap[i]; 1982 physmap[j+1] = physmap[i+1]; 1983 1984 if (physmap[i] < physmap[i+1]) 1985 j += 2; 1986 } 1987 physmap_idx = j - 2; 1988 1989 /* 1990 * Align anything else used in the validation loop. 1991 */ 1992 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1993 1994 /* 1995 * Size up each available chunk of physical memory. 1996 */ 1997 pa_indx = 0; 1998 da_indx = 1; 1999 phys_avail[pa_indx++] = physmap[0]; 2000 phys_avail[pa_indx] = physmap[0]; 2001 dump_avail[da_indx] = physmap[0]; 2002 pte = CMAP1; 2003 2004 /* 2005 * Get dcons buffer address 2006 */ 2007 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2008 kgetenv_quad("dcons.size", &dcons_size) == 0) 2009 dcons_addr = 0; 2010 2011 /* 2012 * Validate the physical memory. The physical memory segments 2013 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2014 * of PAGE_SIZE. 2015 */ 2016 for (i = 0; i <= physmap_idx; i += 2) { 2017 vm_paddr_t end; 2018 vm_paddr_t incr = PHYSMAP_ALIGN; 2019 2020 end = physmap[i + 1]; 2021 2022 for (pa = physmap[i]; pa < end; pa += incr) { 2023 int page_bad, full; 2024 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2025 uint64_t tmp; 2026 2027 incr = PHYSMAP_ALIGN; 2028 full = FALSE; 2029 2030 /* 2031 * block out kernel memory as not available. 2032 */ 2033 if (pa >= 0x200000 && pa < first) 2034 goto do_dump_avail; 2035 2036 /* 2037 * block out dcons buffer 2038 */ 2039 if (dcons_addr > 0 2040 && pa >= trunc_page(dcons_addr) 2041 && pa < dcons_addr + dcons_size) { 2042 goto do_dump_avail; 2043 } 2044 2045 page_bad = FALSE; 2046 2047 /* 2048 * Always test the first and last block supplied in 2049 * the map entry, but it just takes too long to run 2050 * the test these days and we already have to skip 2051 * pages. Handwave it on PHYSMAP_HANDWAVE boundaries. 2052 */ 2053 if (pa != physmap[i]) { 2054 vm_paddr_t bytes = end - pa; 2055 if ((pa & PHYSMAP_HANDWAVE_MASK) == 0 && 2056 bytes >= PHYSMAP_HANDWAVE + PHYSMAP_ALIGN) { 2057 incr = PHYSMAP_HANDWAVE; 2058 goto handwaved; 2059 } 2060 } 2061 2062 /* 2063 * map page into kernel: valid, read/write,non-cacheable 2064 */ 2065 *pte = pa | 2066 kernel_pmap.pmap_bits[PG_V_IDX] | 2067 kernel_pmap.pmap_bits[PG_RW_IDX] | 2068 kernel_pmap.pmap_bits[PG_N_IDX]; 2069 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2070 cpu_mfence(); 2071 2072 tmp = *ptr; 2073 /* 2074 * Test for alternating 1's and 0's 2075 */ 2076 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2077 cpu_mfence(); 2078 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2079 page_bad = TRUE; 2080 /* 2081 * Test for alternating 0's and 1's 2082 */ 2083 *ptr = 0x5555555555555555LLU; 2084 cpu_mfence(); 2085 if (*ptr != 0x5555555555555555LLU) 2086 page_bad = TRUE; 2087 /* 2088 * Test for all 1's 2089 */ 2090 *ptr = 0xffffffffffffffffLLU; 2091 cpu_mfence(); 2092 if (*ptr != 0xffffffffffffffffLLU) 2093 page_bad = TRUE; 2094 /* 2095 * Test for all 0's 2096 */ 2097 *ptr = 0x0; 2098 cpu_mfence(); 2099 if (*ptr != 0x0) 2100 page_bad = TRUE; 2101 /* 2102 * Restore original value. 2103 */ 2104 *ptr = tmp; 2105 handwaved: 2106 2107 /* 2108 * Adjust array of valid/good pages. 2109 */ 2110 if (page_bad == TRUE) 2111 continue; 2112 2113 /* 2114 * If this good page is a continuation of the 2115 * previous set of good pages, then just increase 2116 * the end pointer. Otherwise start a new chunk. 2117 * Note that "end" points one higher than end, 2118 * making the range >= start and < end. 2119 * If we're also doing a speculative memory 2120 * test and we at or past the end, bump up Maxmem 2121 * so that we keep going. The first bad page 2122 * will terminate the loop. 2123 */ 2124 if (phys_avail[pa_indx] == pa) { 2125 phys_avail[pa_indx] += incr; 2126 } else { 2127 pa_indx++; 2128 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2129 kprintf( 2130 "Too many holes in the physical address space, giving up\n"); 2131 pa_indx--; 2132 full = TRUE; 2133 goto do_dump_avail; 2134 } 2135 phys_avail[pa_indx++] = pa; 2136 phys_avail[pa_indx] = pa + incr; 2137 } 2138 physmem += incr / PAGE_SIZE; 2139 do_dump_avail: 2140 if (dump_avail[da_indx] == pa) { 2141 dump_avail[da_indx] += incr; 2142 } else { 2143 da_indx++; 2144 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2145 da_indx--; 2146 goto do_next; 2147 } 2148 dump_avail[da_indx++] = pa; 2149 dump_avail[da_indx] = pa + incr; 2150 } 2151 do_next: 2152 if (full) 2153 break; 2154 } 2155 } 2156 *pte = 0; 2157 cpu_invltlb(); 2158 cpu_mfence(); 2159 2160 /* 2161 * The last chunk must contain at least one page plus the message 2162 * buffer to avoid complicating other code (message buffer address 2163 * calculation, etc.). 2164 */ 2165 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2166 2167 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN + 2168 msgbuf_size >= phys_avail[pa_indx]) { 2169 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 2170 phys_avail[pa_indx--] = 0; 2171 phys_avail[pa_indx--] = 0; 2172 } 2173 2174 Maxmem = atop(phys_avail[pa_indx]); 2175 2176 /* Trim off space for the message buffer. */ 2177 phys_avail[pa_indx] -= msgbuf_size; 2178 2179 avail_end = phys_avail[pa_indx]; 2180 2181 /* Map the message buffer. */ 2182 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2183 pmap_kenter((vm_offset_t)msgbufp + off, 2184 phys_avail[pa_indx] + off); 2185 } 2186 /* Try to get EFI framebuffer working as early as possible */ 2187 if (have_efi_framebuffer) 2188 efi_fb_init_vaddr(1); 2189 } 2190 2191 struct machintr_abi MachIntrABI; 2192 2193 /* 2194 * IDT VECTORS: 2195 * 0 Divide by zero 2196 * 1 Debug 2197 * 2 NMI 2198 * 3 BreakPoint 2199 * 4 OverFlow 2200 * 5 Bound-Range 2201 * 6 Invalid OpCode 2202 * 7 Device Not Available (x87) 2203 * 8 Double-Fault 2204 * 9 Coprocessor Segment overrun (unsupported, reserved) 2205 * 10 Invalid-TSS 2206 * 11 Segment not present 2207 * 12 Stack 2208 * 13 General Protection 2209 * 14 Page Fault 2210 * 15 Reserved 2211 * 16 x87 FP Exception pending 2212 * 17 Alignment Check 2213 * 18 Machine Check 2214 * 19 SIMD floating point 2215 * 20-31 reserved 2216 * 32-255 INTn/external sources 2217 */ 2218 u_int64_t 2219 hammer_time(u_int64_t modulep, u_int64_t physfree) 2220 { 2221 caddr_t kmdp; 2222 int gsel_tss, x, cpu; 2223 #if 0 /* JG */ 2224 int metadata_missing, off; 2225 #endif 2226 struct mdglobaldata *gd; 2227 u_int64_t msr; 2228 2229 /* 2230 * Prevent lowering of the ipl if we call tsleep() early. 2231 */ 2232 gd = &CPU_prvspace[0]->mdglobaldata; 2233 bzero(gd, sizeof(*gd)); 2234 2235 /* 2236 * Note: on both UP and SMP curthread must be set non-NULL 2237 * early in the boot sequence because the system assumes 2238 * that 'curthread' is never NULL. 2239 */ 2240 2241 gd->mi.gd_curthread = &thread0; 2242 thread0.td_gd = &gd->mi; 2243 2244 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2245 2246 #if 0 /* JG */ 2247 metadata_missing = 0; 2248 if (bootinfo.bi_modulep) { 2249 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2250 preload_bootstrap_relocate(KERNBASE); 2251 } else { 2252 metadata_missing = 1; 2253 } 2254 if (bootinfo.bi_envp) 2255 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2256 #endif 2257 2258 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2259 preload_bootstrap_relocate(PTOV_OFFSET); 2260 kmdp = preload_search_by_type("elf kernel"); 2261 if (kmdp == NULL) 2262 kmdp = preload_search_by_type("elf64 kernel"); 2263 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2264 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2265 #ifdef DDB 2266 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2267 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2268 #endif 2269 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2270 2271 if (boothowto & RB_VERBOSE) 2272 bootverbose++; 2273 2274 /* 2275 * Default MachIntrABI to ICU 2276 */ 2277 MachIntrABI = MachIntrABI_ICU; 2278 2279 /* 2280 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask, 2281 * and ncpus_fit_mask remain 0. 2282 */ 2283 ncpus = 1; 2284 ncpus2 = 1; 2285 ncpus_fit = 1; 2286 /* Init basic tunables, hz etc */ 2287 init_param1(); 2288 2289 /* 2290 * make gdt memory segments 2291 */ 2292 gdt_segs[GPROC0_SEL].ssd_base = 2293 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss; 2294 2295 gd->mi.gd_prvspace = CPU_prvspace[0]; 2296 2297 for (x = 0; x < NGDT; x++) { 2298 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2299 ssdtosd(&gdt_segs[x], &gdt[x]); 2300 } 2301 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2302 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2303 2304 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2305 r_gdt.rd_base = (long) gdt; 2306 lgdt(&r_gdt); 2307 2308 wrmsr(MSR_FSBASE, 0); /* User value */ 2309 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2310 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2311 2312 mi_gdinit(&gd->mi, 0); 2313 cpu_gdinit(gd, 0); 2314 proc0paddr = proc0paddr_buff; 2315 mi_proc0init(&gd->mi, proc0paddr); 2316 safepri = TDPRI_MAX; 2317 2318 /* spinlocks and the BGL */ 2319 init_locks(); 2320 2321 /* exceptions */ 2322 for (x = 0; x < NIDT; x++) 2323 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2324 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2325 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2326 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2327 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2328 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2329 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2330 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2331 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2332 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2333 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2334 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2335 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2336 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2337 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2338 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2339 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2340 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2341 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2342 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2343 2344 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2345 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2346 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2347 } 2348 2349 lidt(&r_idt_arr[0]); 2350 2351 /* 2352 * Initialize the console before we print anything out. 2353 */ 2354 cninit(); 2355 2356 #if 0 /* JG */ 2357 if (metadata_missing) 2358 kprintf("WARNING: loader(8) metadata is missing!\n"); 2359 #endif 2360 2361 #if NISA >0 2362 elcr_probe(); 2363 isa_defaultirq(); 2364 #endif 2365 rand_initialize(); 2366 2367 /* 2368 * Initialize IRQ mapping 2369 * 2370 * NOTE: 2371 * SHOULD be after elcr_probe() 2372 */ 2373 MachIntrABI_ICU.initmap(); 2374 MachIntrABI_IOAPIC.initmap(); 2375 2376 #ifdef DDB 2377 kdb_init(); 2378 if (boothowto & RB_KDB) 2379 Debugger("Boot flags requested debugger"); 2380 #endif 2381 2382 #if 0 /* JG */ 2383 finishidentcpu(); /* Final stage of CPU initialization */ 2384 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2385 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2386 #endif 2387 identify_cpu(); /* Final stage of CPU initialization */ 2388 initializecpu(0); /* Initialize CPU registers */ 2389 2390 /* 2391 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better 2392 * because the cpu does significant power management in MWAIT 2393 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2394 * 2395 * On modern amd cpus cpu_idle_hlt=3 is better, because the cpu does 2396 * significant power management in HLT or ACPI (but cpu_idle_hlt=1 2397 * would try to use MWAIT). 2398 * 2399 * On older amd or intel cpus, cpu_idle_hlt=2 is better because ACPI 2400 * is needed to reduce power consumption, but wakeup times are often 2401 * longer. 2402 */ 2403 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2404 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2405 cpu_idle_hlt = 1; 2406 } 2407 if (cpu_vendor_id == CPU_VENDOR_AMD && 2408 CPUID_TO_FAMILY(cpu_id) >= 0x14) { /* Bobcat or later */ 2409 cpu_idle_hlt = 3; 2410 } 2411 2412 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2413 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2414 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2415 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2416 2417 /* 2418 * Some of the virtual machines do not work w/ I/O APIC 2419 * enabled. If the user does not explicitly enable or 2420 * disable the I/O APIC (ioapic_enable < 0), then we 2421 * disable I/O APIC on all virtual machines. 2422 * 2423 * NOTE: 2424 * This must be done after identify_cpu(), which sets 2425 * 'cpu_feature2' 2426 */ 2427 if (ioapic_enable < 0) { 2428 if (cpu_feature2 & CPUID2_VMM) 2429 ioapic_enable = 0; 2430 else 2431 ioapic_enable = 1; 2432 } 2433 2434 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2435 gd->gd_common_tss.tss_rsp0 = 2436 (register_t)(thread0.td_kstack + 2437 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 2438 /* Ensure the stack is aligned to 16 bytes */ 2439 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 2440 2441 /* double fault stack */ 2442 gd->gd_common_tss.tss_ist1 = 2443 (long)&gd->mi.gd_prvspace->idlestack[ 2444 sizeof(gd->mi.gd_prvspace->idlestack)]; 2445 2446 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2447 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 2448 2449 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2450 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2451 gd->gd_common_tssd = *gd->gd_tss_gdt; 2452 ltr(gsel_tss); 2453 2454 /* Set up the fast syscall stuff */ 2455 msr = rdmsr(MSR_EFER) | EFER_SCE; 2456 wrmsr(MSR_EFER, msr); 2457 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2458 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2459 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2460 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2461 wrmsr(MSR_STAR, msr); 2462 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2463 2464 getmemsize(kmdp, physfree); 2465 init_param2(physmem); 2466 2467 /* now running on new page tables, configured,and u/iom is accessible */ 2468 2469 /* Map the message buffer. */ 2470 #if 0 /* JG */ 2471 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2472 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2473 #endif 2474 2475 msgbufinit(msgbufp, MSGBUF_SIZE); 2476 2477 2478 /* transfer to user mode */ 2479 2480 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2481 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2482 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2483 2484 load_ds(_udatasel); 2485 load_es(_udatasel); 2486 load_fs(_udatasel); 2487 2488 /* setup proc 0's pcb */ 2489 thread0.td_pcb->pcb_flags = 0; 2490 thread0.td_pcb->pcb_cr3 = KPML4phys; 2491 thread0.td_pcb->pcb_ext = NULL; 2492 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2493 2494 /* Location of kernel stack for locore */ 2495 return ((u_int64_t)thread0.td_pcb); 2496 } 2497 2498 /* 2499 * Initialize machine-dependant portions of the global data structure. 2500 * Note that the global data area and cpu0's idlestack in the private 2501 * data space were allocated in locore. 2502 * 2503 * Note: the idlethread's cpl is 0 2504 * 2505 * WARNING! Called from early boot, 'mycpu' may not work yet. 2506 */ 2507 void 2508 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2509 { 2510 if (cpu) 2511 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2512 2513 lwkt_init_thread(&gd->mi.gd_idlethread, 2514 gd->mi.gd_prvspace->idlestack, 2515 sizeof(gd->mi.gd_prvspace->idlestack), 2516 0, &gd->mi); 2517 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2518 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2519 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2520 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2521 } 2522 2523 /* 2524 * We only have to check for DMAP bounds, the globaldata space is 2525 * actually part of the kernel_map so we don't have to waste time 2526 * checking CPU_prvspace[*]. 2527 */ 2528 int 2529 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2530 { 2531 #if 0 2532 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2533 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2534 return (TRUE); 2535 } 2536 #endif 2537 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2538 return (TRUE); 2539 return (FALSE); 2540 } 2541 2542 struct globaldata * 2543 globaldata_find(int cpu) 2544 { 2545 KKASSERT(cpu >= 0 && cpu < ncpus); 2546 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2547 } 2548 2549 /* 2550 * This path should be safe from the SYSRET issue because only stopped threads 2551 * can have their %rip adjusted this way (and all heavy weight thread switches 2552 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2553 * convoluted so add a safety by forcing %rip to be cannonical. 2554 */ 2555 int 2556 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2557 { 2558 if (addr & 0x0000800000000000LLU) 2559 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2560 else 2561 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2562 return (0); 2563 } 2564 2565 int 2566 ptrace_single_step(struct lwp *lp) 2567 { 2568 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2569 return (0); 2570 } 2571 2572 int 2573 fill_regs(struct lwp *lp, struct reg *regs) 2574 { 2575 struct trapframe *tp; 2576 2577 if ((tp = lp->lwp_md.md_regs) == NULL) 2578 return EINVAL; 2579 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2580 return (0); 2581 } 2582 2583 int 2584 set_regs(struct lwp *lp, struct reg *regs) 2585 { 2586 struct trapframe *tp; 2587 2588 tp = lp->lwp_md.md_regs; 2589 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2590 !CS_SECURE(regs->r_cs)) 2591 return (EINVAL); 2592 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2593 clear_quickret(); 2594 return (0); 2595 } 2596 2597 static void 2598 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2599 { 2600 struct env87 *penv_87 = &sv_87->sv_env; 2601 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2602 int i; 2603 2604 /* FPU control/status */ 2605 penv_87->en_cw = penv_xmm->en_cw; 2606 penv_87->en_sw = penv_xmm->en_sw; 2607 penv_87->en_tw = penv_xmm->en_tw; 2608 penv_87->en_fip = penv_xmm->en_fip; 2609 penv_87->en_fcs = penv_xmm->en_fcs; 2610 penv_87->en_opcode = penv_xmm->en_opcode; 2611 penv_87->en_foo = penv_xmm->en_foo; 2612 penv_87->en_fos = penv_xmm->en_fos; 2613 2614 /* FPU registers */ 2615 for (i = 0; i < 8; ++i) 2616 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2617 } 2618 2619 static void 2620 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2621 { 2622 struct env87 *penv_87 = &sv_87->sv_env; 2623 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2624 int i; 2625 2626 /* FPU control/status */ 2627 penv_xmm->en_cw = penv_87->en_cw; 2628 penv_xmm->en_sw = penv_87->en_sw; 2629 penv_xmm->en_tw = penv_87->en_tw; 2630 penv_xmm->en_fip = penv_87->en_fip; 2631 penv_xmm->en_fcs = penv_87->en_fcs; 2632 penv_xmm->en_opcode = penv_87->en_opcode; 2633 penv_xmm->en_foo = penv_87->en_foo; 2634 penv_xmm->en_fos = penv_87->en_fos; 2635 2636 /* FPU registers */ 2637 for (i = 0; i < 8; ++i) 2638 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2639 } 2640 2641 int 2642 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2643 { 2644 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2645 return EINVAL; 2646 if (cpu_fxsr) { 2647 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2648 (struct save87 *)fpregs); 2649 return (0); 2650 } 2651 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2652 return (0); 2653 } 2654 2655 int 2656 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2657 { 2658 if (cpu_fxsr) { 2659 set_fpregs_xmm((struct save87 *)fpregs, 2660 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2661 return (0); 2662 } 2663 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2664 return (0); 2665 } 2666 2667 int 2668 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2669 { 2670 struct pcb *pcb; 2671 2672 if (lp == NULL) { 2673 dbregs->dr[0] = rdr0(); 2674 dbregs->dr[1] = rdr1(); 2675 dbregs->dr[2] = rdr2(); 2676 dbregs->dr[3] = rdr3(); 2677 dbregs->dr[4] = rdr4(); 2678 dbregs->dr[5] = rdr5(); 2679 dbregs->dr[6] = rdr6(); 2680 dbregs->dr[7] = rdr7(); 2681 return (0); 2682 } 2683 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2684 return EINVAL; 2685 dbregs->dr[0] = pcb->pcb_dr0; 2686 dbregs->dr[1] = pcb->pcb_dr1; 2687 dbregs->dr[2] = pcb->pcb_dr2; 2688 dbregs->dr[3] = pcb->pcb_dr3; 2689 dbregs->dr[4] = 0; 2690 dbregs->dr[5] = 0; 2691 dbregs->dr[6] = pcb->pcb_dr6; 2692 dbregs->dr[7] = pcb->pcb_dr7; 2693 return (0); 2694 } 2695 2696 int 2697 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2698 { 2699 if (lp == NULL) { 2700 load_dr0(dbregs->dr[0]); 2701 load_dr1(dbregs->dr[1]); 2702 load_dr2(dbregs->dr[2]); 2703 load_dr3(dbregs->dr[3]); 2704 load_dr4(dbregs->dr[4]); 2705 load_dr5(dbregs->dr[5]); 2706 load_dr6(dbregs->dr[6]); 2707 load_dr7(dbregs->dr[7]); 2708 } else { 2709 struct pcb *pcb; 2710 struct ucred *ucred; 2711 int i; 2712 uint64_t mask1, mask2; 2713 2714 /* 2715 * Don't let an illegal value for dr7 get set. Specifically, 2716 * check for undefined settings. Setting these bit patterns 2717 * result in undefined behaviour and can lead to an unexpected 2718 * TRCTRAP. 2719 */ 2720 /* JG this loop looks unreadable */ 2721 /* Check 4 2-bit fields for invalid patterns. 2722 * These fields are R/Wi, for i = 0..3 2723 */ 2724 /* Is 10 in LENi allowed when running in compatibility mode? */ 2725 /* Pattern 10 in R/Wi might be used to indicate 2726 * breakpoint on I/O. Further analysis should be 2727 * carried to decide if it is safe and useful to 2728 * provide access to that capability 2729 */ 2730 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2731 i++, mask1 <<= 4, mask2 <<= 4) 2732 if ((dbregs->dr[7] & mask1) == mask2) 2733 return (EINVAL); 2734 2735 pcb = lp->lwp_thread->td_pcb; 2736 ucred = lp->lwp_proc->p_ucred; 2737 2738 /* 2739 * Don't let a process set a breakpoint that is not within the 2740 * process's address space. If a process could do this, it 2741 * could halt the system by setting a breakpoint in the kernel 2742 * (if ddb was enabled). Thus, we need to check to make sure 2743 * that no breakpoints are being enabled for addresses outside 2744 * process's address space, unless, perhaps, we were called by 2745 * uid 0. 2746 * 2747 * XXX - what about when the watched area of the user's 2748 * address space is written into from within the kernel 2749 * ... wouldn't that still cause a breakpoint to be generated 2750 * from within kernel mode? 2751 */ 2752 2753 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2754 if (dbregs->dr[7] & 0x3) { 2755 /* dr0 is enabled */ 2756 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2757 return (EINVAL); 2758 } 2759 2760 if (dbregs->dr[7] & (0x3<<2)) { 2761 /* dr1 is enabled */ 2762 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2763 return (EINVAL); 2764 } 2765 2766 if (dbregs->dr[7] & (0x3<<4)) { 2767 /* dr2 is enabled */ 2768 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2769 return (EINVAL); 2770 } 2771 2772 if (dbregs->dr[7] & (0x3<<6)) { 2773 /* dr3 is enabled */ 2774 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2775 return (EINVAL); 2776 } 2777 } 2778 2779 pcb->pcb_dr0 = dbregs->dr[0]; 2780 pcb->pcb_dr1 = dbregs->dr[1]; 2781 pcb->pcb_dr2 = dbregs->dr[2]; 2782 pcb->pcb_dr3 = dbregs->dr[3]; 2783 pcb->pcb_dr6 = dbregs->dr[6]; 2784 pcb->pcb_dr7 = dbregs->dr[7]; 2785 2786 pcb->pcb_flags |= PCB_DBREGS; 2787 } 2788 2789 return (0); 2790 } 2791 2792 /* 2793 * Return > 0 if a hardware breakpoint has been hit, and the 2794 * breakpoint was in user space. Return 0, otherwise. 2795 */ 2796 int 2797 user_dbreg_trap(void) 2798 { 2799 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2800 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2801 int nbp; /* number of breakpoints that triggered */ 2802 caddr_t addr[4]; /* breakpoint addresses */ 2803 int i; 2804 2805 dr7 = rdr7(); 2806 if ((dr7 & 0xff) == 0) { 2807 /* 2808 * all GE and LE bits in the dr7 register are zero, 2809 * thus the trap couldn't have been caused by the 2810 * hardware debug registers 2811 */ 2812 return 0; 2813 } 2814 2815 nbp = 0; 2816 dr6 = rdr6(); 2817 bp = dr6 & 0xf; 2818 2819 if (bp == 0) { 2820 /* 2821 * None of the breakpoint bits are set meaning this 2822 * trap was not caused by any of the debug registers 2823 */ 2824 return 0; 2825 } 2826 2827 /* 2828 * at least one of the breakpoints were hit, check to see 2829 * which ones and if any of them are user space addresses 2830 */ 2831 2832 if (bp & 0x01) { 2833 addr[nbp++] = (caddr_t)rdr0(); 2834 } 2835 if (bp & 0x02) { 2836 addr[nbp++] = (caddr_t)rdr1(); 2837 } 2838 if (bp & 0x04) { 2839 addr[nbp++] = (caddr_t)rdr2(); 2840 } 2841 if (bp & 0x08) { 2842 addr[nbp++] = (caddr_t)rdr3(); 2843 } 2844 2845 for (i=0; i<nbp; i++) { 2846 if (addr[i] < 2847 (caddr_t)VM_MAX_USER_ADDRESS) { 2848 /* 2849 * addr[i] is in user space 2850 */ 2851 return nbp; 2852 } 2853 } 2854 2855 /* 2856 * None of the breakpoints are in user space. 2857 */ 2858 return 0; 2859 } 2860 2861 2862 #ifndef DDB 2863 void 2864 Debugger(const char *msg) 2865 { 2866 kprintf("Debugger(\"%s\") called.\n", msg); 2867 } 2868 #endif /* no DDB */ 2869 2870 #ifdef DDB 2871 2872 /* 2873 * Provide inb() and outb() as functions. They are normally only 2874 * available as macros calling inlined functions, thus cannot be 2875 * called inside DDB. 2876 * 2877 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2878 */ 2879 2880 #undef inb 2881 #undef outb 2882 2883 /* silence compiler warnings */ 2884 u_char inb(u_int); 2885 void outb(u_int, u_char); 2886 2887 u_char 2888 inb(u_int port) 2889 { 2890 u_char data; 2891 /* 2892 * We use %%dx and not %1 here because i/o is done at %dx and not at 2893 * %edx, while gcc generates inferior code (movw instead of movl) 2894 * if we tell it to load (u_short) port. 2895 */ 2896 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2897 return (data); 2898 } 2899 2900 void 2901 outb(u_int port, u_char data) 2902 { 2903 u_char al; 2904 /* 2905 * Use an unnecessary assignment to help gcc's register allocator. 2906 * This make a large difference for gcc-1.40 and a tiny difference 2907 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2908 * best results. gcc-2.6.0 can't handle this. 2909 */ 2910 al = data; 2911 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2912 } 2913 2914 #endif /* DDB */ 2915 2916 2917 2918 /* 2919 * initialize all the SMP locks 2920 */ 2921 2922 /* critical region when masking or unmasking interupts */ 2923 struct spinlock_deprecated imen_spinlock; 2924 2925 /* lock region used by kernel profiling */ 2926 struct spinlock_deprecated mcount_spinlock; 2927 2928 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2929 struct spinlock_deprecated com_spinlock; 2930 2931 /* lock regions around the clock hardware */ 2932 struct spinlock_deprecated clock_spinlock; 2933 2934 static void 2935 init_locks(void) 2936 { 2937 /* 2938 * Get the initial mplock with a count of 1 for the BSP. 2939 * This uses a LOGICAL cpu ID, ie BSP == 0. 2940 */ 2941 cpu_get_initial_mplock(); 2942 /* DEPRECATED */ 2943 spin_init_deprecated(&mcount_spinlock); 2944 spin_init_deprecated(&imen_spinlock); 2945 spin_init_deprecated(&com_spinlock); 2946 spin_init_deprecated(&clock_spinlock); 2947 2948 /* our token pool needs to work early */ 2949 lwkt_token_pool_init(); 2950 } 2951 2952 boolean_t 2953 cpu_mwait_hint_valid(uint32_t hint) 2954 { 2955 int cx_idx, sub; 2956 2957 cx_idx = MWAIT_EAX_TO_CX(hint); 2958 if (cx_idx >= CPU_MWAIT_CX_MAX) 2959 return FALSE; 2960 2961 sub = MWAIT_EAX_TO_CX_SUB(hint); 2962 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 2963 return FALSE; 2964 2965 return TRUE; 2966 } 2967 2968 void 2969 cpu_mwait_cx_no_bmsts(void) 2970 { 2971 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 2972 } 2973 2974 void 2975 cpu_mwait_cx_no_bmarb(void) 2976 { 2977 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 2978 } 2979 2980 static int 2981 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 2982 { 2983 int old_cx_idx, sub = 0; 2984 2985 if (hint >= 0) { 2986 old_cx_idx = MWAIT_EAX_TO_CX(hint); 2987 sub = MWAIT_EAX_TO_CX_SUB(hint); 2988 } else if (hint == CPU_MWAIT_HINT_AUTO) { 2989 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 2990 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 2991 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 2992 } else { 2993 old_cx_idx = CPU_MWAIT_CX_MAX; 2994 } 2995 2996 if (!CPU_MWAIT_HAS_CX) 2997 strlcpy(name, "NONE", namelen); 2998 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 2999 strlcpy(name, "AUTO", namelen); 3000 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3001 strlcpy(name, "AUTODEEP", namelen); 3002 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3003 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3004 strlcpy(name, "INVALID", namelen); 3005 else 3006 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3007 3008 return old_cx_idx; 3009 } 3010 3011 static int 3012 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3013 { 3014 int cx_idx, sub, hint; 3015 char *ptr, *start; 3016 3017 if (allow_auto && strcmp(name, "AUTO") == 0) { 3018 hint = CPU_MWAIT_HINT_AUTO; 3019 cx_idx = CPU_MWAIT_C2; 3020 goto done; 3021 } 3022 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3023 hint = CPU_MWAIT_HINT_AUTODEEP; 3024 cx_idx = CPU_MWAIT_C3; 3025 goto done; 3026 } 3027 3028 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3029 return -1; 3030 start = &name[1]; 3031 ptr = NULL; 3032 3033 cx_idx = strtol(start, &ptr, 10); 3034 if (ptr == start || *ptr != '/') 3035 return -1; 3036 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3037 return -1; 3038 3039 start = ptr + 1; 3040 ptr = NULL; 3041 3042 sub = strtol(start, &ptr, 10); 3043 if (*ptr != '\0') 3044 return -1; 3045 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3046 return -1; 3047 3048 hint = MWAIT_EAX_HINT(cx_idx, sub); 3049 done: 3050 *hint0 = hint; 3051 return cx_idx; 3052 } 3053 3054 static int 3055 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3056 { 3057 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3058 return EOPNOTSUPP; 3059 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3060 int error; 3061 3062 error = cputimer_intr_powersave_addreq(); 3063 if (error) 3064 return error; 3065 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3066 cputimer_intr_powersave_remreq(); 3067 } 3068 return 0; 3069 } 3070 3071 static int 3072 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3073 boolean_t allow_auto) 3074 { 3075 int error, cx_idx, old_cx_idx, hint; 3076 char name[CPU_MWAIT_CX_NAMELEN]; 3077 3078 hint = *hint0; 3079 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3080 allow_auto); 3081 3082 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3083 if (error != 0 || req->newptr == NULL) 3084 return error; 3085 3086 if (!CPU_MWAIT_HAS_CX) 3087 return EOPNOTSUPP; 3088 3089 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3090 if (cx_idx < 0) 3091 return EINVAL; 3092 3093 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3094 if (error) 3095 return error; 3096 3097 *hint0 = hint; 3098 return 0; 3099 } 3100 3101 static int 3102 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3103 { 3104 int error, cx_idx, old_cx_idx, hint; 3105 char name[CPU_MWAIT_CX_NAMELEN]; 3106 3107 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3108 3109 hint = stat->hint; 3110 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3111 3112 strlcpy(name, cx_name, sizeof(name)); 3113 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3114 if (cx_idx < 0) 3115 return EINVAL; 3116 3117 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3118 if (error) 3119 return error; 3120 3121 stat->hint = hint; 3122 return 0; 3123 } 3124 3125 static int 3126 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3127 { 3128 int hint = cpu_mwait_halt_global; 3129 int error, cx_idx, cpu; 3130 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3131 3132 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3133 3134 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3135 if (error != 0 || req->newptr == NULL) 3136 return error; 3137 3138 if (!CPU_MWAIT_HAS_CX) 3139 return EOPNOTSUPP; 3140 3141 /* Save name for later per-cpu CX configuration */ 3142 strlcpy(cx_name, name, sizeof(cx_name)); 3143 3144 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3145 if (cx_idx < 0) 3146 return EINVAL; 3147 3148 /* Change per-cpu CX configuration */ 3149 for (cpu = 0; cpu < ncpus; ++cpu) { 3150 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3151 if (error) 3152 return error; 3153 } 3154 3155 cpu_mwait_halt_global = hint; 3156 return 0; 3157 } 3158 3159 static int 3160 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3161 { 3162 struct cpu_idle_stat *stat = arg1; 3163 int error; 3164 3165 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3166 &stat->hint, TRUE); 3167 return error; 3168 } 3169 3170 static int 3171 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3172 { 3173 int error; 3174 3175 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3176 &cpu_mwait_spin, FALSE); 3177 return error; 3178 } 3179 3180 /* 3181 * This manual debugging code is called unconditionally from Xtimer 3182 * (the per-cpu timer interrupt) whether the current thread is in a 3183 * critical section or not) and can be useful in tracking down lockups. 3184 * 3185 * NOTE: MANUAL DEBUG CODE 3186 */ 3187 #if 0 3188 static int saveticks[SMP_MAXCPU]; 3189 static int savecounts[SMP_MAXCPU]; 3190 #endif 3191 3192 void 3193 pcpu_timer_always(struct intrframe *frame) 3194 { 3195 #if 0 3196 globaldata_t gd = mycpu; 3197 int cpu = gd->gd_cpuid; 3198 char buf[64]; 3199 short *gptr; 3200 int i; 3201 3202 if (cpu <= 20) { 3203 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3204 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3205 ++gptr; 3206 3207 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3208 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3209 gd->gd_infomsg); 3210 for (i = 0; buf[i]; ++i) { 3211 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3212 } 3213 } 3214 #if 0 3215 if (saveticks[gd->gd_cpuid] != ticks) { 3216 saveticks[gd->gd_cpuid] = ticks; 3217 savecounts[gd->gd_cpuid] = 0; 3218 } 3219 ++savecounts[gd->gd_cpuid]; 3220 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3221 panic("cpud %d panicing on ticks failure", 3222 gd->gd_cpuid); 3223 } 3224 for (i = 0; i < ncpus; ++i) { 3225 int delta; 3226 if (saveticks[i] && panicstr == NULL) { 3227 delta = saveticks[i] - ticks; 3228 if (delta < -10 || delta > 10) { 3229 panic("cpu %d panicing on cpu %d watchdog", 3230 gd->gd_cpuid, i); 3231 } 3232 } 3233 } 3234 #endif 3235 #endif 3236 } 3237