1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008-2017 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 extern void panicifcpuunsupported(void); 137 138 static void cpu_startup(void *); 139 static void pic_finish(void *); 140 static void cpu_finish(void *); 141 142 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 143 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 144 static void init_locks(void); 145 146 extern void pcpu_timer_always(struct intrframe *); 147 148 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 149 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 150 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 151 152 #ifdef DDB 153 extern vm_offset_t ksym_start, ksym_end; 154 #endif 155 156 struct privatespace CPU_prvspace_bsp __aligned(4096); 157 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 158 159 vm_paddr_t efi_systbl_phys; 160 int _udatasel, _ucodesel, _ucode32sel; 161 u_long atdevbase; 162 int64_t tsc_offsets[MAXCPU]; 163 cpumask_t smp_idleinvl_mask; 164 cpumask_t smp_idleinvl_reqs; 165 166 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 167 168 #if defined(SWTCH_OPTIM_STATS) 169 extern int swtch_optim_stats; 170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 171 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 173 CTLFLAG_RD, &tlb_flush_count, 0, ""); 174 #endif 175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 176 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 177 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, 178 CTLFLAG_RD, &cpu_mwait_spin, 0, "monitor/mwait target state"); 179 180 #define CPU_MWAIT_HAS_CX \ 181 ((cpu_feature2 & CPUID2_MON) && \ 182 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 183 184 #define CPU_MWAIT_CX_NAMELEN 16 185 186 #define CPU_MWAIT_C1 1 187 #define CPU_MWAIT_C2 2 188 #define CPU_MWAIT_C3 3 189 #define CPU_MWAIT_CX_MAX 8 190 191 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 192 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 193 194 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 195 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 196 197 struct cpu_mwait_cx { 198 int subcnt; 199 char name[4]; 200 struct sysctl_ctx_list sysctl_ctx; 201 struct sysctl_oid *sysctl_tree; 202 }; 203 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 204 static char cpu_mwait_cx_supported[256]; 205 206 static int cpu_mwait_c1_hints_cnt; 207 static int cpu_mwait_hints_cnt; 208 static int *cpu_mwait_hints; 209 210 static int cpu_mwait_deep_hints_cnt; 211 static int *cpu_mwait_deep_hints; 212 213 #define CPU_IDLE_REPEAT_DEFAULT 750 214 215 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 216 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 217 static u_int cpu_mwait_repeat_shift = 1; 218 219 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 220 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 221 222 static int cpu_mwait_c3_preamble = 223 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 224 CPU_MWAIT_C3_PREAMBLE_BM_STS; 225 226 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 227 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 228 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 229 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 230 231 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 232 int *, boolean_t); 233 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 234 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 235 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 236 237 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 238 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 239 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 240 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 241 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 242 &cpu_mwait_repeat_shift, 0, ""); 243 244 long physmem = 0; 245 246 u_long ebda_addr = 0; 247 248 int imcr_present = 0; 249 250 int naps = 0; /* # of Applications processors */ 251 252 u_int base_memory; 253 254 static int 255 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 256 { 257 u_long pmem = ctob(physmem); 258 int error; 259 260 error = sysctl_handle_long(oidp, &pmem, 0, req); 261 262 return (error); 263 } 264 265 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 266 0, 0, sysctl_hw_physmem, "LU", 267 "Total system memory in bytes (number of pages * page size)"); 268 269 static int 270 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 271 { 272 u_long usermem = ctob(physmem - vmstats.v_wire_count); 273 int error; 274 275 error = sysctl_handle_long(oidp, &usermem, 0, req); 276 277 return (error); 278 } 279 280 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_ULONG|CTLFLAG_RD, 281 0, 0, sysctl_hw_usermem, "LU", ""); 282 283 static int 284 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 285 { 286 int error; 287 u_long availpages; 288 289 availpages = x86_64_btop(avail_end - avail_start); 290 error = sysctl_handle_long(oidp, &availpages, 0, req); 291 292 return (error); 293 } 294 295 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_ULONG|CTLFLAG_RD, 296 0, 0, sysctl_hw_availpages, "LU", ""); 297 298 vm_paddr_t Maxmem; 299 vm_paddr_t Realmem; 300 301 /* 302 * The number of PHYSMAP entries must be one less than the number of 303 * PHYSSEG entries because the PHYSMAP entry that spans the largest 304 * physical address that is accessible by ISA DMA is split into two 305 * PHYSSEG entries. 306 */ 307 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 308 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 309 310 /* must be 1 less so 0 0 can signal end of chunks */ 311 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 312 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 313 314 static vm_offset_t buffer_sva, buffer_eva; 315 vm_offset_t clean_sva, clean_eva; 316 static vm_offset_t pager_sva, pager_eva; 317 static struct trapframe proc0_tf; 318 319 static void 320 cpu_startup(void *dummy) 321 { 322 caddr_t v; 323 vm_size_t size = 0; 324 vm_offset_t firstaddr; 325 326 /* 327 * Good {morning,afternoon,evening,night}. 328 */ 329 kprintf("%s", version); 330 startrtclock(); 331 printcpuinfo(); 332 panicifcpuunsupported(); 333 kprintf("real memory = %ju (%ju MB)\n", 334 (intmax_t)Realmem, 335 (intmax_t)Realmem / 1024 / 1024); 336 /* 337 * Display any holes after the first chunk of extended memory. 338 */ 339 if (bootverbose) { 340 int indx; 341 342 kprintf("Physical memory chunk(s):\n"); 343 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 344 vm_paddr_t size1; 345 346 size1 = phys_avail[indx].phys_end - 347 phys_avail[indx].phys_beg; 348 349 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 350 (intmax_t)phys_avail[indx].phys_beg, 351 (intmax_t)phys_avail[indx].phys_end - 1, 352 (intmax_t)size1, 353 (intmax_t)(size1 / PAGE_SIZE)); 354 } 355 } 356 357 /* 358 * Allocate space for system data structures. 359 * The first available kernel virtual address is in "v". 360 * As pages of kernel virtual memory are allocated, "v" is incremented. 361 * As pages of memory are allocated and cleared, 362 * "firstaddr" is incremented. 363 * An index into the kernel page table corresponding to the 364 * virtual memory address maintained in "v" is kept in "mapaddr". 365 */ 366 367 /* 368 * Make two passes. The first pass calculates how much memory is 369 * needed and allocates it. The second pass assigns virtual 370 * addresses to the various data structures. 371 */ 372 firstaddr = 0; 373 again: 374 v = (caddr_t)firstaddr; 375 376 #define valloc(name, type, num) \ 377 (name) = (type *)v; v = (caddr_t)((name)+(num)) 378 #define valloclim(name, type, num, lim) \ 379 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 380 381 /* 382 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 383 * For the first 64MB of ram nominally allocate sufficient buffers to 384 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 385 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 386 * the buffer cache we limit the eventual kva reservation to 387 * maxbcache bytes. 388 * 389 * factor represents the 1/4 x ram conversion. 390 */ 391 if (nbuf == 0) { 392 long factor = 4 * NBUFCALCSIZE / 1024; 393 long kbytes = physmem * (PAGE_SIZE / 1024); 394 395 nbuf = 50; 396 if (kbytes > 4096) 397 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 398 if (kbytes > 65536) 399 nbuf += (kbytes - 65536) * 2 / (factor * 5); 400 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 401 nbuf = maxbcache / NBUFCALCSIZE; 402 } 403 404 /* 405 * Do not allow the buffer_map to be more then 1/2 the size of the 406 * kernel_map. 407 */ 408 if (nbuf > (virtual_end - virtual_start + 409 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 410 nbuf = (virtual_end - virtual_start + 411 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 412 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 413 } 414 415 /* 416 * Do not allow the buffer_map to use more than 50% of available 417 * physical-equivalent memory. Since the VM pages which back 418 * individual buffers are typically wired, having too many bufs 419 * can prevent the system from paging properly. 420 */ 421 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 422 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 423 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 424 } 425 426 /* 427 * Do not allow the sizeof(struct buf) * nbuf to exceed 1/4 of 428 * the valloc space which is just the virtual_end - virtual_start 429 * section. This is typically ~2GB regardless of the amount of 430 * memory, so we use 500MB as a metric. 431 * 432 * This is because we use valloc() to allocate the buf header array. 433 * 434 * NOTE: buffer space in bytes is limited by vfs.*bufspace sysctls. 435 */ 436 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 4) { 437 nbuf = (virtual_end - virtual_start) / 438 sizeof(struct buf) / 2; 439 kprintf("Warning: nbufs capped at %ld due to " 440 "valloc considerations\n", 441 nbuf); 442 } 443 444 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 445 #ifdef NSWBUF_MIN 446 if (nswbuf_mem < NSWBUF_MIN) 447 nswbuf_mem = NSWBUF_MIN; 448 #endif 449 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 450 #ifdef NSWBUF_MIN 451 if (nswbuf_kva < NSWBUF_MIN) 452 nswbuf_kva = NSWBUF_MIN; 453 #endif 454 455 valloc(swbuf_mem, struct buf, nswbuf_mem); 456 valloc(swbuf_kva, struct buf, nswbuf_kva); 457 valloc(buf, struct buf, nbuf); 458 459 /* 460 * End of first pass, size has been calculated so allocate memory 461 */ 462 if (firstaddr == 0) { 463 size = (vm_size_t)(v - firstaddr); 464 firstaddr = kmem_alloc(&kernel_map, round_page(size), 465 VM_SUBSYS_BUF); 466 if (firstaddr == 0) 467 panic("startup: no room for tables"); 468 goto again; 469 } 470 471 /* 472 * End of second pass, addresses have been assigned 473 * 474 * nbuf is an int, make sure we don't overflow the field. 475 * 476 * On 64-bit systems we always reserve maximal allocations for 477 * buffer cache buffers and there are no fragmentation issues, 478 * so the KVA segment does not have to be excessively oversized. 479 */ 480 if ((vm_size_t)(v - firstaddr) != size) 481 panic("startup: table size inconsistency"); 482 483 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 484 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 485 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 486 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 487 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 488 buffer_map.system_map = 1; 489 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 490 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 491 pager_map_size); 492 pager_map.system_map = 1; 493 kprintf("avail memory = %ju (%ju MB)\n", 494 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 495 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 496 1024 / 1024); 497 } 498 499 struct cpu_idle_stat { 500 int hint; 501 int reserved; 502 u_long halt; 503 u_long spin; 504 u_long repeat; 505 u_long repeat_last; 506 u_long repeat_delta; 507 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 508 } __cachealign; 509 510 #define CPU_IDLE_STAT_HALT -1 511 #define CPU_IDLE_STAT_SPIN -2 512 513 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 514 515 static int 516 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 517 { 518 int idx = arg2, cpu, error; 519 u_long val = 0; 520 521 if (idx == CPU_IDLE_STAT_HALT) { 522 for (cpu = 0; cpu < ncpus; ++cpu) 523 val += cpu_idle_stats[cpu].halt; 524 } else if (idx == CPU_IDLE_STAT_SPIN) { 525 for (cpu = 0; cpu < ncpus; ++cpu) 526 val += cpu_idle_stats[cpu].spin; 527 } else { 528 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 529 ("invalid index %d", idx)); 530 for (cpu = 0; cpu < ncpus; ++cpu) 531 val += cpu_idle_stats[cpu].mwait_cx[idx]; 532 } 533 534 error = sysctl_handle_quad(oidp, &val, 0, req); 535 if (error || req->newptr == NULL) 536 return error; 537 538 if (idx == CPU_IDLE_STAT_HALT) { 539 for (cpu = 0; cpu < ncpus; ++cpu) 540 cpu_idle_stats[cpu].halt = 0; 541 cpu_idle_stats[0].halt = val; 542 } else if (idx == CPU_IDLE_STAT_SPIN) { 543 for (cpu = 0; cpu < ncpus; ++cpu) 544 cpu_idle_stats[cpu].spin = 0; 545 cpu_idle_stats[0].spin = val; 546 } else { 547 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 548 ("invalid index %d", idx)); 549 for (cpu = 0; cpu < ncpus; ++cpu) 550 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 551 cpu_idle_stats[0].mwait_cx[idx] = val; 552 } 553 return 0; 554 } 555 556 static void 557 cpu_mwait_attach(void) 558 { 559 struct sbuf sb; 560 int hint_idx, i; 561 562 if (!CPU_MWAIT_HAS_CX) 563 return; 564 565 if (cpu_vendor_id == CPU_VENDOR_INTEL && 566 (CPUID_TO_FAMILY(cpu_id) > 0xf || 567 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 568 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 569 int bm_sts = 1; 570 571 /* 572 * Pentium dual-core, Core 2 and beyond do not need any 573 * additional activities to enter deep C-state, i.e. C3(+). 574 */ 575 cpu_mwait_cx_no_bmarb(); 576 577 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 578 if (!bm_sts) 579 cpu_mwait_cx_no_bmsts(); 580 } 581 582 sbuf_new(&sb, cpu_mwait_cx_supported, 583 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 584 585 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 586 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 587 int sub; 588 589 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 590 591 sysctl_ctx_init(&cx->sysctl_ctx); 592 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 593 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 594 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 595 if (cx->sysctl_tree == NULL) 596 continue; 597 598 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 599 SYSCTL_ADD_INT(&cx->sysctl_ctx, 600 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 601 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 602 "sub-state count"); 603 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 604 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 605 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 606 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 607 608 for (sub = 0; sub < cx->subcnt; ++sub) 609 sbuf_printf(&sb, "C%d/%d ", i, sub); 610 } 611 sbuf_trim(&sb); 612 sbuf_finish(&sb); 613 614 /* 615 * Non-deep C-states 616 */ 617 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 618 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 619 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 620 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 621 M_DEVBUF, M_WAITOK); 622 623 hint_idx = 0; 624 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 625 int j, subcnt; 626 627 subcnt = cpu_mwait_cx_info[i].subcnt; 628 for (j = 0; j < subcnt; ++j) { 629 KASSERT(hint_idx < cpu_mwait_hints_cnt, 630 ("invalid mwait hint index %d", hint_idx)); 631 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 632 ++hint_idx; 633 } 634 } 635 KASSERT(hint_idx == cpu_mwait_hints_cnt, 636 ("mwait hint count %d != index %d", 637 cpu_mwait_hints_cnt, hint_idx)); 638 639 if (bootverbose) { 640 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 641 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 642 int hint = cpu_mwait_hints[i]; 643 644 kprintf(" C%d/%d hint 0x%04x\n", 645 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 646 hint); 647 } 648 } 649 650 /* 651 * Deep C-states 652 */ 653 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 654 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 655 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 656 M_DEVBUF, M_WAITOK); 657 658 hint_idx = 0; 659 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 660 int j, subcnt; 661 662 subcnt = cpu_mwait_cx_info[i].subcnt; 663 for (j = 0; j < subcnt; ++j) { 664 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 665 ("invalid mwait deep hint index %d", hint_idx)); 666 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 667 ++hint_idx; 668 } 669 } 670 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 671 ("mwait deep hint count %d != index %d", 672 cpu_mwait_deep_hints_cnt, hint_idx)); 673 674 if (bootverbose) { 675 kprintf("MWAIT deep hints:\n"); 676 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 677 int hint = cpu_mwait_deep_hints[i]; 678 679 kprintf(" C%d/%d hint 0x%04x\n", 680 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 681 hint); 682 } 683 } 684 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 685 686 for (i = 0; i < ncpus; ++i) { 687 char name[16]; 688 689 ksnprintf(name, sizeof(name), "idle%d", i); 690 SYSCTL_ADD_PROC(NULL, 691 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 692 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 693 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 694 } 695 } 696 697 static void 698 cpu_finish(void *dummy __unused) 699 { 700 cpu_setregs(); 701 cpu_mwait_attach(); 702 } 703 704 static void 705 pic_finish(void *dummy __unused) 706 { 707 /* Log ELCR information */ 708 elcr_dump(); 709 710 /* Log MPTABLE information */ 711 mptable_pci_int_dump(); 712 713 /* Finalize PCI */ 714 MachIntrABI.finalize(); 715 } 716 717 /* 718 * Send an interrupt to process. 719 * 720 * Stack is set up to allow sigcode stored 721 * at top to call routine, followed by kcall 722 * to sigreturn routine below. After sigreturn 723 * resets the signal mask, the stack, and the 724 * frame pointer, it returns to the user 725 * specified pc, psl. 726 */ 727 void 728 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 729 { 730 struct lwp *lp = curthread->td_lwp; 731 struct proc *p = lp->lwp_proc; 732 struct trapframe *regs; 733 struct sigacts *psp = p->p_sigacts; 734 struct sigframe sf, *sfp; 735 int oonstack; 736 char *sp; 737 738 regs = lp->lwp_md.md_regs; 739 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 740 741 /* Save user context */ 742 bzero(&sf, sizeof(struct sigframe)); 743 sf.sf_uc.uc_sigmask = *mask; 744 sf.sf_uc.uc_stack = lp->lwp_sigstk; 745 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 746 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 747 /* gcc errors out on optimized bcopy */ 748 _bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 749 750 /* Make the size of the saved context visible to userland */ 751 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 752 753 /* Allocate and validate space for the signal handler context. */ 754 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 755 SIGISMEMBER(psp->ps_sigonstack, sig)) { 756 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 757 sizeof(struct sigframe)); 758 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 759 } else { 760 /* We take red zone into account */ 761 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 762 } 763 764 /* 765 * XXX AVX needs 64-byte alignment but sigframe has other fields and 766 * the embedded ucontext is not at the front, so aligning this won't 767 * help us. Fortunately we bcopy in/out of the sigframe, so the 768 * kernel is ok. 769 * 770 * The problem though is if userland winds up trying to use the 771 * context directly. 772 */ 773 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 774 775 /* Translate the signal is appropriate */ 776 if (p->p_sysent->sv_sigtbl) { 777 if (sig <= p->p_sysent->sv_sigsize) 778 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 779 } 780 781 /* 782 * Build the argument list for the signal handler. 783 * 784 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 785 */ 786 regs->tf_rdi = sig; /* argument 1 */ 787 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 788 789 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 790 /* 791 * Signal handler installed with SA_SIGINFO. 792 * 793 * action(signo, siginfo, ucontext) 794 */ 795 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 796 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 797 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 798 799 /* fill siginfo structure */ 800 sf.sf_si.si_signo = sig; 801 sf.sf_si.si_code = code; 802 sf.sf_si.si_addr = (void *)regs->tf_addr; 803 } else { 804 /* 805 * Old FreeBSD-style arguments. 806 * 807 * handler (signo, code, [uc], addr) 808 */ 809 regs->tf_rsi = (register_t)code; /* argument 2 */ 810 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 811 sf.sf_ahu.sf_handler = catcher; 812 } 813 814 /* 815 * If we're a vm86 process, we want to save the segment registers. 816 * We also change eflags to be our emulated eflags, not the actual 817 * eflags. 818 */ 819 #if 0 /* JG */ 820 if (regs->tf_eflags & PSL_VM) { 821 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 822 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 823 824 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 825 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 826 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 827 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 828 829 if (vm86->vm86_has_vme == 0) 830 sf.sf_uc.uc_mcontext.mc_eflags = 831 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 832 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 833 834 /* 835 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 836 * syscalls made by the signal handler. This just avoids 837 * wasting time for our lazy fixup of such faults. PSL_NT 838 * does nothing in vm86 mode, but vm86 programs can set it 839 * almost legitimately in probes for old cpu types. 840 */ 841 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 842 } 843 #endif 844 845 /* 846 * Save the FPU state and reinit the FP unit 847 */ 848 npxpush(&sf.sf_uc.uc_mcontext); 849 850 /* 851 * Copy the sigframe out to the user's stack. 852 */ 853 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 854 /* 855 * Something is wrong with the stack pointer. 856 * ...Kill the process. 857 */ 858 sigexit(lp, SIGILL); 859 } 860 861 regs->tf_rsp = (register_t)sfp; 862 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 863 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 864 865 /* 866 * x86 abi specifies that the direction flag must be cleared 867 * on function entry 868 */ 869 regs->tf_rflags &= ~(PSL_T | PSL_D); 870 871 /* 872 * 64 bit mode has a code and stack selector but 873 * no data or extra selector. %fs and %gs are not 874 * stored in-context. 875 */ 876 regs->tf_cs = _ucodesel; 877 regs->tf_ss = _udatasel; 878 clear_quickret(); 879 } 880 881 /* 882 * Sanitize the trapframe for a virtual kernel passing control to a custom 883 * VM context. Remove any items that would otherwise create a privilage 884 * issue. 885 * 886 * XXX at the moment we allow userland to set the resume flag. Is this a 887 * bad idea? 888 */ 889 int 890 cpu_sanitize_frame(struct trapframe *frame) 891 { 892 frame->tf_cs = _ucodesel; 893 frame->tf_ss = _udatasel; 894 /* XXX VM (8086) mode not supported? */ 895 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 896 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 897 898 return(0); 899 } 900 901 /* 902 * Sanitize the tls so loading the descriptor does not blow up 903 * on us. For x86_64 we don't have to do anything. 904 */ 905 int 906 cpu_sanitize_tls(struct savetls *tls) 907 { 908 return(0); 909 } 910 911 /* 912 * sigreturn(ucontext_t *sigcntxp) 913 * 914 * System call to cleanup state after a signal 915 * has been taken. Reset signal mask and 916 * stack state from context left by sendsig (above). 917 * Return to previous pc and psl as specified by 918 * context left by sendsig. Check carefully to 919 * make sure that the user has not modified the 920 * state to gain improper privileges. 921 * 922 * MPSAFE 923 */ 924 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 925 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 926 927 int 928 sys_sigreturn(struct sigreturn_args *uap) 929 { 930 struct lwp *lp = curthread->td_lwp; 931 struct trapframe *regs; 932 ucontext_t uc; 933 ucontext_t *ucp; 934 register_t rflags; 935 int cs; 936 int error; 937 938 /* 939 * We have to copy the information into kernel space so userland 940 * can't modify it while we are sniffing it. 941 */ 942 regs = lp->lwp_md.md_regs; 943 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 944 if (error) 945 return (error); 946 ucp = &uc; 947 rflags = ucp->uc_mcontext.mc_rflags; 948 949 /* VM (8086) mode not supported */ 950 rflags &= ~PSL_VM_UNSUPP; 951 952 #if 0 /* JG */ 953 if (eflags & PSL_VM) { 954 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 955 struct vm86_kernel *vm86; 956 957 /* 958 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 959 * set up the vm86 area, and we can't enter vm86 mode. 960 */ 961 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 962 return (EINVAL); 963 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 964 if (vm86->vm86_inited == 0) 965 return (EINVAL); 966 967 /* go back to user mode if both flags are set */ 968 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 969 trapsignal(lp, SIGBUS, 0); 970 971 if (vm86->vm86_has_vme) { 972 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 973 (eflags & VME_USERCHANGE) | PSL_VM; 974 } else { 975 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 976 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 977 (eflags & VM_USERCHANGE) | PSL_VM; 978 } 979 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 980 tf->tf_eflags = eflags; 981 tf->tf_vm86_ds = tf->tf_ds; 982 tf->tf_vm86_es = tf->tf_es; 983 tf->tf_vm86_fs = tf->tf_fs; 984 tf->tf_vm86_gs = tf->tf_gs; 985 tf->tf_ds = _udatasel; 986 tf->tf_es = _udatasel; 987 tf->tf_fs = _udatasel; 988 tf->tf_gs = _udatasel; 989 } else 990 #endif 991 { 992 /* 993 * Don't allow users to change privileged or reserved flags. 994 */ 995 /* 996 * XXX do allow users to change the privileged flag PSL_RF. 997 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 998 * should sometimes set it there too. tf_eflags is kept in 999 * the signal context during signal handling and there is no 1000 * other place to remember it, so the PSL_RF bit may be 1001 * corrupted by the signal handler without us knowing. 1002 * Corruption of the PSL_RF bit at worst causes one more or 1003 * one less debugger trap, so allowing it is fairly harmless. 1004 */ 1005 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 1006 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 1007 return(EINVAL); 1008 } 1009 1010 /* 1011 * Don't allow users to load a valid privileged %cs. Let the 1012 * hardware check for invalid selectors, excess privilege in 1013 * other selectors, invalid %eip's and invalid %esp's. 1014 */ 1015 cs = ucp->uc_mcontext.mc_cs; 1016 if (!CS_SECURE(cs)) { 1017 kprintf("sigreturn: cs = 0x%x\n", cs); 1018 trapsignal(lp, SIGBUS, T_PROTFLT); 1019 return(EINVAL); 1020 } 1021 /* gcc errors out on optimized bcopy */ 1022 _bcopy(&ucp->uc_mcontext.mc_rdi, regs, 1023 sizeof(struct trapframe)); 1024 } 1025 1026 /* 1027 * Restore the FPU state from the frame 1028 */ 1029 crit_enter(); 1030 npxpop(&ucp->uc_mcontext); 1031 1032 if (ucp->uc_mcontext.mc_onstack & 1) 1033 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1034 else 1035 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1036 1037 lp->lwp_sigmask = ucp->uc_sigmask; 1038 SIG_CANTMASK(lp->lwp_sigmask); 1039 clear_quickret(); 1040 crit_exit(); 1041 return(EJUSTRETURN); 1042 } 1043 1044 /* 1045 * Machine dependent boot() routine 1046 * 1047 * I haven't seen anything to put here yet 1048 * Possibly some stuff might be grafted back here from boot() 1049 */ 1050 void 1051 cpu_boot(int howto) 1052 { 1053 } 1054 1055 /* 1056 * Shutdown the CPU as much as possible 1057 */ 1058 void 1059 cpu_halt(void) 1060 { 1061 for (;;) 1062 __asm__ __volatile("hlt"); 1063 } 1064 1065 /* 1066 * cpu_idle() represents the idle LWKT. You cannot return from this function 1067 * (unless you want to blow things up!). Instead we look for runnable threads 1068 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1069 * 1070 * The main loop is entered with a critical section held, we must release 1071 * the critical section before doing anything else. lwkt_switch() will 1072 * check for pending interrupts due to entering and exiting its own 1073 * critical section. 1074 * 1075 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1076 * However, there are cases where the idlethread will be entered with 1077 * the possibility that no IPI will occur and in such cases 1078 * lwkt_switch() sets TDF_IDLE_NOHLT. 1079 * 1080 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1081 * must occur before it starts using ACPI halt. 1082 * 1083 * NOTE: Value overridden in hammer_time(). 1084 */ 1085 static int cpu_idle_hlt = 2; 1086 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1087 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1088 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1089 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1090 1091 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1092 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1093 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1094 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1095 1096 static void 1097 cpu_idle_default_hook(void) 1098 { 1099 /* 1100 * We must guarentee that hlt is exactly the instruction 1101 * following the sti. 1102 */ 1103 __asm __volatile("sti; hlt"); 1104 } 1105 1106 /* Other subsystems (e.g., ACPI) can hook this later. */ 1107 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1108 1109 static __inline int 1110 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1111 { 1112 int hint, cx_idx; 1113 u_int idx; 1114 1115 hint = stat->hint; 1116 if (hint >= 0) 1117 goto done; 1118 1119 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1120 cpu_mwait_repeat_shift; 1121 if (idx >= cpu_mwait_c1_hints_cnt) { 1122 /* Step up faster, once we walked through all C1 states */ 1123 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1124 } 1125 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1126 if (idx >= cpu_mwait_deep_hints_cnt) 1127 idx = cpu_mwait_deep_hints_cnt - 1; 1128 hint = cpu_mwait_deep_hints[idx]; 1129 } else { 1130 if (idx >= cpu_mwait_hints_cnt) 1131 idx = cpu_mwait_hints_cnt - 1; 1132 hint = cpu_mwait_hints[idx]; 1133 } 1134 done: 1135 cx_idx = MWAIT_EAX_TO_CX(hint); 1136 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1137 stat->mwait_cx[cx_idx]++; 1138 return hint; 1139 } 1140 1141 void 1142 cpu_idle(void) 1143 { 1144 globaldata_t gd = mycpu; 1145 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1146 struct thread *td __debugvar = gd->gd_curthread; 1147 int reqflags; 1148 1149 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1150 1151 crit_exit(); 1152 KKASSERT(td->td_critcount == 0); 1153 1154 for (;;) { 1155 /* 1156 * See if there are any LWKTs ready to go. 1157 */ 1158 lwkt_switch(); 1159 1160 /* 1161 * When halting inside a cli we must check for reqflags 1162 * races, particularly [re]schedule requests. Running 1163 * splz() does the job. 1164 * 1165 * cpu_idle_hlt: 1166 * 0 Never halt, just spin 1167 * 1168 * 1 Always use MONITOR/MWAIT if avail, HLT 1169 * otherwise. 1170 * 1171 * Better default for modern (Haswell+) Intel 1172 * cpus. 1173 * 1174 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1175 * use the ACPI halt (default). This is a hybrid 1176 * approach. See machdep.cpu_idle_repeat. 1177 * 1178 * Better default for modern AMD cpus and older 1179 * Intel cpus. 1180 * 1181 * 3 Always use the ACPI halt. This typically 1182 * eats the least amount of power but the cpu 1183 * will be slow waking up. Slows down e.g. 1184 * compiles and other pipe/event oriented stuff. 1185 * 1186 * Usually the best default for AMD cpus. 1187 * 1188 * 4 Always use HLT. 1189 * 1190 * 5 Always spin. 1191 * 1192 * NOTE: Interrupts are enabled and we are not in a critical 1193 * section. 1194 * 1195 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1196 * don't bother capping gd_idle_repeat, it is ok if 1197 * it overflows (we do make it unsigned, however). 1198 * 1199 * Implement optimized invltlb operations when halted 1200 * in idle. By setting the bit in smp_idleinvl_mask 1201 * we inform other cpus that they can set _reqs to 1202 * request an invltlb. Current the code to do that 1203 * sets the bits in _reqs anyway, but then check _mask 1204 * to determine if they can assume the invltlb will execute. 1205 * 1206 * A critical section is required to ensure that interrupts 1207 * do not fully run until after we've had a chance to execute 1208 * the request. 1209 */ 1210 if (gd->gd_idle_repeat == 0) { 1211 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1212 if (stat->repeat > cpu_idle_repeat_max) 1213 stat->repeat = cpu_idle_repeat_max; 1214 stat->repeat_last = 0; 1215 stat->repeat_delta = 0; 1216 } 1217 ++stat->repeat_last; 1218 1219 /* 1220 * General idle thread halt code 1221 * 1222 * IBRS NOTES - IBRS is a SPECTRE mitigation. When going 1223 * idle, disable IBRS to reduce hyperthread 1224 * overhead. 1225 */ 1226 ++gd->gd_idle_repeat; 1227 1228 switch(cpu_idle_hlt) { 1229 default: 1230 case 0: 1231 /* 1232 * Always spin 1233 */ 1234 ; 1235 do_spin: 1236 splz(); 1237 __asm __volatile("sti"); 1238 stat->spin++; 1239 crit_enter_gd(gd); 1240 crit_exit_gd(gd); 1241 break; 1242 case 2: 1243 /* 1244 * Use MONITOR/MWAIT (or HLT) for a few cycles, 1245 * then start using the ACPI halt code if we 1246 * continue to be idle. 1247 */ 1248 if (gd->gd_idle_repeat >= cpu_idle_repeat) 1249 goto do_acpi; 1250 /* FALL THROUGH */ 1251 case 1: 1252 /* 1253 * Always use MONITOR/MWAIT (will use HLT if 1254 * MONITOR/MWAIT not available). 1255 */ 1256 if (cpu_mi_feature & CPU_MI_MONITOR) { 1257 splz(); /* XXX */ 1258 reqflags = gd->gd_reqflags; 1259 if (reqflags & RQF_IDLECHECK_WK_MASK) 1260 goto do_spin; 1261 crit_enter_gd(gd); 1262 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1263 /* 1264 * IBRS/STIBP 1265 */ 1266 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1267 SPEC_CTRL_DUMMY_ENABLE) { 1268 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1269 } 1270 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1271 cpu_mwait_cx_hint(stat), 0); 1272 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1273 SPEC_CTRL_DUMMY_ENABLE) { 1274 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1275 } 1276 stat->halt++; 1277 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1278 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1279 gd->gd_cpuid)) { 1280 cpu_invltlb(); 1281 cpu_mfence(); 1282 } 1283 crit_exit_gd(gd); 1284 break; 1285 } 1286 /* FALLTHROUGH */ 1287 case 4: 1288 /* 1289 * Use HLT 1290 */ 1291 __asm __volatile("cli"); 1292 splz(); 1293 crit_enter_gd(gd); 1294 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1295 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1296 gd->gd_cpuid); 1297 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1298 SPEC_CTRL_DUMMY_ENABLE) { 1299 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1300 } 1301 cpu_idle_default_hook(); 1302 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1303 SPEC_CTRL_DUMMY_ENABLE) { 1304 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1305 } 1306 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1307 gd->gd_cpuid); 1308 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1309 gd->gd_cpuid)) { 1310 cpu_invltlb(); 1311 cpu_mfence(); 1312 } 1313 } 1314 __asm __volatile("sti"); 1315 stat->halt++; 1316 crit_exit_gd(gd); 1317 break; 1318 case 3: 1319 /* 1320 * Use ACPI halt 1321 */ 1322 ; 1323 do_acpi: 1324 __asm __volatile("cli"); 1325 splz(); 1326 crit_enter_gd(gd); 1327 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1328 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1329 gd->gd_cpuid); 1330 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1331 SPEC_CTRL_DUMMY_ENABLE) { 1332 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1333 } 1334 cpu_idle_hook(); 1335 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1336 SPEC_CTRL_DUMMY_ENABLE) { 1337 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1338 } 1339 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1340 gd->gd_cpuid); 1341 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1342 gd->gd_cpuid)) { 1343 cpu_invltlb(); 1344 cpu_mfence(); 1345 } 1346 } 1347 __asm __volatile("sti"); 1348 stat->halt++; 1349 crit_exit_gd(gd); 1350 break; 1351 } 1352 } 1353 } 1354 1355 /* 1356 * Called from deep ACPI via cpu_idle_hook() (see above) to actually halt 1357 * the cpu in C1. ACPI might use other halt methods for deeper states 1358 * and not reach here. 1359 * 1360 * For now we always use HLT as we are not sure what ACPI may have actually 1361 * done. MONITOR/MWAIT might not be appropriate. 1362 * 1363 * NOTE: MONITOR/MWAIT does not appear to throttle AMD cpus, while HLT 1364 * does. On Intel, MONITOR/MWAIT does appear to throttle the cpu. 1365 */ 1366 void 1367 cpu_idle_halt(void) 1368 { 1369 globaldata_t gd; 1370 1371 gd = mycpu; 1372 #if 0 1373 /* DISABLED FOR NOW */ 1374 struct cpu_idle_stat *stat; 1375 int reqflags; 1376 1377 1378 if ((cpu_idle_hlt == 1 || cpu_idle_hlt == 2) && 1379 (cpu_mi_feature & CPU_MI_MONITOR) && 1380 cpu_vendor_id != CPU_VENDOR_AMD) { 1381 /* 1382 * Use MONITOR/MWAIT 1383 * 1384 * (NOTE: On ryzen, MWAIT does not throttle clocks, so we 1385 * have to use HLT) 1386 */ 1387 stat = &cpu_idle_stats[gd->gd_cpuid]; 1388 reqflags = gd->gd_reqflags; 1389 if ((reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1390 __asm __volatile("sti"); 1391 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1392 cpu_mwait_cx_hint(stat), 0); 1393 } else { 1394 __asm __volatile("sti; pause"); 1395 } 1396 } else 1397 #endif 1398 { 1399 /* 1400 * Use HLT 1401 */ 1402 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1403 __asm __volatile("sti; hlt"); 1404 else 1405 __asm __volatile("sti; pause"); 1406 } 1407 } 1408 1409 1410 /* 1411 * Called in a loop indirectly via Xcpustop 1412 */ 1413 void 1414 cpu_smp_stopped(void) 1415 { 1416 globaldata_t gd = mycpu; 1417 volatile __uint64_t *ptr; 1418 __uint64_t ovalue; 1419 1420 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1421 ovalue = *ptr; 1422 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1423 if (cpu_mi_feature & CPU_MI_MONITOR) { 1424 if (cpu_mwait_hints) { 1425 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1426 ovalue, 1427 cpu_mwait_hints[ 1428 cpu_mwait_hints_cnt - 1], 0); 1429 } else { 1430 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1431 ovalue, 0, 0); 1432 } 1433 } else { 1434 cpu_halt(); /* depend on lapic timer */ 1435 } 1436 } 1437 } 1438 1439 /* 1440 * This routine is called if a spinlock has been held through the 1441 * exponential backoff period and is seriously contested. On a real cpu 1442 * we let it spin. 1443 */ 1444 void 1445 cpu_spinlock_contested(void) 1446 { 1447 cpu_pause(); 1448 } 1449 1450 /* 1451 * Clear registers on exec 1452 */ 1453 void 1454 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1455 { 1456 struct thread *td = curthread; 1457 struct lwp *lp = td->td_lwp; 1458 struct pcb *pcb = td->td_pcb; 1459 struct trapframe *regs = lp->lwp_md.md_regs; 1460 1461 user_ldt_free(pcb); 1462 1463 clear_quickret(); 1464 bzero((char *)regs, sizeof(struct trapframe)); 1465 regs->tf_rip = entry; 1466 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1467 regs->tf_rdi = stack; /* argv */ 1468 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1469 regs->tf_ss = _udatasel; 1470 regs->tf_cs = _ucodesel; 1471 regs->tf_rbx = ps_strings; 1472 1473 /* 1474 * Reset the hardware debug registers if they were in use. 1475 * They won't have any meaning for the newly exec'd process. 1476 */ 1477 if (pcb->pcb_flags & PCB_DBREGS) { 1478 pcb->pcb_dr0 = 0; 1479 pcb->pcb_dr1 = 0; 1480 pcb->pcb_dr2 = 0; 1481 pcb->pcb_dr3 = 0; 1482 pcb->pcb_dr6 = 0; 1483 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1484 if (pcb == td->td_pcb) { 1485 /* 1486 * Clear the debug registers on the running 1487 * CPU, otherwise they will end up affecting 1488 * the next process we switch to. 1489 */ 1490 reset_dbregs(); 1491 } 1492 pcb->pcb_flags &= ~PCB_DBREGS; 1493 } 1494 1495 /* 1496 * Initialize the math emulator (if any) for the current process. 1497 * Actually, just clear the bit that says that the emulator has 1498 * been initialized. Initialization is delayed until the process 1499 * traps to the emulator (if it is done at all) mainly because 1500 * emulators don't provide an entry point for initialization. 1501 */ 1502 pcb->pcb_flags &= ~FP_SOFTFP; 1503 1504 /* 1505 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1506 * gd_npxthread. Otherwise a preemptive interrupt thread 1507 * may panic in npxdna(). 1508 */ 1509 crit_enter(); 1510 load_cr0(rcr0() | CR0_MP); 1511 1512 /* 1513 * NOTE: The MSR values must be correct so we can return to 1514 * userland. gd_user_fs/gs must be correct so the switch 1515 * code knows what the current MSR values are. 1516 */ 1517 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1518 pcb->pcb_gsbase = 0; 1519 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1520 mdcpu->gd_user_gs = 0; 1521 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1522 wrmsr(MSR_KGSBASE, 0); 1523 1524 /* Initialize the npx (if any) for the current process. */ 1525 npxinit(); 1526 crit_exit(); 1527 1528 pcb->pcb_ds = _udatasel; 1529 pcb->pcb_es = _udatasel; 1530 pcb->pcb_fs = _udatasel; 1531 pcb->pcb_gs = _udatasel; 1532 } 1533 1534 void 1535 cpu_setregs(void) 1536 { 1537 register_t cr0; 1538 1539 cr0 = rcr0(); 1540 cr0 |= CR0_NE; /* Done by npxinit() */ 1541 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1542 cr0 |= CR0_WP | CR0_AM; 1543 load_cr0(cr0); 1544 load_gs(_udatasel); 1545 } 1546 1547 static int 1548 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1549 { 1550 int error; 1551 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1552 req); 1553 if (!error && req->newptr) 1554 resettodr(); 1555 return (error); 1556 } 1557 1558 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1559 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1560 1561 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1562 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1563 1564 #if 0 /* JG */ 1565 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1566 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1567 #endif 1568 1569 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1570 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1571 1572 static int 1573 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1574 { 1575 struct efi_map_header *efihdr; 1576 caddr_t kmdp; 1577 uint32_t efisize; 1578 1579 kmdp = preload_search_by_type("elf kernel"); 1580 if (kmdp == NULL) 1581 kmdp = preload_search_by_type("elf64 kernel"); 1582 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1583 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1584 if (efihdr == NULL) 1585 return (0); 1586 efisize = *((uint32_t *)efihdr - 1); 1587 return (SYSCTL_OUT(req, efihdr, efisize)); 1588 } 1589 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1590 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1591 1592 /* 1593 * Initialize x86 and configure to run kernel 1594 */ 1595 1596 /* 1597 * Initialize segments & interrupt table 1598 */ 1599 1600 int _default_ldt; 1601 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1602 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1603 #if 0 /* JG */ 1604 union descriptor ldt[NLDT]; /* local descriptor table */ 1605 #endif 1606 1607 /* table descriptors - used to load tables by cpu */ 1608 struct region_descriptor r_gdt; 1609 struct region_descriptor r_idt_arr[MAXCPU]; 1610 1611 /* JG proc0paddr is a virtual address */ 1612 void *proc0paddr; 1613 /* JG alignment? */ 1614 char proc0paddr_buff[LWKT_THREAD_STACK]; 1615 1616 1617 /* software prototypes -- in more palatable form */ 1618 struct soft_segment_descriptor gdt_segs[] = { 1619 /* GNULL_SEL 0 Null Descriptor */ 1620 { 0x0, /* segment base address */ 1621 0x0, /* length */ 1622 0, /* segment type */ 1623 0, /* segment descriptor priority level */ 1624 0, /* segment descriptor present */ 1625 0, /* long */ 1626 0, /* default 32 vs 16 bit size */ 1627 0 /* limit granularity (byte/page units)*/ }, 1628 /* GCODE_SEL 1 Code Descriptor for kernel */ 1629 { 0x0, /* segment base address */ 1630 0xfffff, /* length - all address space */ 1631 SDT_MEMERA, /* segment type */ 1632 SEL_KPL, /* segment descriptor priority level */ 1633 1, /* segment descriptor present */ 1634 1, /* long */ 1635 0, /* default 32 vs 16 bit size */ 1636 1 /* limit granularity (byte/page units)*/ }, 1637 /* GDATA_SEL 2 Data Descriptor for kernel */ 1638 { 0x0, /* segment base address */ 1639 0xfffff, /* length - all address space */ 1640 SDT_MEMRWA, /* segment type */ 1641 SEL_KPL, /* segment descriptor priority level */ 1642 1, /* segment descriptor present */ 1643 1, /* long */ 1644 0, /* default 32 vs 16 bit size */ 1645 1 /* limit granularity (byte/page units)*/ }, 1646 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1647 { 0x0, /* segment base address */ 1648 0xfffff, /* length - all address space */ 1649 SDT_MEMERA, /* segment type */ 1650 SEL_UPL, /* segment descriptor priority level */ 1651 1, /* segment descriptor present */ 1652 0, /* long */ 1653 1, /* default 32 vs 16 bit size */ 1654 1 /* limit granularity (byte/page units)*/ }, 1655 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1656 { 0x0, /* segment base address */ 1657 0xfffff, /* length - all address space */ 1658 SDT_MEMRWA, /* segment type */ 1659 SEL_UPL, /* segment descriptor priority level */ 1660 1, /* segment descriptor present */ 1661 0, /* long */ 1662 1, /* default 32 vs 16 bit size */ 1663 1 /* limit granularity (byte/page units)*/ }, 1664 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1665 { 0x0, /* segment base address */ 1666 0xfffff, /* length - all address space */ 1667 SDT_MEMERA, /* segment type */ 1668 SEL_UPL, /* segment descriptor priority level */ 1669 1, /* segment descriptor present */ 1670 1, /* long */ 1671 0, /* default 32 vs 16 bit size */ 1672 1 /* limit granularity (byte/page units)*/ }, 1673 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1674 { 1675 0x0, /* segment base address */ 1676 sizeof(struct x86_64tss)-1,/* length - all address space */ 1677 SDT_SYSTSS, /* segment type */ 1678 SEL_KPL, /* segment descriptor priority level */ 1679 1, /* segment descriptor present */ 1680 0, /* long */ 1681 0, /* unused - default 32 vs 16 bit size */ 1682 0 /* limit granularity (byte/page units)*/ }, 1683 /* Actually, the TSS is a system descriptor which is double size */ 1684 { 0x0, /* segment base address */ 1685 0x0, /* length */ 1686 0, /* segment type */ 1687 0, /* segment descriptor priority level */ 1688 0, /* segment descriptor present */ 1689 0, /* long */ 1690 0, /* default 32 vs 16 bit size */ 1691 0 /* limit granularity (byte/page units)*/ }, 1692 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1693 { 0x0, /* segment base address */ 1694 0xfffff, /* length - all address space */ 1695 SDT_MEMRWA, /* segment type */ 1696 SEL_UPL, /* segment descriptor priority level */ 1697 1, /* segment descriptor present */ 1698 0, /* long */ 1699 1, /* default 32 vs 16 bit size */ 1700 1 /* limit granularity (byte/page units)*/ }, 1701 }; 1702 1703 void 1704 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1705 { 1706 int cpu; 1707 1708 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1709 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1710 1711 ip->gd_looffset = (uintptr_t)func; 1712 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1713 ip->gd_ist = ist; 1714 ip->gd_xx = 0; 1715 ip->gd_type = typ; 1716 ip->gd_dpl = dpl; 1717 ip->gd_p = 1; 1718 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1719 } 1720 } 1721 1722 void 1723 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1724 { 1725 struct gate_descriptor *ip; 1726 1727 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1728 1729 ip = &idt_arr[cpu][idx]; 1730 ip->gd_looffset = (uintptr_t)func; 1731 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1732 ip->gd_ist = ist; 1733 ip->gd_xx = 0; 1734 ip->gd_type = typ; 1735 ip->gd_dpl = dpl; 1736 ip->gd_p = 1; 1737 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1738 } 1739 1740 #define IDTVEC(name) __CONCAT(X,name) 1741 1742 extern inthand_t 1743 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1744 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1745 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1746 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1747 IDTVEC(xmm), IDTVEC(dblfault), 1748 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1749 1750 void 1751 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1752 { 1753 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1754 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1755 ssd->ssd_type = sd->sd_type; 1756 ssd->ssd_dpl = sd->sd_dpl; 1757 ssd->ssd_p = sd->sd_p; 1758 ssd->ssd_def32 = sd->sd_def32; 1759 ssd->ssd_gran = sd->sd_gran; 1760 } 1761 1762 void 1763 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1764 { 1765 1766 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1767 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1768 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1769 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1770 sd->sd_type = ssd->ssd_type; 1771 sd->sd_dpl = ssd->ssd_dpl; 1772 sd->sd_p = ssd->ssd_p; 1773 sd->sd_long = ssd->ssd_long; 1774 sd->sd_def32 = ssd->ssd_def32; 1775 sd->sd_gran = ssd->ssd_gran; 1776 } 1777 1778 void 1779 ssdtosyssd(struct soft_segment_descriptor *ssd, 1780 struct system_segment_descriptor *sd) 1781 { 1782 1783 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1784 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1785 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1786 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1787 sd->sd_type = ssd->ssd_type; 1788 sd->sd_dpl = ssd->ssd_dpl; 1789 sd->sd_p = ssd->ssd_p; 1790 sd->sd_gran = ssd->ssd_gran; 1791 } 1792 1793 /* 1794 * Populate the (physmap) array with base/bound pairs describing the 1795 * available physical memory in the system, then test this memory and 1796 * build the phys_avail array describing the actually-available memory. 1797 * 1798 * If we cannot accurately determine the physical memory map, then use 1799 * value from the 0xE801 call, and failing that, the RTC. 1800 * 1801 * Total memory size may be set by the kernel environment variable 1802 * hw.physmem or the compile-time define MAXMEM. 1803 * 1804 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1805 * of PAGE_SIZE. This also greatly reduces the memory test time 1806 * which would otherwise be excessive on machines with > 8G of ram. 1807 * 1808 * XXX first should be vm_paddr_t. 1809 */ 1810 1811 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1812 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1813 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1814 1815 vm_paddr_t physmap[PHYSMAP_SIZE]; 1816 struct bios_smap *smapbase, *smap, *smapend; 1817 struct efi_map_header *efihdrbase; 1818 u_int32_t smapsize; 1819 1820 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1821 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1822 1823 static void 1824 add_smap_entries(int *physmap_idx) 1825 { 1826 int i; 1827 1828 smapsize = *((u_int32_t *)smapbase - 1); 1829 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1830 1831 for (smap = smapbase; smap < smapend; smap++) { 1832 if (boothowto & RB_VERBOSE) 1833 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1834 smap->type, smap->base, smap->length); 1835 1836 if (smap->type != SMAP_TYPE_MEMORY) 1837 continue; 1838 1839 if (smap->length == 0) 1840 continue; 1841 1842 for (i = 0; i <= *physmap_idx; i += 2) { 1843 if (smap->base < physmap[i + 1]) { 1844 if (boothowto & RB_VERBOSE) { 1845 kprintf("Overlapping or non-monotonic " 1846 "memory region, ignoring " 1847 "second region\n"); 1848 } 1849 break; 1850 } 1851 } 1852 if (i <= *physmap_idx) 1853 continue; 1854 1855 Realmem += smap->length; 1856 1857 if (smap->base == physmap[*physmap_idx + 1]) { 1858 physmap[*physmap_idx + 1] += smap->length; 1859 continue; 1860 } 1861 1862 *physmap_idx += 2; 1863 if (*physmap_idx == PHYSMAP_SIZE) { 1864 kprintf("Too many segments in the physical " 1865 "address map, giving up\n"); 1866 break; 1867 } 1868 physmap[*physmap_idx] = smap->base; 1869 physmap[*physmap_idx + 1] = smap->base + smap->length; 1870 } 1871 } 1872 1873 static void 1874 add_efi_map_entries(int *physmap_idx) 1875 { 1876 struct efi_md *map, *p; 1877 const char *type; 1878 size_t efisz; 1879 int i, ndesc; 1880 1881 static const char *types[] = { 1882 "Reserved", 1883 "LoaderCode", 1884 "LoaderData", 1885 "BootServicesCode", 1886 "BootServicesData", 1887 "RuntimeServicesCode", 1888 "RuntimeServicesData", 1889 "ConventionalMemory", 1890 "UnusableMemory", 1891 "ACPIReclaimMemory", 1892 "ACPIMemoryNVS", 1893 "MemoryMappedIO", 1894 "MemoryMappedIOPortSpace", 1895 "PalCode" 1896 }; 1897 1898 /* 1899 * Memory map data provided by UEFI via the GetMemoryMap 1900 * Boot Services API. 1901 */ 1902 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1903 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1904 1905 if (efihdrbase->descriptor_size == 0) 1906 return; 1907 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1908 1909 if (boothowto & RB_VERBOSE) 1910 kprintf("%23s %12s %12s %8s %4s\n", 1911 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1912 1913 for (i = 0, p = map; i < ndesc; i++, 1914 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1915 if (boothowto & RB_VERBOSE) { 1916 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1917 type = types[p->md_type]; 1918 else 1919 type = "<INVALID>"; 1920 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1921 p->md_virt, p->md_pages); 1922 if (p->md_attr & EFI_MD_ATTR_UC) 1923 kprintf("UC "); 1924 if (p->md_attr & EFI_MD_ATTR_WC) 1925 kprintf("WC "); 1926 if (p->md_attr & EFI_MD_ATTR_WT) 1927 kprintf("WT "); 1928 if (p->md_attr & EFI_MD_ATTR_WB) 1929 kprintf("WB "); 1930 if (p->md_attr & EFI_MD_ATTR_UCE) 1931 kprintf("UCE "); 1932 if (p->md_attr & EFI_MD_ATTR_WP) 1933 kprintf("WP "); 1934 if (p->md_attr & EFI_MD_ATTR_RP) 1935 kprintf("RP "); 1936 if (p->md_attr & EFI_MD_ATTR_XP) 1937 kprintf("XP "); 1938 if (p->md_attr & EFI_MD_ATTR_RT) 1939 kprintf("RUNTIME"); 1940 kprintf("\n"); 1941 } 1942 1943 switch (p->md_type) { 1944 case EFI_MD_TYPE_CODE: 1945 case EFI_MD_TYPE_DATA: 1946 case EFI_MD_TYPE_BS_CODE: 1947 case EFI_MD_TYPE_BS_DATA: 1948 case EFI_MD_TYPE_FREE: 1949 /* 1950 * We're allowed to use any entry with these types. 1951 */ 1952 break; 1953 default: 1954 continue; 1955 } 1956 1957 Realmem += p->md_pages * PAGE_SIZE; 1958 1959 if (p->md_phys == physmap[*physmap_idx + 1]) { 1960 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1961 continue; 1962 } 1963 1964 *physmap_idx += 2; 1965 if (*physmap_idx == PHYSMAP_SIZE) { 1966 kprintf("Too many segments in the physical " 1967 "address map, giving up\n"); 1968 break; 1969 } 1970 physmap[*physmap_idx] = p->md_phys; 1971 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1972 } 1973 } 1974 1975 struct fb_info efi_fb_info; 1976 static int have_efi_framebuffer = 0; 1977 1978 static void 1979 efi_fb_init_vaddr(int direct_map) 1980 { 1981 uint64_t sz; 1982 vm_offset_t addr, v; 1983 1984 v = efi_fb_info.vaddr; 1985 sz = efi_fb_info.stride * efi_fb_info.height; 1986 1987 if (direct_map) { 1988 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1989 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1990 efi_fb_info.vaddr = addr; 1991 } else { 1992 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1993 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1994 } 1995 } 1996 1997 static u_int 1998 efifb_color_depth(struct efi_fb *efifb) 1999 { 2000 uint32_t mask; 2001 u_int depth; 2002 2003 mask = efifb->fb_mask_red | efifb->fb_mask_green | 2004 efifb->fb_mask_blue | efifb->fb_mask_reserved; 2005 if (mask == 0) 2006 return (0); 2007 for (depth = 1; mask != 1; depth++) 2008 mask >>= 1; 2009 return (depth); 2010 } 2011 2012 int 2013 probe_efi_fb(int early) 2014 { 2015 struct efi_fb *efifb; 2016 caddr_t kmdp; 2017 u_int depth; 2018 2019 if (have_efi_framebuffer) { 2020 if (!early && 2021 (efi_fb_info.vaddr == 0 || 2022 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 2023 efi_fb_init_vaddr(0); 2024 return 0; 2025 } 2026 2027 kmdp = preload_search_by_type("elf kernel"); 2028 if (kmdp == NULL) 2029 kmdp = preload_search_by_type("elf64 kernel"); 2030 efifb = (struct efi_fb *)preload_search_info(kmdp, 2031 MODINFO_METADATA | MODINFOMD_EFI_FB); 2032 if (efifb == NULL) 2033 return 1; 2034 2035 depth = efifb_color_depth(efifb); 2036 /* 2037 * Our bootloader should already notice, when we won't be able to 2038 * use the UEFI framebuffer. 2039 */ 2040 if (depth != 24 && depth != 32) 2041 return 1; 2042 2043 have_efi_framebuffer = 1; 2044 2045 efi_fb_info.is_vga_boot_display = 1; 2046 efi_fb_info.width = efifb->fb_width; 2047 efi_fb_info.height = efifb->fb_height; 2048 efi_fb_info.depth = depth; 2049 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 2050 efi_fb_info.paddr = efifb->fb_addr; 2051 if (early) { 2052 efi_fb_info.vaddr = 0; 2053 } else { 2054 efi_fb_init_vaddr(0); 2055 } 2056 efi_fb_info.fbops.fb_set_par = NULL; 2057 efi_fb_info.fbops.fb_blank = NULL; 2058 efi_fb_info.fbops.fb_debug_enter = NULL; 2059 efi_fb_info.device = NULL; 2060 2061 return 0; 2062 } 2063 2064 static void 2065 efifb_startup(void *arg) 2066 { 2067 probe_efi_fb(0); 2068 } 2069 2070 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 2071 2072 static void 2073 getmemsize(caddr_t kmdp, u_int64_t first) 2074 { 2075 int off, physmap_idx, pa_indx, da_indx; 2076 int i, j; 2077 vm_paddr_t pa; 2078 vm_paddr_t msgbuf_size; 2079 u_long physmem_tunable; 2080 pt_entry_t *pte; 2081 quad_t dcons_addr, dcons_size; 2082 2083 bzero(physmap, sizeof(physmap)); 2084 physmap_idx = 0; 2085 2086 /* 2087 * get memory map from INT 15:E820, kindly supplied by the loader. 2088 * 2089 * subr_module.c says: 2090 * "Consumer may safely assume that size value precedes data." 2091 * ie: an int32_t immediately precedes smap. 2092 */ 2093 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 2094 MODINFO_METADATA | MODINFOMD_EFI_MAP); 2095 smapbase = (struct bios_smap *)preload_search_info(kmdp, 2096 MODINFO_METADATA | MODINFOMD_SMAP); 2097 if (smapbase == NULL && efihdrbase == NULL) 2098 panic("No BIOS smap or EFI map info from loader!"); 2099 2100 if (efihdrbase == NULL) 2101 add_smap_entries(&physmap_idx); 2102 else 2103 add_efi_map_entries(&physmap_idx); 2104 2105 base_memory = physmap[1] / 1024; 2106 /* make hole for AP bootstrap code */ 2107 physmap[1] = mp_bootaddress(base_memory); 2108 2109 /* Save EBDA address, if any */ 2110 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 2111 ebda_addr <<= 4; 2112 2113 /* 2114 * Maxmem isn't the "maximum memory", it's one larger than the 2115 * highest page of the physical address space. It should be 2116 * called something like "Maxphyspage". We may adjust this 2117 * based on ``hw.physmem'' and the results of the memory test. 2118 */ 2119 Maxmem = atop(physmap[physmap_idx + 1]); 2120 2121 #ifdef MAXMEM 2122 Maxmem = MAXMEM / 4; 2123 #endif 2124 2125 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 2126 Maxmem = atop(physmem_tunable); 2127 2128 /* 2129 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 2130 * in the system. 2131 */ 2132 if (Maxmem > atop(physmap[physmap_idx + 1])) 2133 Maxmem = atop(physmap[physmap_idx + 1]); 2134 2135 /* 2136 * Blowing out the DMAP will blow up the system. 2137 */ 2138 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 2139 kprintf("Limiting Maxmem due to DMAP size\n"); 2140 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 2141 } 2142 2143 if (atop(physmap[physmap_idx + 1]) != Maxmem && 2144 (boothowto & RB_VERBOSE)) { 2145 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 2146 } 2147 2148 /* 2149 * Call pmap initialization to make new kernel address space 2150 * 2151 * Mask off page 0. 2152 */ 2153 pmap_bootstrap(&first); 2154 physmap[0] = PAGE_SIZE; 2155 2156 /* 2157 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2158 * exceeding Maxmem. 2159 */ 2160 for (i = j = 0; i <= physmap_idx; i += 2) { 2161 if (physmap[i+1] > ptoa(Maxmem)) 2162 physmap[i+1] = ptoa(Maxmem); 2163 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2164 ~PHYSMAP_ALIGN_MASK; 2165 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2166 2167 physmap[j] = physmap[i]; 2168 physmap[j+1] = physmap[i+1]; 2169 2170 if (physmap[i] < physmap[i+1]) 2171 j += 2; 2172 } 2173 physmap_idx = j - 2; 2174 2175 /* 2176 * Align anything else used in the validation loop. 2177 * 2178 * Also make sure that our 2MB kernel text+data+bss mappings 2179 * do not overlap potentially allocatable space. 2180 */ 2181 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2182 2183 /* 2184 * Size up each available chunk of physical memory. 2185 */ 2186 pa_indx = 0; 2187 da_indx = 0; 2188 phys_avail[pa_indx].phys_beg = physmap[0]; 2189 phys_avail[pa_indx].phys_end = physmap[0]; 2190 dump_avail[da_indx].phys_beg = 0; 2191 dump_avail[da_indx].phys_end = physmap[0]; 2192 pte = CMAP1; 2193 2194 /* 2195 * Get dcons buffer address 2196 */ 2197 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2198 kgetenv_quad("dcons.size", &dcons_size) == 0) 2199 dcons_addr = 0; 2200 2201 /* 2202 * Validate the physical memory. The physical memory segments 2203 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2204 * of PAGE_SIZE. 2205 * 2206 * We no longer perform an exhaustive memory test. Instead we 2207 * simply test the first and last word in each physmap[] 2208 * segment. 2209 */ 2210 for (i = 0; i <= physmap_idx; i += 2) { 2211 vm_paddr_t end; 2212 vm_paddr_t incr; 2213 2214 end = physmap[i + 1]; 2215 2216 for (pa = physmap[i]; pa < end; pa += incr) { 2217 int page_bad, full; 2218 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2219 uint64_t tmp; 2220 2221 full = FALSE; 2222 2223 /* 2224 * Calculate incr. Just test the first and 2225 * last page in each physmap[] segment. 2226 */ 2227 if (pa == end - PAGE_SIZE) 2228 incr = PAGE_SIZE; 2229 else 2230 incr = end - pa - PAGE_SIZE; 2231 2232 /* 2233 * Make sure we don't skip blacked out areas. 2234 */ 2235 if (pa < 0x200000 && 0x200000 < end) { 2236 incr = 0x200000 - pa; 2237 } 2238 if (dcons_addr > 0 && 2239 pa < dcons_addr && 2240 dcons_addr < end) { 2241 incr = dcons_addr - pa; 2242 } 2243 2244 /* 2245 * Block out kernel memory as not available. 2246 */ 2247 if (pa >= 0x200000 && pa < first) { 2248 incr = first - pa; 2249 if (pa + incr > end) 2250 incr = end - pa; 2251 goto do_dump_avail; 2252 } 2253 2254 /* 2255 * Block out the dcons buffer if it exists. 2256 */ 2257 if (dcons_addr > 0 && 2258 pa >= trunc_page(dcons_addr) && 2259 pa < dcons_addr + dcons_size) { 2260 incr = dcons_addr + dcons_size - pa; 2261 incr = (incr + PAGE_MASK) & 2262 ~(vm_paddr_t)PAGE_MASK; 2263 if (pa + incr > end) 2264 incr = end - pa; 2265 goto do_dump_avail; 2266 } 2267 2268 page_bad = FALSE; 2269 2270 /* 2271 * Map the page non-cacheable for the memory 2272 * test. 2273 */ 2274 *pte = pa | 2275 kernel_pmap.pmap_bits[PG_V_IDX] | 2276 kernel_pmap.pmap_bits[PG_RW_IDX] | 2277 kernel_pmap.pmap_bits[PG_N_IDX]; 2278 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2279 cpu_mfence(); 2280 2281 /* 2282 * Save original value for restoration later. 2283 */ 2284 tmp = *ptr; 2285 2286 /* 2287 * Test for alternating 1's and 0's 2288 */ 2289 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2290 cpu_mfence(); 2291 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2292 page_bad = TRUE; 2293 /* 2294 * Test for alternating 0's and 1's 2295 */ 2296 *ptr = 0x5555555555555555LLU; 2297 cpu_mfence(); 2298 if (*ptr != 0x5555555555555555LLU) 2299 page_bad = TRUE; 2300 /* 2301 * Test for all 1's 2302 */ 2303 *ptr = 0xffffffffffffffffLLU; 2304 cpu_mfence(); 2305 if (*ptr != 0xffffffffffffffffLLU) 2306 page_bad = TRUE; 2307 /* 2308 * Test for all 0's 2309 */ 2310 *ptr = 0x0; 2311 cpu_mfence(); 2312 if (*ptr != 0x0) 2313 page_bad = TRUE; 2314 2315 /* 2316 * Restore original value. 2317 */ 2318 *ptr = tmp; 2319 2320 /* 2321 * Adjust array of valid/good pages. 2322 */ 2323 if (page_bad == TRUE) { 2324 incr = PAGE_SIZE; 2325 continue; 2326 } 2327 2328 /* 2329 * Collapse page address into phys_avail[]. Do a 2330 * continuation of the current phys_avail[] index 2331 * when possible. 2332 */ 2333 if (phys_avail[pa_indx].phys_end == pa) { 2334 /* 2335 * Continuation 2336 */ 2337 phys_avail[pa_indx].phys_end += incr; 2338 } else if (phys_avail[pa_indx].phys_beg == 2339 phys_avail[pa_indx].phys_end) { 2340 /* 2341 * Current phys_avail is completely empty, 2342 * reuse the index. 2343 */ 2344 phys_avail[pa_indx].phys_beg = pa; 2345 phys_avail[pa_indx].phys_end = pa + incr; 2346 } else { 2347 /* 2348 * Allocate next phys_avail index. 2349 */ 2350 ++pa_indx; 2351 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2352 kprintf( 2353 "Too many holes in the physical address space, giving up\n"); 2354 --pa_indx; 2355 full = TRUE; 2356 goto do_dump_avail; 2357 } 2358 phys_avail[pa_indx].phys_beg = pa; 2359 phys_avail[pa_indx].phys_end = pa + incr; 2360 } 2361 physmem += incr / PAGE_SIZE; 2362 2363 /* 2364 * pa available for dumping 2365 */ 2366 do_dump_avail: 2367 if (dump_avail[da_indx].phys_end == pa) { 2368 dump_avail[da_indx].phys_end += incr; 2369 } else { 2370 ++da_indx; 2371 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2372 --da_indx; 2373 goto do_next; 2374 } 2375 dump_avail[da_indx].phys_beg = pa; 2376 dump_avail[da_indx].phys_end = pa + incr; 2377 } 2378 do_next: 2379 if (full) 2380 break; 2381 } 2382 } 2383 *pte = 0; 2384 cpu_invltlb(); 2385 cpu_mfence(); 2386 2387 /* 2388 * The last chunk must contain at least one page plus the message 2389 * buffer to avoid complicating other code (message buffer address 2390 * calculation, etc.). 2391 */ 2392 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2393 2394 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2395 phys_avail[pa_indx].phys_end) { 2396 physmem -= atop(phys_avail[pa_indx].phys_end - 2397 phys_avail[pa_indx].phys_beg); 2398 phys_avail[pa_indx].phys_beg = 0; 2399 phys_avail[pa_indx].phys_end = 0; 2400 --pa_indx; 2401 } 2402 2403 Maxmem = atop(phys_avail[pa_indx].phys_end); 2404 2405 /* Trim off space for the message buffer. */ 2406 phys_avail[pa_indx].phys_end -= msgbuf_size; 2407 2408 avail_end = phys_avail[pa_indx].phys_end; 2409 2410 /* Map the message buffer. */ 2411 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2412 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2413 } 2414 /* Try to get EFI framebuffer working as early as possible */ 2415 if (have_efi_framebuffer) 2416 efi_fb_init_vaddr(1); 2417 } 2418 2419 struct machintr_abi MachIntrABI; 2420 2421 /* 2422 * IDT VECTORS: 2423 * 0 Divide by zero 2424 * 1 Debug 2425 * 2 NMI 2426 * 3 BreakPoint 2427 * 4 OverFlow 2428 * 5 Bound-Range 2429 * 6 Invalid OpCode 2430 * 7 Device Not Available (x87) 2431 * 8 Double-Fault 2432 * 9 Coprocessor Segment overrun (unsupported, reserved) 2433 * 10 Invalid-TSS 2434 * 11 Segment not present 2435 * 12 Stack 2436 * 13 General Protection 2437 * 14 Page Fault 2438 * 15 Reserved 2439 * 16 x87 FP Exception pending 2440 * 17 Alignment Check 2441 * 18 Machine Check 2442 * 19 SIMD floating point 2443 * 20-31 reserved 2444 * 32-255 INTn/external sources 2445 */ 2446 u_int64_t 2447 hammer_time(u_int64_t modulep, u_int64_t physfree) 2448 { 2449 caddr_t kmdp; 2450 int gsel_tss, x, cpu; 2451 #if 0 /* JG */ 2452 int metadata_missing, off; 2453 #endif 2454 struct mdglobaldata *gd; 2455 struct privatespace *ps; 2456 u_int64_t msr; 2457 2458 /* 2459 * Prevent lowering of the ipl if we call tsleep() early. 2460 */ 2461 gd = &CPU_prvspace[0]->mdglobaldata; 2462 ps = (struct privatespace *)gd; 2463 bzero(gd, sizeof(*gd)); 2464 bzero(&ps->common_tss, sizeof(ps->common_tss)); 2465 2466 /* 2467 * Note: on both UP and SMP curthread must be set non-NULL 2468 * early in the boot sequence because the system assumes 2469 * that 'curthread' is never NULL. 2470 */ 2471 2472 gd->mi.gd_curthread = &thread0; 2473 thread0.td_gd = &gd->mi; 2474 2475 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2476 2477 #if 0 /* JG */ 2478 metadata_missing = 0; 2479 if (bootinfo.bi_modulep) { 2480 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2481 preload_bootstrap_relocate(KERNBASE); 2482 } else { 2483 metadata_missing = 1; 2484 } 2485 if (bootinfo.bi_envp) 2486 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2487 #endif 2488 2489 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2490 preload_bootstrap_relocate(PTOV_OFFSET); 2491 kmdp = preload_search_by_type("elf kernel"); 2492 if (kmdp == NULL) 2493 kmdp = preload_search_by_type("elf64 kernel"); 2494 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2495 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2496 #ifdef DDB 2497 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2498 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2499 #endif 2500 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2501 2502 if (boothowto & RB_VERBOSE) 2503 bootverbose++; 2504 2505 /* 2506 * Default MachIntrABI to ICU 2507 */ 2508 MachIntrABI = MachIntrABI_ICU; 2509 2510 /* 2511 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2512 */ 2513 ncpus = 1; 2514 ncpus_fit = 1; 2515 /* Init basic tunables, hz etc */ 2516 init_param1(); 2517 2518 /* 2519 * make gdt memory segments 2520 */ 2521 gdt_segs[GPROC0_SEL].ssd_base = 2522 (uintptr_t) &CPU_prvspace[0]->common_tss; 2523 2524 gd->mi.gd_prvspace = CPU_prvspace[0]; 2525 2526 for (x = 0; x < NGDT; x++) { 2527 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2528 ssdtosd(&gdt_segs[x], &gdt[x]); 2529 } 2530 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2531 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2532 2533 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2534 r_gdt.rd_base = (long) gdt; 2535 lgdt(&r_gdt); 2536 2537 wrmsr(MSR_FSBASE, 0); /* User value */ 2538 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2539 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2540 2541 mi_gdinit(&gd->mi, 0); 2542 cpu_gdinit(gd, 0); 2543 proc0paddr = proc0paddr_buff; 2544 mi_proc0init(&gd->mi, proc0paddr); 2545 safepri = TDPRI_MAX; 2546 2547 /* spinlocks and the BGL */ 2548 init_locks(); 2549 2550 /* exceptions */ 2551 for (x = 0; x < NIDT; x++) 2552 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2553 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2554 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 2); 2555 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2556 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2557 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2558 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2559 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2560 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2561 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2562 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2563 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2564 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2565 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2566 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2567 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2568 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2569 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2570 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2571 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2572 2573 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2574 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2575 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2576 } 2577 2578 lidt(&r_idt_arr[0]); 2579 2580 /* 2581 * Initialize the console before we print anything out. 2582 */ 2583 cninit(); 2584 2585 #if 0 /* JG */ 2586 if (metadata_missing) 2587 kprintf("WARNING: loader(8) metadata is missing!\n"); 2588 #endif 2589 2590 #if NISA >0 2591 elcr_probe(); 2592 isa_defaultirq(); 2593 #endif 2594 rand_initialize(); 2595 2596 /* 2597 * Initialize IRQ mapping 2598 * 2599 * NOTE: 2600 * SHOULD be after elcr_probe() 2601 */ 2602 MachIntrABI_ICU.initmap(); 2603 MachIntrABI_IOAPIC.initmap(); 2604 2605 #ifdef DDB 2606 kdb_init(); 2607 if (boothowto & RB_KDB) 2608 Debugger("Boot flags requested debugger"); 2609 #endif 2610 2611 identify_cpu(); /* Final stage of CPU initialization */ 2612 initializecpu(0); /* Initialize CPU registers */ 2613 2614 /* 2615 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2616 * because the cpu does significant power management in MWAIT 2617 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2618 * 2619 * On many AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2620 * significant power management only when using ACPI halt mode. 2621 * (However, on Ryzen, mode 4 (HLT) also does power management). 2622 * 2623 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2624 * is needed to reduce power consumption, but wakeup times are often 2625 * too long. 2626 */ 2627 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2628 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2629 cpu_idle_hlt = 1; 2630 } 2631 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2632 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2633 /* Ryzen or later */ 2634 cpu_idle_hlt = 3; 2635 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2636 /* Bobcat or later */ 2637 cpu_idle_hlt = 3; 2638 } 2639 } 2640 2641 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2642 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2643 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2644 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2645 2646 /* 2647 * Some of the virtual machines do not work w/ I/O APIC 2648 * enabled. If the user does not explicitly enable or 2649 * disable the I/O APIC (ioapic_enable < 0), then we 2650 * disable I/O APIC on all virtual machines. 2651 * 2652 * NOTE: 2653 * This must be done after identify_cpu(), which sets 2654 * 'cpu_feature2' 2655 */ 2656 if (ioapic_enable < 0) { 2657 if (cpu_feature2 & CPUID2_VMM) 2658 ioapic_enable = 0; 2659 else 2660 ioapic_enable = 1; 2661 } 2662 2663 /* 2664 * TSS entry point for interrupts, traps, and exceptions 2665 * (sans NMI). This will always go to near the top of the pcpu 2666 * trampoline area. Hardware-pushed data will be copied into 2667 * the trap-frame on entry, and (if necessary) returned to the 2668 * trampoline on exit. 2669 * 2670 * We store some pcb data for the trampoline code above the 2671 * stack the cpu hw pushes into, and arrange things so the 2672 * address of tr_pcb_rsp is the same as the desired top of 2673 * stack. 2674 */ 2675 ps->common_tss.tss_rsp0 = (register_t)&ps->trampoline.tr_pcb_rsp; 2676 ps->trampoline.tr_pcb_rsp = ps->common_tss.tss_rsp0; 2677 ps->trampoline.tr_pcb_gs_kernel = (register_t)gd; 2678 ps->trampoline.tr_pcb_cr3 = KPML4phys; /* adj to user cr3 live */ 2679 ps->dbltramp.tr_pcb_gs_kernel = (register_t)gd; 2680 ps->dbltramp.tr_pcb_cr3 = KPML4phys; 2681 ps->dbgtramp.tr_pcb_gs_kernel = (register_t)gd; 2682 ps->dbgtramp.tr_pcb_cr3 = KPML4phys; 2683 2684 /* double fault stack */ 2685 ps->common_tss.tss_ist1 = (register_t)&ps->dbltramp.tr_pcb_rsp; 2686 /* #DB debugger needs its own stack */ 2687 ps->common_tss.tss_ist2 = (register_t)&ps->dbgtramp.tr_pcb_rsp; 2688 2689 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2690 ps->common_tss.tss_iobase = sizeof(struct x86_64tss); 2691 2692 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2693 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2694 gd->gd_common_tssd = *gd->gd_tss_gdt; 2695 ltr(gsel_tss); 2696 2697 /* Set up the fast syscall stuff */ 2698 msr = rdmsr(MSR_EFER) | EFER_SCE; 2699 wrmsr(MSR_EFER, msr); 2700 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2701 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2702 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2703 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2704 wrmsr(MSR_STAR, msr); 2705 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2706 2707 getmemsize(kmdp, physfree); 2708 init_param2(physmem); 2709 2710 /* now running on new page tables, configured,and u/iom is accessible */ 2711 2712 /* Map the message buffer. */ 2713 #if 0 /* JG */ 2714 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2715 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2716 #endif 2717 2718 msgbufinit(msgbufp, MSGBUF_SIZE); 2719 2720 2721 /* transfer to user mode */ 2722 2723 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2724 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2725 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2726 2727 load_ds(_udatasel); 2728 load_es(_udatasel); 2729 load_fs(_udatasel); 2730 2731 /* setup proc 0's pcb */ 2732 thread0.td_pcb->pcb_flags = 0; 2733 thread0.td_pcb->pcb_cr3 = KPML4phys; 2734 thread0.td_pcb->pcb_cr3_iso = 0; 2735 thread0.td_pcb->pcb_ext = NULL; 2736 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2737 2738 /* Location of kernel stack for locore */ 2739 return ((u_int64_t)thread0.td_pcb); 2740 } 2741 2742 /* 2743 * Initialize machine-dependant portions of the global data structure. 2744 * Note that the global data area and cpu0's idlestack in the private 2745 * data space were allocated in locore. 2746 * 2747 * Note: the idlethread's cpl is 0 2748 * 2749 * WARNING! Called from early boot, 'mycpu' may not work yet. 2750 */ 2751 void 2752 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2753 { 2754 if (cpu) 2755 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2756 2757 lwkt_init_thread(&gd->mi.gd_idlethread, 2758 gd->mi.gd_prvspace->idlestack, 2759 sizeof(gd->mi.gd_prvspace->idlestack), 2760 0, &gd->mi); 2761 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2762 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2763 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2764 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2765 } 2766 2767 /* 2768 * We only have to check for DMAP bounds, the globaldata space is 2769 * actually part of the kernel_map so we don't have to waste time 2770 * checking CPU_prvspace[*]. 2771 */ 2772 int 2773 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2774 { 2775 #if 0 2776 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2777 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2778 return (TRUE); 2779 } 2780 #endif 2781 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2782 return (TRUE); 2783 return (FALSE); 2784 } 2785 2786 struct globaldata * 2787 globaldata_find(int cpu) 2788 { 2789 KKASSERT(cpu >= 0 && cpu < ncpus); 2790 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2791 } 2792 2793 /* 2794 * This path should be safe from the SYSRET issue because only stopped threads 2795 * can have their %rip adjusted this way (and all heavy weight thread switches 2796 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2797 * convoluted so add a safety by forcing %rip to be cannonical. 2798 */ 2799 int 2800 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2801 { 2802 if (addr & 0x0000800000000000LLU) 2803 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2804 else 2805 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2806 return (0); 2807 } 2808 2809 int 2810 ptrace_single_step(struct lwp *lp) 2811 { 2812 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2813 return (0); 2814 } 2815 2816 int 2817 fill_regs(struct lwp *lp, struct reg *regs) 2818 { 2819 struct trapframe *tp; 2820 2821 if ((tp = lp->lwp_md.md_regs) == NULL) 2822 return EINVAL; 2823 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2824 return (0); 2825 } 2826 2827 int 2828 set_regs(struct lwp *lp, struct reg *regs) 2829 { 2830 struct trapframe *tp; 2831 2832 tp = lp->lwp_md.md_regs; 2833 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2834 !CS_SECURE(regs->r_cs)) 2835 return (EINVAL); 2836 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2837 clear_quickret(); 2838 return (0); 2839 } 2840 2841 static void 2842 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2843 { 2844 struct env87 *penv_87 = &sv_87->sv_env; 2845 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2846 int i; 2847 2848 /* FPU control/status */ 2849 penv_87->en_cw = penv_xmm->en_cw; 2850 penv_87->en_sw = penv_xmm->en_sw; 2851 penv_87->en_tw = penv_xmm->en_tw; 2852 penv_87->en_fip = penv_xmm->en_fip; 2853 penv_87->en_fcs = penv_xmm->en_fcs; 2854 penv_87->en_opcode = penv_xmm->en_opcode; 2855 penv_87->en_foo = penv_xmm->en_foo; 2856 penv_87->en_fos = penv_xmm->en_fos; 2857 2858 /* FPU registers */ 2859 for (i = 0; i < 8; ++i) 2860 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2861 } 2862 2863 static void 2864 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2865 { 2866 struct env87 *penv_87 = &sv_87->sv_env; 2867 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2868 int i; 2869 2870 /* FPU control/status */ 2871 penv_xmm->en_cw = penv_87->en_cw; 2872 penv_xmm->en_sw = penv_87->en_sw; 2873 penv_xmm->en_tw = penv_87->en_tw; 2874 penv_xmm->en_fip = penv_87->en_fip; 2875 penv_xmm->en_fcs = penv_87->en_fcs; 2876 penv_xmm->en_opcode = penv_87->en_opcode; 2877 penv_xmm->en_foo = penv_87->en_foo; 2878 penv_xmm->en_fos = penv_87->en_fos; 2879 2880 /* FPU registers */ 2881 for (i = 0; i < 8; ++i) 2882 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2883 } 2884 2885 int 2886 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2887 { 2888 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2889 return EINVAL; 2890 if (cpu_fxsr) { 2891 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2892 (struct save87 *)fpregs); 2893 return (0); 2894 } 2895 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2896 return (0); 2897 } 2898 2899 int 2900 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2901 { 2902 if (cpu_fxsr) { 2903 set_fpregs_xmm((struct save87 *)fpregs, 2904 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2905 return (0); 2906 } 2907 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2908 return (0); 2909 } 2910 2911 int 2912 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2913 { 2914 struct pcb *pcb; 2915 2916 if (lp == NULL) { 2917 dbregs->dr[0] = rdr0(); 2918 dbregs->dr[1] = rdr1(); 2919 dbregs->dr[2] = rdr2(); 2920 dbregs->dr[3] = rdr3(); 2921 dbregs->dr[4] = rdr4(); 2922 dbregs->dr[5] = rdr5(); 2923 dbregs->dr[6] = rdr6(); 2924 dbregs->dr[7] = rdr7(); 2925 return (0); 2926 } 2927 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2928 return EINVAL; 2929 dbregs->dr[0] = pcb->pcb_dr0; 2930 dbregs->dr[1] = pcb->pcb_dr1; 2931 dbregs->dr[2] = pcb->pcb_dr2; 2932 dbregs->dr[3] = pcb->pcb_dr3; 2933 dbregs->dr[4] = 0; 2934 dbregs->dr[5] = 0; 2935 dbregs->dr[6] = pcb->pcb_dr6; 2936 dbregs->dr[7] = pcb->pcb_dr7; 2937 return (0); 2938 } 2939 2940 int 2941 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2942 { 2943 if (lp == NULL) { 2944 load_dr0(dbregs->dr[0]); 2945 load_dr1(dbregs->dr[1]); 2946 load_dr2(dbregs->dr[2]); 2947 load_dr3(dbregs->dr[3]); 2948 load_dr4(dbregs->dr[4]); 2949 load_dr5(dbregs->dr[5]); 2950 load_dr6(dbregs->dr[6]); 2951 load_dr7(dbregs->dr[7]); 2952 } else { 2953 struct pcb *pcb; 2954 struct ucred *ucred; 2955 int i; 2956 uint64_t mask1, mask2; 2957 2958 /* 2959 * Don't let an illegal value for dr7 get set. Specifically, 2960 * check for undefined settings. Setting these bit patterns 2961 * result in undefined behaviour and can lead to an unexpected 2962 * TRCTRAP. 2963 */ 2964 /* JG this loop looks unreadable */ 2965 /* Check 4 2-bit fields for invalid patterns. 2966 * These fields are R/Wi, for i = 0..3 2967 */ 2968 /* Is 10 in LENi allowed when running in compatibility mode? */ 2969 /* Pattern 10 in R/Wi might be used to indicate 2970 * breakpoint on I/O. Further analysis should be 2971 * carried to decide if it is safe and useful to 2972 * provide access to that capability 2973 */ 2974 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2975 i++, mask1 <<= 4, mask2 <<= 4) 2976 if ((dbregs->dr[7] & mask1) == mask2) 2977 return (EINVAL); 2978 2979 pcb = lp->lwp_thread->td_pcb; 2980 ucred = lp->lwp_proc->p_ucred; 2981 2982 /* 2983 * Don't let a process set a breakpoint that is not within the 2984 * process's address space. If a process could do this, it 2985 * could halt the system by setting a breakpoint in the kernel 2986 * (if ddb was enabled). Thus, we need to check to make sure 2987 * that no breakpoints are being enabled for addresses outside 2988 * process's address space, unless, perhaps, we were called by 2989 * uid 0. 2990 * 2991 * XXX - what about when the watched area of the user's 2992 * address space is written into from within the kernel 2993 * ... wouldn't that still cause a breakpoint to be generated 2994 * from within kernel mode? 2995 */ 2996 2997 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2998 if (dbregs->dr[7] & 0x3) { 2999 /* dr0 is enabled */ 3000 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 3001 return (EINVAL); 3002 } 3003 3004 if (dbregs->dr[7] & (0x3<<2)) { 3005 /* dr1 is enabled */ 3006 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 3007 return (EINVAL); 3008 } 3009 3010 if (dbregs->dr[7] & (0x3<<4)) { 3011 /* dr2 is enabled */ 3012 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 3013 return (EINVAL); 3014 } 3015 3016 if (dbregs->dr[7] & (0x3<<6)) { 3017 /* dr3 is enabled */ 3018 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 3019 return (EINVAL); 3020 } 3021 } 3022 3023 pcb->pcb_dr0 = dbregs->dr[0]; 3024 pcb->pcb_dr1 = dbregs->dr[1]; 3025 pcb->pcb_dr2 = dbregs->dr[2]; 3026 pcb->pcb_dr3 = dbregs->dr[3]; 3027 pcb->pcb_dr6 = dbregs->dr[6]; 3028 pcb->pcb_dr7 = dbregs->dr[7]; 3029 3030 pcb->pcb_flags |= PCB_DBREGS; 3031 } 3032 3033 return (0); 3034 } 3035 3036 /* 3037 * Return > 0 if a hardware breakpoint has been hit, and the 3038 * breakpoint was in user space. Return 0, otherwise. 3039 */ 3040 int 3041 user_dbreg_trap(void) 3042 { 3043 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 3044 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 3045 int nbp; /* number of breakpoints that triggered */ 3046 caddr_t addr[4]; /* breakpoint addresses */ 3047 int i; 3048 3049 dr7 = rdr7(); 3050 if ((dr7 & 0xff) == 0) { 3051 /* 3052 * all GE and LE bits in the dr7 register are zero, 3053 * thus the trap couldn't have been caused by the 3054 * hardware debug registers 3055 */ 3056 return 0; 3057 } 3058 3059 nbp = 0; 3060 dr6 = rdr6(); 3061 bp = dr6 & 0xf; 3062 3063 if (bp == 0) { 3064 /* 3065 * None of the breakpoint bits are set meaning this 3066 * trap was not caused by any of the debug registers 3067 */ 3068 return 0; 3069 } 3070 3071 /* 3072 * at least one of the breakpoints were hit, check to see 3073 * which ones and if any of them are user space addresses 3074 */ 3075 3076 if (bp & 0x01) { 3077 addr[nbp++] = (caddr_t)rdr0(); 3078 } 3079 if (bp & 0x02) { 3080 addr[nbp++] = (caddr_t)rdr1(); 3081 } 3082 if (bp & 0x04) { 3083 addr[nbp++] = (caddr_t)rdr2(); 3084 } 3085 if (bp & 0x08) { 3086 addr[nbp++] = (caddr_t)rdr3(); 3087 } 3088 3089 for (i = 0; i < nbp; i++) { 3090 if (addr[i] < (caddr_t)VM_MAX_USER_ADDRESS) { 3091 /* 3092 * addr[i] is in user space 3093 */ 3094 return nbp; 3095 } 3096 } 3097 3098 /* 3099 * None of the breakpoints are in user space. 3100 */ 3101 return 0; 3102 } 3103 3104 3105 #ifndef DDB 3106 void 3107 Debugger(const char *msg) 3108 { 3109 kprintf("Debugger(\"%s\") called.\n", msg); 3110 } 3111 #endif /* no DDB */ 3112 3113 #ifdef DDB 3114 3115 /* 3116 * Provide inb() and outb() as functions. They are normally only 3117 * available as macros calling inlined functions, thus cannot be 3118 * called inside DDB. 3119 * 3120 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 3121 */ 3122 3123 #undef inb 3124 #undef outb 3125 3126 /* silence compiler warnings */ 3127 u_char inb(u_int); 3128 void outb(u_int, u_char); 3129 3130 u_char 3131 inb(u_int port) 3132 { 3133 u_char data; 3134 /* 3135 * We use %%dx and not %1 here because i/o is done at %dx and not at 3136 * %edx, while gcc generates inferior code (movw instead of movl) 3137 * if we tell it to load (u_short) port. 3138 */ 3139 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 3140 return (data); 3141 } 3142 3143 void 3144 outb(u_int port, u_char data) 3145 { 3146 u_char al; 3147 /* 3148 * Use an unnecessary assignment to help gcc's register allocator. 3149 * This make a large difference for gcc-1.40 and a tiny difference 3150 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 3151 * best results. gcc-2.6.0 can't handle this. 3152 */ 3153 al = data; 3154 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 3155 } 3156 3157 #endif /* DDB */ 3158 3159 3160 3161 /* 3162 * initialize all the SMP locks 3163 */ 3164 3165 /* critical region when masking or unmasking interupts */ 3166 struct spinlock_deprecated imen_spinlock; 3167 3168 /* lock region used by kernel profiling */ 3169 struct spinlock_deprecated mcount_spinlock; 3170 3171 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 3172 struct spinlock_deprecated com_spinlock; 3173 3174 /* lock regions around the clock hardware */ 3175 struct spinlock_deprecated clock_spinlock; 3176 3177 static void 3178 init_locks(void) 3179 { 3180 /* 3181 * Get the initial mplock with a count of 1 for the BSP. 3182 * This uses a LOGICAL cpu ID, ie BSP == 0. 3183 */ 3184 cpu_get_initial_mplock(); 3185 /* DEPRECATED */ 3186 spin_init_deprecated(&mcount_spinlock); 3187 spin_init_deprecated(&imen_spinlock); 3188 spin_init_deprecated(&com_spinlock); 3189 spin_init_deprecated(&clock_spinlock); 3190 3191 /* our token pool needs to work early */ 3192 lwkt_token_pool_init(); 3193 } 3194 3195 boolean_t 3196 cpu_mwait_hint_valid(uint32_t hint) 3197 { 3198 int cx_idx, sub; 3199 3200 cx_idx = MWAIT_EAX_TO_CX(hint); 3201 if (cx_idx >= CPU_MWAIT_CX_MAX) 3202 return FALSE; 3203 3204 sub = MWAIT_EAX_TO_CX_SUB(hint); 3205 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3206 return FALSE; 3207 3208 return TRUE; 3209 } 3210 3211 void 3212 cpu_mwait_cx_no_bmsts(void) 3213 { 3214 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3215 } 3216 3217 void 3218 cpu_mwait_cx_no_bmarb(void) 3219 { 3220 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3221 } 3222 3223 static int 3224 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3225 { 3226 int old_cx_idx, sub = 0; 3227 3228 if (hint >= 0) { 3229 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3230 sub = MWAIT_EAX_TO_CX_SUB(hint); 3231 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3232 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3233 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3234 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3235 } else { 3236 old_cx_idx = CPU_MWAIT_CX_MAX; 3237 } 3238 3239 if (!CPU_MWAIT_HAS_CX) 3240 strlcpy(name, "NONE", namelen); 3241 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3242 strlcpy(name, "AUTO", namelen); 3243 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3244 strlcpy(name, "AUTODEEP", namelen); 3245 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3246 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3247 strlcpy(name, "INVALID", namelen); 3248 else 3249 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3250 3251 return old_cx_idx; 3252 } 3253 3254 static int 3255 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3256 { 3257 int cx_idx, sub, hint; 3258 char *ptr, *start; 3259 3260 if (allow_auto && strcmp(name, "AUTO") == 0) { 3261 hint = CPU_MWAIT_HINT_AUTO; 3262 cx_idx = CPU_MWAIT_C2; 3263 goto done; 3264 } 3265 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3266 hint = CPU_MWAIT_HINT_AUTODEEP; 3267 cx_idx = CPU_MWAIT_C3; 3268 goto done; 3269 } 3270 3271 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3272 return -1; 3273 start = &name[1]; 3274 ptr = NULL; 3275 3276 cx_idx = strtol(start, &ptr, 10); 3277 if (ptr == start || *ptr != '/') 3278 return -1; 3279 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3280 return -1; 3281 3282 start = ptr + 1; 3283 ptr = NULL; 3284 3285 sub = strtol(start, &ptr, 10); 3286 if (*ptr != '\0') 3287 return -1; 3288 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3289 return -1; 3290 3291 hint = MWAIT_EAX_HINT(cx_idx, sub); 3292 done: 3293 *hint0 = hint; 3294 return cx_idx; 3295 } 3296 3297 static int 3298 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3299 { 3300 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3301 return EOPNOTSUPP; 3302 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3303 int error; 3304 3305 error = cputimer_intr_powersave_addreq(); 3306 if (error) 3307 return error; 3308 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3309 cputimer_intr_powersave_remreq(); 3310 } 3311 return 0; 3312 } 3313 3314 static int 3315 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3316 boolean_t allow_auto) 3317 { 3318 int error, cx_idx, old_cx_idx, hint; 3319 char name[CPU_MWAIT_CX_NAMELEN]; 3320 3321 hint = *hint0; 3322 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3323 allow_auto); 3324 3325 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3326 if (error != 0 || req->newptr == NULL) 3327 return error; 3328 3329 if (!CPU_MWAIT_HAS_CX) 3330 return EOPNOTSUPP; 3331 3332 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3333 if (cx_idx < 0) 3334 return EINVAL; 3335 3336 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3337 if (error) 3338 return error; 3339 3340 *hint0 = hint; 3341 return 0; 3342 } 3343 3344 static int 3345 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3346 { 3347 int error, cx_idx, old_cx_idx, hint; 3348 char name[CPU_MWAIT_CX_NAMELEN]; 3349 3350 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3351 3352 hint = stat->hint; 3353 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3354 3355 strlcpy(name, cx_name, sizeof(name)); 3356 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3357 if (cx_idx < 0) 3358 return EINVAL; 3359 3360 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3361 if (error) 3362 return error; 3363 3364 stat->hint = hint; 3365 return 0; 3366 } 3367 3368 static int 3369 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3370 { 3371 int hint = cpu_mwait_halt_global; 3372 int error, cx_idx, cpu; 3373 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3374 3375 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3376 3377 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3378 if (error != 0 || req->newptr == NULL) 3379 return error; 3380 3381 if (!CPU_MWAIT_HAS_CX) 3382 return EOPNOTSUPP; 3383 3384 /* Save name for later per-cpu CX configuration */ 3385 strlcpy(cx_name, name, sizeof(cx_name)); 3386 3387 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3388 if (cx_idx < 0) 3389 return EINVAL; 3390 3391 /* Change per-cpu CX configuration */ 3392 for (cpu = 0; cpu < ncpus; ++cpu) { 3393 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3394 if (error) 3395 return error; 3396 } 3397 3398 cpu_mwait_halt_global = hint; 3399 return 0; 3400 } 3401 3402 static int 3403 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3404 { 3405 struct cpu_idle_stat *stat = arg1; 3406 int error; 3407 3408 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3409 &stat->hint, TRUE); 3410 return error; 3411 } 3412 3413 static int 3414 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3415 { 3416 int error; 3417 3418 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3419 &cpu_mwait_spin, FALSE); 3420 return error; 3421 } 3422 3423 /* 3424 * This manual debugging code is called unconditionally from Xtimer 3425 * (the per-cpu timer interrupt) whether the current thread is in a 3426 * critical section or not) and can be useful in tracking down lockups. 3427 * 3428 * NOTE: MANUAL DEBUG CODE 3429 */ 3430 #if 0 3431 static int saveticks[SMP_MAXCPU]; 3432 static int savecounts[SMP_MAXCPU]; 3433 #endif 3434 3435 void 3436 pcpu_timer_always(struct intrframe *frame) 3437 { 3438 #if 0 3439 globaldata_t gd = mycpu; 3440 int cpu = gd->gd_cpuid; 3441 char buf[64]; 3442 short *gptr; 3443 int i; 3444 3445 if (cpu <= 20) { 3446 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3447 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3448 ++gptr; 3449 3450 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3451 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3452 gd->gd_infomsg); 3453 for (i = 0; buf[i]; ++i) { 3454 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3455 } 3456 } 3457 #if 0 3458 if (saveticks[gd->gd_cpuid] != ticks) { 3459 saveticks[gd->gd_cpuid] = ticks; 3460 savecounts[gd->gd_cpuid] = 0; 3461 } 3462 ++savecounts[gd->gd_cpuid]; 3463 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3464 panic("cpud %d panicing on ticks failure", 3465 gd->gd_cpuid); 3466 } 3467 for (i = 0; i < ncpus; ++i) { 3468 int delta; 3469 if (saveticks[i] && panicstr == NULL) { 3470 delta = saveticks[i] - ticks; 3471 if (delta < -10 || delta > 10) { 3472 panic("cpu %d panicing on cpu %d watchdog", 3473 gd->gd_cpuid, i); 3474 } 3475 } 3476 } 3477 #endif 3478 #endif 3479 } 3480