1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008-2017 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 extern void panicifcpuunsupported(void); 137 138 static void cpu_startup(void *); 139 static void pic_finish(void *); 140 static void cpu_finish(void *); 141 142 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 143 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 144 static void init_locks(void); 145 146 extern void pcpu_timer_always(struct intrframe *); 147 148 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 149 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 150 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 151 152 #ifdef DDB 153 extern vm_offset_t ksym_start, ksym_end; 154 #endif 155 156 struct privatespace CPU_prvspace_bsp __aligned(4096); 157 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 158 159 vm_paddr_t efi_systbl_phys; 160 int _udatasel, _ucodesel, _ucode32sel; 161 u_long atdevbase; 162 int64_t tsc_offsets[MAXCPU]; 163 cpumask_t smp_idleinvl_mask; 164 cpumask_t smp_idleinvl_reqs; 165 166 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 167 168 #if defined(SWTCH_OPTIM_STATS) 169 extern int swtch_optim_stats; 170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 171 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 173 CTLFLAG_RD, &tlb_flush_count, 0, ""); 174 #endif 175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 176 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 177 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, 178 CTLFLAG_RD, &cpu_mwait_spin, 0, "monitor/mwait target state"); 179 180 #define CPU_MWAIT_HAS_CX \ 181 ((cpu_feature2 & CPUID2_MON) && \ 182 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 183 184 #define CPU_MWAIT_CX_NAMELEN 16 185 186 #define CPU_MWAIT_C1 1 187 #define CPU_MWAIT_C2 2 188 #define CPU_MWAIT_C3 3 189 #define CPU_MWAIT_CX_MAX 8 190 191 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 192 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 193 194 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 195 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 196 197 struct cpu_mwait_cx { 198 int subcnt; 199 char name[4]; 200 struct sysctl_ctx_list sysctl_ctx; 201 struct sysctl_oid *sysctl_tree; 202 }; 203 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 204 static char cpu_mwait_cx_supported[256]; 205 206 static int cpu_mwait_c1_hints_cnt; 207 static int cpu_mwait_hints_cnt; 208 static int *cpu_mwait_hints; 209 210 static int cpu_mwait_deep_hints_cnt; 211 static int *cpu_mwait_deep_hints; 212 213 #define CPU_IDLE_REPEAT_DEFAULT 750 214 215 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 216 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 217 static u_int cpu_mwait_repeat_shift = 1; 218 219 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 220 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 221 222 static int cpu_mwait_c3_preamble = 223 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 224 CPU_MWAIT_C3_PREAMBLE_BM_STS; 225 226 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 227 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 228 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 229 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 230 231 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 232 int *, boolean_t); 233 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 234 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 235 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 236 237 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 238 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 239 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 240 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 241 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 242 &cpu_mwait_repeat_shift, 0, ""); 243 244 long physmem = 0; 245 246 u_long ebda_addr = 0; 247 248 int imcr_present = 0; 249 250 int naps = 0; /* # of Applications processors */ 251 252 u_int base_memory; 253 254 static int 255 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 256 { 257 u_long pmem = ctob(physmem); 258 int error; 259 260 error = sysctl_handle_long(oidp, &pmem, 0, req); 261 262 return (error); 263 } 264 265 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 266 0, 0, sysctl_hw_physmem, "LU", 267 "Total system memory in bytes (number of pages * page size)"); 268 269 static int 270 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 271 { 272 u_long usermem = ctob(physmem - vmstats.v_wire_count); 273 int error; 274 275 error = sysctl_handle_long(oidp, &usermem, 0, req); 276 277 return (error); 278 } 279 280 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_ULONG|CTLFLAG_RD, 281 0, 0, sysctl_hw_usermem, "LU", ""); 282 283 static int 284 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 285 { 286 int error; 287 u_long availpages; 288 289 availpages = x86_64_btop(avail_end - avail_start); 290 error = sysctl_handle_long(oidp, &availpages, 0, req); 291 292 return (error); 293 } 294 295 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_ULONG|CTLFLAG_RD, 296 0, 0, sysctl_hw_availpages, "LU", ""); 297 298 vm_paddr_t Maxmem; 299 vm_paddr_t Realmem; 300 301 /* 302 * The number of PHYSMAP entries must be one less than the number of 303 * PHYSSEG entries because the PHYSMAP entry that spans the largest 304 * physical address that is accessible by ISA DMA is split into two 305 * PHYSSEG entries. 306 */ 307 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 308 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 309 310 /* must be 1 less so 0 0 can signal end of chunks */ 311 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 312 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 313 314 static vm_offset_t buffer_sva, buffer_eva; 315 vm_offset_t clean_sva, clean_eva; 316 static vm_offset_t pager_sva, pager_eva; 317 static struct trapframe proc0_tf; 318 319 static void 320 cpu_startup(void *dummy) 321 { 322 caddr_t v; 323 vm_size_t size = 0; 324 vm_offset_t firstaddr; 325 326 /* 327 * Good {morning,afternoon,evening,night}. 328 */ 329 kprintf("%s", version); 330 startrtclock(); 331 printcpuinfo(); 332 panicifcpuunsupported(); 333 kprintf("real memory = %ju (%ju MB)\n", 334 (intmax_t)Realmem, 335 (intmax_t)Realmem / 1024 / 1024); 336 /* 337 * Display any holes after the first chunk of extended memory. 338 */ 339 if (bootverbose) { 340 int indx; 341 342 kprintf("Physical memory chunk(s):\n"); 343 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 344 vm_paddr_t size1; 345 346 size1 = phys_avail[indx].phys_end - 347 phys_avail[indx].phys_beg; 348 349 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 350 (intmax_t)phys_avail[indx].phys_beg, 351 (intmax_t)phys_avail[indx].phys_end - 1, 352 (intmax_t)size1, 353 (intmax_t)(size1 / PAGE_SIZE)); 354 } 355 } 356 357 /* 358 * Allocate space for system data structures. 359 * The first available kernel virtual address is in "v". 360 * As pages of kernel virtual memory are allocated, "v" is incremented. 361 * As pages of memory are allocated and cleared, 362 * "firstaddr" is incremented. 363 * An index into the kernel page table corresponding to the 364 * virtual memory address maintained in "v" is kept in "mapaddr". 365 */ 366 367 /* 368 * Make two passes. The first pass calculates how much memory is 369 * needed and allocates it. The second pass assigns virtual 370 * addresses to the various data structures. 371 */ 372 firstaddr = 0; 373 again: 374 v = (caddr_t)firstaddr; 375 376 #define valloc(name, type, num) \ 377 (name) = (type *)v; v = (caddr_t)((name)+(num)) 378 #define valloclim(name, type, num, lim) \ 379 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 380 381 /* 382 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 383 * For the first 64MB of ram nominally allocate sufficient buffers to 384 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 385 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 386 * the buffer cache we limit the eventual kva reservation to 387 * maxbcache bytes. 388 * 389 * factor represents the 1/4 x ram conversion. 390 */ 391 if (nbuf == 0) { 392 long factor = 4 * NBUFCALCSIZE / 1024; 393 long kbytes = physmem * (PAGE_SIZE / 1024); 394 395 nbuf = 50; 396 if (kbytes > 4096) 397 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 398 if (kbytes > 65536) 399 nbuf += (kbytes - 65536) * 2 / (factor * 5); 400 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 401 nbuf = maxbcache / NBUFCALCSIZE; 402 } 403 404 /* 405 * Do not allow the buffer_map to be more then 1/2 the size of the 406 * kernel_map. 407 */ 408 if (nbuf > (virtual_end - virtual_start + 409 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 410 nbuf = (virtual_end - virtual_start + 411 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 412 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 413 } 414 415 /* 416 * Do not allow the buffer_map to use more than 50% of available 417 * physical-equivalent memory. Since the VM pages which back 418 * individual buffers are typically wired, having too many bufs 419 * can prevent the system from paging properly. 420 */ 421 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 422 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 423 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 424 } 425 426 /* 427 * Do not allow the sizeof(struct buf) * nbuf to exceed 1/4 of 428 * the valloc space which is just the virtual_end - virtual_start 429 * section. This is typically ~2GB regardless of the amount of 430 * memory, so we use 500MB as a metric. 431 * 432 * This is because we use valloc() to allocate the buf header array. 433 * 434 * NOTE: buffer space in bytes is limited by vfs.*bufspace sysctls. 435 */ 436 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 4) { 437 nbuf = (virtual_end - virtual_start) / 438 sizeof(struct buf) / 2; 439 kprintf("Warning: nbufs capped at %ld due to " 440 "valloc considerations\n", 441 nbuf); 442 } 443 444 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 445 #ifdef NSWBUF_MIN 446 if (nswbuf_mem < NSWBUF_MIN) 447 nswbuf_mem = NSWBUF_MIN; 448 #endif 449 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 450 #ifdef NSWBUF_MIN 451 if (nswbuf_kva < NSWBUF_MIN) 452 nswbuf_kva = NSWBUF_MIN; 453 #endif 454 455 valloc(swbuf_mem, struct buf, nswbuf_mem); 456 valloc(swbuf_kva, struct buf, nswbuf_kva); 457 valloc(buf, struct buf, nbuf); 458 459 /* 460 * End of first pass, size has been calculated so allocate memory 461 */ 462 if (firstaddr == 0) { 463 size = (vm_size_t)(v - firstaddr); 464 firstaddr = kmem_alloc(&kernel_map, round_page(size), 465 VM_SUBSYS_BUF); 466 if (firstaddr == 0) 467 panic("startup: no room for tables"); 468 goto again; 469 } 470 471 /* 472 * End of second pass, addresses have been assigned 473 * 474 * nbuf is an int, make sure we don't overflow the field. 475 * 476 * On 64-bit systems we always reserve maximal allocations for 477 * buffer cache buffers and there are no fragmentation issues, 478 * so the KVA segment does not have to be excessively oversized. 479 */ 480 if ((vm_size_t)(v - firstaddr) != size) 481 panic("startup: table size inconsistency"); 482 483 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 484 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 485 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 486 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 487 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 488 buffer_map.system_map = 1; 489 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 490 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 491 pager_map_size); 492 pager_map.system_map = 1; 493 kprintf("avail memory = %ju (%ju MB)\n", 494 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 495 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 496 1024 / 1024); 497 } 498 499 struct cpu_idle_stat { 500 int hint; 501 int reserved; 502 u_long halt; 503 u_long spin; 504 u_long repeat; 505 u_long repeat_last; 506 u_long repeat_delta; 507 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 508 } __cachealign; 509 510 #define CPU_IDLE_STAT_HALT -1 511 #define CPU_IDLE_STAT_SPIN -2 512 513 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 514 515 static int 516 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 517 { 518 int idx = arg2, cpu, error; 519 u_long val = 0; 520 521 if (idx == CPU_IDLE_STAT_HALT) { 522 for (cpu = 0; cpu < ncpus; ++cpu) 523 val += cpu_idle_stats[cpu].halt; 524 } else if (idx == CPU_IDLE_STAT_SPIN) { 525 for (cpu = 0; cpu < ncpus; ++cpu) 526 val += cpu_idle_stats[cpu].spin; 527 } else { 528 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 529 ("invalid index %d", idx)); 530 for (cpu = 0; cpu < ncpus; ++cpu) 531 val += cpu_idle_stats[cpu].mwait_cx[idx]; 532 } 533 534 error = sysctl_handle_quad(oidp, &val, 0, req); 535 if (error || req->newptr == NULL) 536 return error; 537 538 if (idx == CPU_IDLE_STAT_HALT) { 539 for (cpu = 0; cpu < ncpus; ++cpu) 540 cpu_idle_stats[cpu].halt = 0; 541 cpu_idle_stats[0].halt = val; 542 } else if (idx == CPU_IDLE_STAT_SPIN) { 543 for (cpu = 0; cpu < ncpus; ++cpu) 544 cpu_idle_stats[cpu].spin = 0; 545 cpu_idle_stats[0].spin = val; 546 } else { 547 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 548 ("invalid index %d", idx)); 549 for (cpu = 0; cpu < ncpus; ++cpu) 550 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 551 cpu_idle_stats[0].mwait_cx[idx] = val; 552 } 553 return 0; 554 } 555 556 static void 557 cpu_mwait_attach(void) 558 { 559 struct sbuf sb; 560 int hint_idx, i; 561 562 if (!CPU_MWAIT_HAS_CX) 563 return; 564 565 if (cpu_vendor_id == CPU_VENDOR_INTEL && 566 (CPUID_TO_FAMILY(cpu_id) > 0xf || 567 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 568 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 569 int bm_sts = 1; 570 571 /* 572 * Pentium dual-core, Core 2 and beyond do not need any 573 * additional activities to enter deep C-state, i.e. C3(+). 574 */ 575 cpu_mwait_cx_no_bmarb(); 576 577 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 578 if (!bm_sts) 579 cpu_mwait_cx_no_bmsts(); 580 } 581 582 sbuf_new(&sb, cpu_mwait_cx_supported, 583 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 584 585 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 586 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 587 int sub; 588 589 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 590 591 sysctl_ctx_init(&cx->sysctl_ctx); 592 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 593 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 594 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 595 if (cx->sysctl_tree == NULL) 596 continue; 597 598 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 599 SYSCTL_ADD_INT(&cx->sysctl_ctx, 600 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 601 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 602 "sub-state count"); 603 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 604 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 605 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 606 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 607 608 for (sub = 0; sub < cx->subcnt; ++sub) 609 sbuf_printf(&sb, "C%d/%d ", i, sub); 610 } 611 sbuf_trim(&sb); 612 sbuf_finish(&sb); 613 614 /* 615 * Non-deep C-states 616 */ 617 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 618 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 619 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 620 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 621 M_DEVBUF, M_WAITOK); 622 623 hint_idx = 0; 624 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 625 int j, subcnt; 626 627 subcnt = cpu_mwait_cx_info[i].subcnt; 628 for (j = 0; j < subcnt; ++j) { 629 KASSERT(hint_idx < cpu_mwait_hints_cnt, 630 ("invalid mwait hint index %d", hint_idx)); 631 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 632 ++hint_idx; 633 } 634 } 635 KASSERT(hint_idx == cpu_mwait_hints_cnt, 636 ("mwait hint count %d != index %d", 637 cpu_mwait_hints_cnt, hint_idx)); 638 639 if (bootverbose) { 640 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 641 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 642 int hint = cpu_mwait_hints[i]; 643 644 kprintf(" C%d/%d hint 0x%04x\n", 645 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 646 hint); 647 } 648 } 649 650 /* 651 * Deep C-states 652 */ 653 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 654 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 655 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 656 M_DEVBUF, M_WAITOK); 657 658 hint_idx = 0; 659 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 660 int j, subcnt; 661 662 subcnt = cpu_mwait_cx_info[i].subcnt; 663 for (j = 0; j < subcnt; ++j) { 664 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 665 ("invalid mwait deep hint index %d", hint_idx)); 666 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 667 ++hint_idx; 668 } 669 } 670 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 671 ("mwait deep hint count %d != index %d", 672 cpu_mwait_deep_hints_cnt, hint_idx)); 673 674 if (bootverbose) { 675 kprintf("MWAIT deep hints:\n"); 676 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 677 int hint = cpu_mwait_deep_hints[i]; 678 679 kprintf(" C%d/%d hint 0x%04x\n", 680 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 681 hint); 682 } 683 } 684 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 685 686 for (i = 0; i < ncpus; ++i) { 687 char name[16]; 688 689 ksnprintf(name, sizeof(name), "idle%d", i); 690 SYSCTL_ADD_PROC(NULL, 691 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 692 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 693 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 694 } 695 } 696 697 static void 698 cpu_finish(void *dummy __unused) 699 { 700 cpu_setregs(); 701 cpu_mwait_attach(); 702 } 703 704 static void 705 pic_finish(void *dummy __unused) 706 { 707 /* Log ELCR information */ 708 elcr_dump(); 709 710 /* Log MPTABLE information */ 711 mptable_pci_int_dump(); 712 713 /* Finalize PCI */ 714 MachIntrABI.finalize(); 715 } 716 717 /* 718 * Send an interrupt to process. 719 * 720 * Stack is set up to allow sigcode stored 721 * at top to call routine, followed by kcall 722 * to sigreturn routine below. After sigreturn 723 * resets the signal mask, the stack, and the 724 * frame pointer, it returns to the user 725 * specified pc, psl. 726 */ 727 void 728 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 729 { 730 struct lwp *lp = curthread->td_lwp; 731 struct proc *p = lp->lwp_proc; 732 struct trapframe *regs; 733 struct sigacts *psp = p->p_sigacts; 734 struct sigframe sf, *sfp; 735 int oonstack; 736 char *sp; 737 738 regs = lp->lwp_md.md_regs; 739 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 740 741 /* Save user context */ 742 bzero(&sf, sizeof(struct sigframe)); 743 sf.sf_uc.uc_sigmask = *mask; 744 sf.sf_uc.uc_stack = lp->lwp_sigstk; 745 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 746 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 747 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 748 749 /* Make the size of the saved context visible to userland */ 750 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 751 752 /* Allocate and validate space for the signal handler context. */ 753 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 754 SIGISMEMBER(psp->ps_sigonstack, sig)) { 755 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 756 sizeof(struct sigframe)); 757 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 758 } else { 759 /* We take red zone into account */ 760 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 761 } 762 763 /* 764 * XXX AVX needs 64-byte alignment but sigframe has other fields and 765 * the embedded ucontext is not at the front, so aligning this won't 766 * help us. Fortunately we bcopy in/out of the sigframe, so the 767 * kernel is ok. 768 * 769 * The problem though is if userland winds up trying to use the 770 * context directly. 771 */ 772 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 773 774 /* Translate the signal is appropriate */ 775 if (p->p_sysent->sv_sigtbl) { 776 if (sig <= p->p_sysent->sv_sigsize) 777 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 778 } 779 780 /* 781 * Build the argument list for the signal handler. 782 * 783 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 784 */ 785 regs->tf_rdi = sig; /* argument 1 */ 786 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 787 788 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 789 /* 790 * Signal handler installed with SA_SIGINFO. 791 * 792 * action(signo, siginfo, ucontext) 793 */ 794 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 795 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 796 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 797 798 /* fill siginfo structure */ 799 sf.sf_si.si_signo = sig; 800 sf.sf_si.si_code = code; 801 sf.sf_si.si_addr = (void *)regs->tf_addr; 802 } else { 803 /* 804 * Old FreeBSD-style arguments. 805 * 806 * handler (signo, code, [uc], addr) 807 */ 808 regs->tf_rsi = (register_t)code; /* argument 2 */ 809 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 810 sf.sf_ahu.sf_handler = catcher; 811 } 812 813 /* 814 * If we're a vm86 process, we want to save the segment registers. 815 * We also change eflags to be our emulated eflags, not the actual 816 * eflags. 817 */ 818 #if 0 /* JG */ 819 if (regs->tf_eflags & PSL_VM) { 820 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 821 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 822 823 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 824 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 825 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 826 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 827 828 if (vm86->vm86_has_vme == 0) 829 sf.sf_uc.uc_mcontext.mc_eflags = 830 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 831 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 832 833 /* 834 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 835 * syscalls made by the signal handler. This just avoids 836 * wasting time for our lazy fixup of such faults. PSL_NT 837 * does nothing in vm86 mode, but vm86 programs can set it 838 * almost legitimately in probes for old cpu types. 839 */ 840 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 841 } 842 #endif 843 844 /* 845 * Save the FPU state and reinit the FP unit 846 */ 847 npxpush(&sf.sf_uc.uc_mcontext); 848 849 /* 850 * Copy the sigframe out to the user's stack. 851 */ 852 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 853 /* 854 * Something is wrong with the stack pointer. 855 * ...Kill the process. 856 */ 857 sigexit(lp, SIGILL); 858 } 859 860 regs->tf_rsp = (register_t)sfp; 861 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 862 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 863 864 /* 865 * x86 abi specifies that the direction flag must be cleared 866 * on function entry 867 */ 868 regs->tf_rflags &= ~(PSL_T | PSL_D); 869 870 /* 871 * 64 bit mode has a code and stack selector but 872 * no data or extra selector. %fs and %gs are not 873 * stored in-context. 874 */ 875 regs->tf_cs = _ucodesel; 876 regs->tf_ss = _udatasel; 877 clear_quickret(); 878 } 879 880 /* 881 * Sanitize the trapframe for a virtual kernel passing control to a custom 882 * VM context. Remove any items that would otherwise create a privilage 883 * issue. 884 * 885 * XXX at the moment we allow userland to set the resume flag. Is this a 886 * bad idea? 887 */ 888 int 889 cpu_sanitize_frame(struct trapframe *frame) 890 { 891 frame->tf_cs = _ucodesel; 892 frame->tf_ss = _udatasel; 893 /* XXX VM (8086) mode not supported? */ 894 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 895 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 896 897 return(0); 898 } 899 900 /* 901 * Sanitize the tls so loading the descriptor does not blow up 902 * on us. For x86_64 we don't have to do anything. 903 */ 904 int 905 cpu_sanitize_tls(struct savetls *tls) 906 { 907 return(0); 908 } 909 910 /* 911 * sigreturn(ucontext_t *sigcntxp) 912 * 913 * System call to cleanup state after a signal 914 * has been taken. Reset signal mask and 915 * stack state from context left by sendsig (above). 916 * Return to previous pc and psl as specified by 917 * context left by sendsig. Check carefully to 918 * make sure that the user has not modified the 919 * state to gain improper privileges. 920 * 921 * MPSAFE 922 */ 923 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 924 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 925 926 int 927 sys_sigreturn(struct sigreturn_args *uap) 928 { 929 struct lwp *lp = curthread->td_lwp; 930 struct trapframe *regs; 931 ucontext_t uc; 932 ucontext_t *ucp; 933 register_t rflags; 934 int cs; 935 int error; 936 937 /* 938 * We have to copy the information into kernel space so userland 939 * can't modify it while we are sniffing it. 940 */ 941 regs = lp->lwp_md.md_regs; 942 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 943 if (error) 944 return (error); 945 ucp = &uc; 946 rflags = ucp->uc_mcontext.mc_rflags; 947 948 /* VM (8086) mode not supported */ 949 rflags &= ~PSL_VM_UNSUPP; 950 951 #if 0 /* JG */ 952 if (eflags & PSL_VM) { 953 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 954 struct vm86_kernel *vm86; 955 956 /* 957 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 958 * set up the vm86 area, and we can't enter vm86 mode. 959 */ 960 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 961 return (EINVAL); 962 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 963 if (vm86->vm86_inited == 0) 964 return (EINVAL); 965 966 /* go back to user mode if both flags are set */ 967 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 968 trapsignal(lp, SIGBUS, 0); 969 970 if (vm86->vm86_has_vme) { 971 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 972 (eflags & VME_USERCHANGE) | PSL_VM; 973 } else { 974 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 975 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 976 (eflags & VM_USERCHANGE) | PSL_VM; 977 } 978 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 979 tf->tf_eflags = eflags; 980 tf->tf_vm86_ds = tf->tf_ds; 981 tf->tf_vm86_es = tf->tf_es; 982 tf->tf_vm86_fs = tf->tf_fs; 983 tf->tf_vm86_gs = tf->tf_gs; 984 tf->tf_ds = _udatasel; 985 tf->tf_es = _udatasel; 986 tf->tf_fs = _udatasel; 987 tf->tf_gs = _udatasel; 988 } else 989 #endif 990 { 991 /* 992 * Don't allow users to change privileged or reserved flags. 993 */ 994 /* 995 * XXX do allow users to change the privileged flag PSL_RF. 996 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 997 * should sometimes set it there too. tf_eflags is kept in 998 * the signal context during signal handling and there is no 999 * other place to remember it, so the PSL_RF bit may be 1000 * corrupted by the signal handler without us knowing. 1001 * Corruption of the PSL_RF bit at worst causes one more or 1002 * one less debugger trap, so allowing it is fairly harmless. 1003 */ 1004 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 1005 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 1006 return(EINVAL); 1007 } 1008 1009 /* 1010 * Don't allow users to load a valid privileged %cs. Let the 1011 * hardware check for invalid selectors, excess privilege in 1012 * other selectors, invalid %eip's and invalid %esp's. 1013 */ 1014 cs = ucp->uc_mcontext.mc_cs; 1015 if (!CS_SECURE(cs)) { 1016 kprintf("sigreturn: cs = 0x%x\n", cs); 1017 trapsignal(lp, SIGBUS, T_PROTFLT); 1018 return(EINVAL); 1019 } 1020 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1021 } 1022 1023 /* 1024 * Restore the FPU state from the frame 1025 */ 1026 crit_enter(); 1027 npxpop(&ucp->uc_mcontext); 1028 1029 if (ucp->uc_mcontext.mc_onstack & 1) 1030 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1031 else 1032 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1033 1034 lp->lwp_sigmask = ucp->uc_sigmask; 1035 SIG_CANTMASK(lp->lwp_sigmask); 1036 clear_quickret(); 1037 crit_exit(); 1038 return(EJUSTRETURN); 1039 } 1040 1041 /* 1042 * Machine dependent boot() routine 1043 * 1044 * I haven't seen anything to put here yet 1045 * Possibly some stuff might be grafted back here from boot() 1046 */ 1047 void 1048 cpu_boot(int howto) 1049 { 1050 } 1051 1052 /* 1053 * Shutdown the CPU as much as possible 1054 */ 1055 void 1056 cpu_halt(void) 1057 { 1058 for (;;) 1059 __asm__ __volatile("hlt"); 1060 } 1061 1062 /* 1063 * cpu_idle() represents the idle LWKT. You cannot return from this function 1064 * (unless you want to blow things up!). Instead we look for runnable threads 1065 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1066 * 1067 * The main loop is entered with a critical section held, we must release 1068 * the critical section before doing anything else. lwkt_switch() will 1069 * check for pending interrupts due to entering and exiting its own 1070 * critical section. 1071 * 1072 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1073 * However, there are cases where the idlethread will be entered with 1074 * the possibility that no IPI will occur and in such cases 1075 * lwkt_switch() sets TDF_IDLE_NOHLT. 1076 * 1077 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1078 * must occur before it starts using ACPI halt. 1079 * 1080 * NOTE: Value overridden in hammer_time(). 1081 */ 1082 static int cpu_idle_hlt = 2; 1083 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1084 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1085 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1086 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1087 1088 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1089 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1090 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1091 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1092 1093 static void 1094 cpu_idle_default_hook(void) 1095 { 1096 /* 1097 * We must guarentee that hlt is exactly the instruction 1098 * following the sti. 1099 */ 1100 __asm __volatile("sti; hlt"); 1101 } 1102 1103 /* Other subsystems (e.g., ACPI) can hook this later. */ 1104 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1105 1106 static __inline int 1107 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1108 { 1109 int hint, cx_idx; 1110 u_int idx; 1111 1112 hint = stat->hint; 1113 if (hint >= 0) 1114 goto done; 1115 1116 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1117 cpu_mwait_repeat_shift; 1118 if (idx >= cpu_mwait_c1_hints_cnt) { 1119 /* Step up faster, once we walked through all C1 states */ 1120 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1121 } 1122 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1123 if (idx >= cpu_mwait_deep_hints_cnt) 1124 idx = cpu_mwait_deep_hints_cnt - 1; 1125 hint = cpu_mwait_deep_hints[idx]; 1126 } else { 1127 if (idx >= cpu_mwait_hints_cnt) 1128 idx = cpu_mwait_hints_cnt - 1; 1129 hint = cpu_mwait_hints[idx]; 1130 } 1131 done: 1132 cx_idx = MWAIT_EAX_TO_CX(hint); 1133 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1134 stat->mwait_cx[cx_idx]++; 1135 return hint; 1136 } 1137 1138 void 1139 cpu_idle(void) 1140 { 1141 globaldata_t gd = mycpu; 1142 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1143 struct thread *td __debugvar = gd->gd_curthread; 1144 int reqflags; 1145 1146 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1147 1148 crit_exit(); 1149 KKASSERT(td->td_critcount == 0); 1150 1151 for (;;) { 1152 /* 1153 * See if there are any LWKTs ready to go. 1154 */ 1155 lwkt_switch(); 1156 1157 /* 1158 * When halting inside a cli we must check for reqflags 1159 * races, particularly [re]schedule requests. Running 1160 * splz() does the job. 1161 * 1162 * cpu_idle_hlt: 1163 * 0 Never halt, just spin 1164 * 1165 * 1 Always use MONITOR/MWAIT if avail, HLT 1166 * otherwise. 1167 * 1168 * Better default for modern (Haswell+) Intel 1169 * cpus. 1170 * 1171 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1172 * use the ACPI halt (default). This is a hybrid 1173 * approach. See machdep.cpu_idle_repeat. 1174 * 1175 * Better default for modern AMD cpus and older 1176 * Intel cpus. 1177 * 1178 * 3 Always use the ACPI halt. This typically 1179 * eats the least amount of power but the cpu 1180 * will be slow waking up. Slows down e.g. 1181 * compiles and other pipe/event oriented stuff. 1182 * 1183 * Usually the best default for AMD cpus. 1184 * 1185 * 4 Always use HLT. 1186 * 1187 * 5 Always spin. 1188 * 1189 * NOTE: Interrupts are enabled and we are not in a critical 1190 * section. 1191 * 1192 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1193 * don't bother capping gd_idle_repeat, it is ok if 1194 * it overflows (we do make it unsigned, however). 1195 * 1196 * Implement optimized invltlb operations when halted 1197 * in idle. By setting the bit in smp_idleinvl_mask 1198 * we inform other cpus that they can set _reqs to 1199 * request an invltlb. Current the code to do that 1200 * sets the bits in _reqs anyway, but then check _mask 1201 * to determine if they can assume the invltlb will execute. 1202 * 1203 * A critical section is required to ensure that interrupts 1204 * do not fully run until after we've had a chance to execute 1205 * the request. 1206 */ 1207 if (gd->gd_idle_repeat == 0) { 1208 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1209 if (stat->repeat > cpu_idle_repeat_max) 1210 stat->repeat = cpu_idle_repeat_max; 1211 stat->repeat_last = 0; 1212 stat->repeat_delta = 0; 1213 } 1214 ++stat->repeat_last; 1215 1216 /* 1217 * General idle thread halt code 1218 * 1219 * IBRS NOTES - IBRS is a SPECTRE mitigation. When going 1220 * idle, disable IBRS to reduce hyperthread 1221 * overhead. 1222 */ 1223 ++gd->gd_idle_repeat; 1224 1225 switch(cpu_idle_hlt) { 1226 default: 1227 case 0: 1228 /* 1229 * Always spin 1230 */ 1231 ; 1232 do_spin: 1233 splz(); 1234 __asm __volatile("sti"); 1235 stat->spin++; 1236 crit_enter_gd(gd); 1237 crit_exit_gd(gd); 1238 break; 1239 case 2: 1240 /* 1241 * Use MONITOR/MWAIT (or HLT) for a few cycles, 1242 * then start using the ACPI halt code if we 1243 * continue to be idle. 1244 */ 1245 if (gd->gd_idle_repeat >= cpu_idle_repeat) 1246 goto do_acpi; 1247 /* FALL THROUGH */ 1248 case 1: 1249 /* 1250 * Always use MONITOR/MWAIT (will use HLT if 1251 * MONITOR/MWAIT not available). 1252 */ 1253 if (cpu_mi_feature & CPU_MI_MONITOR) { 1254 splz(); /* XXX */ 1255 reqflags = gd->gd_reqflags; 1256 if (reqflags & RQF_IDLECHECK_WK_MASK) 1257 goto do_spin; 1258 crit_enter_gd(gd); 1259 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1260 /* 1261 * IBRS/STIBP 1262 */ 1263 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1264 SPEC_CTRL_DUMMY_ENABLE) { 1265 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1266 } 1267 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1268 cpu_mwait_cx_hint(stat), 0); 1269 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1270 SPEC_CTRL_DUMMY_ENABLE) { 1271 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1272 } 1273 stat->halt++; 1274 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1275 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1276 gd->gd_cpuid)) { 1277 cpu_invltlb(); 1278 cpu_mfence(); 1279 } 1280 crit_exit_gd(gd); 1281 break; 1282 } 1283 /* FALLTHROUGH */ 1284 case 4: 1285 /* 1286 * Use HLT 1287 */ 1288 __asm __volatile("cli"); 1289 splz(); 1290 crit_enter_gd(gd); 1291 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1292 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1293 gd->gd_cpuid); 1294 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1295 SPEC_CTRL_DUMMY_ENABLE) { 1296 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1297 } 1298 cpu_idle_default_hook(); 1299 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1300 SPEC_CTRL_DUMMY_ENABLE) { 1301 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1302 } 1303 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1304 gd->gd_cpuid); 1305 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1306 gd->gd_cpuid)) { 1307 cpu_invltlb(); 1308 cpu_mfence(); 1309 } 1310 } 1311 __asm __volatile("sti"); 1312 stat->halt++; 1313 crit_exit_gd(gd); 1314 break; 1315 case 3: 1316 /* 1317 * Use ACPI halt 1318 */ 1319 ; 1320 do_acpi: 1321 __asm __volatile("cli"); 1322 splz(); 1323 crit_enter_gd(gd); 1324 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1325 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1326 gd->gd_cpuid); 1327 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1328 SPEC_CTRL_DUMMY_ENABLE) { 1329 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1330 } 1331 cpu_idle_hook(); 1332 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1333 SPEC_CTRL_DUMMY_ENABLE) { 1334 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1335 } 1336 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1337 gd->gd_cpuid); 1338 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1339 gd->gd_cpuid)) { 1340 cpu_invltlb(); 1341 cpu_mfence(); 1342 } 1343 } 1344 __asm __volatile("sti"); 1345 stat->halt++; 1346 crit_exit_gd(gd); 1347 break; 1348 } 1349 } 1350 } 1351 1352 /* 1353 * Called from deep ACPI via cpu_idle_hook() (see above) to actually halt 1354 * the cpu in C1. ACPI might use other halt methods for deeper states 1355 * and not reach here. 1356 * 1357 * For now we always use HLT as we are not sure what ACPI may have actually 1358 * done. MONITOR/MWAIT might not be appropriate. 1359 * 1360 * NOTE: MONITOR/MWAIT does not appear to throttle AMD cpus, while HLT 1361 * does. On Intel, MONITOR/MWAIT does appear to throttle the cpu. 1362 */ 1363 void 1364 cpu_idle_halt(void) 1365 { 1366 globaldata_t gd; 1367 1368 gd = mycpu; 1369 #if 0 1370 /* DISABLED FOR NOW */ 1371 struct cpu_idle_stat *stat; 1372 int reqflags; 1373 1374 1375 if ((cpu_idle_hlt == 1 || cpu_idle_hlt == 2) && 1376 (cpu_mi_feature & CPU_MI_MONITOR) && 1377 cpu_vendor_id != CPU_VENDOR_AMD) { 1378 /* 1379 * Use MONITOR/MWAIT 1380 * 1381 * (NOTE: On ryzen, MWAIT does not throttle clocks, so we 1382 * have to use HLT) 1383 */ 1384 stat = &cpu_idle_stats[gd->gd_cpuid]; 1385 reqflags = gd->gd_reqflags; 1386 if ((reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1387 __asm __volatile("sti"); 1388 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1389 cpu_mwait_cx_hint(stat), 0); 1390 } else { 1391 __asm __volatile("sti; pause"); 1392 } 1393 } else 1394 #endif 1395 { 1396 /* 1397 * Use HLT 1398 */ 1399 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1400 __asm __volatile("sti; hlt"); 1401 else 1402 __asm __volatile("sti; pause"); 1403 } 1404 } 1405 1406 1407 /* 1408 * Called in a loop indirectly via Xcpustop 1409 */ 1410 void 1411 cpu_smp_stopped(void) 1412 { 1413 globaldata_t gd = mycpu; 1414 volatile __uint64_t *ptr; 1415 __uint64_t ovalue; 1416 1417 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1418 ovalue = *ptr; 1419 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1420 if (cpu_mi_feature & CPU_MI_MONITOR) { 1421 if (cpu_mwait_hints) { 1422 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1423 ovalue, 1424 cpu_mwait_hints[ 1425 cpu_mwait_hints_cnt - 1], 0); 1426 } else { 1427 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1428 ovalue, 0, 0); 1429 } 1430 } else { 1431 cpu_halt(); /* depend on lapic timer */ 1432 } 1433 } 1434 } 1435 1436 /* 1437 * This routine is called if a spinlock has been held through the 1438 * exponential backoff period and is seriously contested. On a real cpu 1439 * we let it spin. 1440 */ 1441 void 1442 cpu_spinlock_contested(void) 1443 { 1444 cpu_pause(); 1445 } 1446 1447 /* 1448 * Clear registers on exec 1449 */ 1450 void 1451 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1452 { 1453 struct thread *td = curthread; 1454 struct lwp *lp = td->td_lwp; 1455 struct pcb *pcb = td->td_pcb; 1456 struct trapframe *regs = lp->lwp_md.md_regs; 1457 1458 user_ldt_free(pcb); 1459 1460 clear_quickret(); 1461 bzero((char *)regs, sizeof(struct trapframe)); 1462 regs->tf_rip = entry; 1463 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1464 regs->tf_rdi = stack; /* argv */ 1465 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1466 regs->tf_ss = _udatasel; 1467 regs->tf_cs = _ucodesel; 1468 regs->tf_rbx = ps_strings; 1469 1470 /* 1471 * Reset the hardware debug registers if they were in use. 1472 * They won't have any meaning for the newly exec'd process. 1473 */ 1474 if (pcb->pcb_flags & PCB_DBREGS) { 1475 pcb->pcb_dr0 = 0; 1476 pcb->pcb_dr1 = 0; 1477 pcb->pcb_dr2 = 0; 1478 pcb->pcb_dr3 = 0; 1479 pcb->pcb_dr6 = 0; 1480 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1481 if (pcb == td->td_pcb) { 1482 /* 1483 * Clear the debug registers on the running 1484 * CPU, otherwise they will end up affecting 1485 * the next process we switch to. 1486 */ 1487 reset_dbregs(); 1488 } 1489 pcb->pcb_flags &= ~PCB_DBREGS; 1490 } 1491 1492 /* 1493 * Initialize the math emulator (if any) for the current process. 1494 * Actually, just clear the bit that says that the emulator has 1495 * been initialized. Initialization is delayed until the process 1496 * traps to the emulator (if it is done at all) mainly because 1497 * emulators don't provide an entry point for initialization. 1498 */ 1499 pcb->pcb_flags &= ~FP_SOFTFP; 1500 1501 /* 1502 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1503 * gd_npxthread. Otherwise a preemptive interrupt thread 1504 * may panic in npxdna(). 1505 */ 1506 crit_enter(); 1507 load_cr0(rcr0() | CR0_MP); 1508 1509 /* 1510 * NOTE: The MSR values must be correct so we can return to 1511 * userland. gd_user_fs/gs must be correct so the switch 1512 * code knows what the current MSR values are. 1513 */ 1514 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1515 pcb->pcb_gsbase = 0; 1516 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1517 mdcpu->gd_user_gs = 0; 1518 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1519 wrmsr(MSR_KGSBASE, 0); 1520 1521 /* Initialize the npx (if any) for the current process. */ 1522 npxinit(); 1523 crit_exit(); 1524 1525 pcb->pcb_ds = _udatasel; 1526 pcb->pcb_es = _udatasel; 1527 pcb->pcb_fs = _udatasel; 1528 pcb->pcb_gs = _udatasel; 1529 } 1530 1531 void 1532 cpu_setregs(void) 1533 { 1534 register_t cr0; 1535 1536 cr0 = rcr0(); 1537 cr0 |= CR0_NE; /* Done by npxinit() */ 1538 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1539 cr0 |= CR0_WP | CR0_AM; 1540 load_cr0(cr0); 1541 load_gs(_udatasel); 1542 } 1543 1544 static int 1545 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1546 { 1547 int error; 1548 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1549 req); 1550 if (!error && req->newptr) 1551 resettodr(); 1552 return (error); 1553 } 1554 1555 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1556 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1557 1558 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1559 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1560 1561 #if 0 /* JG */ 1562 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1563 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1564 #endif 1565 1566 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1567 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1568 1569 static int 1570 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1571 { 1572 struct efi_map_header *efihdr; 1573 caddr_t kmdp; 1574 uint32_t efisize; 1575 1576 kmdp = preload_search_by_type("elf kernel"); 1577 if (kmdp == NULL) 1578 kmdp = preload_search_by_type("elf64 kernel"); 1579 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1580 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1581 if (efihdr == NULL) 1582 return (0); 1583 efisize = *((uint32_t *)efihdr - 1); 1584 return (SYSCTL_OUT(req, efihdr, efisize)); 1585 } 1586 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1587 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1588 1589 /* 1590 * Initialize x86 and configure to run kernel 1591 */ 1592 1593 /* 1594 * Initialize segments & interrupt table 1595 */ 1596 1597 int _default_ldt; 1598 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1599 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1600 #if 0 /* JG */ 1601 union descriptor ldt[NLDT]; /* local descriptor table */ 1602 #endif 1603 1604 /* table descriptors - used to load tables by cpu */ 1605 struct region_descriptor r_gdt; 1606 struct region_descriptor r_idt_arr[MAXCPU]; 1607 1608 /* JG proc0paddr is a virtual address */ 1609 void *proc0paddr; 1610 /* JG alignment? */ 1611 char proc0paddr_buff[LWKT_THREAD_STACK]; 1612 1613 1614 /* software prototypes -- in more palatable form */ 1615 struct soft_segment_descriptor gdt_segs[] = { 1616 /* GNULL_SEL 0 Null Descriptor */ 1617 { 0x0, /* segment base address */ 1618 0x0, /* length */ 1619 0, /* segment type */ 1620 0, /* segment descriptor priority level */ 1621 0, /* segment descriptor present */ 1622 0, /* long */ 1623 0, /* default 32 vs 16 bit size */ 1624 0 /* limit granularity (byte/page units)*/ }, 1625 /* GCODE_SEL 1 Code Descriptor for kernel */ 1626 { 0x0, /* segment base address */ 1627 0xfffff, /* length - all address space */ 1628 SDT_MEMERA, /* segment type */ 1629 SEL_KPL, /* segment descriptor priority level */ 1630 1, /* segment descriptor present */ 1631 1, /* long */ 1632 0, /* default 32 vs 16 bit size */ 1633 1 /* limit granularity (byte/page units)*/ }, 1634 /* GDATA_SEL 2 Data Descriptor for kernel */ 1635 { 0x0, /* segment base address */ 1636 0xfffff, /* length - all address space */ 1637 SDT_MEMRWA, /* segment type */ 1638 SEL_KPL, /* segment descriptor priority level */ 1639 1, /* segment descriptor present */ 1640 1, /* long */ 1641 0, /* default 32 vs 16 bit size */ 1642 1 /* limit granularity (byte/page units)*/ }, 1643 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1644 { 0x0, /* segment base address */ 1645 0xfffff, /* length - all address space */ 1646 SDT_MEMERA, /* segment type */ 1647 SEL_UPL, /* segment descriptor priority level */ 1648 1, /* segment descriptor present */ 1649 0, /* long */ 1650 1, /* default 32 vs 16 bit size */ 1651 1 /* limit granularity (byte/page units)*/ }, 1652 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1653 { 0x0, /* segment base address */ 1654 0xfffff, /* length - all address space */ 1655 SDT_MEMRWA, /* segment type */ 1656 SEL_UPL, /* segment descriptor priority level */ 1657 1, /* segment descriptor present */ 1658 0, /* long */ 1659 1, /* default 32 vs 16 bit size */ 1660 1 /* limit granularity (byte/page units)*/ }, 1661 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1662 { 0x0, /* segment base address */ 1663 0xfffff, /* length - all address space */ 1664 SDT_MEMERA, /* segment type */ 1665 SEL_UPL, /* segment descriptor priority level */ 1666 1, /* segment descriptor present */ 1667 1, /* long */ 1668 0, /* default 32 vs 16 bit size */ 1669 1 /* limit granularity (byte/page units)*/ }, 1670 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1671 { 1672 0x0, /* segment base address */ 1673 sizeof(struct x86_64tss)-1,/* length - all address space */ 1674 SDT_SYSTSS, /* segment type */ 1675 SEL_KPL, /* segment descriptor priority level */ 1676 1, /* segment descriptor present */ 1677 0, /* long */ 1678 0, /* unused - default 32 vs 16 bit size */ 1679 0 /* limit granularity (byte/page units)*/ }, 1680 /* Actually, the TSS is a system descriptor which is double size */ 1681 { 0x0, /* segment base address */ 1682 0x0, /* length */ 1683 0, /* segment type */ 1684 0, /* segment descriptor priority level */ 1685 0, /* segment descriptor present */ 1686 0, /* long */ 1687 0, /* default 32 vs 16 bit size */ 1688 0 /* limit granularity (byte/page units)*/ }, 1689 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1690 { 0x0, /* segment base address */ 1691 0xfffff, /* length - all address space */ 1692 SDT_MEMRWA, /* segment type */ 1693 SEL_UPL, /* segment descriptor priority level */ 1694 1, /* segment descriptor present */ 1695 0, /* long */ 1696 1, /* default 32 vs 16 bit size */ 1697 1 /* limit granularity (byte/page units)*/ }, 1698 }; 1699 1700 void 1701 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1702 { 1703 int cpu; 1704 1705 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1706 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1707 1708 ip->gd_looffset = (uintptr_t)func; 1709 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1710 ip->gd_ist = ist; 1711 ip->gd_xx = 0; 1712 ip->gd_type = typ; 1713 ip->gd_dpl = dpl; 1714 ip->gd_p = 1; 1715 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1716 } 1717 } 1718 1719 void 1720 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1721 { 1722 struct gate_descriptor *ip; 1723 1724 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1725 1726 ip = &idt_arr[cpu][idx]; 1727 ip->gd_looffset = (uintptr_t)func; 1728 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1729 ip->gd_ist = ist; 1730 ip->gd_xx = 0; 1731 ip->gd_type = typ; 1732 ip->gd_dpl = dpl; 1733 ip->gd_p = 1; 1734 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1735 } 1736 1737 #define IDTVEC(name) __CONCAT(X,name) 1738 1739 extern inthand_t 1740 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1741 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1742 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1743 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1744 IDTVEC(xmm), IDTVEC(dblfault), 1745 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1746 1747 void 1748 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1749 { 1750 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1751 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1752 ssd->ssd_type = sd->sd_type; 1753 ssd->ssd_dpl = sd->sd_dpl; 1754 ssd->ssd_p = sd->sd_p; 1755 ssd->ssd_def32 = sd->sd_def32; 1756 ssd->ssd_gran = sd->sd_gran; 1757 } 1758 1759 void 1760 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1761 { 1762 1763 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1764 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1765 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1766 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1767 sd->sd_type = ssd->ssd_type; 1768 sd->sd_dpl = ssd->ssd_dpl; 1769 sd->sd_p = ssd->ssd_p; 1770 sd->sd_long = ssd->ssd_long; 1771 sd->sd_def32 = ssd->ssd_def32; 1772 sd->sd_gran = ssd->ssd_gran; 1773 } 1774 1775 void 1776 ssdtosyssd(struct soft_segment_descriptor *ssd, 1777 struct system_segment_descriptor *sd) 1778 { 1779 1780 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1781 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1782 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1783 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1784 sd->sd_type = ssd->ssd_type; 1785 sd->sd_dpl = ssd->ssd_dpl; 1786 sd->sd_p = ssd->ssd_p; 1787 sd->sd_gran = ssd->ssd_gran; 1788 } 1789 1790 /* 1791 * Populate the (physmap) array with base/bound pairs describing the 1792 * available physical memory in the system, then test this memory and 1793 * build the phys_avail array describing the actually-available memory. 1794 * 1795 * If we cannot accurately determine the physical memory map, then use 1796 * value from the 0xE801 call, and failing that, the RTC. 1797 * 1798 * Total memory size may be set by the kernel environment variable 1799 * hw.physmem or the compile-time define MAXMEM. 1800 * 1801 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1802 * of PAGE_SIZE. This also greatly reduces the memory test time 1803 * which would otherwise be excessive on machines with > 8G of ram. 1804 * 1805 * XXX first should be vm_paddr_t. 1806 */ 1807 1808 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1809 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1810 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1811 1812 vm_paddr_t physmap[PHYSMAP_SIZE]; 1813 struct bios_smap *smapbase, *smap, *smapend; 1814 struct efi_map_header *efihdrbase; 1815 u_int32_t smapsize; 1816 1817 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1818 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1819 1820 static void 1821 add_smap_entries(int *physmap_idx) 1822 { 1823 int i; 1824 1825 smapsize = *((u_int32_t *)smapbase - 1); 1826 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1827 1828 for (smap = smapbase; smap < smapend; smap++) { 1829 if (boothowto & RB_VERBOSE) 1830 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1831 smap->type, smap->base, smap->length); 1832 1833 if (smap->type != SMAP_TYPE_MEMORY) 1834 continue; 1835 1836 if (smap->length == 0) 1837 continue; 1838 1839 for (i = 0; i <= *physmap_idx; i += 2) { 1840 if (smap->base < physmap[i + 1]) { 1841 if (boothowto & RB_VERBOSE) { 1842 kprintf("Overlapping or non-monotonic " 1843 "memory region, ignoring " 1844 "second region\n"); 1845 } 1846 break; 1847 } 1848 } 1849 if (i <= *physmap_idx) 1850 continue; 1851 1852 Realmem += smap->length; 1853 1854 if (smap->base == physmap[*physmap_idx + 1]) { 1855 physmap[*physmap_idx + 1] += smap->length; 1856 continue; 1857 } 1858 1859 *physmap_idx += 2; 1860 if (*physmap_idx == PHYSMAP_SIZE) { 1861 kprintf("Too many segments in the physical " 1862 "address map, giving up\n"); 1863 break; 1864 } 1865 physmap[*physmap_idx] = smap->base; 1866 physmap[*physmap_idx + 1] = smap->base + smap->length; 1867 } 1868 } 1869 1870 static void 1871 add_efi_map_entries(int *physmap_idx) 1872 { 1873 struct efi_md *map, *p; 1874 const char *type; 1875 size_t efisz; 1876 int i, ndesc; 1877 1878 static const char *types[] = { 1879 "Reserved", 1880 "LoaderCode", 1881 "LoaderData", 1882 "BootServicesCode", 1883 "BootServicesData", 1884 "RuntimeServicesCode", 1885 "RuntimeServicesData", 1886 "ConventionalMemory", 1887 "UnusableMemory", 1888 "ACPIReclaimMemory", 1889 "ACPIMemoryNVS", 1890 "MemoryMappedIO", 1891 "MemoryMappedIOPortSpace", 1892 "PalCode" 1893 }; 1894 1895 /* 1896 * Memory map data provided by UEFI via the GetMemoryMap 1897 * Boot Services API. 1898 */ 1899 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1900 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1901 1902 if (efihdrbase->descriptor_size == 0) 1903 return; 1904 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1905 1906 if (boothowto & RB_VERBOSE) 1907 kprintf("%23s %12s %12s %8s %4s\n", 1908 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1909 1910 for (i = 0, p = map; i < ndesc; i++, 1911 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1912 if (boothowto & RB_VERBOSE) { 1913 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1914 type = types[p->md_type]; 1915 else 1916 type = "<INVALID>"; 1917 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1918 p->md_virt, p->md_pages); 1919 if (p->md_attr & EFI_MD_ATTR_UC) 1920 kprintf("UC "); 1921 if (p->md_attr & EFI_MD_ATTR_WC) 1922 kprintf("WC "); 1923 if (p->md_attr & EFI_MD_ATTR_WT) 1924 kprintf("WT "); 1925 if (p->md_attr & EFI_MD_ATTR_WB) 1926 kprintf("WB "); 1927 if (p->md_attr & EFI_MD_ATTR_UCE) 1928 kprintf("UCE "); 1929 if (p->md_attr & EFI_MD_ATTR_WP) 1930 kprintf("WP "); 1931 if (p->md_attr & EFI_MD_ATTR_RP) 1932 kprintf("RP "); 1933 if (p->md_attr & EFI_MD_ATTR_XP) 1934 kprintf("XP "); 1935 if (p->md_attr & EFI_MD_ATTR_RT) 1936 kprintf("RUNTIME"); 1937 kprintf("\n"); 1938 } 1939 1940 switch (p->md_type) { 1941 case EFI_MD_TYPE_CODE: 1942 case EFI_MD_TYPE_DATA: 1943 case EFI_MD_TYPE_BS_CODE: 1944 case EFI_MD_TYPE_BS_DATA: 1945 case EFI_MD_TYPE_FREE: 1946 /* 1947 * We're allowed to use any entry with these types. 1948 */ 1949 break; 1950 default: 1951 continue; 1952 } 1953 1954 Realmem += p->md_pages * PAGE_SIZE; 1955 1956 if (p->md_phys == physmap[*physmap_idx + 1]) { 1957 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1958 continue; 1959 } 1960 1961 *physmap_idx += 2; 1962 if (*physmap_idx == PHYSMAP_SIZE) { 1963 kprintf("Too many segments in the physical " 1964 "address map, giving up\n"); 1965 break; 1966 } 1967 physmap[*physmap_idx] = p->md_phys; 1968 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1969 } 1970 } 1971 1972 struct fb_info efi_fb_info; 1973 static int have_efi_framebuffer = 0; 1974 1975 static void 1976 efi_fb_init_vaddr(int direct_map) 1977 { 1978 uint64_t sz; 1979 vm_offset_t addr, v; 1980 1981 v = efi_fb_info.vaddr; 1982 sz = efi_fb_info.stride * efi_fb_info.height; 1983 1984 if (direct_map) { 1985 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1986 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1987 efi_fb_info.vaddr = addr; 1988 } else { 1989 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1990 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1991 } 1992 } 1993 1994 static u_int 1995 efifb_color_depth(struct efi_fb *efifb) 1996 { 1997 uint32_t mask; 1998 u_int depth; 1999 2000 mask = efifb->fb_mask_red | efifb->fb_mask_green | 2001 efifb->fb_mask_blue | efifb->fb_mask_reserved; 2002 if (mask == 0) 2003 return (0); 2004 for (depth = 1; mask != 1; depth++) 2005 mask >>= 1; 2006 return (depth); 2007 } 2008 2009 int 2010 probe_efi_fb(int early) 2011 { 2012 struct efi_fb *efifb; 2013 caddr_t kmdp; 2014 u_int depth; 2015 2016 if (have_efi_framebuffer) { 2017 if (!early && 2018 (efi_fb_info.vaddr == 0 || 2019 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 2020 efi_fb_init_vaddr(0); 2021 return 0; 2022 } 2023 2024 kmdp = preload_search_by_type("elf kernel"); 2025 if (kmdp == NULL) 2026 kmdp = preload_search_by_type("elf64 kernel"); 2027 efifb = (struct efi_fb *)preload_search_info(kmdp, 2028 MODINFO_METADATA | MODINFOMD_EFI_FB); 2029 if (efifb == NULL) 2030 return 1; 2031 2032 depth = efifb_color_depth(efifb); 2033 /* 2034 * Our bootloader should already notice, when we won't be able to 2035 * use the UEFI framebuffer. 2036 */ 2037 if (depth != 24 && depth != 32) 2038 return 1; 2039 2040 have_efi_framebuffer = 1; 2041 2042 efi_fb_info.is_vga_boot_display = 1; 2043 efi_fb_info.width = efifb->fb_width; 2044 efi_fb_info.height = efifb->fb_height; 2045 efi_fb_info.depth = depth; 2046 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 2047 efi_fb_info.paddr = efifb->fb_addr; 2048 if (early) { 2049 efi_fb_info.vaddr = 0; 2050 } else { 2051 efi_fb_init_vaddr(0); 2052 } 2053 efi_fb_info.fbops.fb_set_par = NULL; 2054 efi_fb_info.fbops.fb_blank = NULL; 2055 efi_fb_info.fbops.fb_debug_enter = NULL; 2056 efi_fb_info.device = NULL; 2057 2058 return 0; 2059 } 2060 2061 static void 2062 efifb_startup(void *arg) 2063 { 2064 probe_efi_fb(0); 2065 } 2066 2067 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 2068 2069 static void 2070 getmemsize(caddr_t kmdp, u_int64_t first) 2071 { 2072 int off, physmap_idx, pa_indx, da_indx; 2073 int i, j; 2074 vm_paddr_t pa; 2075 vm_paddr_t msgbuf_size; 2076 u_long physmem_tunable; 2077 pt_entry_t *pte; 2078 quad_t dcons_addr, dcons_size; 2079 2080 bzero(physmap, sizeof(physmap)); 2081 physmap_idx = 0; 2082 2083 /* 2084 * get memory map from INT 15:E820, kindly supplied by the loader. 2085 * 2086 * subr_module.c says: 2087 * "Consumer may safely assume that size value precedes data." 2088 * ie: an int32_t immediately precedes smap. 2089 */ 2090 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 2091 MODINFO_METADATA | MODINFOMD_EFI_MAP); 2092 smapbase = (struct bios_smap *)preload_search_info(kmdp, 2093 MODINFO_METADATA | MODINFOMD_SMAP); 2094 if (smapbase == NULL && efihdrbase == NULL) 2095 panic("No BIOS smap or EFI map info from loader!"); 2096 2097 if (efihdrbase == NULL) 2098 add_smap_entries(&physmap_idx); 2099 else 2100 add_efi_map_entries(&physmap_idx); 2101 2102 base_memory = physmap[1] / 1024; 2103 /* make hole for AP bootstrap code */ 2104 physmap[1] = mp_bootaddress(base_memory); 2105 2106 /* Save EBDA address, if any */ 2107 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 2108 ebda_addr <<= 4; 2109 2110 /* 2111 * Maxmem isn't the "maximum memory", it's one larger than the 2112 * highest page of the physical address space. It should be 2113 * called something like "Maxphyspage". We may adjust this 2114 * based on ``hw.physmem'' and the results of the memory test. 2115 */ 2116 Maxmem = atop(physmap[physmap_idx + 1]); 2117 2118 #ifdef MAXMEM 2119 Maxmem = MAXMEM / 4; 2120 #endif 2121 2122 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 2123 Maxmem = atop(physmem_tunable); 2124 2125 /* 2126 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 2127 * in the system. 2128 */ 2129 if (Maxmem > atop(physmap[physmap_idx + 1])) 2130 Maxmem = atop(physmap[physmap_idx + 1]); 2131 2132 /* 2133 * Blowing out the DMAP will blow up the system. 2134 */ 2135 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 2136 kprintf("Limiting Maxmem due to DMAP size\n"); 2137 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 2138 } 2139 2140 if (atop(physmap[physmap_idx + 1]) != Maxmem && 2141 (boothowto & RB_VERBOSE)) { 2142 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 2143 } 2144 2145 /* 2146 * Call pmap initialization to make new kernel address space 2147 * 2148 * Mask off page 0. 2149 */ 2150 pmap_bootstrap(&first); 2151 physmap[0] = PAGE_SIZE; 2152 2153 /* 2154 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2155 * exceeding Maxmem. 2156 */ 2157 for (i = j = 0; i <= physmap_idx; i += 2) { 2158 if (physmap[i+1] > ptoa(Maxmem)) 2159 physmap[i+1] = ptoa(Maxmem); 2160 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2161 ~PHYSMAP_ALIGN_MASK; 2162 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2163 2164 physmap[j] = physmap[i]; 2165 physmap[j+1] = physmap[i+1]; 2166 2167 if (physmap[i] < physmap[i+1]) 2168 j += 2; 2169 } 2170 physmap_idx = j - 2; 2171 2172 /* 2173 * Align anything else used in the validation loop. 2174 * 2175 * Also make sure that our 2MB kernel text+data+bss mappings 2176 * do not overlap potentially allocatable space. 2177 */ 2178 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2179 2180 /* 2181 * Size up each available chunk of physical memory. 2182 */ 2183 pa_indx = 0; 2184 da_indx = 0; 2185 phys_avail[pa_indx].phys_beg = physmap[0]; 2186 phys_avail[pa_indx].phys_end = physmap[0]; 2187 dump_avail[da_indx].phys_beg = 0; 2188 dump_avail[da_indx].phys_end = physmap[0]; 2189 pte = CMAP1; 2190 2191 /* 2192 * Get dcons buffer address 2193 */ 2194 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2195 kgetenv_quad("dcons.size", &dcons_size) == 0) 2196 dcons_addr = 0; 2197 2198 /* 2199 * Validate the physical memory. The physical memory segments 2200 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2201 * of PAGE_SIZE. 2202 * 2203 * We no longer perform an exhaustive memory test. Instead we 2204 * simply test the first and last word in each physmap[] 2205 * segment. 2206 */ 2207 for (i = 0; i <= physmap_idx; i += 2) { 2208 vm_paddr_t end; 2209 vm_paddr_t incr; 2210 2211 end = physmap[i + 1]; 2212 2213 for (pa = physmap[i]; pa < end; pa += incr) { 2214 int page_bad, full; 2215 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2216 uint64_t tmp; 2217 2218 full = FALSE; 2219 2220 /* 2221 * Calculate incr. Just test the first and 2222 * last page in each physmap[] segment. 2223 */ 2224 if (pa == end - PAGE_SIZE) 2225 incr = PAGE_SIZE; 2226 else 2227 incr = end - pa - PAGE_SIZE; 2228 2229 /* 2230 * Make sure we don't skip blacked out areas. 2231 */ 2232 if (pa < 0x200000 && 0x200000 < end) { 2233 incr = 0x200000 - pa; 2234 } 2235 if (dcons_addr > 0 && 2236 pa < dcons_addr && 2237 dcons_addr < end) { 2238 incr = dcons_addr - pa; 2239 } 2240 2241 /* 2242 * Block out kernel memory as not available. 2243 */ 2244 if (pa >= 0x200000 && pa < first) { 2245 incr = first - pa; 2246 if (pa + incr > end) 2247 incr = end - pa; 2248 goto do_dump_avail; 2249 } 2250 2251 /* 2252 * Block out the dcons buffer if it exists. 2253 */ 2254 if (dcons_addr > 0 && 2255 pa >= trunc_page(dcons_addr) && 2256 pa < dcons_addr + dcons_size) { 2257 incr = dcons_addr + dcons_size - pa; 2258 incr = (incr + PAGE_MASK) & 2259 ~(vm_paddr_t)PAGE_MASK; 2260 if (pa + incr > end) 2261 incr = end - pa; 2262 goto do_dump_avail; 2263 } 2264 2265 page_bad = FALSE; 2266 2267 /* 2268 * Map the page non-cacheable for the memory 2269 * test. 2270 */ 2271 *pte = pa | 2272 kernel_pmap.pmap_bits[PG_V_IDX] | 2273 kernel_pmap.pmap_bits[PG_RW_IDX] | 2274 kernel_pmap.pmap_bits[PG_N_IDX]; 2275 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2276 cpu_mfence(); 2277 2278 /* 2279 * Save original value for restoration later. 2280 */ 2281 tmp = *ptr; 2282 2283 /* 2284 * Test for alternating 1's and 0's 2285 */ 2286 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2287 cpu_mfence(); 2288 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2289 page_bad = TRUE; 2290 /* 2291 * Test for alternating 0's and 1's 2292 */ 2293 *ptr = 0x5555555555555555LLU; 2294 cpu_mfence(); 2295 if (*ptr != 0x5555555555555555LLU) 2296 page_bad = TRUE; 2297 /* 2298 * Test for all 1's 2299 */ 2300 *ptr = 0xffffffffffffffffLLU; 2301 cpu_mfence(); 2302 if (*ptr != 0xffffffffffffffffLLU) 2303 page_bad = TRUE; 2304 /* 2305 * Test for all 0's 2306 */ 2307 *ptr = 0x0; 2308 cpu_mfence(); 2309 if (*ptr != 0x0) 2310 page_bad = TRUE; 2311 2312 /* 2313 * Restore original value. 2314 */ 2315 *ptr = tmp; 2316 2317 /* 2318 * Adjust array of valid/good pages. 2319 */ 2320 if (page_bad == TRUE) { 2321 incr = PAGE_SIZE; 2322 continue; 2323 } 2324 2325 /* 2326 * Collapse page address into phys_avail[]. Do a 2327 * continuation of the current phys_avail[] index 2328 * when possible. 2329 */ 2330 if (phys_avail[pa_indx].phys_end == pa) { 2331 /* 2332 * Continuation 2333 */ 2334 phys_avail[pa_indx].phys_end += incr; 2335 } else if (phys_avail[pa_indx].phys_beg == 2336 phys_avail[pa_indx].phys_end) { 2337 /* 2338 * Current phys_avail is completely empty, 2339 * reuse the index. 2340 */ 2341 phys_avail[pa_indx].phys_beg = pa; 2342 phys_avail[pa_indx].phys_end = pa + incr; 2343 } else { 2344 /* 2345 * Allocate next phys_avail index. 2346 */ 2347 ++pa_indx; 2348 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2349 kprintf( 2350 "Too many holes in the physical address space, giving up\n"); 2351 --pa_indx; 2352 full = TRUE; 2353 goto do_dump_avail; 2354 } 2355 phys_avail[pa_indx].phys_beg = pa; 2356 phys_avail[pa_indx].phys_end = pa + incr; 2357 } 2358 physmem += incr / PAGE_SIZE; 2359 2360 /* 2361 * pa available for dumping 2362 */ 2363 do_dump_avail: 2364 if (dump_avail[da_indx].phys_end == pa) { 2365 dump_avail[da_indx].phys_end += incr; 2366 } else { 2367 ++da_indx; 2368 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2369 --da_indx; 2370 goto do_next; 2371 } 2372 dump_avail[da_indx].phys_beg = pa; 2373 dump_avail[da_indx].phys_end = pa + incr; 2374 } 2375 do_next: 2376 if (full) 2377 break; 2378 } 2379 } 2380 *pte = 0; 2381 cpu_invltlb(); 2382 cpu_mfence(); 2383 2384 /* 2385 * The last chunk must contain at least one page plus the message 2386 * buffer to avoid complicating other code (message buffer address 2387 * calculation, etc.). 2388 */ 2389 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2390 2391 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2392 phys_avail[pa_indx].phys_end) { 2393 physmem -= atop(phys_avail[pa_indx].phys_end - 2394 phys_avail[pa_indx].phys_beg); 2395 phys_avail[pa_indx].phys_beg = 0; 2396 phys_avail[pa_indx].phys_end = 0; 2397 --pa_indx; 2398 } 2399 2400 Maxmem = atop(phys_avail[pa_indx].phys_end); 2401 2402 /* Trim off space for the message buffer. */ 2403 phys_avail[pa_indx].phys_end -= msgbuf_size; 2404 2405 avail_end = phys_avail[pa_indx].phys_end; 2406 2407 /* Map the message buffer. */ 2408 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2409 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2410 } 2411 /* Try to get EFI framebuffer working as early as possible */ 2412 if (have_efi_framebuffer) 2413 efi_fb_init_vaddr(1); 2414 } 2415 2416 struct machintr_abi MachIntrABI; 2417 2418 /* 2419 * IDT VECTORS: 2420 * 0 Divide by zero 2421 * 1 Debug 2422 * 2 NMI 2423 * 3 BreakPoint 2424 * 4 OverFlow 2425 * 5 Bound-Range 2426 * 6 Invalid OpCode 2427 * 7 Device Not Available (x87) 2428 * 8 Double-Fault 2429 * 9 Coprocessor Segment overrun (unsupported, reserved) 2430 * 10 Invalid-TSS 2431 * 11 Segment not present 2432 * 12 Stack 2433 * 13 General Protection 2434 * 14 Page Fault 2435 * 15 Reserved 2436 * 16 x87 FP Exception pending 2437 * 17 Alignment Check 2438 * 18 Machine Check 2439 * 19 SIMD floating point 2440 * 20-31 reserved 2441 * 32-255 INTn/external sources 2442 */ 2443 u_int64_t 2444 hammer_time(u_int64_t modulep, u_int64_t physfree) 2445 { 2446 caddr_t kmdp; 2447 int gsel_tss, x, cpu; 2448 #if 0 /* JG */ 2449 int metadata_missing, off; 2450 #endif 2451 struct mdglobaldata *gd; 2452 struct privatespace *ps; 2453 u_int64_t msr; 2454 2455 /* 2456 * Prevent lowering of the ipl if we call tsleep() early. 2457 */ 2458 gd = &CPU_prvspace[0]->mdglobaldata; 2459 ps = (struct privatespace *)gd; 2460 bzero(gd, sizeof(*gd)); 2461 bzero(&ps->common_tss, sizeof(ps->common_tss)); 2462 2463 /* 2464 * Note: on both UP and SMP curthread must be set non-NULL 2465 * early in the boot sequence because the system assumes 2466 * that 'curthread' is never NULL. 2467 */ 2468 2469 gd->mi.gd_curthread = &thread0; 2470 thread0.td_gd = &gd->mi; 2471 2472 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2473 2474 #if 0 /* JG */ 2475 metadata_missing = 0; 2476 if (bootinfo.bi_modulep) { 2477 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2478 preload_bootstrap_relocate(KERNBASE); 2479 } else { 2480 metadata_missing = 1; 2481 } 2482 if (bootinfo.bi_envp) 2483 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2484 #endif 2485 2486 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2487 preload_bootstrap_relocate(PTOV_OFFSET); 2488 kmdp = preload_search_by_type("elf kernel"); 2489 if (kmdp == NULL) 2490 kmdp = preload_search_by_type("elf64 kernel"); 2491 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2492 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2493 #ifdef DDB 2494 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2495 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2496 #endif 2497 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2498 2499 if (boothowto & RB_VERBOSE) 2500 bootverbose++; 2501 2502 /* 2503 * Default MachIntrABI to ICU 2504 */ 2505 MachIntrABI = MachIntrABI_ICU; 2506 2507 /* 2508 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2509 */ 2510 ncpus = 1; 2511 ncpus_fit = 1; 2512 /* Init basic tunables, hz etc */ 2513 init_param1(); 2514 2515 /* 2516 * make gdt memory segments 2517 */ 2518 gdt_segs[GPROC0_SEL].ssd_base = 2519 (uintptr_t) &CPU_prvspace[0]->common_tss; 2520 2521 gd->mi.gd_prvspace = CPU_prvspace[0]; 2522 2523 for (x = 0; x < NGDT; x++) { 2524 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2525 ssdtosd(&gdt_segs[x], &gdt[x]); 2526 } 2527 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2528 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2529 2530 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2531 r_gdt.rd_base = (long) gdt; 2532 lgdt(&r_gdt); 2533 2534 wrmsr(MSR_FSBASE, 0); /* User value */ 2535 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2536 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2537 2538 mi_gdinit(&gd->mi, 0); 2539 cpu_gdinit(gd, 0); 2540 proc0paddr = proc0paddr_buff; 2541 mi_proc0init(&gd->mi, proc0paddr); 2542 safepri = TDPRI_MAX; 2543 2544 /* spinlocks and the BGL */ 2545 init_locks(); 2546 2547 /* exceptions */ 2548 for (x = 0; x < NIDT; x++) 2549 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2550 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2551 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 2); 2552 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2553 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2554 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2555 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2556 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2557 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2558 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2559 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2560 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2561 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2562 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2563 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2564 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2565 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2566 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2567 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2568 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2569 2570 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2571 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2572 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2573 } 2574 2575 lidt(&r_idt_arr[0]); 2576 2577 /* 2578 * Initialize the console before we print anything out. 2579 */ 2580 cninit(); 2581 2582 #if 0 /* JG */ 2583 if (metadata_missing) 2584 kprintf("WARNING: loader(8) metadata is missing!\n"); 2585 #endif 2586 2587 #if NISA >0 2588 elcr_probe(); 2589 isa_defaultirq(); 2590 #endif 2591 rand_initialize(); 2592 2593 /* 2594 * Initialize IRQ mapping 2595 * 2596 * NOTE: 2597 * SHOULD be after elcr_probe() 2598 */ 2599 MachIntrABI_ICU.initmap(); 2600 MachIntrABI_IOAPIC.initmap(); 2601 2602 #ifdef DDB 2603 kdb_init(); 2604 if (boothowto & RB_KDB) 2605 Debugger("Boot flags requested debugger"); 2606 #endif 2607 2608 identify_cpu(); /* Final stage of CPU initialization */ 2609 initializecpu(0); /* Initialize CPU registers */ 2610 2611 /* 2612 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2613 * because the cpu does significant power management in MWAIT 2614 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2615 * 2616 * On many AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2617 * significant power management only when using ACPI halt mode. 2618 * (However, on Ryzen, mode 4 (HLT) also does power management). 2619 * 2620 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2621 * is needed to reduce power consumption, but wakeup times are often 2622 * too long. 2623 */ 2624 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2625 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2626 cpu_idle_hlt = 1; 2627 } 2628 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2629 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2630 /* Ryzen or later */ 2631 cpu_idle_hlt = 3; 2632 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2633 /* Bobcat or later */ 2634 cpu_idle_hlt = 3; 2635 } 2636 } 2637 2638 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2639 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2640 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2641 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2642 2643 /* 2644 * Some of the virtual machines do not work w/ I/O APIC 2645 * enabled. If the user does not explicitly enable or 2646 * disable the I/O APIC (ioapic_enable < 0), then we 2647 * disable I/O APIC on all virtual machines. 2648 * 2649 * NOTE: 2650 * This must be done after identify_cpu(), which sets 2651 * 'cpu_feature2' 2652 */ 2653 if (ioapic_enable < 0) { 2654 if (cpu_feature2 & CPUID2_VMM) 2655 ioapic_enable = 0; 2656 else 2657 ioapic_enable = 1; 2658 } 2659 2660 /* 2661 * TSS entry point for interrupts, traps, and exceptions 2662 * (sans NMI). This will always go to near the top of the pcpu 2663 * trampoline area. Hardware-pushed data will be copied into 2664 * the trap-frame on entry, and (if necessary) returned to the 2665 * trampoline on exit. 2666 * 2667 * We store some pcb data for the trampoline code above the 2668 * stack the cpu hw pushes into, and arrange things so the 2669 * address of tr_pcb_rsp is the same as the desired top of 2670 * stack. 2671 */ 2672 ps->common_tss.tss_rsp0 = (register_t)&ps->trampoline.tr_pcb_rsp; 2673 ps->trampoline.tr_pcb_rsp = ps->common_tss.tss_rsp0; 2674 ps->trampoline.tr_pcb_gs_kernel = (register_t)gd; 2675 ps->trampoline.tr_pcb_cr3 = KPML4phys; /* adj to user cr3 live */ 2676 ps->dbltramp.tr_pcb_gs_kernel = (register_t)gd; 2677 ps->dbltramp.tr_pcb_cr3 = KPML4phys; 2678 ps->dbgtramp.tr_pcb_gs_kernel = (register_t)gd; 2679 ps->dbgtramp.tr_pcb_cr3 = KPML4phys; 2680 2681 /* double fault stack */ 2682 ps->common_tss.tss_ist1 = (register_t)&ps->dbltramp.tr_pcb_rsp; 2683 /* #DB debugger needs its own stack */ 2684 ps->common_tss.tss_ist2 = (register_t)&ps->dbgtramp.tr_pcb_rsp; 2685 2686 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2687 ps->common_tss.tss_iobase = sizeof(struct x86_64tss); 2688 2689 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2690 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2691 gd->gd_common_tssd = *gd->gd_tss_gdt; 2692 ltr(gsel_tss); 2693 2694 /* Set up the fast syscall stuff */ 2695 msr = rdmsr(MSR_EFER) | EFER_SCE; 2696 wrmsr(MSR_EFER, msr); 2697 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2698 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2699 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2700 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2701 wrmsr(MSR_STAR, msr); 2702 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2703 2704 getmemsize(kmdp, physfree); 2705 init_param2(physmem); 2706 2707 /* now running on new page tables, configured,and u/iom is accessible */ 2708 2709 /* Map the message buffer. */ 2710 #if 0 /* JG */ 2711 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2712 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2713 #endif 2714 2715 msgbufinit(msgbufp, MSGBUF_SIZE); 2716 2717 2718 /* transfer to user mode */ 2719 2720 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2721 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2722 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2723 2724 load_ds(_udatasel); 2725 load_es(_udatasel); 2726 load_fs(_udatasel); 2727 2728 /* setup proc 0's pcb */ 2729 thread0.td_pcb->pcb_flags = 0; 2730 thread0.td_pcb->pcb_cr3 = KPML4phys; 2731 thread0.td_pcb->pcb_cr3_iso = 0; 2732 thread0.td_pcb->pcb_ext = NULL; 2733 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2734 2735 /* Location of kernel stack for locore */ 2736 return ((u_int64_t)thread0.td_pcb); 2737 } 2738 2739 /* 2740 * Initialize machine-dependant portions of the global data structure. 2741 * Note that the global data area and cpu0's idlestack in the private 2742 * data space were allocated in locore. 2743 * 2744 * Note: the idlethread's cpl is 0 2745 * 2746 * WARNING! Called from early boot, 'mycpu' may not work yet. 2747 */ 2748 void 2749 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2750 { 2751 if (cpu) 2752 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2753 2754 lwkt_init_thread(&gd->mi.gd_idlethread, 2755 gd->mi.gd_prvspace->idlestack, 2756 sizeof(gd->mi.gd_prvspace->idlestack), 2757 0, &gd->mi); 2758 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2759 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2760 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2761 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2762 } 2763 2764 /* 2765 * We only have to check for DMAP bounds, the globaldata space is 2766 * actually part of the kernel_map so we don't have to waste time 2767 * checking CPU_prvspace[*]. 2768 */ 2769 int 2770 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2771 { 2772 #if 0 2773 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2774 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2775 return (TRUE); 2776 } 2777 #endif 2778 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2779 return (TRUE); 2780 return (FALSE); 2781 } 2782 2783 struct globaldata * 2784 globaldata_find(int cpu) 2785 { 2786 KKASSERT(cpu >= 0 && cpu < ncpus); 2787 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2788 } 2789 2790 /* 2791 * This path should be safe from the SYSRET issue because only stopped threads 2792 * can have their %rip adjusted this way (and all heavy weight thread switches 2793 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2794 * convoluted so add a safety by forcing %rip to be cannonical. 2795 */ 2796 int 2797 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2798 { 2799 if (addr & 0x0000800000000000LLU) 2800 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2801 else 2802 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2803 return (0); 2804 } 2805 2806 int 2807 ptrace_single_step(struct lwp *lp) 2808 { 2809 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2810 return (0); 2811 } 2812 2813 int 2814 fill_regs(struct lwp *lp, struct reg *regs) 2815 { 2816 struct trapframe *tp; 2817 2818 if ((tp = lp->lwp_md.md_regs) == NULL) 2819 return EINVAL; 2820 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2821 return (0); 2822 } 2823 2824 int 2825 set_regs(struct lwp *lp, struct reg *regs) 2826 { 2827 struct trapframe *tp; 2828 2829 tp = lp->lwp_md.md_regs; 2830 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2831 !CS_SECURE(regs->r_cs)) 2832 return (EINVAL); 2833 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2834 clear_quickret(); 2835 return (0); 2836 } 2837 2838 static void 2839 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2840 { 2841 struct env87 *penv_87 = &sv_87->sv_env; 2842 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2843 int i; 2844 2845 /* FPU control/status */ 2846 penv_87->en_cw = penv_xmm->en_cw; 2847 penv_87->en_sw = penv_xmm->en_sw; 2848 penv_87->en_tw = penv_xmm->en_tw; 2849 penv_87->en_fip = penv_xmm->en_fip; 2850 penv_87->en_fcs = penv_xmm->en_fcs; 2851 penv_87->en_opcode = penv_xmm->en_opcode; 2852 penv_87->en_foo = penv_xmm->en_foo; 2853 penv_87->en_fos = penv_xmm->en_fos; 2854 2855 /* FPU registers */ 2856 for (i = 0; i < 8; ++i) 2857 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2858 } 2859 2860 static void 2861 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2862 { 2863 struct env87 *penv_87 = &sv_87->sv_env; 2864 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2865 int i; 2866 2867 /* FPU control/status */ 2868 penv_xmm->en_cw = penv_87->en_cw; 2869 penv_xmm->en_sw = penv_87->en_sw; 2870 penv_xmm->en_tw = penv_87->en_tw; 2871 penv_xmm->en_fip = penv_87->en_fip; 2872 penv_xmm->en_fcs = penv_87->en_fcs; 2873 penv_xmm->en_opcode = penv_87->en_opcode; 2874 penv_xmm->en_foo = penv_87->en_foo; 2875 penv_xmm->en_fos = penv_87->en_fos; 2876 2877 /* FPU registers */ 2878 for (i = 0; i < 8; ++i) 2879 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2880 } 2881 2882 int 2883 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2884 { 2885 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2886 return EINVAL; 2887 if (cpu_fxsr) { 2888 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2889 (struct save87 *)fpregs); 2890 return (0); 2891 } 2892 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2893 return (0); 2894 } 2895 2896 int 2897 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2898 { 2899 if (cpu_fxsr) { 2900 set_fpregs_xmm((struct save87 *)fpregs, 2901 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2902 return (0); 2903 } 2904 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2905 return (0); 2906 } 2907 2908 int 2909 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2910 { 2911 struct pcb *pcb; 2912 2913 if (lp == NULL) { 2914 dbregs->dr[0] = rdr0(); 2915 dbregs->dr[1] = rdr1(); 2916 dbregs->dr[2] = rdr2(); 2917 dbregs->dr[3] = rdr3(); 2918 dbregs->dr[4] = rdr4(); 2919 dbregs->dr[5] = rdr5(); 2920 dbregs->dr[6] = rdr6(); 2921 dbregs->dr[7] = rdr7(); 2922 return (0); 2923 } 2924 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2925 return EINVAL; 2926 dbregs->dr[0] = pcb->pcb_dr0; 2927 dbregs->dr[1] = pcb->pcb_dr1; 2928 dbregs->dr[2] = pcb->pcb_dr2; 2929 dbregs->dr[3] = pcb->pcb_dr3; 2930 dbregs->dr[4] = 0; 2931 dbregs->dr[5] = 0; 2932 dbregs->dr[6] = pcb->pcb_dr6; 2933 dbregs->dr[7] = pcb->pcb_dr7; 2934 return (0); 2935 } 2936 2937 int 2938 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2939 { 2940 if (lp == NULL) { 2941 load_dr0(dbregs->dr[0]); 2942 load_dr1(dbregs->dr[1]); 2943 load_dr2(dbregs->dr[2]); 2944 load_dr3(dbregs->dr[3]); 2945 load_dr4(dbregs->dr[4]); 2946 load_dr5(dbregs->dr[5]); 2947 load_dr6(dbregs->dr[6]); 2948 load_dr7(dbregs->dr[7]); 2949 } else { 2950 struct pcb *pcb; 2951 struct ucred *ucred; 2952 int i; 2953 uint64_t mask1, mask2; 2954 2955 /* 2956 * Don't let an illegal value for dr7 get set. Specifically, 2957 * check for undefined settings. Setting these bit patterns 2958 * result in undefined behaviour and can lead to an unexpected 2959 * TRCTRAP. 2960 */ 2961 /* JG this loop looks unreadable */ 2962 /* Check 4 2-bit fields for invalid patterns. 2963 * These fields are R/Wi, for i = 0..3 2964 */ 2965 /* Is 10 in LENi allowed when running in compatibility mode? */ 2966 /* Pattern 10 in R/Wi might be used to indicate 2967 * breakpoint on I/O. Further analysis should be 2968 * carried to decide if it is safe and useful to 2969 * provide access to that capability 2970 */ 2971 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2972 i++, mask1 <<= 4, mask2 <<= 4) 2973 if ((dbregs->dr[7] & mask1) == mask2) 2974 return (EINVAL); 2975 2976 pcb = lp->lwp_thread->td_pcb; 2977 ucred = lp->lwp_proc->p_ucred; 2978 2979 /* 2980 * Don't let a process set a breakpoint that is not within the 2981 * process's address space. If a process could do this, it 2982 * could halt the system by setting a breakpoint in the kernel 2983 * (if ddb was enabled). Thus, we need to check to make sure 2984 * that no breakpoints are being enabled for addresses outside 2985 * process's address space, unless, perhaps, we were called by 2986 * uid 0. 2987 * 2988 * XXX - what about when the watched area of the user's 2989 * address space is written into from within the kernel 2990 * ... wouldn't that still cause a breakpoint to be generated 2991 * from within kernel mode? 2992 */ 2993 2994 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2995 if (dbregs->dr[7] & 0x3) { 2996 /* dr0 is enabled */ 2997 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2998 return (EINVAL); 2999 } 3000 3001 if (dbregs->dr[7] & (0x3<<2)) { 3002 /* dr1 is enabled */ 3003 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 3004 return (EINVAL); 3005 } 3006 3007 if (dbregs->dr[7] & (0x3<<4)) { 3008 /* dr2 is enabled */ 3009 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 3010 return (EINVAL); 3011 } 3012 3013 if (dbregs->dr[7] & (0x3<<6)) { 3014 /* dr3 is enabled */ 3015 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 3016 return (EINVAL); 3017 } 3018 } 3019 3020 pcb->pcb_dr0 = dbregs->dr[0]; 3021 pcb->pcb_dr1 = dbregs->dr[1]; 3022 pcb->pcb_dr2 = dbregs->dr[2]; 3023 pcb->pcb_dr3 = dbregs->dr[3]; 3024 pcb->pcb_dr6 = dbregs->dr[6]; 3025 pcb->pcb_dr7 = dbregs->dr[7]; 3026 3027 pcb->pcb_flags |= PCB_DBREGS; 3028 } 3029 3030 return (0); 3031 } 3032 3033 /* 3034 * Return > 0 if a hardware breakpoint has been hit, and the 3035 * breakpoint was in user space. Return 0, otherwise. 3036 */ 3037 int 3038 user_dbreg_trap(void) 3039 { 3040 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 3041 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 3042 int nbp; /* number of breakpoints that triggered */ 3043 caddr_t addr[4]; /* breakpoint addresses */ 3044 int i; 3045 3046 dr7 = rdr7(); 3047 if ((dr7 & 0xff) == 0) { 3048 /* 3049 * all GE and LE bits in the dr7 register are zero, 3050 * thus the trap couldn't have been caused by the 3051 * hardware debug registers 3052 */ 3053 return 0; 3054 } 3055 3056 nbp = 0; 3057 dr6 = rdr6(); 3058 bp = dr6 & 0xf; 3059 3060 if (bp == 0) { 3061 /* 3062 * None of the breakpoint bits are set meaning this 3063 * trap was not caused by any of the debug registers 3064 */ 3065 return 0; 3066 } 3067 3068 /* 3069 * at least one of the breakpoints were hit, check to see 3070 * which ones and if any of them are user space addresses 3071 */ 3072 3073 if (bp & 0x01) { 3074 addr[nbp++] = (caddr_t)rdr0(); 3075 } 3076 if (bp & 0x02) { 3077 addr[nbp++] = (caddr_t)rdr1(); 3078 } 3079 if (bp & 0x04) { 3080 addr[nbp++] = (caddr_t)rdr2(); 3081 } 3082 if (bp & 0x08) { 3083 addr[nbp++] = (caddr_t)rdr3(); 3084 } 3085 3086 for (i = 0; i < nbp; i++) { 3087 if (addr[i] < (caddr_t)VM_MAX_USER_ADDRESS) { 3088 /* 3089 * addr[i] is in user space 3090 */ 3091 return nbp; 3092 } 3093 } 3094 3095 /* 3096 * None of the breakpoints are in user space. 3097 */ 3098 return 0; 3099 } 3100 3101 3102 #ifndef DDB 3103 void 3104 Debugger(const char *msg) 3105 { 3106 kprintf("Debugger(\"%s\") called.\n", msg); 3107 } 3108 #endif /* no DDB */ 3109 3110 #ifdef DDB 3111 3112 /* 3113 * Provide inb() and outb() as functions. They are normally only 3114 * available as macros calling inlined functions, thus cannot be 3115 * called inside DDB. 3116 * 3117 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 3118 */ 3119 3120 #undef inb 3121 #undef outb 3122 3123 /* silence compiler warnings */ 3124 u_char inb(u_int); 3125 void outb(u_int, u_char); 3126 3127 u_char 3128 inb(u_int port) 3129 { 3130 u_char data; 3131 /* 3132 * We use %%dx and not %1 here because i/o is done at %dx and not at 3133 * %edx, while gcc generates inferior code (movw instead of movl) 3134 * if we tell it to load (u_short) port. 3135 */ 3136 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 3137 return (data); 3138 } 3139 3140 void 3141 outb(u_int port, u_char data) 3142 { 3143 u_char al; 3144 /* 3145 * Use an unnecessary assignment to help gcc's register allocator. 3146 * This make a large difference for gcc-1.40 and a tiny difference 3147 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 3148 * best results. gcc-2.6.0 can't handle this. 3149 */ 3150 al = data; 3151 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 3152 } 3153 3154 #endif /* DDB */ 3155 3156 3157 3158 /* 3159 * initialize all the SMP locks 3160 */ 3161 3162 /* critical region when masking or unmasking interupts */ 3163 struct spinlock_deprecated imen_spinlock; 3164 3165 /* lock region used by kernel profiling */ 3166 struct spinlock_deprecated mcount_spinlock; 3167 3168 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 3169 struct spinlock_deprecated com_spinlock; 3170 3171 /* lock regions around the clock hardware */ 3172 struct spinlock_deprecated clock_spinlock; 3173 3174 static void 3175 init_locks(void) 3176 { 3177 /* 3178 * Get the initial mplock with a count of 1 for the BSP. 3179 * This uses a LOGICAL cpu ID, ie BSP == 0. 3180 */ 3181 cpu_get_initial_mplock(); 3182 /* DEPRECATED */ 3183 spin_init_deprecated(&mcount_spinlock); 3184 spin_init_deprecated(&imen_spinlock); 3185 spin_init_deprecated(&com_spinlock); 3186 spin_init_deprecated(&clock_spinlock); 3187 3188 /* our token pool needs to work early */ 3189 lwkt_token_pool_init(); 3190 } 3191 3192 boolean_t 3193 cpu_mwait_hint_valid(uint32_t hint) 3194 { 3195 int cx_idx, sub; 3196 3197 cx_idx = MWAIT_EAX_TO_CX(hint); 3198 if (cx_idx >= CPU_MWAIT_CX_MAX) 3199 return FALSE; 3200 3201 sub = MWAIT_EAX_TO_CX_SUB(hint); 3202 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3203 return FALSE; 3204 3205 return TRUE; 3206 } 3207 3208 void 3209 cpu_mwait_cx_no_bmsts(void) 3210 { 3211 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3212 } 3213 3214 void 3215 cpu_mwait_cx_no_bmarb(void) 3216 { 3217 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3218 } 3219 3220 static int 3221 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3222 { 3223 int old_cx_idx, sub = 0; 3224 3225 if (hint >= 0) { 3226 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3227 sub = MWAIT_EAX_TO_CX_SUB(hint); 3228 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3229 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3230 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3231 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3232 } else { 3233 old_cx_idx = CPU_MWAIT_CX_MAX; 3234 } 3235 3236 if (!CPU_MWAIT_HAS_CX) 3237 strlcpy(name, "NONE", namelen); 3238 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3239 strlcpy(name, "AUTO", namelen); 3240 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3241 strlcpy(name, "AUTODEEP", namelen); 3242 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3243 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3244 strlcpy(name, "INVALID", namelen); 3245 else 3246 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3247 3248 return old_cx_idx; 3249 } 3250 3251 static int 3252 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3253 { 3254 int cx_idx, sub, hint; 3255 char *ptr, *start; 3256 3257 if (allow_auto && strcmp(name, "AUTO") == 0) { 3258 hint = CPU_MWAIT_HINT_AUTO; 3259 cx_idx = CPU_MWAIT_C2; 3260 goto done; 3261 } 3262 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3263 hint = CPU_MWAIT_HINT_AUTODEEP; 3264 cx_idx = CPU_MWAIT_C3; 3265 goto done; 3266 } 3267 3268 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3269 return -1; 3270 start = &name[1]; 3271 ptr = NULL; 3272 3273 cx_idx = strtol(start, &ptr, 10); 3274 if (ptr == start || *ptr != '/') 3275 return -1; 3276 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3277 return -1; 3278 3279 start = ptr + 1; 3280 ptr = NULL; 3281 3282 sub = strtol(start, &ptr, 10); 3283 if (*ptr != '\0') 3284 return -1; 3285 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3286 return -1; 3287 3288 hint = MWAIT_EAX_HINT(cx_idx, sub); 3289 done: 3290 *hint0 = hint; 3291 return cx_idx; 3292 } 3293 3294 static int 3295 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3296 { 3297 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3298 return EOPNOTSUPP; 3299 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3300 int error; 3301 3302 error = cputimer_intr_powersave_addreq(); 3303 if (error) 3304 return error; 3305 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3306 cputimer_intr_powersave_remreq(); 3307 } 3308 return 0; 3309 } 3310 3311 static int 3312 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3313 boolean_t allow_auto) 3314 { 3315 int error, cx_idx, old_cx_idx, hint; 3316 char name[CPU_MWAIT_CX_NAMELEN]; 3317 3318 hint = *hint0; 3319 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3320 allow_auto); 3321 3322 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3323 if (error != 0 || req->newptr == NULL) 3324 return error; 3325 3326 if (!CPU_MWAIT_HAS_CX) 3327 return EOPNOTSUPP; 3328 3329 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3330 if (cx_idx < 0) 3331 return EINVAL; 3332 3333 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3334 if (error) 3335 return error; 3336 3337 *hint0 = hint; 3338 return 0; 3339 } 3340 3341 static int 3342 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3343 { 3344 int error, cx_idx, old_cx_idx, hint; 3345 char name[CPU_MWAIT_CX_NAMELEN]; 3346 3347 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3348 3349 hint = stat->hint; 3350 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3351 3352 strlcpy(name, cx_name, sizeof(name)); 3353 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3354 if (cx_idx < 0) 3355 return EINVAL; 3356 3357 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3358 if (error) 3359 return error; 3360 3361 stat->hint = hint; 3362 return 0; 3363 } 3364 3365 static int 3366 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3367 { 3368 int hint = cpu_mwait_halt_global; 3369 int error, cx_idx, cpu; 3370 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3371 3372 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3373 3374 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3375 if (error != 0 || req->newptr == NULL) 3376 return error; 3377 3378 if (!CPU_MWAIT_HAS_CX) 3379 return EOPNOTSUPP; 3380 3381 /* Save name for later per-cpu CX configuration */ 3382 strlcpy(cx_name, name, sizeof(cx_name)); 3383 3384 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3385 if (cx_idx < 0) 3386 return EINVAL; 3387 3388 /* Change per-cpu CX configuration */ 3389 for (cpu = 0; cpu < ncpus; ++cpu) { 3390 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3391 if (error) 3392 return error; 3393 } 3394 3395 cpu_mwait_halt_global = hint; 3396 return 0; 3397 } 3398 3399 static int 3400 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3401 { 3402 struct cpu_idle_stat *stat = arg1; 3403 int error; 3404 3405 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3406 &stat->hint, TRUE); 3407 return error; 3408 } 3409 3410 static int 3411 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3412 { 3413 int error; 3414 3415 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3416 &cpu_mwait_spin, FALSE); 3417 return error; 3418 } 3419 3420 /* 3421 * This manual debugging code is called unconditionally from Xtimer 3422 * (the per-cpu timer interrupt) whether the current thread is in a 3423 * critical section or not) and can be useful in tracking down lockups. 3424 * 3425 * NOTE: MANUAL DEBUG CODE 3426 */ 3427 #if 0 3428 static int saveticks[SMP_MAXCPU]; 3429 static int savecounts[SMP_MAXCPU]; 3430 #endif 3431 3432 void 3433 pcpu_timer_always(struct intrframe *frame) 3434 { 3435 #if 0 3436 globaldata_t gd = mycpu; 3437 int cpu = gd->gd_cpuid; 3438 char buf[64]; 3439 short *gptr; 3440 int i; 3441 3442 if (cpu <= 20) { 3443 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3444 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3445 ++gptr; 3446 3447 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3448 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3449 gd->gd_infomsg); 3450 for (i = 0; buf[i]; ++i) { 3451 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3452 } 3453 } 3454 #if 0 3455 if (saveticks[gd->gd_cpuid] != ticks) { 3456 saveticks[gd->gd_cpuid] = ticks; 3457 savecounts[gd->gd_cpuid] = 0; 3458 } 3459 ++savecounts[gd->gd_cpuid]; 3460 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3461 panic("cpud %d panicing on ticks failure", 3462 gd->gd_cpuid); 3463 } 3464 for (i = 0; i < ncpus; ++i) { 3465 int delta; 3466 if (saveticks[i] && panicstr == NULL) { 3467 delta = saveticks[i] - ticks; 3468 if (delta < -10 || delta > 10) { 3469 panic("cpu %d panicing on cpu %d watchdog", 3470 gd->gd_cpuid, i); 3471 } 3472 } 3473 } 3474 #endif 3475 #endif 3476 } 3477