1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_compat.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_directio.h" 49 #include "opt_inet.h" 50 #include "opt_msgbuf.h" 51 #include "opt_swap.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/sysproto.h> 56 #include <sys/signalvar.h> 57 #include <sys/kernel.h> 58 #include <sys/linker.h> 59 #include <sys/malloc.h> 60 #include <sys/proc.h> 61 #include <sys/priv.h> 62 #include <sys/buf.h> 63 #include <sys/reboot.h> 64 #include <sys/mbuf.h> 65 #include <sys/msgbuf.h> 66 #include <sys/sysent.h> 67 #include <sys/sysctl.h> 68 #include <sys/vmmeter.h> 69 #include <sys/bus.h> 70 #include <sys/usched.h> 71 #include <sys/reg.h> 72 #include <sys/sbuf.h> 73 #include <sys/ctype.h> 74 #include <sys/serialize.h> 75 #include <sys/systimer.h> 76 77 #include <vm/vm.h> 78 #include <vm/vm_param.h> 79 #include <sys/lock.h> 80 #include <vm/vm_kern.h> 81 #include <vm/vm_object.h> 82 #include <vm/vm_page.h> 83 #include <vm/vm_map.h> 84 #include <vm/vm_pager.h> 85 #include <vm/vm_extern.h> 86 87 #include <sys/thread2.h> 88 #include <sys/mplock2.h> 89 #include <sys/mutex2.h> 90 91 #include <sys/user.h> 92 #include <sys/exec.h> 93 #include <sys/cons.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #ifdef PERFMON 110 #include <machine/perfmon.h> 111 #endif 112 #include <machine/cputypes.h> 113 #include <machine/intr_machdep.h> 114 115 #ifdef OLD_BUS_ARCH 116 #include <bus/isa/isa_device.h> 117 #endif 118 #include <machine_base/isa/isa_intr.h> 119 #include <bus/isa/rtc.h> 120 #include <sys/random.h> 121 #include <sys/ptrace.h> 122 #include <machine/sigframe.h> 123 124 #include <sys/machintr.h> 125 #include <machine_base/icu/icu_abi.h> 126 #include <machine_base/icu/elcr_var.h> 127 #include <machine_base/apic/lapic.h> 128 #include <machine_base/apic/ioapic.h> 129 #include <machine_base/apic/ioapic_abi.h> 130 #include <machine/mptable.h> 131 132 #define PHYSMAP_ENTRIES 10 133 134 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 135 136 extern void printcpuinfo(void); /* XXX header file */ 137 extern void identify_cpu(void); 138 #if 0 /* JG */ 139 extern void finishidentcpu(void); 140 #endif 141 extern void panicifcpuunsupported(void); 142 143 static void cpu_startup(void *); 144 static void pic_finish(void *); 145 static void cpu_finish(void *); 146 147 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 148 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 149 #ifdef DIRECTIO 150 extern void ffs_rawread_setup(void); 151 #endif /* DIRECTIO */ 152 static void init_locks(void); 153 154 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 155 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 156 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 157 158 #ifdef DDB 159 extern vm_offset_t ksym_start, ksym_end; 160 #endif 161 162 struct privatespace CPU_prvspace_bsp __aligned(4096); 163 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 164 165 int _udatasel, _ucodesel, _ucode32sel; 166 u_long atdevbase; 167 int64_t tsc_offsets[MAXCPU]; 168 169 static int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 170 171 #if defined(SWTCH_OPTIM_STATS) 172 extern int swtch_optim_stats; 173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 174 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 176 CTLFLAG_RD, &tlb_flush_count, 0, ""); 177 #endif 178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 179 CTLFLAG_RD, &cpu_mwait_halt, 0, ""); 180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0, 181 "monitor/mwait target state"); 182 183 #define CPU_MWAIT_C1 1 184 #define CPU_MWAIT_C2 2 185 #define CPU_MWAIT_C3 3 186 #define CPU_MWAIT_CX_MAX 8 187 188 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 189 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 190 191 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 192 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 193 194 struct cpu_mwait_cx { 195 int subcnt; 196 char name[4]; 197 struct sysctl_ctx_list sysctl_ctx; 198 struct sysctl_oid *sysctl_tree; 199 }; 200 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 201 static char cpu_mwait_cx_supported[256]; 202 203 static int cpu_mwait_c1_hints_cnt; 204 static int cpu_mwait_hints_cnt; 205 static int *cpu_mwait_hints; 206 207 static int cpu_mwait_deep_hints_cnt; 208 static int *cpu_mwait_deep_hints; 209 210 #define CPU_IDLE_REPEAT_DEFAULT 750 211 212 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 213 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 214 static u_int cpu_mwait_repeat_shift = 1; 215 216 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 217 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 218 219 static int cpu_mwait_c3_preamble = 220 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 221 CPU_MWAIT_C3_PREAMBLE_BM_STS; 222 223 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 224 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 225 226 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER; 227 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 228 int *, boolean_t); 229 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 230 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 231 232 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 233 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 234 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 235 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 236 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 237 &cpu_mwait_repeat_shift, 0, ""); 238 239 long physmem = 0; 240 241 u_long ebda_addr = 0; 242 243 int imcr_present = 0; 244 245 int naps = 0; /* # of Applications processors */ 246 247 u_int base_memory; 248 struct mtx dt_lock; /* lock for GDT and LDT */ 249 250 static int 251 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 252 { 253 u_long pmem = ctob(physmem); 254 255 int error = sysctl_handle_long(oidp, &pmem, 0, req); 256 return (error); 257 } 258 259 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 260 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 261 262 static int 263 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 264 { 265 int error = sysctl_handle_int(oidp, 0, 266 ctob(physmem - vmstats.v_wire_count), req); 267 return (error); 268 } 269 270 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 271 0, 0, sysctl_hw_usermem, "IU", ""); 272 273 static int 274 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 275 { 276 int error = sysctl_handle_int(oidp, 0, 277 x86_64_btop(avail_end - avail_start), req); 278 return (error); 279 } 280 281 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 282 0, 0, sysctl_hw_availpages, "I", ""); 283 284 vm_paddr_t Maxmem; 285 vm_paddr_t Realmem; 286 287 /* 288 * The number of PHYSMAP entries must be one less than the number of 289 * PHYSSEG entries because the PHYSMAP entry that spans the largest 290 * physical address that is accessible by ISA DMA is split into two 291 * PHYSSEG entries. 292 */ 293 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 294 295 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 296 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 297 298 /* must be 2 less so 0 0 can signal end of chunks */ 299 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2) 300 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2) 301 302 static vm_offset_t buffer_sva, buffer_eva; 303 vm_offset_t clean_sva, clean_eva; 304 static vm_offset_t pager_sva, pager_eva; 305 static struct trapframe proc0_tf; 306 307 static void 308 cpu_startup(void *dummy) 309 { 310 caddr_t v; 311 vm_size_t size = 0; 312 vm_offset_t firstaddr; 313 314 /* 315 * Good {morning,afternoon,evening,night}. 316 */ 317 kprintf("%s", version); 318 startrtclock(); 319 printcpuinfo(); 320 panicifcpuunsupported(); 321 #ifdef PERFMON 322 perfmon_init(); 323 #endif 324 kprintf("real memory = %ju (%ju MB)\n", 325 (intmax_t)Realmem, 326 (intmax_t)Realmem / 1024 / 1024); 327 /* 328 * Display any holes after the first chunk of extended memory. 329 */ 330 if (bootverbose) { 331 int indx; 332 333 kprintf("Physical memory chunk(s):\n"); 334 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 335 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx]; 336 337 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 338 (intmax_t)phys_avail[indx], 339 (intmax_t)phys_avail[indx + 1] - 1, 340 (intmax_t)size1, 341 (intmax_t)(size1 / PAGE_SIZE)); 342 } 343 } 344 345 /* 346 * Allocate space for system data structures. 347 * The first available kernel virtual address is in "v". 348 * As pages of kernel virtual memory are allocated, "v" is incremented. 349 * As pages of memory are allocated and cleared, 350 * "firstaddr" is incremented. 351 * An index into the kernel page table corresponding to the 352 * virtual memory address maintained in "v" is kept in "mapaddr". 353 */ 354 355 /* 356 * Make two passes. The first pass calculates how much memory is 357 * needed and allocates it. The second pass assigns virtual 358 * addresses to the various data structures. 359 */ 360 firstaddr = 0; 361 again: 362 v = (caddr_t)firstaddr; 363 364 #define valloc(name, type, num) \ 365 (name) = (type *)v; v = (caddr_t)((name)+(num)) 366 #define valloclim(name, type, num, lim) \ 367 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 368 369 /* 370 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE. 371 * For the first 64MB of ram nominally allocate sufficient buffers to 372 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 373 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 374 * the buffer cache we limit the eventual kva reservation to 375 * maxbcache bytes. 376 * 377 * factor represents the 1/4 x ram conversion. 378 */ 379 if (nbuf == 0) { 380 long factor = 4 * BKVASIZE / 1024; 381 long kbytes = physmem * (PAGE_SIZE / 1024); 382 383 nbuf = 50; 384 if (kbytes > 4096) 385 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 386 if (kbytes > 65536) 387 nbuf += (kbytes - 65536) * 2 / (factor * 5); 388 if (maxbcache && nbuf > maxbcache / BKVASIZE) 389 nbuf = maxbcache / BKVASIZE; 390 } 391 392 /* 393 * Do not allow the buffer_map to be more then 1/2 the size of the 394 * kernel_map. 395 */ 396 if (nbuf > (virtual_end - virtual_start + 397 virtual2_end - virtual2_start) / (BKVASIZE * 2)) { 398 nbuf = (virtual_end - virtual_start + 399 virtual2_end - virtual2_start) / (BKVASIZE * 2); 400 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 401 } 402 403 /* 404 * Do not allow the buffer_map to use more than 50% of available 405 * physical-equivalent memory. Since the VM pages which back 406 * individual buffers are typically wired, having too many bufs 407 * can prevent the system from paging properly. 408 */ 409 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) { 410 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2); 411 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 412 } 413 414 /* 415 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 416 * the valloc space which is just the virtual_end - virtual_start 417 * section. We use valloc() to allocate the buf header array. 418 */ 419 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 420 nbuf = (virtual_end - virtual_start) / 421 sizeof(struct buf) / 2; 422 kprintf("Warning: nbufs capped at %ld due to valloc " 423 "considerations", nbuf); 424 } 425 426 nswbuf = lmax(lmin(nbuf / 4, 256), 16); 427 #ifdef NSWBUF_MIN 428 if (nswbuf < NSWBUF_MIN) 429 nswbuf = NSWBUF_MIN; 430 #endif 431 #ifdef DIRECTIO 432 ffs_rawread_setup(); 433 #endif 434 435 valloc(swbuf, struct buf, nswbuf); 436 valloc(buf, struct buf, nbuf); 437 438 /* 439 * End of first pass, size has been calculated so allocate memory 440 */ 441 if (firstaddr == 0) { 442 size = (vm_size_t)(v - firstaddr); 443 firstaddr = kmem_alloc(&kernel_map, round_page(size)); 444 if (firstaddr == 0) 445 panic("startup: no room for tables"); 446 goto again; 447 } 448 449 /* 450 * End of second pass, addresses have been assigned 451 * 452 * nbuf is an int, make sure we don't overflow the field. 453 * 454 * On 64-bit systems we always reserve maximal allocations for 455 * buffer cache buffers and there are no fragmentation issues, 456 * so the KVA segment does not have to be excessively oversized. 457 */ 458 if ((vm_size_t)(v - firstaddr) != size) 459 panic("startup: table size inconsistency"); 460 461 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 462 ((vm_offset_t)(nbuf + 16) * BKVASIZE) + 463 (nswbuf * MAXPHYS) + pager_map_size); 464 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 465 ((vm_offset_t)(nbuf + 16) * BKVASIZE)); 466 buffer_map.system_map = 1; 467 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 468 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size); 469 pager_map.system_map = 1; 470 471 #if defined(USERCONFIG) 472 userconfig(); 473 cninit(); /* the preferred console may have changed */ 474 #endif 475 476 kprintf("avail memory = %ju (%ju MB)\n", 477 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 478 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 479 1024 / 1024); 480 } 481 482 struct cpu_idle_stat { 483 u_long halt; 484 u_long spin; 485 u_long repeat; 486 u_long repeat_last; 487 u_long repeat_delta; 488 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 489 } __cachealign; 490 491 #define CPU_IDLE_STAT_HALT -1 492 #define CPU_IDLE_STAT_SPIN -2 493 494 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 495 496 static int 497 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 498 { 499 int idx = arg2, cpu, error; 500 u_long val = 0; 501 502 if (idx == CPU_IDLE_STAT_HALT) { 503 for (cpu = 0; cpu < ncpus; ++cpu) 504 val += cpu_idle_stats[cpu].halt; 505 } else if (idx == CPU_IDLE_STAT_SPIN) { 506 for (cpu = 0; cpu < ncpus; ++cpu) 507 val += cpu_idle_stats[cpu].spin; 508 } else { 509 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 510 ("invalid index %d", idx)); 511 for (cpu = 0; cpu < ncpus; ++cpu) 512 val += cpu_idle_stats[cpu].mwait_cx[idx]; 513 } 514 515 error = sysctl_handle_quad(oidp, &val, 0, req); 516 if (error || req->newptr == NULL) 517 return error; 518 519 if (idx == CPU_IDLE_STAT_HALT) { 520 for (cpu = 0; cpu < ncpus; ++cpu) 521 cpu_idle_stats[cpu].halt = 0; 522 cpu_idle_stats[0].halt = val; 523 } else if (idx == CPU_IDLE_STAT_SPIN) { 524 for (cpu = 0; cpu < ncpus; ++cpu) 525 cpu_idle_stats[cpu].spin = 0; 526 cpu_idle_stats[0].spin = val; 527 } else { 528 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 529 ("invalid index %d", idx)); 530 for (cpu = 0; cpu < ncpus; ++cpu) 531 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 532 cpu_idle_stats[0].mwait_cx[idx] = val; 533 } 534 return 0; 535 } 536 537 static void 538 cpu_mwait_attach(void) 539 { 540 struct sbuf sb; 541 int hint_idx, i; 542 543 if ((cpu_feature2 & CPUID2_MON) == 0 || 544 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0) 545 return; 546 547 if (cpu_vendor_id == CPU_VENDOR_INTEL && 548 (CPUID_TO_FAMILY(cpu_id) > 0xf || 549 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 550 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 551 int bm_sts = 1; 552 553 /* 554 * Pentium dual-core, Core 2 and beyond do not need any 555 * additional activities to enter deep C-state, i.e. C3(+). 556 */ 557 cpu_mwait_cx_no_bmarb(); 558 559 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 560 if (!bm_sts) 561 cpu_mwait_cx_no_bmsts(); 562 } 563 564 sbuf_new(&sb, cpu_mwait_cx_supported, 565 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 566 567 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 568 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 569 int sub; 570 571 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 572 573 sysctl_ctx_init(&cx->sysctl_ctx); 574 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 575 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 576 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 577 if (cx->sysctl_tree == NULL) 578 continue; 579 580 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 581 SYSCTL_ADD_INT(&cx->sysctl_ctx, 582 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 583 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 584 "sub-state count"); 585 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 586 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 587 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 588 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 589 590 for (sub = 0; sub < cx->subcnt; ++sub) 591 sbuf_printf(&sb, "C%d/%d ", i, sub); 592 } 593 sbuf_trim(&sb); 594 sbuf_finish(&sb); 595 596 /* 597 * Non-deep C-states 598 */ 599 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 600 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 601 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 602 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 603 M_DEVBUF, M_WAITOK); 604 605 hint_idx = 0; 606 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 607 int j, subcnt; 608 609 subcnt = cpu_mwait_cx_info[i].subcnt; 610 for (j = 0; j < subcnt; ++j) { 611 KASSERT(hint_idx < cpu_mwait_hints_cnt, 612 ("invalid mwait hint index %d", hint_idx)); 613 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 614 ++hint_idx; 615 } 616 } 617 KASSERT(hint_idx == cpu_mwait_hints_cnt, 618 ("mwait hint count %d != index %d", 619 cpu_mwait_hints_cnt, hint_idx)); 620 621 if (bootverbose) { 622 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 623 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 624 int hint = cpu_mwait_hints[i]; 625 626 kprintf(" C%d/%d hint 0x%04x\n", 627 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 628 hint); 629 } 630 } 631 632 /* 633 * Deep C-states 634 */ 635 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 636 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 637 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 638 M_DEVBUF, M_WAITOK); 639 640 hint_idx = 0; 641 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 642 int j, subcnt; 643 644 subcnt = cpu_mwait_cx_info[i].subcnt; 645 for (j = 0; j < subcnt; ++j) { 646 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 647 ("invalid mwait deep hint index %d", hint_idx)); 648 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 649 ++hint_idx; 650 } 651 } 652 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 653 ("mwait deep hint count %d != index %d", 654 cpu_mwait_deep_hints_cnt, hint_idx)); 655 656 if (bootverbose) { 657 kprintf("MWAIT deep hints:\n"); 658 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 659 int hint = cpu_mwait_deep_hints[i]; 660 661 kprintf(" C%d/%d hint 0x%04x\n", 662 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 663 hint); 664 } 665 } 666 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 667 } 668 669 static void 670 cpu_finish(void *dummy __unused) 671 { 672 cpu_setregs(); 673 cpu_mwait_attach(); 674 } 675 676 static void 677 pic_finish(void *dummy __unused) 678 { 679 /* Log ELCR information */ 680 elcr_dump(); 681 682 /* Log MPTABLE information */ 683 mptable_pci_int_dump(); 684 685 /* Finalize PCI */ 686 MachIntrABI.finalize(); 687 } 688 689 /* 690 * Send an interrupt to process. 691 * 692 * Stack is set up to allow sigcode stored 693 * at top to call routine, followed by kcall 694 * to sigreturn routine below. After sigreturn 695 * resets the signal mask, the stack, and the 696 * frame pointer, it returns to the user 697 * specified pc, psl. 698 */ 699 void 700 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 701 { 702 struct lwp *lp = curthread->td_lwp; 703 struct proc *p = lp->lwp_proc; 704 struct trapframe *regs; 705 struct sigacts *psp = p->p_sigacts; 706 struct sigframe sf, *sfp; 707 int oonstack; 708 char *sp; 709 710 regs = lp->lwp_md.md_regs; 711 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 712 713 /* Save user context */ 714 bzero(&sf, sizeof(struct sigframe)); 715 sf.sf_uc.uc_sigmask = *mask; 716 sf.sf_uc.uc_stack = lp->lwp_sigstk; 717 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 718 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 719 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 720 721 /* Make the size of the saved context visible to userland */ 722 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 723 724 /* Allocate and validate space for the signal handler context. */ 725 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 726 SIGISMEMBER(psp->ps_sigonstack, sig)) { 727 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 728 sizeof(struct sigframe)); 729 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 730 } else { 731 /* We take red zone into account */ 732 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 733 } 734 735 /* 736 * XXX AVX needs 64-byte alignment but sigframe has other fields and 737 * the embedded ucontext is not at the front, so aligning this won't 738 * help us. Fortunately we bcopy in/out of the sigframe, so the 739 * kernel is ok. 740 * 741 * The problem though is if userland winds up trying to use the 742 * context directly. 743 */ 744 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 745 746 /* Translate the signal is appropriate */ 747 if (p->p_sysent->sv_sigtbl) { 748 if (sig <= p->p_sysent->sv_sigsize) 749 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 750 } 751 752 /* 753 * Build the argument list for the signal handler. 754 * 755 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 756 */ 757 regs->tf_rdi = sig; /* argument 1 */ 758 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 759 760 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 761 /* 762 * Signal handler installed with SA_SIGINFO. 763 * 764 * action(signo, siginfo, ucontext) 765 */ 766 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 767 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 768 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 769 770 /* fill siginfo structure */ 771 sf.sf_si.si_signo = sig; 772 sf.sf_si.si_code = code; 773 sf.sf_si.si_addr = (void *)regs->tf_addr; 774 } else { 775 /* 776 * Old FreeBSD-style arguments. 777 * 778 * handler (signo, code, [uc], addr) 779 */ 780 regs->tf_rsi = (register_t)code; /* argument 2 */ 781 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 782 sf.sf_ahu.sf_handler = catcher; 783 } 784 785 /* 786 * If we're a vm86 process, we want to save the segment registers. 787 * We also change eflags to be our emulated eflags, not the actual 788 * eflags. 789 */ 790 #if 0 /* JG */ 791 if (regs->tf_eflags & PSL_VM) { 792 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 793 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 794 795 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 796 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 797 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 798 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 799 800 if (vm86->vm86_has_vme == 0) 801 sf.sf_uc.uc_mcontext.mc_eflags = 802 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 803 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 804 805 /* 806 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 807 * syscalls made by the signal handler. This just avoids 808 * wasting time for our lazy fixup of such faults. PSL_NT 809 * does nothing in vm86 mode, but vm86 programs can set it 810 * almost legitimately in probes for old cpu types. 811 */ 812 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 813 } 814 #endif 815 816 /* 817 * Save the FPU state and reinit the FP unit 818 */ 819 npxpush(&sf.sf_uc.uc_mcontext); 820 821 /* 822 * Copy the sigframe out to the user's stack. 823 */ 824 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 825 /* 826 * Something is wrong with the stack pointer. 827 * ...Kill the process. 828 */ 829 sigexit(lp, SIGILL); 830 } 831 832 regs->tf_rsp = (register_t)sfp; 833 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 834 835 /* 836 * i386 abi specifies that the direction flag must be cleared 837 * on function entry 838 */ 839 regs->tf_rflags &= ~(PSL_T|PSL_D); 840 841 /* 842 * 64 bit mode has a code and stack selector but 843 * no data or extra selector. %fs and %gs are not 844 * stored in-context. 845 */ 846 regs->tf_cs = _ucodesel; 847 regs->tf_ss = _udatasel; 848 clear_quickret(); 849 } 850 851 /* 852 * Sanitize the trapframe for a virtual kernel passing control to a custom 853 * VM context. Remove any items that would otherwise create a privilage 854 * issue. 855 * 856 * XXX at the moment we allow userland to set the resume flag. Is this a 857 * bad idea? 858 */ 859 int 860 cpu_sanitize_frame(struct trapframe *frame) 861 { 862 frame->tf_cs = _ucodesel; 863 frame->tf_ss = _udatasel; 864 /* XXX VM (8086) mode not supported? */ 865 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 866 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 867 868 return(0); 869 } 870 871 /* 872 * Sanitize the tls so loading the descriptor does not blow up 873 * on us. For x86_64 we don't have to do anything. 874 */ 875 int 876 cpu_sanitize_tls(struct savetls *tls) 877 { 878 return(0); 879 } 880 881 /* 882 * sigreturn(ucontext_t *sigcntxp) 883 * 884 * System call to cleanup state after a signal 885 * has been taken. Reset signal mask and 886 * stack state from context left by sendsig (above). 887 * Return to previous pc and psl as specified by 888 * context left by sendsig. Check carefully to 889 * make sure that the user has not modified the 890 * state to gain improper privileges. 891 * 892 * MPSAFE 893 */ 894 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 895 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 896 897 int 898 sys_sigreturn(struct sigreturn_args *uap) 899 { 900 struct lwp *lp = curthread->td_lwp; 901 struct trapframe *regs; 902 ucontext_t uc; 903 ucontext_t *ucp; 904 register_t rflags; 905 int cs; 906 int error; 907 908 /* 909 * We have to copy the information into kernel space so userland 910 * can't modify it while we are sniffing it. 911 */ 912 regs = lp->lwp_md.md_regs; 913 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 914 if (error) 915 return (error); 916 ucp = &uc; 917 rflags = ucp->uc_mcontext.mc_rflags; 918 919 /* VM (8086) mode not supported */ 920 rflags &= ~PSL_VM_UNSUPP; 921 922 #if 0 /* JG */ 923 if (eflags & PSL_VM) { 924 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 925 struct vm86_kernel *vm86; 926 927 /* 928 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 929 * set up the vm86 area, and we can't enter vm86 mode. 930 */ 931 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 932 return (EINVAL); 933 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 934 if (vm86->vm86_inited == 0) 935 return (EINVAL); 936 937 /* go back to user mode if both flags are set */ 938 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 939 trapsignal(lp, SIGBUS, 0); 940 941 if (vm86->vm86_has_vme) { 942 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 943 (eflags & VME_USERCHANGE) | PSL_VM; 944 } else { 945 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 946 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 947 (eflags & VM_USERCHANGE) | PSL_VM; 948 } 949 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 950 tf->tf_eflags = eflags; 951 tf->tf_vm86_ds = tf->tf_ds; 952 tf->tf_vm86_es = tf->tf_es; 953 tf->tf_vm86_fs = tf->tf_fs; 954 tf->tf_vm86_gs = tf->tf_gs; 955 tf->tf_ds = _udatasel; 956 tf->tf_es = _udatasel; 957 tf->tf_fs = _udatasel; 958 tf->tf_gs = _udatasel; 959 } else 960 #endif 961 { 962 /* 963 * Don't allow users to change privileged or reserved flags. 964 */ 965 /* 966 * XXX do allow users to change the privileged flag PSL_RF. 967 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 968 * should sometimes set it there too. tf_eflags is kept in 969 * the signal context during signal handling and there is no 970 * other place to remember it, so the PSL_RF bit may be 971 * corrupted by the signal handler without us knowing. 972 * Corruption of the PSL_RF bit at worst causes one more or 973 * one less debugger trap, so allowing it is fairly harmless. 974 */ 975 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 976 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 977 return(EINVAL); 978 } 979 980 /* 981 * Don't allow users to load a valid privileged %cs. Let the 982 * hardware check for invalid selectors, excess privilege in 983 * other selectors, invalid %eip's and invalid %esp's. 984 */ 985 cs = ucp->uc_mcontext.mc_cs; 986 if (!CS_SECURE(cs)) { 987 kprintf("sigreturn: cs = 0x%x\n", cs); 988 trapsignal(lp, SIGBUS, T_PROTFLT); 989 return(EINVAL); 990 } 991 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 992 } 993 994 /* 995 * Restore the FPU state from the frame 996 */ 997 crit_enter(); 998 npxpop(&ucp->uc_mcontext); 999 1000 if (ucp->uc_mcontext.mc_onstack & 1) 1001 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1002 else 1003 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1004 1005 lp->lwp_sigmask = ucp->uc_sigmask; 1006 SIG_CANTMASK(lp->lwp_sigmask); 1007 clear_quickret(); 1008 crit_exit(); 1009 return(EJUSTRETURN); 1010 } 1011 1012 /* 1013 * Machine dependent boot() routine 1014 * 1015 * I haven't seen anything to put here yet 1016 * Possibly some stuff might be grafted back here from boot() 1017 */ 1018 void 1019 cpu_boot(int howto) 1020 { 1021 } 1022 1023 /* 1024 * Shutdown the CPU as much as possible 1025 */ 1026 void 1027 cpu_halt(void) 1028 { 1029 for (;;) 1030 __asm__ __volatile("hlt"); 1031 } 1032 1033 /* 1034 * cpu_idle() represents the idle LWKT. You cannot return from this function 1035 * (unless you want to blow things up!). Instead we look for runnable threads 1036 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1037 * 1038 * The main loop is entered with a critical section held, we must release 1039 * the critical section before doing anything else. lwkt_switch() will 1040 * check for pending interrupts due to entering and exiting its own 1041 * critical section. 1042 * 1043 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1044 * However, there are cases where the idlethread will be entered with 1045 * the possibility that no IPI will occur and in such cases 1046 * lwkt_switch() sets TDF_IDLE_NOHLT. 1047 * 1048 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1049 * must occur before it starts using ACPI halt. 1050 * 1051 * NOTE: Value overridden in hammer_time(). 1052 */ 1053 static int cpu_idle_hlt = 2; 1054 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1055 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1056 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1057 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1058 1059 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1060 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1061 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1062 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1063 1064 static void 1065 cpu_idle_default_hook(void) 1066 { 1067 /* 1068 * We must guarentee that hlt is exactly the instruction 1069 * following the sti. 1070 */ 1071 __asm __volatile("sti; hlt"); 1072 } 1073 1074 /* Other subsystems (e.g., ACPI) can hook this later. */ 1075 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1076 1077 static __inline int 1078 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1079 { 1080 int hint, cx_idx; 1081 u_int idx; 1082 1083 if (cpu_mwait_halt >= 0) { 1084 hint = cpu_mwait_halt; 1085 goto done; 1086 } 1087 1088 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1089 cpu_mwait_repeat_shift; 1090 if (idx >= cpu_mwait_c1_hints_cnt) { 1091 /* Step up faster, once we walked through all C1 states */ 1092 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1093 } 1094 if (cpu_mwait_halt == CPU_MWAIT_HINT_AUTODEEP) { 1095 if (idx >= cpu_mwait_deep_hints_cnt) 1096 idx = cpu_mwait_deep_hints_cnt - 1; 1097 hint = cpu_mwait_deep_hints[idx]; 1098 } else { 1099 if (idx >= cpu_mwait_hints_cnt) 1100 idx = cpu_mwait_hints_cnt - 1; 1101 hint = cpu_mwait_hints[idx]; 1102 } 1103 done: 1104 cx_idx = MWAIT_EAX_TO_CX(hint); 1105 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1106 stat->mwait_cx[cx_idx]++; 1107 return hint; 1108 } 1109 1110 void 1111 cpu_idle(void) 1112 { 1113 globaldata_t gd = mycpu; 1114 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1115 struct thread *td __debugvar = gd->gd_curthread; 1116 int reqflags; 1117 int quick; 1118 1119 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1120 1121 crit_exit(); 1122 KKASSERT(td->td_critcount == 0); 1123 1124 for (;;) { 1125 /* 1126 * See if there are any LWKTs ready to go. 1127 */ 1128 lwkt_switch(); 1129 1130 /* 1131 * When halting inside a cli we must check for reqflags 1132 * races, particularly [re]schedule requests. Running 1133 * splz() does the job. 1134 * 1135 * cpu_idle_hlt: 1136 * 0 Never halt, just spin 1137 * 1138 * 1 Always use HLT (or MONITOR/MWAIT if avail). 1139 * 1140 * Better default for modern (Haswell+) Intel 1141 * cpus. 1142 * 1143 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1144 * use the ACPI halt (default). This is a hybrid 1145 * approach. See machdep.cpu_idle_repeat. 1146 * 1147 * Better default for modern AMD cpus and older 1148 * Intel cpus. 1149 * 1150 * 3 Always use the ACPI halt. This typically 1151 * eats the least amount of power but the cpu 1152 * will be slow waking up. Slows down e.g. 1153 * compiles and other pipe/event oriented stuff. 1154 * 1155 * 4 Always use HLT. 1156 * 1157 * NOTE: Interrupts are enabled and we are not in a critical 1158 * section. 1159 * 1160 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1161 * don't bother capping gd_idle_repeat, it is ok if 1162 * it overflows. 1163 */ 1164 if (gd->gd_idle_repeat == 0) { 1165 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1166 if (stat->repeat > cpu_idle_repeat_max) 1167 stat->repeat = cpu_idle_repeat_max; 1168 stat->repeat_last = 0; 1169 stat->repeat_delta = 0; 1170 } 1171 ++stat->repeat_last; 1172 1173 ++gd->gd_idle_repeat; 1174 reqflags = gd->gd_reqflags; 1175 quick = (cpu_idle_hlt == 1) || 1176 (cpu_idle_hlt < 3 && 1177 gd->gd_idle_repeat < cpu_idle_repeat); 1178 1179 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1180 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1181 splz(); /* XXX */ 1182 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1183 cpu_mwait_cx_hint(stat), 0); 1184 stat->halt++; 1185 } else if (cpu_idle_hlt) { 1186 __asm __volatile("cli"); 1187 splz(); 1188 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1189 if (quick) 1190 cpu_idle_default_hook(); 1191 else 1192 cpu_idle_hook(); 1193 } 1194 __asm __volatile("sti"); 1195 stat->halt++; 1196 } else { 1197 splz(); 1198 __asm __volatile("sti"); 1199 stat->spin++; 1200 } 1201 } 1202 } 1203 1204 /* 1205 * This routine is called if a spinlock has been held through the 1206 * exponential backoff period and is seriously contested. On a real cpu 1207 * we let it spin. 1208 */ 1209 void 1210 cpu_spinlock_contested(void) 1211 { 1212 cpu_pause(); 1213 } 1214 1215 /* 1216 * Clear registers on exec 1217 */ 1218 void 1219 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1220 { 1221 struct thread *td = curthread; 1222 struct lwp *lp = td->td_lwp; 1223 struct pcb *pcb = td->td_pcb; 1224 struct trapframe *regs = lp->lwp_md.md_regs; 1225 1226 /* was i386_user_cleanup() in NetBSD */ 1227 user_ldt_free(pcb); 1228 1229 clear_quickret(); 1230 bzero((char *)regs, sizeof(struct trapframe)); 1231 regs->tf_rip = entry; 1232 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1233 regs->tf_rdi = stack; /* argv */ 1234 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1235 regs->tf_ss = _udatasel; 1236 regs->tf_cs = _ucodesel; 1237 regs->tf_rbx = ps_strings; 1238 1239 /* 1240 * Reset the hardware debug registers if they were in use. 1241 * They won't have any meaning for the newly exec'd process. 1242 */ 1243 if (pcb->pcb_flags & PCB_DBREGS) { 1244 pcb->pcb_dr0 = 0; 1245 pcb->pcb_dr1 = 0; 1246 pcb->pcb_dr2 = 0; 1247 pcb->pcb_dr3 = 0; 1248 pcb->pcb_dr6 = 0; 1249 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1250 if (pcb == td->td_pcb) { 1251 /* 1252 * Clear the debug registers on the running 1253 * CPU, otherwise they will end up affecting 1254 * the next process we switch to. 1255 */ 1256 reset_dbregs(); 1257 } 1258 pcb->pcb_flags &= ~PCB_DBREGS; 1259 } 1260 1261 /* 1262 * Initialize the math emulator (if any) for the current process. 1263 * Actually, just clear the bit that says that the emulator has 1264 * been initialized. Initialization is delayed until the process 1265 * traps to the emulator (if it is done at all) mainly because 1266 * emulators don't provide an entry point for initialization. 1267 */ 1268 pcb->pcb_flags &= ~FP_SOFTFP; 1269 1270 /* 1271 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1272 * gd_npxthread. Otherwise a preemptive interrupt thread 1273 * may panic in npxdna(). 1274 */ 1275 crit_enter(); 1276 load_cr0(rcr0() | CR0_MP); 1277 1278 /* 1279 * NOTE: The MSR values must be correct so we can return to 1280 * userland. gd_user_fs/gs must be correct so the switch 1281 * code knows what the current MSR values are. 1282 */ 1283 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1284 pcb->pcb_gsbase = 0; 1285 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1286 mdcpu->gd_user_gs = 0; 1287 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1288 wrmsr(MSR_KGSBASE, 0); 1289 1290 /* Initialize the npx (if any) for the current process. */ 1291 npxinit(); 1292 crit_exit(); 1293 1294 pcb->pcb_ds = _udatasel; 1295 pcb->pcb_es = _udatasel; 1296 pcb->pcb_fs = _udatasel; 1297 pcb->pcb_gs = _udatasel; 1298 } 1299 1300 void 1301 cpu_setregs(void) 1302 { 1303 register_t cr0; 1304 1305 cr0 = rcr0(); 1306 cr0 |= CR0_NE; /* Done by npxinit() */ 1307 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1308 cr0 |= CR0_WP | CR0_AM; 1309 load_cr0(cr0); 1310 load_gs(_udatasel); 1311 } 1312 1313 static int 1314 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1315 { 1316 int error; 1317 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1318 req); 1319 if (!error && req->newptr) 1320 resettodr(); 1321 return (error); 1322 } 1323 1324 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1325 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1326 1327 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1328 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1329 1330 #if 0 /* JG */ 1331 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1332 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1333 #endif 1334 1335 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1336 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1337 1338 extern u_long bootdev; /* not a cdev_t - encoding is different */ 1339 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 1340 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)"); 1341 1342 /* 1343 * Initialize 386 and configure to run kernel 1344 */ 1345 1346 /* 1347 * Initialize segments & interrupt table 1348 */ 1349 1350 int _default_ldt; 1351 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1352 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1353 #if 0 /* JG */ 1354 union descriptor ldt[NLDT]; /* local descriptor table */ 1355 #endif 1356 1357 /* table descriptors - used to load tables by cpu */ 1358 struct region_descriptor r_gdt; 1359 struct region_descriptor r_idt_arr[MAXCPU]; 1360 1361 /* JG proc0paddr is a virtual address */ 1362 void *proc0paddr; 1363 /* JG alignment? */ 1364 char proc0paddr_buff[LWKT_THREAD_STACK]; 1365 1366 1367 /* software prototypes -- in more palatable form */ 1368 struct soft_segment_descriptor gdt_segs[] = { 1369 /* GNULL_SEL 0 Null Descriptor */ 1370 { 0x0, /* segment base address */ 1371 0x0, /* length */ 1372 0, /* segment type */ 1373 0, /* segment descriptor priority level */ 1374 0, /* segment descriptor present */ 1375 0, /* long */ 1376 0, /* default 32 vs 16 bit size */ 1377 0 /* limit granularity (byte/page units)*/ }, 1378 /* GCODE_SEL 1 Code Descriptor for kernel */ 1379 { 0x0, /* segment base address */ 1380 0xfffff, /* length - all address space */ 1381 SDT_MEMERA, /* segment type */ 1382 SEL_KPL, /* segment descriptor priority level */ 1383 1, /* segment descriptor present */ 1384 1, /* long */ 1385 0, /* default 32 vs 16 bit size */ 1386 1 /* limit granularity (byte/page units)*/ }, 1387 /* GDATA_SEL 2 Data Descriptor for kernel */ 1388 { 0x0, /* segment base address */ 1389 0xfffff, /* length - all address space */ 1390 SDT_MEMRWA, /* segment type */ 1391 SEL_KPL, /* segment descriptor priority level */ 1392 1, /* segment descriptor present */ 1393 1, /* long */ 1394 0, /* default 32 vs 16 bit size */ 1395 1 /* limit granularity (byte/page units)*/ }, 1396 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1397 { 0x0, /* segment base address */ 1398 0xfffff, /* length - all address space */ 1399 SDT_MEMERA, /* segment type */ 1400 SEL_UPL, /* segment descriptor priority level */ 1401 1, /* segment descriptor present */ 1402 0, /* long */ 1403 1, /* default 32 vs 16 bit size */ 1404 1 /* limit granularity (byte/page units)*/ }, 1405 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1406 { 0x0, /* segment base address */ 1407 0xfffff, /* length - all address space */ 1408 SDT_MEMRWA, /* segment type */ 1409 SEL_UPL, /* segment descriptor priority level */ 1410 1, /* segment descriptor present */ 1411 0, /* long */ 1412 1, /* default 32 vs 16 bit size */ 1413 1 /* limit granularity (byte/page units)*/ }, 1414 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1415 { 0x0, /* segment base address */ 1416 0xfffff, /* length - all address space */ 1417 SDT_MEMERA, /* segment type */ 1418 SEL_UPL, /* segment descriptor priority level */ 1419 1, /* segment descriptor present */ 1420 1, /* long */ 1421 0, /* default 32 vs 16 bit size */ 1422 1 /* limit granularity (byte/page units)*/ }, 1423 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1424 { 1425 0x0, /* segment base address */ 1426 sizeof(struct x86_64tss)-1,/* length - all address space */ 1427 SDT_SYSTSS, /* segment type */ 1428 SEL_KPL, /* segment descriptor priority level */ 1429 1, /* segment descriptor present */ 1430 0, /* long */ 1431 0, /* unused - default 32 vs 16 bit size */ 1432 0 /* limit granularity (byte/page units)*/ }, 1433 /* Actually, the TSS is a system descriptor which is double size */ 1434 { 0x0, /* segment base address */ 1435 0x0, /* length */ 1436 0, /* segment type */ 1437 0, /* segment descriptor priority level */ 1438 0, /* segment descriptor present */ 1439 0, /* long */ 1440 0, /* default 32 vs 16 bit size */ 1441 0 /* limit granularity (byte/page units)*/ }, 1442 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1443 { 0x0, /* segment base address */ 1444 0xfffff, /* length - all address space */ 1445 SDT_MEMRWA, /* segment type */ 1446 SEL_UPL, /* segment descriptor priority level */ 1447 1, /* segment descriptor present */ 1448 0, /* long */ 1449 1, /* default 32 vs 16 bit size */ 1450 1 /* limit granularity (byte/page units)*/ }, 1451 }; 1452 1453 void 1454 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1455 { 1456 int cpu; 1457 1458 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1459 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1460 1461 ip->gd_looffset = (uintptr_t)func; 1462 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1463 ip->gd_ist = ist; 1464 ip->gd_xx = 0; 1465 ip->gd_type = typ; 1466 ip->gd_dpl = dpl; 1467 ip->gd_p = 1; 1468 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1469 } 1470 } 1471 1472 void 1473 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1474 { 1475 struct gate_descriptor *ip; 1476 1477 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1478 1479 ip = &idt_arr[cpu][idx]; 1480 ip->gd_looffset = (uintptr_t)func; 1481 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1482 ip->gd_ist = ist; 1483 ip->gd_xx = 0; 1484 ip->gd_type = typ; 1485 ip->gd_dpl = dpl; 1486 ip->gd_p = 1; 1487 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1488 } 1489 1490 #define IDTVEC(name) __CONCAT(X,name) 1491 1492 extern inthand_t 1493 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1494 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1495 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1496 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1497 IDTVEC(xmm), IDTVEC(dblfault), 1498 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1499 1500 #ifdef DEBUG_INTERRUPTS 1501 extern inthand_t *Xrsvdary[256]; 1502 #endif 1503 1504 void 1505 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1506 { 1507 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1508 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1509 ssd->ssd_type = sd->sd_type; 1510 ssd->ssd_dpl = sd->sd_dpl; 1511 ssd->ssd_p = sd->sd_p; 1512 ssd->ssd_def32 = sd->sd_def32; 1513 ssd->ssd_gran = sd->sd_gran; 1514 } 1515 1516 void 1517 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1518 { 1519 1520 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1521 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1522 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1523 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1524 sd->sd_type = ssd->ssd_type; 1525 sd->sd_dpl = ssd->ssd_dpl; 1526 sd->sd_p = ssd->ssd_p; 1527 sd->sd_long = ssd->ssd_long; 1528 sd->sd_def32 = ssd->ssd_def32; 1529 sd->sd_gran = ssd->ssd_gran; 1530 } 1531 1532 void 1533 ssdtosyssd(struct soft_segment_descriptor *ssd, 1534 struct system_segment_descriptor *sd) 1535 { 1536 1537 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1538 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1539 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1540 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1541 sd->sd_type = ssd->ssd_type; 1542 sd->sd_dpl = ssd->ssd_dpl; 1543 sd->sd_p = ssd->ssd_p; 1544 sd->sd_gran = ssd->ssd_gran; 1545 } 1546 1547 /* 1548 * Populate the (physmap) array with base/bound pairs describing the 1549 * available physical memory in the system, then test this memory and 1550 * build the phys_avail array describing the actually-available memory. 1551 * 1552 * If we cannot accurately determine the physical memory map, then use 1553 * value from the 0xE801 call, and failing that, the RTC. 1554 * 1555 * Total memory size may be set by the kernel environment variable 1556 * hw.physmem or the compile-time define MAXMEM. 1557 * 1558 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1559 * of PAGE_SIZE. This also greatly reduces the memory test time 1560 * which would otherwise be excessive on machines with > 8G of ram. 1561 * 1562 * XXX first should be vm_paddr_t. 1563 */ 1564 1565 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1566 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1567 vm_paddr_t physmap[PHYSMAP_SIZE]; 1568 struct bios_smap *smapbase, *smap, *smapend; 1569 u_int32_t smapsize; 1570 1571 static void 1572 getmemsize(caddr_t kmdp, u_int64_t first) 1573 { 1574 int off, physmap_idx, pa_indx, da_indx; 1575 int i, j; 1576 vm_paddr_t pa; 1577 vm_paddr_t msgbuf_size; 1578 u_long physmem_tunable; 1579 pt_entry_t *pte; 1580 quad_t dcons_addr, dcons_size; 1581 1582 bzero(physmap, sizeof(physmap)); 1583 physmap_idx = 0; 1584 1585 /* 1586 * get memory map from INT 15:E820, kindly supplied by the loader. 1587 * 1588 * subr_module.c says: 1589 * "Consumer may safely assume that size value precedes data." 1590 * ie: an int32_t immediately precedes smap. 1591 */ 1592 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1593 MODINFO_METADATA | MODINFOMD_SMAP); 1594 if (smapbase == NULL) 1595 panic("No BIOS smap info from loader!"); 1596 1597 smapsize = *((u_int32_t *)smapbase - 1); 1598 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1599 1600 for (smap = smapbase; smap < smapend; smap++) { 1601 if (boothowto & RB_VERBOSE) 1602 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1603 smap->type, smap->base, smap->length); 1604 1605 if (smap->type != SMAP_TYPE_MEMORY) 1606 continue; 1607 1608 if (smap->length == 0) 1609 continue; 1610 1611 for (i = 0; i <= physmap_idx; i += 2) { 1612 if (smap->base < physmap[i + 1]) { 1613 if (boothowto & RB_VERBOSE) { 1614 kprintf("Overlapping or non-monotonic " 1615 "memory region, ignoring " 1616 "second region\n"); 1617 } 1618 break; 1619 } 1620 } 1621 if (i <= physmap_idx) 1622 continue; 1623 1624 Realmem += smap->length; 1625 1626 if (smap->base == physmap[physmap_idx + 1]) { 1627 physmap[physmap_idx + 1] += smap->length; 1628 continue; 1629 } 1630 1631 physmap_idx += 2; 1632 if (physmap_idx == PHYSMAP_SIZE) { 1633 kprintf("Too many segments in the physical " 1634 "address map, giving up\n"); 1635 break; 1636 } 1637 physmap[physmap_idx] = smap->base; 1638 physmap[physmap_idx + 1] = smap->base + smap->length; 1639 } 1640 1641 base_memory = physmap[1] / 1024; 1642 /* make hole for AP bootstrap code */ 1643 physmap[1] = mp_bootaddress(base_memory); 1644 1645 /* Save EBDA address, if any */ 1646 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1647 ebda_addr <<= 4; 1648 1649 /* 1650 * Maxmem isn't the "maximum memory", it's one larger than the 1651 * highest page of the physical address space. It should be 1652 * called something like "Maxphyspage". We may adjust this 1653 * based on ``hw.physmem'' and the results of the memory test. 1654 */ 1655 Maxmem = atop(physmap[physmap_idx + 1]); 1656 1657 #ifdef MAXMEM 1658 Maxmem = MAXMEM / 4; 1659 #endif 1660 1661 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1662 Maxmem = atop(physmem_tunable); 1663 1664 /* 1665 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1666 * in the system. 1667 */ 1668 if (Maxmem > atop(physmap[physmap_idx + 1])) 1669 Maxmem = atop(physmap[physmap_idx + 1]); 1670 1671 /* 1672 * Blowing out the DMAP will blow up the system. 1673 */ 1674 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1675 kprintf("Limiting Maxmem due to DMAP size\n"); 1676 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1677 } 1678 1679 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1680 (boothowto & RB_VERBOSE)) { 1681 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1682 } 1683 1684 /* 1685 * Call pmap initialization to make new kernel address space 1686 * 1687 * Mask off page 0. 1688 */ 1689 pmap_bootstrap(&first); 1690 physmap[0] = PAGE_SIZE; 1691 1692 /* 1693 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1694 * exceeding Maxmem. 1695 */ 1696 for (i = j = 0; i <= physmap_idx; i += 2) { 1697 if (physmap[i+1] > ptoa(Maxmem)) 1698 physmap[i+1] = ptoa(Maxmem); 1699 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1700 ~PHYSMAP_ALIGN_MASK; 1701 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1702 1703 physmap[j] = physmap[i]; 1704 physmap[j+1] = physmap[i+1]; 1705 1706 if (physmap[i] < physmap[i+1]) 1707 j += 2; 1708 } 1709 physmap_idx = j - 2; 1710 1711 /* 1712 * Align anything else used in the validation loop. 1713 */ 1714 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1715 1716 /* 1717 * Size up each available chunk of physical memory. 1718 */ 1719 pa_indx = 0; 1720 da_indx = 1; 1721 phys_avail[pa_indx++] = physmap[0]; 1722 phys_avail[pa_indx] = physmap[0]; 1723 dump_avail[da_indx] = physmap[0]; 1724 pte = CMAP1; 1725 1726 /* 1727 * Get dcons buffer address 1728 */ 1729 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 1730 kgetenv_quad("dcons.size", &dcons_size) == 0) 1731 dcons_addr = 0; 1732 1733 /* 1734 * Validate the physical memory. The physical memory segments 1735 * have already been aligned to PHYSMAP_ALIGN which is a multiple 1736 * of PAGE_SIZE. 1737 */ 1738 for (i = 0; i <= physmap_idx; i += 2) { 1739 vm_paddr_t end; 1740 1741 end = physmap[i + 1]; 1742 1743 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) { 1744 int tmp, page_bad, full; 1745 int *ptr = (int *)CADDR1; 1746 1747 full = FALSE; 1748 /* 1749 * block out kernel memory as not available. 1750 */ 1751 if (pa >= 0x200000 && pa < first) 1752 goto do_dump_avail; 1753 1754 /* 1755 * block out dcons buffer 1756 */ 1757 if (dcons_addr > 0 1758 && pa >= trunc_page(dcons_addr) 1759 && pa < dcons_addr + dcons_size) { 1760 goto do_dump_avail; 1761 } 1762 1763 page_bad = FALSE; 1764 1765 /* 1766 * map page into kernel: valid, read/write,non-cacheable 1767 */ 1768 *pte = pa | 1769 kernel_pmap.pmap_bits[PG_V_IDX] | 1770 kernel_pmap.pmap_bits[PG_RW_IDX] | 1771 kernel_pmap.pmap_bits[PG_N_IDX]; 1772 cpu_invltlb(); 1773 1774 tmp = *ptr; 1775 /* 1776 * Test for alternating 1's and 0's 1777 */ 1778 *(volatile int *)ptr = 0xaaaaaaaa; 1779 cpu_mfence(); 1780 if (*(volatile int *)ptr != 0xaaaaaaaa) 1781 page_bad = TRUE; 1782 /* 1783 * Test for alternating 0's and 1's 1784 */ 1785 *(volatile int *)ptr = 0x55555555; 1786 cpu_mfence(); 1787 if (*(volatile int *)ptr != 0x55555555) 1788 page_bad = TRUE; 1789 /* 1790 * Test for all 1's 1791 */ 1792 *(volatile int *)ptr = 0xffffffff; 1793 cpu_mfence(); 1794 if (*(volatile int *)ptr != 0xffffffff) 1795 page_bad = TRUE; 1796 /* 1797 * Test for all 0's 1798 */ 1799 *(volatile int *)ptr = 0x0; 1800 cpu_mfence(); 1801 if (*(volatile int *)ptr != 0x0) 1802 page_bad = TRUE; 1803 /* 1804 * Restore original value. 1805 */ 1806 *ptr = tmp; 1807 1808 /* 1809 * Adjust array of valid/good pages. 1810 */ 1811 if (page_bad == TRUE) 1812 continue; 1813 /* 1814 * If this good page is a continuation of the 1815 * previous set of good pages, then just increase 1816 * the end pointer. Otherwise start a new chunk. 1817 * Note that "end" points one higher than end, 1818 * making the range >= start and < end. 1819 * If we're also doing a speculative memory 1820 * test and we at or past the end, bump up Maxmem 1821 * so that we keep going. The first bad page 1822 * will terminate the loop. 1823 */ 1824 if (phys_avail[pa_indx] == pa) { 1825 phys_avail[pa_indx] += PHYSMAP_ALIGN; 1826 } else { 1827 pa_indx++; 1828 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1829 kprintf( 1830 "Too many holes in the physical address space, giving up\n"); 1831 pa_indx--; 1832 full = TRUE; 1833 goto do_dump_avail; 1834 } 1835 phys_avail[pa_indx++] = pa; 1836 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN; 1837 } 1838 physmem += PHYSMAP_ALIGN / PAGE_SIZE; 1839 do_dump_avail: 1840 if (dump_avail[da_indx] == pa) { 1841 dump_avail[da_indx] += PHYSMAP_ALIGN; 1842 } else { 1843 da_indx++; 1844 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1845 da_indx--; 1846 goto do_next; 1847 } 1848 dump_avail[da_indx++] = pa; 1849 dump_avail[da_indx] = pa + PHYSMAP_ALIGN; 1850 } 1851 do_next: 1852 if (full) 1853 break; 1854 } 1855 } 1856 *pte = 0; 1857 cpu_invltlb(); 1858 1859 /* 1860 * The last chunk must contain at least one page plus the message 1861 * buffer to avoid complicating other code (message buffer address 1862 * calculation, etc.). 1863 */ 1864 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1865 1866 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN + 1867 msgbuf_size >= phys_avail[pa_indx]) { 1868 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1869 phys_avail[pa_indx--] = 0; 1870 phys_avail[pa_indx--] = 0; 1871 } 1872 1873 Maxmem = atop(phys_avail[pa_indx]); 1874 1875 /* Trim off space for the message buffer. */ 1876 phys_avail[pa_indx] -= msgbuf_size; 1877 1878 avail_end = phys_avail[pa_indx]; 1879 1880 /* Map the message buffer. */ 1881 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 1882 pmap_kenter((vm_offset_t)msgbufp + off, 1883 phys_avail[pa_indx] + off); 1884 } 1885 } 1886 1887 struct machintr_abi MachIntrABI; 1888 1889 /* 1890 * IDT VECTORS: 1891 * 0 Divide by zero 1892 * 1 Debug 1893 * 2 NMI 1894 * 3 BreakPoint 1895 * 4 OverFlow 1896 * 5 Bound-Range 1897 * 6 Invalid OpCode 1898 * 7 Device Not Available (x87) 1899 * 8 Double-Fault 1900 * 9 Coprocessor Segment overrun (unsupported, reserved) 1901 * 10 Invalid-TSS 1902 * 11 Segment not present 1903 * 12 Stack 1904 * 13 General Protection 1905 * 14 Page Fault 1906 * 15 Reserved 1907 * 16 x87 FP Exception pending 1908 * 17 Alignment Check 1909 * 18 Machine Check 1910 * 19 SIMD floating point 1911 * 20-31 reserved 1912 * 32-255 INTn/external sources 1913 */ 1914 u_int64_t 1915 hammer_time(u_int64_t modulep, u_int64_t physfree) 1916 { 1917 caddr_t kmdp; 1918 int gsel_tss, x, cpu; 1919 #if 0 /* JG */ 1920 int metadata_missing, off; 1921 #endif 1922 struct mdglobaldata *gd; 1923 u_int64_t msr; 1924 1925 /* 1926 * Prevent lowering of the ipl if we call tsleep() early. 1927 */ 1928 gd = &CPU_prvspace[0]->mdglobaldata; 1929 bzero(gd, sizeof(*gd)); 1930 1931 /* 1932 * Note: on both UP and SMP curthread must be set non-NULL 1933 * early in the boot sequence because the system assumes 1934 * that 'curthread' is never NULL. 1935 */ 1936 1937 gd->mi.gd_curthread = &thread0; 1938 thread0.td_gd = &gd->mi; 1939 1940 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 1941 1942 #if 0 /* JG */ 1943 metadata_missing = 0; 1944 if (bootinfo.bi_modulep) { 1945 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 1946 preload_bootstrap_relocate(KERNBASE); 1947 } else { 1948 metadata_missing = 1; 1949 } 1950 if (bootinfo.bi_envp) 1951 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 1952 #endif 1953 1954 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 1955 preload_bootstrap_relocate(PTOV_OFFSET); 1956 kmdp = preload_search_by_type("elf kernel"); 1957 if (kmdp == NULL) 1958 kmdp = preload_search_by_type("elf64 kernel"); 1959 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1960 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 1961 #ifdef DDB 1962 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1963 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1964 #endif 1965 1966 if (boothowto & RB_VERBOSE) 1967 bootverbose++; 1968 1969 /* 1970 * Default MachIntrABI to ICU 1971 */ 1972 MachIntrABI = MachIntrABI_ICU; 1973 1974 /* 1975 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask, 1976 * and ncpus_fit_mask remain 0. 1977 */ 1978 ncpus = 1; 1979 ncpus2 = 1; 1980 ncpus_fit = 1; 1981 /* Init basic tunables, hz etc */ 1982 init_param1(); 1983 1984 /* 1985 * make gdt memory segments 1986 */ 1987 gdt_segs[GPROC0_SEL].ssd_base = 1988 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss; 1989 1990 gd->mi.gd_prvspace = CPU_prvspace[0]; 1991 1992 for (x = 0; x < NGDT; x++) { 1993 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 1994 ssdtosd(&gdt_segs[x], &gdt[x]); 1995 } 1996 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1997 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1998 1999 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2000 r_gdt.rd_base = (long) gdt; 2001 lgdt(&r_gdt); 2002 2003 wrmsr(MSR_FSBASE, 0); /* User value */ 2004 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2005 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2006 2007 mi_gdinit(&gd->mi, 0); 2008 cpu_gdinit(gd, 0); 2009 proc0paddr = proc0paddr_buff; 2010 mi_proc0init(&gd->mi, proc0paddr); 2011 safepri = TDPRI_MAX; 2012 2013 /* spinlocks and the BGL */ 2014 init_locks(); 2015 2016 /* exceptions */ 2017 for (x = 0; x < NIDT; x++) 2018 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2019 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2020 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2021 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2022 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2023 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2024 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2025 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2026 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2027 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2028 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2029 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2030 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2031 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2032 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2033 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2034 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2035 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2036 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2037 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2038 2039 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2040 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2041 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2042 } 2043 2044 lidt(&r_idt_arr[0]); 2045 2046 /* 2047 * Initialize the console before we print anything out. 2048 */ 2049 cninit(); 2050 2051 #if 0 /* JG */ 2052 if (metadata_missing) 2053 kprintf("WARNING: loader(8) metadata is missing!\n"); 2054 #endif 2055 2056 #if NISA >0 2057 elcr_probe(); 2058 isa_defaultirq(); 2059 #endif 2060 rand_initialize(); 2061 2062 /* 2063 * Initialize IRQ mapping 2064 * 2065 * NOTE: 2066 * SHOULD be after elcr_probe() 2067 */ 2068 MachIntrABI_ICU.initmap(); 2069 MachIntrABI_IOAPIC.initmap(); 2070 2071 #ifdef DDB 2072 kdb_init(); 2073 if (boothowto & RB_KDB) 2074 Debugger("Boot flags requested debugger"); 2075 #endif 2076 2077 #if 0 /* JG */ 2078 finishidentcpu(); /* Final stage of CPU initialization */ 2079 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2080 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2081 #endif 2082 identify_cpu(); /* Final stage of CPU initialization */ 2083 initializecpu(0); /* Initialize CPU registers */ 2084 2085 /* 2086 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better 2087 * becaue the cpu does significant power management in HLT 2088 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2089 * 2090 * On modern amd cpus or on any older amd or intel cpu, 2091 * cpu_idle_hlt=2 is better because ACPI is needed to reduce power 2092 * consumption. 2093 */ 2094 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2095 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2096 cpu_idle_hlt = 1; 2097 } 2098 2099 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2100 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2101 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2102 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2103 2104 /* 2105 * Some of the virtual machines do not work w/ I/O APIC 2106 * enabled. If the user does not explicitly enable or 2107 * disable the I/O APIC (ioapic_enable < 0), then we 2108 * disable I/O APIC on all virtual machines. 2109 * 2110 * NOTE: 2111 * This must be done after identify_cpu(), which sets 2112 * 'cpu_feature2' 2113 */ 2114 if (ioapic_enable < 0) { 2115 if (cpu_feature2 & CPUID2_VMM) 2116 ioapic_enable = 0; 2117 else 2118 ioapic_enable = 1; 2119 } 2120 2121 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2122 gd->gd_common_tss.tss_rsp0 = 2123 (register_t)(thread0.td_kstack + 2124 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 2125 /* Ensure the stack is aligned to 16 bytes */ 2126 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 2127 2128 /* double fault stack */ 2129 gd->gd_common_tss.tss_ist1 = 2130 (long)&gd->mi.gd_prvspace->idlestack[ 2131 sizeof(gd->mi.gd_prvspace->idlestack)]; 2132 2133 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2134 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 2135 2136 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2137 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2138 gd->gd_common_tssd = *gd->gd_tss_gdt; 2139 ltr(gsel_tss); 2140 2141 /* Set up the fast syscall stuff */ 2142 msr = rdmsr(MSR_EFER) | EFER_SCE; 2143 wrmsr(MSR_EFER, msr); 2144 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2145 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2146 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2147 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2148 wrmsr(MSR_STAR, msr); 2149 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2150 2151 getmemsize(kmdp, physfree); 2152 init_param2(physmem); 2153 2154 /* now running on new page tables, configured,and u/iom is accessible */ 2155 2156 /* Map the message buffer. */ 2157 #if 0 /* JG */ 2158 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2159 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2160 #endif 2161 2162 msgbufinit(msgbufp, MSGBUF_SIZE); 2163 2164 2165 /* transfer to user mode */ 2166 2167 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2168 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2169 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2170 2171 load_ds(_udatasel); 2172 load_es(_udatasel); 2173 load_fs(_udatasel); 2174 2175 /* setup proc 0's pcb */ 2176 thread0.td_pcb->pcb_flags = 0; 2177 thread0.td_pcb->pcb_cr3 = KPML4phys; 2178 thread0.td_pcb->pcb_ext = NULL; 2179 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2180 2181 /* Location of kernel stack for locore */ 2182 return ((u_int64_t)thread0.td_pcb); 2183 } 2184 2185 /* 2186 * Initialize machine-dependant portions of the global data structure. 2187 * Note that the global data area and cpu0's idlestack in the private 2188 * data space were allocated in locore. 2189 * 2190 * Note: the idlethread's cpl is 0 2191 * 2192 * WARNING! Called from early boot, 'mycpu' may not work yet. 2193 */ 2194 void 2195 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2196 { 2197 if (cpu) 2198 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2199 2200 lwkt_init_thread(&gd->mi.gd_idlethread, 2201 gd->mi.gd_prvspace->idlestack, 2202 sizeof(gd->mi.gd_prvspace->idlestack), 2203 0, &gd->mi); 2204 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2205 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2206 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2207 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2208 } 2209 2210 /* 2211 * We only have to check for DMAP bounds, the globaldata space is 2212 * actually part of the kernel_map so we don't have to waste time 2213 * checking CPU_prvspace[*]. 2214 */ 2215 int 2216 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2217 { 2218 #if 0 2219 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2220 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2221 return (TRUE); 2222 } 2223 #endif 2224 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2225 return (TRUE); 2226 return (FALSE); 2227 } 2228 2229 struct globaldata * 2230 globaldata_find(int cpu) 2231 { 2232 KKASSERT(cpu >= 0 && cpu < ncpus); 2233 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2234 } 2235 2236 /* 2237 * This path should be safe from the SYSRET issue because only stopped threads 2238 * can have their %rip adjusted this way (and all heavy weight thread switches 2239 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2240 * convoluted so add a safety by forcing %rip to be cannonical. 2241 */ 2242 int 2243 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2244 { 2245 if (addr & 0x0000800000000000LLU) 2246 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2247 else 2248 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2249 return (0); 2250 } 2251 2252 int 2253 ptrace_single_step(struct lwp *lp) 2254 { 2255 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2256 return (0); 2257 } 2258 2259 int 2260 fill_regs(struct lwp *lp, struct reg *regs) 2261 { 2262 struct trapframe *tp; 2263 2264 if ((tp = lp->lwp_md.md_regs) == NULL) 2265 return EINVAL; 2266 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2267 return (0); 2268 } 2269 2270 int 2271 set_regs(struct lwp *lp, struct reg *regs) 2272 { 2273 struct trapframe *tp; 2274 2275 tp = lp->lwp_md.md_regs; 2276 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2277 !CS_SECURE(regs->r_cs)) 2278 return (EINVAL); 2279 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2280 clear_quickret(); 2281 return (0); 2282 } 2283 2284 static void 2285 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2286 { 2287 struct env87 *penv_87 = &sv_87->sv_env; 2288 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2289 int i; 2290 2291 /* FPU control/status */ 2292 penv_87->en_cw = penv_xmm->en_cw; 2293 penv_87->en_sw = penv_xmm->en_sw; 2294 penv_87->en_tw = penv_xmm->en_tw; 2295 penv_87->en_fip = penv_xmm->en_fip; 2296 penv_87->en_fcs = penv_xmm->en_fcs; 2297 penv_87->en_opcode = penv_xmm->en_opcode; 2298 penv_87->en_foo = penv_xmm->en_foo; 2299 penv_87->en_fos = penv_xmm->en_fos; 2300 2301 /* FPU registers */ 2302 for (i = 0; i < 8; ++i) 2303 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2304 } 2305 2306 static void 2307 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2308 { 2309 struct env87 *penv_87 = &sv_87->sv_env; 2310 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2311 int i; 2312 2313 /* FPU control/status */ 2314 penv_xmm->en_cw = penv_87->en_cw; 2315 penv_xmm->en_sw = penv_87->en_sw; 2316 penv_xmm->en_tw = penv_87->en_tw; 2317 penv_xmm->en_fip = penv_87->en_fip; 2318 penv_xmm->en_fcs = penv_87->en_fcs; 2319 penv_xmm->en_opcode = penv_87->en_opcode; 2320 penv_xmm->en_foo = penv_87->en_foo; 2321 penv_xmm->en_fos = penv_87->en_fos; 2322 2323 /* FPU registers */ 2324 for (i = 0; i < 8; ++i) 2325 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2326 } 2327 2328 int 2329 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2330 { 2331 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2332 return EINVAL; 2333 if (cpu_fxsr) { 2334 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2335 (struct save87 *)fpregs); 2336 return (0); 2337 } 2338 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2339 return (0); 2340 } 2341 2342 int 2343 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2344 { 2345 if (cpu_fxsr) { 2346 set_fpregs_xmm((struct save87 *)fpregs, 2347 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2348 return (0); 2349 } 2350 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2351 return (0); 2352 } 2353 2354 int 2355 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2356 { 2357 struct pcb *pcb; 2358 2359 if (lp == NULL) { 2360 dbregs->dr[0] = rdr0(); 2361 dbregs->dr[1] = rdr1(); 2362 dbregs->dr[2] = rdr2(); 2363 dbregs->dr[3] = rdr3(); 2364 dbregs->dr[4] = rdr4(); 2365 dbregs->dr[5] = rdr5(); 2366 dbregs->dr[6] = rdr6(); 2367 dbregs->dr[7] = rdr7(); 2368 return (0); 2369 } 2370 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2371 return EINVAL; 2372 dbregs->dr[0] = pcb->pcb_dr0; 2373 dbregs->dr[1] = pcb->pcb_dr1; 2374 dbregs->dr[2] = pcb->pcb_dr2; 2375 dbregs->dr[3] = pcb->pcb_dr3; 2376 dbregs->dr[4] = 0; 2377 dbregs->dr[5] = 0; 2378 dbregs->dr[6] = pcb->pcb_dr6; 2379 dbregs->dr[7] = pcb->pcb_dr7; 2380 return (0); 2381 } 2382 2383 int 2384 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2385 { 2386 if (lp == NULL) { 2387 load_dr0(dbregs->dr[0]); 2388 load_dr1(dbregs->dr[1]); 2389 load_dr2(dbregs->dr[2]); 2390 load_dr3(dbregs->dr[3]); 2391 load_dr4(dbregs->dr[4]); 2392 load_dr5(dbregs->dr[5]); 2393 load_dr6(dbregs->dr[6]); 2394 load_dr7(dbregs->dr[7]); 2395 } else { 2396 struct pcb *pcb; 2397 struct ucred *ucred; 2398 int i; 2399 uint64_t mask1, mask2; 2400 2401 /* 2402 * Don't let an illegal value for dr7 get set. Specifically, 2403 * check for undefined settings. Setting these bit patterns 2404 * result in undefined behaviour and can lead to an unexpected 2405 * TRCTRAP. 2406 */ 2407 /* JG this loop looks unreadable */ 2408 /* Check 4 2-bit fields for invalid patterns. 2409 * These fields are R/Wi, for i = 0..3 2410 */ 2411 /* Is 10 in LENi allowed when running in compatibility mode? */ 2412 /* Pattern 10 in R/Wi might be used to indicate 2413 * breakpoint on I/O. Further analysis should be 2414 * carried to decide if it is safe and useful to 2415 * provide access to that capability 2416 */ 2417 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2418 i++, mask1 <<= 4, mask2 <<= 4) 2419 if ((dbregs->dr[7] & mask1) == mask2) 2420 return (EINVAL); 2421 2422 pcb = lp->lwp_thread->td_pcb; 2423 ucred = lp->lwp_proc->p_ucred; 2424 2425 /* 2426 * Don't let a process set a breakpoint that is not within the 2427 * process's address space. If a process could do this, it 2428 * could halt the system by setting a breakpoint in the kernel 2429 * (if ddb was enabled). Thus, we need to check to make sure 2430 * that no breakpoints are being enabled for addresses outside 2431 * process's address space, unless, perhaps, we were called by 2432 * uid 0. 2433 * 2434 * XXX - what about when the watched area of the user's 2435 * address space is written into from within the kernel 2436 * ... wouldn't that still cause a breakpoint to be generated 2437 * from within kernel mode? 2438 */ 2439 2440 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2441 if (dbregs->dr[7] & 0x3) { 2442 /* dr0 is enabled */ 2443 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2444 return (EINVAL); 2445 } 2446 2447 if (dbregs->dr[7] & (0x3<<2)) { 2448 /* dr1 is enabled */ 2449 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2450 return (EINVAL); 2451 } 2452 2453 if (dbregs->dr[7] & (0x3<<4)) { 2454 /* dr2 is enabled */ 2455 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2456 return (EINVAL); 2457 } 2458 2459 if (dbregs->dr[7] & (0x3<<6)) { 2460 /* dr3 is enabled */ 2461 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2462 return (EINVAL); 2463 } 2464 } 2465 2466 pcb->pcb_dr0 = dbregs->dr[0]; 2467 pcb->pcb_dr1 = dbregs->dr[1]; 2468 pcb->pcb_dr2 = dbregs->dr[2]; 2469 pcb->pcb_dr3 = dbregs->dr[3]; 2470 pcb->pcb_dr6 = dbregs->dr[6]; 2471 pcb->pcb_dr7 = dbregs->dr[7]; 2472 2473 pcb->pcb_flags |= PCB_DBREGS; 2474 } 2475 2476 return (0); 2477 } 2478 2479 /* 2480 * Return > 0 if a hardware breakpoint has been hit, and the 2481 * breakpoint was in user space. Return 0, otherwise. 2482 */ 2483 int 2484 user_dbreg_trap(void) 2485 { 2486 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2487 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2488 int nbp; /* number of breakpoints that triggered */ 2489 caddr_t addr[4]; /* breakpoint addresses */ 2490 int i; 2491 2492 dr7 = rdr7(); 2493 if ((dr7 & 0xff) == 0) { 2494 /* 2495 * all GE and LE bits in the dr7 register are zero, 2496 * thus the trap couldn't have been caused by the 2497 * hardware debug registers 2498 */ 2499 return 0; 2500 } 2501 2502 nbp = 0; 2503 dr6 = rdr6(); 2504 bp = dr6 & 0xf; 2505 2506 if (bp == 0) { 2507 /* 2508 * None of the breakpoint bits are set meaning this 2509 * trap was not caused by any of the debug registers 2510 */ 2511 return 0; 2512 } 2513 2514 /* 2515 * at least one of the breakpoints were hit, check to see 2516 * which ones and if any of them are user space addresses 2517 */ 2518 2519 if (bp & 0x01) { 2520 addr[nbp++] = (caddr_t)rdr0(); 2521 } 2522 if (bp & 0x02) { 2523 addr[nbp++] = (caddr_t)rdr1(); 2524 } 2525 if (bp & 0x04) { 2526 addr[nbp++] = (caddr_t)rdr2(); 2527 } 2528 if (bp & 0x08) { 2529 addr[nbp++] = (caddr_t)rdr3(); 2530 } 2531 2532 for (i=0; i<nbp; i++) { 2533 if (addr[i] < 2534 (caddr_t)VM_MAX_USER_ADDRESS) { 2535 /* 2536 * addr[i] is in user space 2537 */ 2538 return nbp; 2539 } 2540 } 2541 2542 /* 2543 * None of the breakpoints are in user space. 2544 */ 2545 return 0; 2546 } 2547 2548 2549 #ifndef DDB 2550 void 2551 Debugger(const char *msg) 2552 { 2553 kprintf("Debugger(\"%s\") called.\n", msg); 2554 } 2555 #endif /* no DDB */ 2556 2557 #ifdef DDB 2558 2559 /* 2560 * Provide inb() and outb() as functions. They are normally only 2561 * available as macros calling inlined functions, thus cannot be 2562 * called inside DDB. 2563 * 2564 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2565 */ 2566 2567 #undef inb 2568 #undef outb 2569 2570 /* silence compiler warnings */ 2571 u_char inb(u_int); 2572 void outb(u_int, u_char); 2573 2574 u_char 2575 inb(u_int port) 2576 { 2577 u_char data; 2578 /* 2579 * We use %%dx and not %1 here because i/o is done at %dx and not at 2580 * %edx, while gcc generates inferior code (movw instead of movl) 2581 * if we tell it to load (u_short) port. 2582 */ 2583 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2584 return (data); 2585 } 2586 2587 void 2588 outb(u_int port, u_char data) 2589 { 2590 u_char al; 2591 /* 2592 * Use an unnecessary assignment to help gcc's register allocator. 2593 * This make a large difference for gcc-1.40 and a tiny difference 2594 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2595 * best results. gcc-2.6.0 can't handle this. 2596 */ 2597 al = data; 2598 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2599 } 2600 2601 #endif /* DDB */ 2602 2603 2604 2605 /* 2606 * initialize all the SMP locks 2607 */ 2608 2609 /* critical region when masking or unmasking interupts */ 2610 struct spinlock_deprecated imen_spinlock; 2611 2612 /* critical region for old style disable_intr/enable_intr */ 2613 struct spinlock_deprecated mpintr_spinlock; 2614 2615 /* critical region around INTR() routines */ 2616 struct spinlock_deprecated intr_spinlock; 2617 2618 /* lock region used by kernel profiling */ 2619 struct spinlock_deprecated mcount_spinlock; 2620 2621 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2622 struct spinlock_deprecated com_spinlock; 2623 2624 /* lock regions around the clock hardware */ 2625 struct spinlock_deprecated clock_spinlock; 2626 2627 static void 2628 init_locks(void) 2629 { 2630 /* 2631 * Get the initial mplock with a count of 1 for the BSP. 2632 * This uses a LOGICAL cpu ID, ie BSP == 0. 2633 */ 2634 cpu_get_initial_mplock(); 2635 /* DEPRECATED */ 2636 spin_lock_init(&mcount_spinlock); 2637 spin_lock_init(&intr_spinlock); 2638 spin_lock_init(&mpintr_spinlock); 2639 spin_lock_init(&imen_spinlock); 2640 spin_lock_init(&com_spinlock); 2641 spin_lock_init(&clock_spinlock); 2642 2643 /* our token pool needs to work early */ 2644 lwkt_token_pool_init(); 2645 } 2646 2647 boolean_t 2648 cpu_mwait_hint_valid(uint32_t hint) 2649 { 2650 int cx_idx, sub; 2651 2652 cx_idx = MWAIT_EAX_TO_CX(hint); 2653 if (cx_idx >= CPU_MWAIT_CX_MAX) 2654 return FALSE; 2655 2656 sub = MWAIT_EAX_TO_CX_SUB(hint); 2657 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 2658 return FALSE; 2659 2660 return TRUE; 2661 } 2662 2663 void 2664 cpu_mwait_cx_no_bmsts(void) 2665 { 2666 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 2667 } 2668 2669 void 2670 cpu_mwait_cx_no_bmarb(void) 2671 { 2672 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 2673 } 2674 2675 static int 2676 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 2677 boolean_t allow_auto) 2678 { 2679 int error, cx_idx, old_cx_idx, sub = 0, hint; 2680 char name[16], *ptr, *start; 2681 2682 hint = *hint0; 2683 if (hint >= 0) { 2684 old_cx_idx = MWAIT_EAX_TO_CX(hint); 2685 sub = MWAIT_EAX_TO_CX_SUB(hint); 2686 } else if (hint == CPU_MWAIT_HINT_AUTO) { 2687 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 2688 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 2689 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 2690 } else { 2691 old_cx_idx = CPU_MWAIT_CX_MAX; 2692 } 2693 2694 if ((cpu_feature2 & CPUID2_MON) == 0 || 2695 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0) 2696 strlcpy(name, "NONE", sizeof(name)); 2697 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 2698 strlcpy(name, "AUTO", sizeof(name)); 2699 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 2700 strlcpy(name, "AUTODEEP", sizeof(name)); 2701 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 2702 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 2703 strlcpy(name, "INVALID", sizeof(name)); 2704 else 2705 ksnprintf(name, sizeof(name), "C%d/%d", old_cx_idx, sub); 2706 2707 error = sysctl_handle_string(oidp, name, sizeof(name), req); 2708 if (error != 0 || req->newptr == NULL) 2709 return error; 2710 2711 if ((cpu_feature2 & CPUID2_MON) == 0 || 2712 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0) 2713 return EOPNOTSUPP; 2714 2715 if (allow_auto && strcmp(name, "AUTO") == 0) { 2716 hint = CPU_MWAIT_HINT_AUTO; 2717 cx_idx = CPU_MWAIT_C2; 2718 goto done; 2719 } 2720 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 2721 hint = CPU_MWAIT_HINT_AUTODEEP; 2722 cx_idx = CPU_MWAIT_C3; 2723 goto done; 2724 } 2725 2726 if (strlen(name) < 4 || toupper(name[0]) != 'C') 2727 return EINVAL; 2728 start = &name[1]; 2729 ptr = NULL; 2730 2731 cx_idx = strtol(start, &ptr, 10); 2732 if (ptr == start || *ptr != '/') 2733 return EINVAL; 2734 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 2735 return EINVAL; 2736 2737 start = ptr + 1; 2738 ptr = NULL; 2739 2740 sub = strtol(start, &ptr, 10); 2741 if (*ptr != '\0') 2742 return EINVAL; 2743 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 2744 return EINVAL; 2745 2746 hint = MWAIT_EAX_HINT(cx_idx, sub); 2747 done: 2748 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 2749 return EOPNOTSUPP; 2750 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 2751 error = cputimer_intr_powersave_addreq(); 2752 if (error) 2753 return error; 2754 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 2755 cputimer_intr_powersave_remreq(); 2756 } 2757 2758 *hint0 = hint; 2759 return 0; 2760 } 2761 2762 static int 2763 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 2764 { 2765 int error; 2766 2767 lwkt_serialize_enter(&cpu_mwait_cx_slize); 2768 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 2769 &cpu_mwait_halt, TRUE); 2770 lwkt_serialize_exit(&cpu_mwait_cx_slize); 2771 return error; 2772 } 2773 2774 static int 2775 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 2776 { 2777 int error; 2778 2779 lwkt_serialize_enter(&cpu_mwait_cx_slize); 2780 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 2781 &cpu_mwait_spin, FALSE); 2782 lwkt_serialize_exit(&cpu_mwait_cx_slize); 2783 return error; 2784 } 2785