1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 #if 0 /* JG */ 137 extern void finishidentcpu(void); 138 #endif 139 extern void panicifcpuunsupported(void); 140 141 static void cpu_startup(void *); 142 static void pic_finish(void *); 143 static void cpu_finish(void *); 144 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 static void init_locks(void); 148 149 extern void pcpu_timer_always(struct intrframe *); 150 151 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 152 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 153 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 154 155 #ifdef DDB 156 extern vm_offset_t ksym_start, ksym_end; 157 #endif 158 159 struct privatespace CPU_prvspace_bsp __aligned(4096); 160 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 161 162 vm_paddr_t efi_systbl_phys; 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 cpumask_t smp_idleinvl_mask; 167 cpumask_t smp_idleinvl_reqs; 168 169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 170 171 #if defined(SWTCH_OPTIM_STATS) 172 extern int swtch_optim_stats; 173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 174 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 176 CTLFLAG_RD, &tlb_flush_count, 0, ""); 177 #endif 178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0, 181 "monitor/mwait target state"); 182 183 #define CPU_MWAIT_HAS_CX \ 184 ((cpu_feature2 & CPUID2_MON) && \ 185 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 186 187 #define CPU_MWAIT_CX_NAMELEN 16 188 189 #define CPU_MWAIT_C1 1 190 #define CPU_MWAIT_C2 2 191 #define CPU_MWAIT_C3 3 192 #define CPU_MWAIT_CX_MAX 8 193 194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 196 197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 199 200 struct cpu_mwait_cx { 201 int subcnt; 202 char name[4]; 203 struct sysctl_ctx_list sysctl_ctx; 204 struct sysctl_oid *sysctl_tree; 205 }; 206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 207 static char cpu_mwait_cx_supported[256]; 208 209 static int cpu_mwait_c1_hints_cnt; 210 static int cpu_mwait_hints_cnt; 211 static int *cpu_mwait_hints; 212 213 static int cpu_mwait_deep_hints_cnt; 214 static int *cpu_mwait_deep_hints; 215 216 #define CPU_IDLE_REPEAT_DEFAULT 750 217 218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 220 static u_int cpu_mwait_repeat_shift = 1; 221 222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 224 225 static int cpu_mwait_c3_preamble = 226 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 227 CPU_MWAIT_C3_PREAMBLE_BM_STS; 228 229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 230 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 233 234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 235 int *, boolean_t); 236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 239 240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 245 &cpu_mwait_repeat_shift, 0, ""); 246 247 long physmem = 0; 248 249 u_long ebda_addr = 0; 250 251 int imcr_present = 0; 252 253 int naps = 0; /* # of Applications processors */ 254 255 u_int base_memory; 256 struct mtx dt_lock; /* lock for GDT and LDT */ 257 258 static int 259 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 260 { 261 u_long pmem = ctob(physmem); 262 263 int error = sysctl_handle_long(oidp, &pmem, 0, req); 264 return (error); 265 } 266 267 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 268 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 269 270 static int 271 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 272 { 273 int error = sysctl_handle_int(oidp, 0, 274 ctob(physmem - vmstats.v_wire_count), req); 275 return (error); 276 } 277 278 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 279 0, 0, sysctl_hw_usermem, "IU", ""); 280 281 static int 282 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 283 { 284 int error = sysctl_handle_int(oidp, 0, 285 x86_64_btop(avail_end - avail_start), req); 286 return (error); 287 } 288 289 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 290 0, 0, sysctl_hw_availpages, "I", ""); 291 292 vm_paddr_t Maxmem; 293 vm_paddr_t Realmem; 294 295 /* 296 * The number of PHYSMAP entries must be one less than the number of 297 * PHYSSEG entries because the PHYSMAP entry that spans the largest 298 * physical address that is accessible by ISA DMA is split into two 299 * PHYSSEG entries. 300 */ 301 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 302 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 303 304 /* must be 1 less so 0 0 can signal end of chunks */ 305 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 306 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 307 308 static vm_offset_t buffer_sva, buffer_eva; 309 vm_offset_t clean_sva, clean_eva; 310 static vm_offset_t pager_sva, pager_eva; 311 static struct trapframe proc0_tf; 312 313 static void 314 cpu_startup(void *dummy) 315 { 316 caddr_t v; 317 vm_size_t size = 0; 318 vm_offset_t firstaddr; 319 320 /* 321 * Good {morning,afternoon,evening,night}. 322 */ 323 kprintf("%s", version); 324 startrtclock(); 325 printcpuinfo(); 326 panicifcpuunsupported(); 327 kprintf("real memory = %ju (%ju MB)\n", 328 (intmax_t)Realmem, 329 (intmax_t)Realmem / 1024 / 1024); 330 /* 331 * Display any holes after the first chunk of extended memory. 332 */ 333 if (bootverbose) { 334 int indx; 335 336 kprintf("Physical memory chunk(s):\n"); 337 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 338 vm_paddr_t size1; 339 340 size1 = phys_avail[indx].phys_end - 341 phys_avail[indx].phys_beg; 342 343 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 344 (intmax_t)phys_avail[indx].phys_beg, 345 (intmax_t)phys_avail[indx].phys_end - 1, 346 (intmax_t)size1, 347 (intmax_t)(size1 / PAGE_SIZE)); 348 } 349 } 350 351 /* 352 * Allocate space for system data structures. 353 * The first available kernel virtual address is in "v". 354 * As pages of kernel virtual memory are allocated, "v" is incremented. 355 * As pages of memory are allocated and cleared, 356 * "firstaddr" is incremented. 357 * An index into the kernel page table corresponding to the 358 * virtual memory address maintained in "v" is kept in "mapaddr". 359 */ 360 361 /* 362 * Make two passes. The first pass calculates how much memory is 363 * needed and allocates it. The second pass assigns virtual 364 * addresses to the various data structures. 365 */ 366 firstaddr = 0; 367 again: 368 v = (caddr_t)firstaddr; 369 370 #define valloc(name, type, num) \ 371 (name) = (type *)v; v = (caddr_t)((name)+(num)) 372 #define valloclim(name, type, num, lim) \ 373 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 374 375 /* 376 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 377 * For the first 64MB of ram nominally allocate sufficient buffers to 378 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 379 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 380 * the buffer cache we limit the eventual kva reservation to 381 * maxbcache bytes. 382 * 383 * factor represents the 1/4 x ram conversion. 384 */ 385 if (nbuf == 0) { 386 long factor = 4 * NBUFCALCSIZE / 1024; 387 long kbytes = physmem * (PAGE_SIZE / 1024); 388 389 nbuf = 50; 390 if (kbytes > 4096) 391 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 392 if (kbytes > 65536) 393 nbuf += (kbytes - 65536) * 2 / (factor * 5); 394 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 395 nbuf = maxbcache / NBUFCALCSIZE; 396 } 397 398 /* 399 * Do not allow the buffer_map to be more then 1/2 the size of the 400 * kernel_map. 401 */ 402 if (nbuf > (virtual_end - virtual_start + 403 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 404 nbuf = (virtual_end - virtual_start + 405 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 406 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 407 } 408 409 /* 410 * Do not allow the buffer_map to use more than 50% of available 411 * physical-equivalent memory. Since the VM pages which back 412 * individual buffers are typically wired, having too many bufs 413 * can prevent the system from paging properly. 414 */ 415 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 416 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 417 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 418 } 419 420 /* 421 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 422 * the valloc space which is just the virtual_end - virtual_start 423 * section. We use valloc() to allocate the buf header array. 424 */ 425 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 426 nbuf = (virtual_end - virtual_start) / 427 sizeof(struct buf) / 2; 428 kprintf("Warning: nbufs capped at %ld due to valloc " 429 "considerations\n", nbuf); 430 } 431 432 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 433 #ifdef NSWBUF_MIN 434 if (nswbuf_mem < NSWBUF_MIN) 435 nswbuf_mem = NSWBUF_MIN; 436 #endif 437 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 438 #ifdef NSWBUF_MIN 439 if (nswbuf_kva < NSWBUF_MIN) 440 nswbuf_kva = NSWBUF_MIN; 441 #endif 442 443 valloc(swbuf_mem, struct buf, nswbuf_mem); 444 valloc(swbuf_kva, struct buf, nswbuf_kva); 445 valloc(buf, struct buf, nbuf); 446 447 /* 448 * End of first pass, size has been calculated so allocate memory 449 */ 450 if (firstaddr == 0) { 451 size = (vm_size_t)(v - firstaddr); 452 firstaddr = kmem_alloc(&kernel_map, round_page(size), 453 VM_SUBSYS_BUF); 454 if (firstaddr == 0) 455 panic("startup: no room for tables"); 456 goto again; 457 } 458 459 /* 460 * End of second pass, addresses have been assigned 461 * 462 * nbuf is an int, make sure we don't overflow the field. 463 * 464 * On 64-bit systems we always reserve maximal allocations for 465 * buffer cache buffers and there are no fragmentation issues, 466 * so the KVA segment does not have to be excessively oversized. 467 */ 468 if ((vm_size_t)(v - firstaddr) != size) 469 panic("startup: table size inconsistency"); 470 471 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 472 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 473 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 474 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 475 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 476 buffer_map.system_map = 1; 477 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 478 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 479 pager_map_size); 480 pager_map.system_map = 1; 481 kprintf("avail memory = %ju (%ju MB)\n", 482 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 483 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 484 1024 / 1024); 485 } 486 487 struct cpu_idle_stat { 488 int hint; 489 int reserved; 490 u_long halt; 491 u_long spin; 492 u_long repeat; 493 u_long repeat_last; 494 u_long repeat_delta; 495 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 496 } __cachealign; 497 498 #define CPU_IDLE_STAT_HALT -1 499 #define CPU_IDLE_STAT_SPIN -2 500 501 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 502 503 static int 504 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 505 { 506 int idx = arg2, cpu, error; 507 u_long val = 0; 508 509 if (idx == CPU_IDLE_STAT_HALT) { 510 for (cpu = 0; cpu < ncpus; ++cpu) 511 val += cpu_idle_stats[cpu].halt; 512 } else if (idx == CPU_IDLE_STAT_SPIN) { 513 for (cpu = 0; cpu < ncpus; ++cpu) 514 val += cpu_idle_stats[cpu].spin; 515 } else { 516 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 517 ("invalid index %d", idx)); 518 for (cpu = 0; cpu < ncpus; ++cpu) 519 val += cpu_idle_stats[cpu].mwait_cx[idx]; 520 } 521 522 error = sysctl_handle_quad(oidp, &val, 0, req); 523 if (error || req->newptr == NULL) 524 return error; 525 526 if (idx == CPU_IDLE_STAT_HALT) { 527 for (cpu = 0; cpu < ncpus; ++cpu) 528 cpu_idle_stats[cpu].halt = 0; 529 cpu_idle_stats[0].halt = val; 530 } else if (idx == CPU_IDLE_STAT_SPIN) { 531 for (cpu = 0; cpu < ncpus; ++cpu) 532 cpu_idle_stats[cpu].spin = 0; 533 cpu_idle_stats[0].spin = val; 534 } else { 535 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 536 ("invalid index %d", idx)); 537 for (cpu = 0; cpu < ncpus; ++cpu) 538 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 539 cpu_idle_stats[0].mwait_cx[idx] = val; 540 } 541 return 0; 542 } 543 544 static void 545 cpu_mwait_attach(void) 546 { 547 struct sbuf sb; 548 int hint_idx, i; 549 550 if (!CPU_MWAIT_HAS_CX) 551 return; 552 553 if (cpu_vendor_id == CPU_VENDOR_INTEL && 554 (CPUID_TO_FAMILY(cpu_id) > 0xf || 555 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 556 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 557 int bm_sts = 1; 558 559 /* 560 * Pentium dual-core, Core 2 and beyond do not need any 561 * additional activities to enter deep C-state, i.e. C3(+). 562 */ 563 cpu_mwait_cx_no_bmarb(); 564 565 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 566 if (!bm_sts) 567 cpu_mwait_cx_no_bmsts(); 568 } 569 570 sbuf_new(&sb, cpu_mwait_cx_supported, 571 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 572 573 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 574 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 575 int sub; 576 577 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 578 579 sysctl_ctx_init(&cx->sysctl_ctx); 580 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 581 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 582 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 583 if (cx->sysctl_tree == NULL) 584 continue; 585 586 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 587 SYSCTL_ADD_INT(&cx->sysctl_ctx, 588 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 589 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 590 "sub-state count"); 591 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 592 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 593 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 594 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 595 596 for (sub = 0; sub < cx->subcnt; ++sub) 597 sbuf_printf(&sb, "C%d/%d ", i, sub); 598 } 599 sbuf_trim(&sb); 600 sbuf_finish(&sb); 601 602 /* 603 * Non-deep C-states 604 */ 605 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 606 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 607 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 608 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 609 M_DEVBUF, M_WAITOK); 610 611 hint_idx = 0; 612 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 613 int j, subcnt; 614 615 subcnt = cpu_mwait_cx_info[i].subcnt; 616 for (j = 0; j < subcnt; ++j) { 617 KASSERT(hint_idx < cpu_mwait_hints_cnt, 618 ("invalid mwait hint index %d", hint_idx)); 619 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 620 ++hint_idx; 621 } 622 } 623 KASSERT(hint_idx == cpu_mwait_hints_cnt, 624 ("mwait hint count %d != index %d", 625 cpu_mwait_hints_cnt, hint_idx)); 626 627 if (bootverbose) { 628 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 629 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 630 int hint = cpu_mwait_hints[i]; 631 632 kprintf(" C%d/%d hint 0x%04x\n", 633 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 634 hint); 635 } 636 } 637 638 /* 639 * Deep C-states 640 */ 641 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 642 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 643 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 644 M_DEVBUF, M_WAITOK); 645 646 hint_idx = 0; 647 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 648 int j, subcnt; 649 650 subcnt = cpu_mwait_cx_info[i].subcnt; 651 for (j = 0; j < subcnt; ++j) { 652 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 653 ("invalid mwait deep hint index %d", hint_idx)); 654 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 655 ++hint_idx; 656 } 657 } 658 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 659 ("mwait deep hint count %d != index %d", 660 cpu_mwait_deep_hints_cnt, hint_idx)); 661 662 if (bootverbose) { 663 kprintf("MWAIT deep hints:\n"); 664 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 665 int hint = cpu_mwait_deep_hints[i]; 666 667 kprintf(" C%d/%d hint 0x%04x\n", 668 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 669 hint); 670 } 671 } 672 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 673 674 for (i = 0; i < ncpus; ++i) { 675 char name[16]; 676 677 ksnprintf(name, sizeof(name), "idle%d", i); 678 SYSCTL_ADD_PROC(NULL, 679 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 680 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 681 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 682 } 683 } 684 685 static void 686 cpu_finish(void *dummy __unused) 687 { 688 cpu_setregs(); 689 cpu_mwait_attach(); 690 } 691 692 static void 693 pic_finish(void *dummy __unused) 694 { 695 /* Log ELCR information */ 696 elcr_dump(); 697 698 /* Log MPTABLE information */ 699 mptable_pci_int_dump(); 700 701 /* Finalize PCI */ 702 MachIntrABI.finalize(); 703 } 704 705 /* 706 * Send an interrupt to process. 707 * 708 * Stack is set up to allow sigcode stored 709 * at top to call routine, followed by kcall 710 * to sigreturn routine below. After sigreturn 711 * resets the signal mask, the stack, and the 712 * frame pointer, it returns to the user 713 * specified pc, psl. 714 */ 715 void 716 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 717 { 718 struct lwp *lp = curthread->td_lwp; 719 struct proc *p = lp->lwp_proc; 720 struct trapframe *regs; 721 struct sigacts *psp = p->p_sigacts; 722 struct sigframe sf, *sfp; 723 int oonstack; 724 char *sp; 725 726 regs = lp->lwp_md.md_regs; 727 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 728 729 /* Save user context */ 730 bzero(&sf, sizeof(struct sigframe)); 731 sf.sf_uc.uc_sigmask = *mask; 732 sf.sf_uc.uc_stack = lp->lwp_sigstk; 733 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 734 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 735 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 736 737 /* Make the size of the saved context visible to userland */ 738 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 739 740 /* Allocate and validate space for the signal handler context. */ 741 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 742 SIGISMEMBER(psp->ps_sigonstack, sig)) { 743 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 744 sizeof(struct sigframe)); 745 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 746 } else { 747 /* We take red zone into account */ 748 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 749 } 750 751 /* 752 * XXX AVX needs 64-byte alignment but sigframe has other fields and 753 * the embedded ucontext is not at the front, so aligning this won't 754 * help us. Fortunately we bcopy in/out of the sigframe, so the 755 * kernel is ok. 756 * 757 * The problem though is if userland winds up trying to use the 758 * context directly. 759 */ 760 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 761 762 /* Translate the signal is appropriate */ 763 if (p->p_sysent->sv_sigtbl) { 764 if (sig <= p->p_sysent->sv_sigsize) 765 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 766 } 767 768 /* 769 * Build the argument list for the signal handler. 770 * 771 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 772 */ 773 regs->tf_rdi = sig; /* argument 1 */ 774 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 775 776 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 777 /* 778 * Signal handler installed with SA_SIGINFO. 779 * 780 * action(signo, siginfo, ucontext) 781 */ 782 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 783 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 784 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 785 786 /* fill siginfo structure */ 787 sf.sf_si.si_signo = sig; 788 sf.sf_si.si_code = code; 789 sf.sf_si.si_addr = (void *)regs->tf_addr; 790 } else { 791 /* 792 * Old FreeBSD-style arguments. 793 * 794 * handler (signo, code, [uc], addr) 795 */ 796 regs->tf_rsi = (register_t)code; /* argument 2 */ 797 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 798 sf.sf_ahu.sf_handler = catcher; 799 } 800 801 /* 802 * If we're a vm86 process, we want to save the segment registers. 803 * We also change eflags to be our emulated eflags, not the actual 804 * eflags. 805 */ 806 #if 0 /* JG */ 807 if (regs->tf_eflags & PSL_VM) { 808 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 809 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 810 811 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 812 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 813 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 814 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 815 816 if (vm86->vm86_has_vme == 0) 817 sf.sf_uc.uc_mcontext.mc_eflags = 818 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 819 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 820 821 /* 822 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 823 * syscalls made by the signal handler. This just avoids 824 * wasting time for our lazy fixup of such faults. PSL_NT 825 * does nothing in vm86 mode, but vm86 programs can set it 826 * almost legitimately in probes for old cpu types. 827 */ 828 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 829 } 830 #endif 831 832 /* 833 * Save the FPU state and reinit the FP unit 834 */ 835 npxpush(&sf.sf_uc.uc_mcontext); 836 837 /* 838 * Copy the sigframe out to the user's stack. 839 */ 840 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 841 /* 842 * Something is wrong with the stack pointer. 843 * ...Kill the process. 844 */ 845 sigexit(lp, SIGILL); 846 } 847 848 regs->tf_rsp = (register_t)sfp; 849 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 850 851 /* 852 * i386 abi specifies that the direction flag must be cleared 853 * on function entry 854 */ 855 regs->tf_rflags &= ~(PSL_T | PSL_D); 856 857 /* 858 * 64 bit mode has a code and stack selector but 859 * no data or extra selector. %fs and %gs are not 860 * stored in-context. 861 */ 862 regs->tf_cs = _ucodesel; 863 regs->tf_ss = _udatasel; 864 clear_quickret(); 865 } 866 867 /* 868 * Sanitize the trapframe for a virtual kernel passing control to a custom 869 * VM context. Remove any items that would otherwise create a privilage 870 * issue. 871 * 872 * XXX at the moment we allow userland to set the resume flag. Is this a 873 * bad idea? 874 */ 875 int 876 cpu_sanitize_frame(struct trapframe *frame) 877 { 878 frame->tf_cs = _ucodesel; 879 frame->tf_ss = _udatasel; 880 /* XXX VM (8086) mode not supported? */ 881 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 882 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 883 884 return(0); 885 } 886 887 /* 888 * Sanitize the tls so loading the descriptor does not blow up 889 * on us. For x86_64 we don't have to do anything. 890 */ 891 int 892 cpu_sanitize_tls(struct savetls *tls) 893 { 894 return(0); 895 } 896 897 /* 898 * sigreturn(ucontext_t *sigcntxp) 899 * 900 * System call to cleanup state after a signal 901 * has been taken. Reset signal mask and 902 * stack state from context left by sendsig (above). 903 * Return to previous pc and psl as specified by 904 * context left by sendsig. Check carefully to 905 * make sure that the user has not modified the 906 * state to gain improper privileges. 907 * 908 * MPSAFE 909 */ 910 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 911 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 912 913 int 914 sys_sigreturn(struct sigreturn_args *uap) 915 { 916 struct lwp *lp = curthread->td_lwp; 917 struct trapframe *regs; 918 ucontext_t uc; 919 ucontext_t *ucp; 920 register_t rflags; 921 int cs; 922 int error; 923 924 /* 925 * We have to copy the information into kernel space so userland 926 * can't modify it while we are sniffing it. 927 */ 928 regs = lp->lwp_md.md_regs; 929 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 930 if (error) 931 return (error); 932 ucp = &uc; 933 rflags = ucp->uc_mcontext.mc_rflags; 934 935 /* VM (8086) mode not supported */ 936 rflags &= ~PSL_VM_UNSUPP; 937 938 #if 0 /* JG */ 939 if (eflags & PSL_VM) { 940 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 941 struct vm86_kernel *vm86; 942 943 /* 944 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 945 * set up the vm86 area, and we can't enter vm86 mode. 946 */ 947 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 948 return (EINVAL); 949 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 950 if (vm86->vm86_inited == 0) 951 return (EINVAL); 952 953 /* go back to user mode if both flags are set */ 954 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 955 trapsignal(lp, SIGBUS, 0); 956 957 if (vm86->vm86_has_vme) { 958 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 959 (eflags & VME_USERCHANGE) | PSL_VM; 960 } else { 961 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 962 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 963 (eflags & VM_USERCHANGE) | PSL_VM; 964 } 965 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 966 tf->tf_eflags = eflags; 967 tf->tf_vm86_ds = tf->tf_ds; 968 tf->tf_vm86_es = tf->tf_es; 969 tf->tf_vm86_fs = tf->tf_fs; 970 tf->tf_vm86_gs = tf->tf_gs; 971 tf->tf_ds = _udatasel; 972 tf->tf_es = _udatasel; 973 tf->tf_fs = _udatasel; 974 tf->tf_gs = _udatasel; 975 } else 976 #endif 977 { 978 /* 979 * Don't allow users to change privileged or reserved flags. 980 */ 981 /* 982 * XXX do allow users to change the privileged flag PSL_RF. 983 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 984 * should sometimes set it there too. tf_eflags is kept in 985 * the signal context during signal handling and there is no 986 * other place to remember it, so the PSL_RF bit may be 987 * corrupted by the signal handler without us knowing. 988 * Corruption of the PSL_RF bit at worst causes one more or 989 * one less debugger trap, so allowing it is fairly harmless. 990 */ 991 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 992 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 993 return(EINVAL); 994 } 995 996 /* 997 * Don't allow users to load a valid privileged %cs. Let the 998 * hardware check for invalid selectors, excess privilege in 999 * other selectors, invalid %eip's and invalid %esp's. 1000 */ 1001 cs = ucp->uc_mcontext.mc_cs; 1002 if (!CS_SECURE(cs)) { 1003 kprintf("sigreturn: cs = 0x%x\n", cs); 1004 trapsignal(lp, SIGBUS, T_PROTFLT); 1005 return(EINVAL); 1006 } 1007 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1008 } 1009 1010 /* 1011 * Restore the FPU state from the frame 1012 */ 1013 crit_enter(); 1014 npxpop(&ucp->uc_mcontext); 1015 1016 if (ucp->uc_mcontext.mc_onstack & 1) 1017 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1018 else 1019 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1020 1021 lp->lwp_sigmask = ucp->uc_sigmask; 1022 SIG_CANTMASK(lp->lwp_sigmask); 1023 clear_quickret(); 1024 crit_exit(); 1025 return(EJUSTRETURN); 1026 } 1027 1028 /* 1029 * Machine dependent boot() routine 1030 * 1031 * I haven't seen anything to put here yet 1032 * Possibly some stuff might be grafted back here from boot() 1033 */ 1034 void 1035 cpu_boot(int howto) 1036 { 1037 } 1038 1039 /* 1040 * Shutdown the CPU as much as possible 1041 */ 1042 void 1043 cpu_halt(void) 1044 { 1045 for (;;) 1046 __asm__ __volatile("hlt"); 1047 } 1048 1049 /* 1050 * cpu_idle() represents the idle LWKT. You cannot return from this function 1051 * (unless you want to blow things up!). Instead we look for runnable threads 1052 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1053 * 1054 * The main loop is entered with a critical section held, we must release 1055 * the critical section before doing anything else. lwkt_switch() will 1056 * check for pending interrupts due to entering and exiting its own 1057 * critical section. 1058 * 1059 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1060 * However, there are cases where the idlethread will be entered with 1061 * the possibility that no IPI will occur and in such cases 1062 * lwkt_switch() sets TDF_IDLE_NOHLT. 1063 * 1064 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1065 * must occur before it starts using ACPI halt. 1066 * 1067 * NOTE: Value overridden in hammer_time(). 1068 */ 1069 static int cpu_idle_hlt = 2; 1070 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1071 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1072 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1073 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1074 1075 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1076 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1077 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1078 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1079 1080 static void 1081 cpu_idle_default_hook(void) 1082 { 1083 /* 1084 * We must guarentee that hlt is exactly the instruction 1085 * following the sti. 1086 */ 1087 __asm __volatile("sti; hlt"); 1088 } 1089 1090 /* Other subsystems (e.g., ACPI) can hook this later. */ 1091 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1092 1093 static __inline int 1094 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1095 { 1096 int hint, cx_idx; 1097 u_int idx; 1098 1099 hint = stat->hint; 1100 if (hint >= 0) 1101 goto done; 1102 1103 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1104 cpu_mwait_repeat_shift; 1105 if (idx >= cpu_mwait_c1_hints_cnt) { 1106 /* Step up faster, once we walked through all C1 states */ 1107 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1108 } 1109 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1110 if (idx >= cpu_mwait_deep_hints_cnt) 1111 idx = cpu_mwait_deep_hints_cnt - 1; 1112 hint = cpu_mwait_deep_hints[idx]; 1113 } else { 1114 if (idx >= cpu_mwait_hints_cnt) 1115 idx = cpu_mwait_hints_cnt - 1; 1116 hint = cpu_mwait_hints[idx]; 1117 } 1118 done: 1119 cx_idx = MWAIT_EAX_TO_CX(hint); 1120 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1121 stat->mwait_cx[cx_idx]++; 1122 return hint; 1123 } 1124 1125 void 1126 cpu_idle(void) 1127 { 1128 globaldata_t gd = mycpu; 1129 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1130 struct thread *td __debugvar = gd->gd_curthread; 1131 int reqflags; 1132 int quick; 1133 1134 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1135 1136 crit_exit(); 1137 KKASSERT(td->td_critcount == 0); 1138 1139 for (;;) { 1140 /* 1141 * See if there are any LWKTs ready to go. 1142 */ 1143 lwkt_switch(); 1144 1145 /* 1146 * When halting inside a cli we must check for reqflags 1147 * races, particularly [re]schedule requests. Running 1148 * splz() does the job. 1149 * 1150 * cpu_idle_hlt: 1151 * 0 Never halt, just spin 1152 * 1153 * 1 Always use MONITOR/MWAIT if avail, HLT 1154 * otherwise. 1155 * 1156 * Better default for modern (Haswell+) Intel 1157 * cpus. 1158 * 1159 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1160 * use the ACPI halt (default). This is a hybrid 1161 * approach. See machdep.cpu_idle_repeat. 1162 * 1163 * Better default for modern AMD cpus and older 1164 * Intel cpus. 1165 * 1166 * 3 Always use the ACPI halt. This typically 1167 * eats the least amount of power but the cpu 1168 * will be slow waking up. Slows down e.g. 1169 * compiles and other pipe/event oriented stuff. 1170 * 1171 * Usually the best default for AMD cpus. 1172 * 1173 * 4 Always use HLT. 1174 * 1175 * 5 Always spin. 1176 * 1177 * NOTE: Interrupts are enabled and we are not in a critical 1178 * section. 1179 * 1180 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1181 * don't bother capping gd_idle_repeat, it is ok if 1182 * it overflows. 1183 * 1184 * Implement optimized invltlb operations when halted 1185 * in idle. By setting the bit in smp_idleinvl_mask 1186 * we inform other cpus that they can set _reqs to 1187 * request an invltlb. Current the code to do that 1188 * sets the bits in _reqs anyway, but then check _mask 1189 * to determine if they can assume the invltlb will execute. 1190 * 1191 * A critical section is required to ensure that interrupts 1192 * do not fully run until after we've had a chance to execute 1193 * the request. 1194 */ 1195 if (gd->gd_idle_repeat == 0) { 1196 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1197 if (stat->repeat > cpu_idle_repeat_max) 1198 stat->repeat = cpu_idle_repeat_max; 1199 stat->repeat_last = 0; 1200 stat->repeat_delta = 0; 1201 } 1202 ++stat->repeat_last; 1203 1204 ++gd->gd_idle_repeat; 1205 reqflags = gd->gd_reqflags; 1206 quick = (cpu_idle_hlt == 1) || 1207 (cpu_idle_hlt == 2 && 1208 gd->gd_idle_repeat < cpu_idle_repeat); 1209 1210 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1211 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1212 splz(); /* XXX */ 1213 crit_enter_gd(gd); 1214 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1215 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1216 cpu_mwait_cx_hint(stat), 0); 1217 stat->halt++; 1218 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1219 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1220 gd->gd_cpuid)) { 1221 cpu_invltlb(); 1222 cpu_mfence(); 1223 } 1224 crit_exit_gd(gd); 1225 } else if (cpu_idle_hlt) { 1226 __asm __volatile("cli"); 1227 splz(); 1228 crit_enter_gd(gd); 1229 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1230 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1231 if (cpu_idle_hlt == 5) { 1232 __asm __volatile("sti"); 1233 } else if (quick || cpu_idle_hlt == 4) { 1234 cpu_idle_default_hook(); 1235 } else { 1236 cpu_idle_hook(); 1237 } 1238 } 1239 __asm __volatile("sti"); 1240 stat->halt++; 1241 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1242 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1243 gd->gd_cpuid)) { 1244 cpu_invltlb(); 1245 cpu_mfence(); 1246 } 1247 crit_exit_gd(gd); 1248 } else { 1249 splz(); 1250 __asm __volatile("sti"); 1251 stat->spin++; 1252 crit_enter_gd(gd); 1253 crit_exit_gd(gd); 1254 } 1255 } 1256 } 1257 1258 /* 1259 * Called in a loop indirectly via Xcpustop 1260 */ 1261 void 1262 cpu_smp_stopped(void) 1263 { 1264 globaldata_t gd = mycpu; 1265 volatile __uint64_t *ptr; 1266 __uint64_t ovalue; 1267 1268 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1269 ovalue = *ptr; 1270 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1271 if (cpu_mi_feature & CPU_MI_MONITOR) { 1272 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), ovalue, 1273 cpu_mwait_hints[CPU_MWAIT_C1], 0); 1274 } else { 1275 cpu_halt(); /* depend on lapic timer */ 1276 } 1277 } 1278 } 1279 1280 /* 1281 * This routine is called if a spinlock has been held through the 1282 * exponential backoff period and is seriously contested. On a real cpu 1283 * we let it spin. 1284 */ 1285 void 1286 cpu_spinlock_contested(void) 1287 { 1288 cpu_pause(); 1289 } 1290 1291 /* 1292 * Clear registers on exec 1293 */ 1294 void 1295 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1296 { 1297 struct thread *td = curthread; 1298 struct lwp *lp = td->td_lwp; 1299 struct pcb *pcb = td->td_pcb; 1300 struct trapframe *regs = lp->lwp_md.md_regs; 1301 1302 /* was i386_user_cleanup() in NetBSD */ 1303 user_ldt_free(pcb); 1304 1305 clear_quickret(); 1306 bzero((char *)regs, sizeof(struct trapframe)); 1307 regs->tf_rip = entry; 1308 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1309 regs->tf_rdi = stack; /* argv */ 1310 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1311 regs->tf_ss = _udatasel; 1312 regs->tf_cs = _ucodesel; 1313 regs->tf_rbx = ps_strings; 1314 1315 /* 1316 * Reset the hardware debug registers if they were in use. 1317 * They won't have any meaning for the newly exec'd process. 1318 */ 1319 if (pcb->pcb_flags & PCB_DBREGS) { 1320 pcb->pcb_dr0 = 0; 1321 pcb->pcb_dr1 = 0; 1322 pcb->pcb_dr2 = 0; 1323 pcb->pcb_dr3 = 0; 1324 pcb->pcb_dr6 = 0; 1325 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1326 if (pcb == td->td_pcb) { 1327 /* 1328 * Clear the debug registers on the running 1329 * CPU, otherwise they will end up affecting 1330 * the next process we switch to. 1331 */ 1332 reset_dbregs(); 1333 } 1334 pcb->pcb_flags &= ~PCB_DBREGS; 1335 } 1336 1337 /* 1338 * Initialize the math emulator (if any) for the current process. 1339 * Actually, just clear the bit that says that the emulator has 1340 * been initialized. Initialization is delayed until the process 1341 * traps to the emulator (if it is done at all) mainly because 1342 * emulators don't provide an entry point for initialization. 1343 */ 1344 pcb->pcb_flags &= ~FP_SOFTFP; 1345 1346 /* 1347 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1348 * gd_npxthread. Otherwise a preemptive interrupt thread 1349 * may panic in npxdna(). 1350 */ 1351 crit_enter(); 1352 load_cr0(rcr0() | CR0_MP); 1353 1354 /* 1355 * NOTE: The MSR values must be correct so we can return to 1356 * userland. gd_user_fs/gs must be correct so the switch 1357 * code knows what the current MSR values are. 1358 */ 1359 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1360 pcb->pcb_gsbase = 0; 1361 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1362 mdcpu->gd_user_gs = 0; 1363 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1364 wrmsr(MSR_KGSBASE, 0); 1365 1366 /* Initialize the npx (if any) for the current process. */ 1367 npxinit(); 1368 crit_exit(); 1369 1370 pcb->pcb_ds = _udatasel; 1371 pcb->pcb_es = _udatasel; 1372 pcb->pcb_fs = _udatasel; 1373 pcb->pcb_gs = _udatasel; 1374 } 1375 1376 void 1377 cpu_setregs(void) 1378 { 1379 register_t cr0; 1380 1381 cr0 = rcr0(); 1382 cr0 |= CR0_NE; /* Done by npxinit() */ 1383 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1384 cr0 |= CR0_WP | CR0_AM; 1385 load_cr0(cr0); 1386 load_gs(_udatasel); 1387 } 1388 1389 static int 1390 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1391 { 1392 int error; 1393 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1394 req); 1395 if (!error && req->newptr) 1396 resettodr(); 1397 return (error); 1398 } 1399 1400 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1401 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1402 1403 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1404 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1405 1406 #if 0 /* JG */ 1407 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1408 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1409 #endif 1410 1411 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1412 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1413 1414 extern u_long bootdev; /* not a cdev_t - encoding is different */ 1415 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 1416 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)"); 1417 1418 static int 1419 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1420 { 1421 struct efi_map_header *efihdr; 1422 caddr_t kmdp; 1423 uint32_t efisize; 1424 1425 kmdp = preload_search_by_type("elf kernel"); 1426 if (kmdp == NULL) 1427 kmdp = preload_search_by_type("elf64 kernel"); 1428 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1429 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1430 if (efihdr == NULL) 1431 return (0); 1432 efisize = *((uint32_t *)efihdr - 1); 1433 return (SYSCTL_OUT(req, efihdr, efisize)); 1434 } 1435 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1436 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1437 1438 /* 1439 * Initialize 386 and configure to run kernel 1440 */ 1441 1442 /* 1443 * Initialize segments & interrupt table 1444 */ 1445 1446 int _default_ldt; 1447 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1448 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1449 #if 0 /* JG */ 1450 union descriptor ldt[NLDT]; /* local descriptor table */ 1451 #endif 1452 1453 /* table descriptors - used to load tables by cpu */ 1454 struct region_descriptor r_gdt; 1455 struct region_descriptor r_idt_arr[MAXCPU]; 1456 1457 /* JG proc0paddr is a virtual address */ 1458 void *proc0paddr; 1459 /* JG alignment? */ 1460 char proc0paddr_buff[LWKT_THREAD_STACK]; 1461 1462 1463 /* software prototypes -- in more palatable form */ 1464 struct soft_segment_descriptor gdt_segs[] = { 1465 /* GNULL_SEL 0 Null Descriptor */ 1466 { 0x0, /* segment base address */ 1467 0x0, /* length */ 1468 0, /* segment type */ 1469 0, /* segment descriptor priority level */ 1470 0, /* segment descriptor present */ 1471 0, /* long */ 1472 0, /* default 32 vs 16 bit size */ 1473 0 /* limit granularity (byte/page units)*/ }, 1474 /* GCODE_SEL 1 Code Descriptor for kernel */ 1475 { 0x0, /* segment base address */ 1476 0xfffff, /* length - all address space */ 1477 SDT_MEMERA, /* segment type */ 1478 SEL_KPL, /* segment descriptor priority level */ 1479 1, /* segment descriptor present */ 1480 1, /* long */ 1481 0, /* default 32 vs 16 bit size */ 1482 1 /* limit granularity (byte/page units)*/ }, 1483 /* GDATA_SEL 2 Data Descriptor for kernel */ 1484 { 0x0, /* segment base address */ 1485 0xfffff, /* length - all address space */ 1486 SDT_MEMRWA, /* segment type */ 1487 SEL_KPL, /* segment descriptor priority level */ 1488 1, /* segment descriptor present */ 1489 1, /* long */ 1490 0, /* default 32 vs 16 bit size */ 1491 1 /* limit granularity (byte/page units)*/ }, 1492 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1493 { 0x0, /* segment base address */ 1494 0xfffff, /* length - all address space */ 1495 SDT_MEMERA, /* segment type */ 1496 SEL_UPL, /* segment descriptor priority level */ 1497 1, /* segment descriptor present */ 1498 0, /* long */ 1499 1, /* default 32 vs 16 bit size */ 1500 1 /* limit granularity (byte/page units)*/ }, 1501 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1502 { 0x0, /* segment base address */ 1503 0xfffff, /* length - all address space */ 1504 SDT_MEMRWA, /* segment type */ 1505 SEL_UPL, /* segment descriptor priority level */ 1506 1, /* segment descriptor present */ 1507 0, /* long */ 1508 1, /* default 32 vs 16 bit size */ 1509 1 /* limit granularity (byte/page units)*/ }, 1510 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1511 { 0x0, /* segment base address */ 1512 0xfffff, /* length - all address space */ 1513 SDT_MEMERA, /* segment type */ 1514 SEL_UPL, /* segment descriptor priority level */ 1515 1, /* segment descriptor present */ 1516 1, /* long */ 1517 0, /* default 32 vs 16 bit size */ 1518 1 /* limit granularity (byte/page units)*/ }, 1519 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1520 { 1521 0x0, /* segment base address */ 1522 sizeof(struct x86_64tss)-1,/* length - all address space */ 1523 SDT_SYSTSS, /* segment type */ 1524 SEL_KPL, /* segment descriptor priority level */ 1525 1, /* segment descriptor present */ 1526 0, /* long */ 1527 0, /* unused - default 32 vs 16 bit size */ 1528 0 /* limit granularity (byte/page units)*/ }, 1529 /* Actually, the TSS is a system descriptor which is double size */ 1530 { 0x0, /* segment base address */ 1531 0x0, /* length */ 1532 0, /* segment type */ 1533 0, /* segment descriptor priority level */ 1534 0, /* segment descriptor present */ 1535 0, /* long */ 1536 0, /* default 32 vs 16 bit size */ 1537 0 /* limit granularity (byte/page units)*/ }, 1538 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1539 { 0x0, /* segment base address */ 1540 0xfffff, /* length - all address space */ 1541 SDT_MEMRWA, /* segment type */ 1542 SEL_UPL, /* segment descriptor priority level */ 1543 1, /* segment descriptor present */ 1544 0, /* long */ 1545 1, /* default 32 vs 16 bit size */ 1546 1 /* limit granularity (byte/page units)*/ }, 1547 }; 1548 1549 void 1550 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1551 { 1552 int cpu; 1553 1554 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1555 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1556 1557 ip->gd_looffset = (uintptr_t)func; 1558 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1559 ip->gd_ist = ist; 1560 ip->gd_xx = 0; 1561 ip->gd_type = typ; 1562 ip->gd_dpl = dpl; 1563 ip->gd_p = 1; 1564 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1565 } 1566 } 1567 1568 void 1569 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1570 { 1571 struct gate_descriptor *ip; 1572 1573 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1574 1575 ip = &idt_arr[cpu][idx]; 1576 ip->gd_looffset = (uintptr_t)func; 1577 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1578 ip->gd_ist = ist; 1579 ip->gd_xx = 0; 1580 ip->gd_type = typ; 1581 ip->gd_dpl = dpl; 1582 ip->gd_p = 1; 1583 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1584 } 1585 1586 #define IDTVEC(name) __CONCAT(X,name) 1587 1588 extern inthand_t 1589 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1590 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1591 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1592 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1593 IDTVEC(xmm), IDTVEC(dblfault), 1594 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1595 1596 void 1597 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1598 { 1599 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1600 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1601 ssd->ssd_type = sd->sd_type; 1602 ssd->ssd_dpl = sd->sd_dpl; 1603 ssd->ssd_p = sd->sd_p; 1604 ssd->ssd_def32 = sd->sd_def32; 1605 ssd->ssd_gran = sd->sd_gran; 1606 } 1607 1608 void 1609 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1610 { 1611 1612 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1613 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1614 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1615 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1616 sd->sd_type = ssd->ssd_type; 1617 sd->sd_dpl = ssd->ssd_dpl; 1618 sd->sd_p = ssd->ssd_p; 1619 sd->sd_long = ssd->ssd_long; 1620 sd->sd_def32 = ssd->ssd_def32; 1621 sd->sd_gran = ssd->ssd_gran; 1622 } 1623 1624 void 1625 ssdtosyssd(struct soft_segment_descriptor *ssd, 1626 struct system_segment_descriptor *sd) 1627 { 1628 1629 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1630 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1631 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1632 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1633 sd->sd_type = ssd->ssd_type; 1634 sd->sd_dpl = ssd->ssd_dpl; 1635 sd->sd_p = ssd->ssd_p; 1636 sd->sd_gran = ssd->ssd_gran; 1637 } 1638 1639 /* 1640 * Populate the (physmap) array with base/bound pairs describing the 1641 * available physical memory in the system, then test this memory and 1642 * build the phys_avail array describing the actually-available memory. 1643 * 1644 * If we cannot accurately determine the physical memory map, then use 1645 * value from the 0xE801 call, and failing that, the RTC. 1646 * 1647 * Total memory size may be set by the kernel environment variable 1648 * hw.physmem or the compile-time define MAXMEM. 1649 * 1650 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1651 * of PAGE_SIZE. This also greatly reduces the memory test time 1652 * which would otherwise be excessive on machines with > 8G of ram. 1653 * 1654 * XXX first should be vm_paddr_t. 1655 */ 1656 1657 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1658 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1659 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1660 1661 vm_paddr_t physmap[PHYSMAP_SIZE]; 1662 struct bios_smap *smapbase, *smap, *smapend; 1663 struct efi_map_header *efihdrbase; 1664 u_int32_t smapsize; 1665 1666 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1667 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1668 1669 static void 1670 add_smap_entries(int *physmap_idx) 1671 { 1672 int i; 1673 1674 smapsize = *((u_int32_t *)smapbase - 1); 1675 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1676 1677 for (smap = smapbase; smap < smapend; smap++) { 1678 if (boothowto & RB_VERBOSE) 1679 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1680 smap->type, smap->base, smap->length); 1681 1682 if (smap->type != SMAP_TYPE_MEMORY) 1683 continue; 1684 1685 if (smap->length == 0) 1686 continue; 1687 1688 for (i = 0; i <= *physmap_idx; i += 2) { 1689 if (smap->base < physmap[i + 1]) { 1690 if (boothowto & RB_VERBOSE) { 1691 kprintf("Overlapping or non-monotonic " 1692 "memory region, ignoring " 1693 "second region\n"); 1694 } 1695 break; 1696 } 1697 } 1698 if (i <= *physmap_idx) 1699 continue; 1700 1701 Realmem += smap->length; 1702 1703 if (smap->base == physmap[*physmap_idx + 1]) { 1704 physmap[*physmap_idx + 1] += smap->length; 1705 continue; 1706 } 1707 1708 *physmap_idx += 2; 1709 if (*physmap_idx == PHYSMAP_SIZE) { 1710 kprintf("Too many segments in the physical " 1711 "address map, giving up\n"); 1712 break; 1713 } 1714 physmap[*physmap_idx] = smap->base; 1715 physmap[*physmap_idx + 1] = smap->base + smap->length; 1716 } 1717 } 1718 1719 static void 1720 add_efi_map_entries(int *physmap_idx) 1721 { 1722 struct efi_md *map, *p; 1723 const char *type; 1724 size_t efisz; 1725 int i, ndesc; 1726 1727 static const char *types[] = { 1728 "Reserved", 1729 "LoaderCode", 1730 "LoaderData", 1731 "BootServicesCode", 1732 "BootServicesData", 1733 "RuntimeServicesCode", 1734 "RuntimeServicesData", 1735 "ConventionalMemory", 1736 "UnusableMemory", 1737 "ACPIReclaimMemory", 1738 "ACPIMemoryNVS", 1739 "MemoryMappedIO", 1740 "MemoryMappedIOPortSpace", 1741 "PalCode" 1742 }; 1743 1744 /* 1745 * Memory map data provided by UEFI via the GetMemoryMap 1746 * Boot Services API. 1747 */ 1748 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1749 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1750 1751 if (efihdrbase->descriptor_size == 0) 1752 return; 1753 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1754 1755 if (boothowto & RB_VERBOSE) 1756 kprintf("%23s %12s %12s %8s %4s\n", 1757 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1758 1759 for (i = 0, p = map; i < ndesc; i++, 1760 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1761 if (boothowto & RB_VERBOSE) { 1762 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1763 type = types[p->md_type]; 1764 else 1765 type = "<INVALID>"; 1766 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1767 p->md_virt, p->md_pages); 1768 if (p->md_attr & EFI_MD_ATTR_UC) 1769 kprintf("UC "); 1770 if (p->md_attr & EFI_MD_ATTR_WC) 1771 kprintf("WC "); 1772 if (p->md_attr & EFI_MD_ATTR_WT) 1773 kprintf("WT "); 1774 if (p->md_attr & EFI_MD_ATTR_WB) 1775 kprintf("WB "); 1776 if (p->md_attr & EFI_MD_ATTR_UCE) 1777 kprintf("UCE "); 1778 if (p->md_attr & EFI_MD_ATTR_WP) 1779 kprintf("WP "); 1780 if (p->md_attr & EFI_MD_ATTR_RP) 1781 kprintf("RP "); 1782 if (p->md_attr & EFI_MD_ATTR_XP) 1783 kprintf("XP "); 1784 if (p->md_attr & EFI_MD_ATTR_RT) 1785 kprintf("RUNTIME"); 1786 kprintf("\n"); 1787 } 1788 1789 switch (p->md_type) { 1790 case EFI_MD_TYPE_CODE: 1791 case EFI_MD_TYPE_DATA: 1792 case EFI_MD_TYPE_BS_CODE: 1793 case EFI_MD_TYPE_BS_DATA: 1794 case EFI_MD_TYPE_FREE: 1795 /* 1796 * We're allowed to use any entry with these types. 1797 */ 1798 break; 1799 default: 1800 continue; 1801 } 1802 1803 Realmem += p->md_pages * PAGE_SIZE; 1804 1805 if (p->md_phys == physmap[*physmap_idx + 1]) { 1806 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1807 continue; 1808 } 1809 1810 *physmap_idx += 2; 1811 if (*physmap_idx == PHYSMAP_SIZE) { 1812 kprintf("Too many segments in the physical " 1813 "address map, giving up\n"); 1814 break; 1815 } 1816 physmap[*physmap_idx] = p->md_phys; 1817 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1818 } 1819 } 1820 1821 struct fb_info efi_fb_info; 1822 static int have_efi_framebuffer = 0; 1823 1824 static void 1825 efi_fb_init_vaddr(int direct_map) 1826 { 1827 uint64_t sz; 1828 vm_offset_t addr, v; 1829 1830 v = efi_fb_info.vaddr; 1831 sz = efi_fb_info.stride * efi_fb_info.height; 1832 1833 if (direct_map) { 1834 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1835 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1836 efi_fb_info.vaddr = addr; 1837 } else { 1838 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1839 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1840 } 1841 } 1842 1843 int 1844 probe_efi_fb(int early) 1845 { 1846 struct efi_fb *efifb; 1847 caddr_t kmdp; 1848 1849 if (have_efi_framebuffer) { 1850 if (!early && 1851 (efi_fb_info.vaddr == 0 || 1852 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 1853 efi_fb_init_vaddr(0); 1854 return 0; 1855 } 1856 1857 kmdp = preload_search_by_type("elf kernel"); 1858 if (kmdp == NULL) 1859 kmdp = preload_search_by_type("elf64 kernel"); 1860 efifb = (struct efi_fb *)preload_search_info(kmdp, 1861 MODINFO_METADATA | MODINFOMD_EFI_FB); 1862 if (efifb == NULL) 1863 return 1; 1864 1865 have_efi_framebuffer = 1; 1866 1867 efi_fb_info.is_vga_boot_display = 1; 1868 efi_fb_info.width = efifb->fb_width; 1869 efi_fb_info.height = efifb->fb_height; 1870 efi_fb_info.stride = efifb->fb_stride * 4; 1871 efi_fb_info.depth = 32; 1872 efi_fb_info.paddr = efifb->fb_addr; 1873 if (early) { 1874 efi_fb_info.vaddr = 0; 1875 } else { 1876 efi_fb_init_vaddr(0); 1877 } 1878 efi_fb_info.fbops.fb_set_par = NULL; 1879 efi_fb_info.fbops.fb_blank = NULL; 1880 efi_fb_info.fbops.fb_debug_enter = NULL; 1881 efi_fb_info.device = NULL; 1882 1883 return 0; 1884 } 1885 1886 static void 1887 efifb_startup(void *arg) 1888 { 1889 probe_efi_fb(0); 1890 } 1891 1892 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 1893 1894 static void 1895 getmemsize(caddr_t kmdp, u_int64_t first) 1896 { 1897 int off, physmap_idx, pa_indx, da_indx; 1898 int i, j; 1899 vm_paddr_t pa; 1900 vm_paddr_t msgbuf_size; 1901 u_long physmem_tunable; 1902 pt_entry_t *pte; 1903 quad_t dcons_addr, dcons_size; 1904 1905 bzero(physmap, sizeof(physmap)); 1906 physmap_idx = 0; 1907 1908 /* 1909 * get memory map from INT 15:E820, kindly supplied by the loader. 1910 * 1911 * subr_module.c says: 1912 * "Consumer may safely assume that size value precedes data." 1913 * ie: an int32_t immediately precedes smap. 1914 */ 1915 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 1916 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1917 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1918 MODINFO_METADATA | MODINFOMD_SMAP); 1919 if (smapbase == NULL && efihdrbase == NULL) 1920 panic("No BIOS smap or EFI map info from loader!"); 1921 1922 if (efihdrbase == NULL) 1923 add_smap_entries(&physmap_idx); 1924 else 1925 add_efi_map_entries(&physmap_idx); 1926 1927 base_memory = physmap[1] / 1024; 1928 /* make hole for AP bootstrap code */ 1929 physmap[1] = mp_bootaddress(base_memory); 1930 1931 /* Save EBDA address, if any */ 1932 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1933 ebda_addr <<= 4; 1934 1935 /* 1936 * Maxmem isn't the "maximum memory", it's one larger than the 1937 * highest page of the physical address space. It should be 1938 * called something like "Maxphyspage". We may adjust this 1939 * based on ``hw.physmem'' and the results of the memory test. 1940 */ 1941 Maxmem = atop(physmap[physmap_idx + 1]); 1942 1943 #ifdef MAXMEM 1944 Maxmem = MAXMEM / 4; 1945 #endif 1946 1947 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1948 Maxmem = atop(physmem_tunable); 1949 1950 /* 1951 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1952 * in the system. 1953 */ 1954 if (Maxmem > atop(physmap[physmap_idx + 1])) 1955 Maxmem = atop(physmap[physmap_idx + 1]); 1956 1957 /* 1958 * Blowing out the DMAP will blow up the system. 1959 */ 1960 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1961 kprintf("Limiting Maxmem due to DMAP size\n"); 1962 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1963 } 1964 1965 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1966 (boothowto & RB_VERBOSE)) { 1967 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1968 } 1969 1970 /* 1971 * Call pmap initialization to make new kernel address space 1972 * 1973 * Mask off page 0. 1974 */ 1975 pmap_bootstrap(&first); 1976 physmap[0] = PAGE_SIZE; 1977 1978 /* 1979 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1980 * exceeding Maxmem. 1981 */ 1982 for (i = j = 0; i <= physmap_idx; i += 2) { 1983 if (physmap[i+1] > ptoa(Maxmem)) 1984 physmap[i+1] = ptoa(Maxmem); 1985 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1986 ~PHYSMAP_ALIGN_MASK; 1987 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1988 1989 physmap[j] = physmap[i]; 1990 physmap[j+1] = physmap[i+1]; 1991 1992 if (physmap[i] < physmap[i+1]) 1993 j += 2; 1994 } 1995 physmap_idx = j - 2; 1996 1997 /* 1998 * Align anything else used in the validation loop. 1999 */ 2000 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2001 2002 /* 2003 * Size up each available chunk of physical memory. 2004 */ 2005 pa_indx = 0; 2006 da_indx = 0; 2007 phys_avail[pa_indx].phys_beg = physmap[0]; 2008 phys_avail[pa_indx].phys_end = physmap[0]; 2009 dump_avail[da_indx].phys_beg = 0; 2010 dump_avail[da_indx].phys_end = physmap[0]; 2011 pte = CMAP1; 2012 2013 /* 2014 * Get dcons buffer address 2015 */ 2016 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2017 kgetenv_quad("dcons.size", &dcons_size) == 0) 2018 dcons_addr = 0; 2019 2020 /* 2021 * Validate the physical memory. The physical memory segments 2022 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2023 * of PAGE_SIZE. 2024 */ 2025 for (i = 0; i <= physmap_idx; i += 2) { 2026 vm_paddr_t end; 2027 vm_paddr_t incr = PHYSMAP_ALIGN; 2028 2029 end = physmap[i + 1]; 2030 2031 for (pa = physmap[i]; pa < end; pa += incr) { 2032 int page_bad, full; 2033 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2034 uint64_t tmp; 2035 2036 incr = PHYSMAP_ALIGN; 2037 full = FALSE; 2038 2039 /* 2040 * block out kernel memory as not available. 2041 */ 2042 if (pa >= 0x200000 && pa < first) 2043 goto do_dump_avail; 2044 2045 /* 2046 * block out dcons buffer 2047 */ 2048 if (dcons_addr > 0 2049 && pa >= trunc_page(dcons_addr) 2050 && pa < dcons_addr + dcons_size) { 2051 goto do_dump_avail; 2052 } 2053 2054 page_bad = FALSE; 2055 2056 /* 2057 * Always test the first and last block supplied in 2058 * the map entry, but it just takes too long to run 2059 * the test these days and we already have to skip 2060 * pages. Handwave it on PHYSMAP_HANDWAVE boundaries. 2061 */ 2062 if (pa != physmap[i]) { 2063 vm_paddr_t bytes = end - pa; 2064 if ((pa & PHYSMAP_HANDWAVE_MASK) == 0 && 2065 bytes >= PHYSMAP_HANDWAVE + PHYSMAP_ALIGN) { 2066 incr = PHYSMAP_HANDWAVE; 2067 goto handwaved; 2068 } 2069 } 2070 2071 /* 2072 * map page into kernel: valid, read/write,non-cacheable 2073 */ 2074 *pte = pa | 2075 kernel_pmap.pmap_bits[PG_V_IDX] | 2076 kernel_pmap.pmap_bits[PG_RW_IDX] | 2077 kernel_pmap.pmap_bits[PG_N_IDX]; 2078 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2079 cpu_mfence(); 2080 2081 tmp = *ptr; 2082 /* 2083 * Test for alternating 1's and 0's 2084 */ 2085 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2086 cpu_mfence(); 2087 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2088 page_bad = TRUE; 2089 /* 2090 * Test for alternating 0's and 1's 2091 */ 2092 *ptr = 0x5555555555555555LLU; 2093 cpu_mfence(); 2094 if (*ptr != 0x5555555555555555LLU) 2095 page_bad = TRUE; 2096 /* 2097 * Test for all 1's 2098 */ 2099 *ptr = 0xffffffffffffffffLLU; 2100 cpu_mfence(); 2101 if (*ptr != 0xffffffffffffffffLLU) 2102 page_bad = TRUE; 2103 /* 2104 * Test for all 0's 2105 */ 2106 *ptr = 0x0; 2107 cpu_mfence(); 2108 if (*ptr != 0x0) 2109 page_bad = TRUE; 2110 /* 2111 * Restore original value. 2112 */ 2113 *ptr = tmp; 2114 handwaved: 2115 2116 /* 2117 * Adjust array of valid/good pages. 2118 */ 2119 if (page_bad == TRUE) 2120 continue; 2121 2122 /* 2123 * If this good page is a continuation of the 2124 * previous set of good pages, then just increase 2125 * the end pointer. Otherwise start a new chunk. 2126 * Note that "end" points one higher than end, 2127 * making the range >= start and < end. 2128 * If we're also doing a speculative memory 2129 * test and we at or past the end, bump up Maxmem 2130 * so that we keep going. The first bad page 2131 * will terminate the loop. 2132 */ 2133 if (phys_avail[pa_indx].phys_end == pa) { 2134 phys_avail[pa_indx].phys_end += incr; 2135 } else { 2136 ++pa_indx; 2137 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2138 kprintf( 2139 "Too many holes in the physical address space, giving up\n"); 2140 --pa_indx; 2141 full = TRUE; 2142 goto do_dump_avail; 2143 } 2144 phys_avail[pa_indx].phys_beg = pa; 2145 phys_avail[pa_indx].phys_end = pa + incr; 2146 } 2147 physmem += incr / PAGE_SIZE; 2148 do_dump_avail: 2149 if (dump_avail[da_indx].phys_end == pa) { 2150 dump_avail[da_indx].phys_end += incr; 2151 } else { 2152 ++da_indx; 2153 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2154 --da_indx; 2155 goto do_next; 2156 } 2157 dump_avail[da_indx].phys_beg = pa; 2158 dump_avail[da_indx].phys_end = pa + incr; 2159 } 2160 do_next: 2161 if (full) 2162 break; 2163 } 2164 } 2165 *pte = 0; 2166 cpu_invltlb(); 2167 cpu_mfence(); 2168 2169 /* 2170 * The last chunk must contain at least one page plus the message 2171 * buffer to avoid complicating other code (message buffer address 2172 * calculation, etc.). 2173 */ 2174 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2175 2176 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2177 phys_avail[pa_indx].phys_end) { 2178 physmem -= atop(phys_avail[pa_indx].phys_end - 2179 phys_avail[pa_indx].phys_beg); 2180 phys_avail[pa_indx].phys_beg = 0; 2181 phys_avail[pa_indx].phys_end = 0; 2182 --pa_indx; 2183 } 2184 2185 Maxmem = atop(phys_avail[pa_indx].phys_end); 2186 2187 /* Trim off space for the message buffer. */ 2188 phys_avail[pa_indx].phys_end -= msgbuf_size; 2189 2190 avail_end = phys_avail[pa_indx].phys_end; 2191 2192 /* Map the message buffer. */ 2193 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2194 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2195 } 2196 /* Try to get EFI framebuffer working as early as possible */ 2197 if (have_efi_framebuffer) 2198 efi_fb_init_vaddr(1); 2199 } 2200 2201 struct machintr_abi MachIntrABI; 2202 2203 /* 2204 * IDT VECTORS: 2205 * 0 Divide by zero 2206 * 1 Debug 2207 * 2 NMI 2208 * 3 BreakPoint 2209 * 4 OverFlow 2210 * 5 Bound-Range 2211 * 6 Invalid OpCode 2212 * 7 Device Not Available (x87) 2213 * 8 Double-Fault 2214 * 9 Coprocessor Segment overrun (unsupported, reserved) 2215 * 10 Invalid-TSS 2216 * 11 Segment not present 2217 * 12 Stack 2218 * 13 General Protection 2219 * 14 Page Fault 2220 * 15 Reserved 2221 * 16 x87 FP Exception pending 2222 * 17 Alignment Check 2223 * 18 Machine Check 2224 * 19 SIMD floating point 2225 * 20-31 reserved 2226 * 32-255 INTn/external sources 2227 */ 2228 u_int64_t 2229 hammer_time(u_int64_t modulep, u_int64_t physfree) 2230 { 2231 caddr_t kmdp; 2232 int gsel_tss, x, cpu; 2233 #if 0 /* JG */ 2234 int metadata_missing, off; 2235 #endif 2236 struct mdglobaldata *gd; 2237 u_int64_t msr; 2238 2239 /* 2240 * Prevent lowering of the ipl if we call tsleep() early. 2241 */ 2242 gd = &CPU_prvspace[0]->mdglobaldata; 2243 bzero(gd, sizeof(*gd)); 2244 2245 /* 2246 * Note: on both UP and SMP curthread must be set non-NULL 2247 * early in the boot sequence because the system assumes 2248 * that 'curthread' is never NULL. 2249 */ 2250 2251 gd->mi.gd_curthread = &thread0; 2252 thread0.td_gd = &gd->mi; 2253 2254 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2255 2256 #if 0 /* JG */ 2257 metadata_missing = 0; 2258 if (bootinfo.bi_modulep) { 2259 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2260 preload_bootstrap_relocate(KERNBASE); 2261 } else { 2262 metadata_missing = 1; 2263 } 2264 if (bootinfo.bi_envp) 2265 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2266 #endif 2267 2268 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2269 preload_bootstrap_relocate(PTOV_OFFSET); 2270 kmdp = preload_search_by_type("elf kernel"); 2271 if (kmdp == NULL) 2272 kmdp = preload_search_by_type("elf64 kernel"); 2273 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2274 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2275 #ifdef DDB 2276 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2277 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2278 #endif 2279 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2280 2281 if (boothowto & RB_VERBOSE) 2282 bootverbose++; 2283 2284 /* 2285 * Default MachIntrABI to ICU 2286 */ 2287 MachIntrABI = MachIntrABI_ICU; 2288 2289 /* 2290 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask, 2291 * and ncpus_fit_mask remain 0. 2292 */ 2293 ncpus = 1; 2294 ncpus2 = 1; 2295 ncpus_fit = 1; 2296 /* Init basic tunables, hz etc */ 2297 init_param1(); 2298 2299 /* 2300 * make gdt memory segments 2301 */ 2302 gdt_segs[GPROC0_SEL].ssd_base = 2303 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss; 2304 2305 gd->mi.gd_prvspace = CPU_prvspace[0]; 2306 2307 for (x = 0; x < NGDT; x++) { 2308 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2309 ssdtosd(&gdt_segs[x], &gdt[x]); 2310 } 2311 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2312 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2313 2314 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2315 r_gdt.rd_base = (long) gdt; 2316 lgdt(&r_gdt); 2317 2318 wrmsr(MSR_FSBASE, 0); /* User value */ 2319 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2320 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2321 2322 mi_gdinit(&gd->mi, 0); 2323 cpu_gdinit(gd, 0); 2324 proc0paddr = proc0paddr_buff; 2325 mi_proc0init(&gd->mi, proc0paddr); 2326 safepri = TDPRI_MAX; 2327 2328 /* spinlocks and the BGL */ 2329 init_locks(); 2330 2331 /* exceptions */ 2332 for (x = 0; x < NIDT; x++) 2333 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2334 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2335 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2336 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2337 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2338 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2339 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2340 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2341 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2342 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2343 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2344 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2345 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2346 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2347 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2348 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2349 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2350 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2351 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2352 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2353 2354 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2355 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2356 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2357 } 2358 2359 lidt(&r_idt_arr[0]); 2360 2361 /* 2362 * Initialize the console before we print anything out. 2363 */ 2364 cninit(); 2365 2366 #if 0 /* JG */ 2367 if (metadata_missing) 2368 kprintf("WARNING: loader(8) metadata is missing!\n"); 2369 #endif 2370 2371 #if NISA >0 2372 elcr_probe(); 2373 isa_defaultirq(); 2374 #endif 2375 rand_initialize(); 2376 2377 /* 2378 * Initialize IRQ mapping 2379 * 2380 * NOTE: 2381 * SHOULD be after elcr_probe() 2382 */ 2383 MachIntrABI_ICU.initmap(); 2384 MachIntrABI_IOAPIC.initmap(); 2385 2386 #ifdef DDB 2387 kdb_init(); 2388 if (boothowto & RB_KDB) 2389 Debugger("Boot flags requested debugger"); 2390 #endif 2391 2392 #if 0 /* JG */ 2393 finishidentcpu(); /* Final stage of CPU initialization */ 2394 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2395 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2396 #endif 2397 identify_cpu(); /* Final stage of CPU initialization */ 2398 initializecpu(0); /* Initialize CPU registers */ 2399 2400 /* 2401 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2402 * because the cpu does significant power management in MWAIT 2403 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2404 * 2405 * On modern AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2406 * significant power management only when using ACPI halt mode. 2407 * 2408 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2409 * is needed to reduce power consumption, but wakeup times are often 2410 * too long longer. 2411 */ 2412 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2413 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2414 cpu_idle_hlt = 1; 2415 } 2416 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2417 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2418 /* Ryzen or later */ 2419 cpu_idle_hlt = 3; 2420 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2421 /* Bobcat or later */ 2422 cpu_idle_hlt = 3; 2423 } 2424 } 2425 2426 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2427 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2428 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2429 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2430 2431 /* 2432 * Some of the virtual machines do not work w/ I/O APIC 2433 * enabled. If the user does not explicitly enable or 2434 * disable the I/O APIC (ioapic_enable < 0), then we 2435 * disable I/O APIC on all virtual machines. 2436 * 2437 * NOTE: 2438 * This must be done after identify_cpu(), which sets 2439 * 'cpu_feature2' 2440 */ 2441 if (ioapic_enable < 0) { 2442 if (cpu_feature2 & CPUID2_VMM) 2443 ioapic_enable = 0; 2444 else 2445 ioapic_enable = 1; 2446 } 2447 2448 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2449 gd->gd_common_tss.tss_rsp0 = 2450 (register_t)(thread0.td_kstack + 2451 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 2452 /* Ensure the stack is aligned to 16 bytes */ 2453 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 2454 2455 /* double fault stack */ 2456 gd->gd_common_tss.tss_ist1 = 2457 (long)&gd->mi.gd_prvspace->idlestack[ 2458 sizeof(gd->mi.gd_prvspace->idlestack)]; 2459 2460 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2461 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 2462 2463 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2464 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2465 gd->gd_common_tssd = *gd->gd_tss_gdt; 2466 ltr(gsel_tss); 2467 2468 /* Set up the fast syscall stuff */ 2469 msr = rdmsr(MSR_EFER) | EFER_SCE; 2470 wrmsr(MSR_EFER, msr); 2471 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2472 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2473 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2474 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2475 wrmsr(MSR_STAR, msr); 2476 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2477 2478 getmemsize(kmdp, physfree); 2479 init_param2(physmem); 2480 2481 /* now running on new page tables, configured,and u/iom is accessible */ 2482 2483 /* Map the message buffer. */ 2484 #if 0 /* JG */ 2485 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2486 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2487 #endif 2488 2489 msgbufinit(msgbufp, MSGBUF_SIZE); 2490 2491 2492 /* transfer to user mode */ 2493 2494 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2495 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2496 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2497 2498 load_ds(_udatasel); 2499 load_es(_udatasel); 2500 load_fs(_udatasel); 2501 2502 /* setup proc 0's pcb */ 2503 thread0.td_pcb->pcb_flags = 0; 2504 thread0.td_pcb->pcb_cr3 = KPML4phys; 2505 thread0.td_pcb->pcb_ext = NULL; 2506 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2507 2508 /* Location of kernel stack for locore */ 2509 return ((u_int64_t)thread0.td_pcb); 2510 } 2511 2512 /* 2513 * Initialize machine-dependant portions of the global data structure. 2514 * Note that the global data area and cpu0's idlestack in the private 2515 * data space were allocated in locore. 2516 * 2517 * Note: the idlethread's cpl is 0 2518 * 2519 * WARNING! Called from early boot, 'mycpu' may not work yet. 2520 */ 2521 void 2522 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2523 { 2524 if (cpu) 2525 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2526 2527 lwkt_init_thread(&gd->mi.gd_idlethread, 2528 gd->mi.gd_prvspace->idlestack, 2529 sizeof(gd->mi.gd_prvspace->idlestack), 2530 0, &gd->mi); 2531 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2532 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2533 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2534 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2535 } 2536 2537 /* 2538 * We only have to check for DMAP bounds, the globaldata space is 2539 * actually part of the kernel_map so we don't have to waste time 2540 * checking CPU_prvspace[*]. 2541 */ 2542 int 2543 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2544 { 2545 #if 0 2546 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2547 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2548 return (TRUE); 2549 } 2550 #endif 2551 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2552 return (TRUE); 2553 return (FALSE); 2554 } 2555 2556 struct globaldata * 2557 globaldata_find(int cpu) 2558 { 2559 KKASSERT(cpu >= 0 && cpu < ncpus); 2560 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2561 } 2562 2563 /* 2564 * This path should be safe from the SYSRET issue because only stopped threads 2565 * can have their %rip adjusted this way (and all heavy weight thread switches 2566 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2567 * convoluted so add a safety by forcing %rip to be cannonical. 2568 */ 2569 int 2570 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2571 { 2572 if (addr & 0x0000800000000000LLU) 2573 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2574 else 2575 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2576 return (0); 2577 } 2578 2579 int 2580 ptrace_single_step(struct lwp *lp) 2581 { 2582 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2583 return (0); 2584 } 2585 2586 int 2587 fill_regs(struct lwp *lp, struct reg *regs) 2588 { 2589 struct trapframe *tp; 2590 2591 if ((tp = lp->lwp_md.md_regs) == NULL) 2592 return EINVAL; 2593 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2594 return (0); 2595 } 2596 2597 int 2598 set_regs(struct lwp *lp, struct reg *regs) 2599 { 2600 struct trapframe *tp; 2601 2602 tp = lp->lwp_md.md_regs; 2603 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2604 !CS_SECURE(regs->r_cs)) 2605 return (EINVAL); 2606 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2607 clear_quickret(); 2608 return (0); 2609 } 2610 2611 static void 2612 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2613 { 2614 struct env87 *penv_87 = &sv_87->sv_env; 2615 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2616 int i; 2617 2618 /* FPU control/status */ 2619 penv_87->en_cw = penv_xmm->en_cw; 2620 penv_87->en_sw = penv_xmm->en_sw; 2621 penv_87->en_tw = penv_xmm->en_tw; 2622 penv_87->en_fip = penv_xmm->en_fip; 2623 penv_87->en_fcs = penv_xmm->en_fcs; 2624 penv_87->en_opcode = penv_xmm->en_opcode; 2625 penv_87->en_foo = penv_xmm->en_foo; 2626 penv_87->en_fos = penv_xmm->en_fos; 2627 2628 /* FPU registers */ 2629 for (i = 0; i < 8; ++i) 2630 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2631 } 2632 2633 static void 2634 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2635 { 2636 struct env87 *penv_87 = &sv_87->sv_env; 2637 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2638 int i; 2639 2640 /* FPU control/status */ 2641 penv_xmm->en_cw = penv_87->en_cw; 2642 penv_xmm->en_sw = penv_87->en_sw; 2643 penv_xmm->en_tw = penv_87->en_tw; 2644 penv_xmm->en_fip = penv_87->en_fip; 2645 penv_xmm->en_fcs = penv_87->en_fcs; 2646 penv_xmm->en_opcode = penv_87->en_opcode; 2647 penv_xmm->en_foo = penv_87->en_foo; 2648 penv_xmm->en_fos = penv_87->en_fos; 2649 2650 /* FPU registers */ 2651 for (i = 0; i < 8; ++i) 2652 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2653 } 2654 2655 int 2656 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2657 { 2658 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2659 return EINVAL; 2660 if (cpu_fxsr) { 2661 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2662 (struct save87 *)fpregs); 2663 return (0); 2664 } 2665 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2666 return (0); 2667 } 2668 2669 int 2670 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2671 { 2672 if (cpu_fxsr) { 2673 set_fpregs_xmm((struct save87 *)fpregs, 2674 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2675 return (0); 2676 } 2677 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2678 return (0); 2679 } 2680 2681 int 2682 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2683 { 2684 struct pcb *pcb; 2685 2686 if (lp == NULL) { 2687 dbregs->dr[0] = rdr0(); 2688 dbregs->dr[1] = rdr1(); 2689 dbregs->dr[2] = rdr2(); 2690 dbregs->dr[3] = rdr3(); 2691 dbregs->dr[4] = rdr4(); 2692 dbregs->dr[5] = rdr5(); 2693 dbregs->dr[6] = rdr6(); 2694 dbregs->dr[7] = rdr7(); 2695 return (0); 2696 } 2697 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2698 return EINVAL; 2699 dbregs->dr[0] = pcb->pcb_dr0; 2700 dbregs->dr[1] = pcb->pcb_dr1; 2701 dbregs->dr[2] = pcb->pcb_dr2; 2702 dbregs->dr[3] = pcb->pcb_dr3; 2703 dbregs->dr[4] = 0; 2704 dbregs->dr[5] = 0; 2705 dbregs->dr[6] = pcb->pcb_dr6; 2706 dbregs->dr[7] = pcb->pcb_dr7; 2707 return (0); 2708 } 2709 2710 int 2711 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2712 { 2713 if (lp == NULL) { 2714 load_dr0(dbregs->dr[0]); 2715 load_dr1(dbregs->dr[1]); 2716 load_dr2(dbregs->dr[2]); 2717 load_dr3(dbregs->dr[3]); 2718 load_dr4(dbregs->dr[4]); 2719 load_dr5(dbregs->dr[5]); 2720 load_dr6(dbregs->dr[6]); 2721 load_dr7(dbregs->dr[7]); 2722 } else { 2723 struct pcb *pcb; 2724 struct ucred *ucred; 2725 int i; 2726 uint64_t mask1, mask2; 2727 2728 /* 2729 * Don't let an illegal value for dr7 get set. Specifically, 2730 * check for undefined settings. Setting these bit patterns 2731 * result in undefined behaviour and can lead to an unexpected 2732 * TRCTRAP. 2733 */ 2734 /* JG this loop looks unreadable */ 2735 /* Check 4 2-bit fields for invalid patterns. 2736 * These fields are R/Wi, for i = 0..3 2737 */ 2738 /* Is 10 in LENi allowed when running in compatibility mode? */ 2739 /* Pattern 10 in R/Wi might be used to indicate 2740 * breakpoint on I/O. Further analysis should be 2741 * carried to decide if it is safe and useful to 2742 * provide access to that capability 2743 */ 2744 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2745 i++, mask1 <<= 4, mask2 <<= 4) 2746 if ((dbregs->dr[7] & mask1) == mask2) 2747 return (EINVAL); 2748 2749 pcb = lp->lwp_thread->td_pcb; 2750 ucred = lp->lwp_proc->p_ucred; 2751 2752 /* 2753 * Don't let a process set a breakpoint that is not within the 2754 * process's address space. If a process could do this, it 2755 * could halt the system by setting a breakpoint in the kernel 2756 * (if ddb was enabled). Thus, we need to check to make sure 2757 * that no breakpoints are being enabled for addresses outside 2758 * process's address space, unless, perhaps, we were called by 2759 * uid 0. 2760 * 2761 * XXX - what about when the watched area of the user's 2762 * address space is written into from within the kernel 2763 * ... wouldn't that still cause a breakpoint to be generated 2764 * from within kernel mode? 2765 */ 2766 2767 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2768 if (dbregs->dr[7] & 0x3) { 2769 /* dr0 is enabled */ 2770 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2771 return (EINVAL); 2772 } 2773 2774 if (dbregs->dr[7] & (0x3<<2)) { 2775 /* dr1 is enabled */ 2776 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2777 return (EINVAL); 2778 } 2779 2780 if (dbregs->dr[7] & (0x3<<4)) { 2781 /* dr2 is enabled */ 2782 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2783 return (EINVAL); 2784 } 2785 2786 if (dbregs->dr[7] & (0x3<<6)) { 2787 /* dr3 is enabled */ 2788 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2789 return (EINVAL); 2790 } 2791 } 2792 2793 pcb->pcb_dr0 = dbregs->dr[0]; 2794 pcb->pcb_dr1 = dbregs->dr[1]; 2795 pcb->pcb_dr2 = dbregs->dr[2]; 2796 pcb->pcb_dr3 = dbregs->dr[3]; 2797 pcb->pcb_dr6 = dbregs->dr[6]; 2798 pcb->pcb_dr7 = dbregs->dr[7]; 2799 2800 pcb->pcb_flags |= PCB_DBREGS; 2801 } 2802 2803 return (0); 2804 } 2805 2806 /* 2807 * Return > 0 if a hardware breakpoint has been hit, and the 2808 * breakpoint was in user space. Return 0, otherwise. 2809 */ 2810 int 2811 user_dbreg_trap(void) 2812 { 2813 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2814 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2815 int nbp; /* number of breakpoints that triggered */ 2816 caddr_t addr[4]; /* breakpoint addresses */ 2817 int i; 2818 2819 dr7 = rdr7(); 2820 if ((dr7 & 0xff) == 0) { 2821 /* 2822 * all GE and LE bits in the dr7 register are zero, 2823 * thus the trap couldn't have been caused by the 2824 * hardware debug registers 2825 */ 2826 return 0; 2827 } 2828 2829 nbp = 0; 2830 dr6 = rdr6(); 2831 bp = dr6 & 0xf; 2832 2833 if (bp == 0) { 2834 /* 2835 * None of the breakpoint bits are set meaning this 2836 * trap was not caused by any of the debug registers 2837 */ 2838 return 0; 2839 } 2840 2841 /* 2842 * at least one of the breakpoints were hit, check to see 2843 * which ones and if any of them are user space addresses 2844 */ 2845 2846 if (bp & 0x01) { 2847 addr[nbp++] = (caddr_t)rdr0(); 2848 } 2849 if (bp & 0x02) { 2850 addr[nbp++] = (caddr_t)rdr1(); 2851 } 2852 if (bp & 0x04) { 2853 addr[nbp++] = (caddr_t)rdr2(); 2854 } 2855 if (bp & 0x08) { 2856 addr[nbp++] = (caddr_t)rdr3(); 2857 } 2858 2859 for (i=0; i<nbp; i++) { 2860 if (addr[i] < 2861 (caddr_t)VM_MAX_USER_ADDRESS) { 2862 /* 2863 * addr[i] is in user space 2864 */ 2865 return nbp; 2866 } 2867 } 2868 2869 /* 2870 * None of the breakpoints are in user space. 2871 */ 2872 return 0; 2873 } 2874 2875 2876 #ifndef DDB 2877 void 2878 Debugger(const char *msg) 2879 { 2880 kprintf("Debugger(\"%s\") called.\n", msg); 2881 } 2882 #endif /* no DDB */ 2883 2884 #ifdef DDB 2885 2886 /* 2887 * Provide inb() and outb() as functions. They are normally only 2888 * available as macros calling inlined functions, thus cannot be 2889 * called inside DDB. 2890 * 2891 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2892 */ 2893 2894 #undef inb 2895 #undef outb 2896 2897 /* silence compiler warnings */ 2898 u_char inb(u_int); 2899 void outb(u_int, u_char); 2900 2901 u_char 2902 inb(u_int port) 2903 { 2904 u_char data; 2905 /* 2906 * We use %%dx and not %1 here because i/o is done at %dx and not at 2907 * %edx, while gcc generates inferior code (movw instead of movl) 2908 * if we tell it to load (u_short) port. 2909 */ 2910 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2911 return (data); 2912 } 2913 2914 void 2915 outb(u_int port, u_char data) 2916 { 2917 u_char al; 2918 /* 2919 * Use an unnecessary assignment to help gcc's register allocator. 2920 * This make a large difference for gcc-1.40 and a tiny difference 2921 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2922 * best results. gcc-2.6.0 can't handle this. 2923 */ 2924 al = data; 2925 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2926 } 2927 2928 #endif /* DDB */ 2929 2930 2931 2932 /* 2933 * initialize all the SMP locks 2934 */ 2935 2936 /* critical region when masking or unmasking interupts */ 2937 struct spinlock_deprecated imen_spinlock; 2938 2939 /* lock region used by kernel profiling */ 2940 struct spinlock_deprecated mcount_spinlock; 2941 2942 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2943 struct spinlock_deprecated com_spinlock; 2944 2945 /* lock regions around the clock hardware */ 2946 struct spinlock_deprecated clock_spinlock; 2947 2948 static void 2949 init_locks(void) 2950 { 2951 /* 2952 * Get the initial mplock with a count of 1 for the BSP. 2953 * This uses a LOGICAL cpu ID, ie BSP == 0. 2954 */ 2955 cpu_get_initial_mplock(); 2956 /* DEPRECATED */ 2957 spin_init_deprecated(&mcount_spinlock); 2958 spin_init_deprecated(&imen_spinlock); 2959 spin_init_deprecated(&com_spinlock); 2960 spin_init_deprecated(&clock_spinlock); 2961 2962 /* our token pool needs to work early */ 2963 lwkt_token_pool_init(); 2964 } 2965 2966 boolean_t 2967 cpu_mwait_hint_valid(uint32_t hint) 2968 { 2969 int cx_idx, sub; 2970 2971 cx_idx = MWAIT_EAX_TO_CX(hint); 2972 if (cx_idx >= CPU_MWAIT_CX_MAX) 2973 return FALSE; 2974 2975 sub = MWAIT_EAX_TO_CX_SUB(hint); 2976 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 2977 return FALSE; 2978 2979 return TRUE; 2980 } 2981 2982 void 2983 cpu_mwait_cx_no_bmsts(void) 2984 { 2985 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 2986 } 2987 2988 void 2989 cpu_mwait_cx_no_bmarb(void) 2990 { 2991 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 2992 } 2993 2994 static int 2995 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 2996 { 2997 int old_cx_idx, sub = 0; 2998 2999 if (hint >= 0) { 3000 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3001 sub = MWAIT_EAX_TO_CX_SUB(hint); 3002 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3003 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3004 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3005 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3006 } else { 3007 old_cx_idx = CPU_MWAIT_CX_MAX; 3008 } 3009 3010 if (!CPU_MWAIT_HAS_CX) 3011 strlcpy(name, "NONE", namelen); 3012 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3013 strlcpy(name, "AUTO", namelen); 3014 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3015 strlcpy(name, "AUTODEEP", namelen); 3016 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3017 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3018 strlcpy(name, "INVALID", namelen); 3019 else 3020 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3021 3022 return old_cx_idx; 3023 } 3024 3025 static int 3026 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3027 { 3028 int cx_idx, sub, hint; 3029 char *ptr, *start; 3030 3031 if (allow_auto && strcmp(name, "AUTO") == 0) { 3032 hint = CPU_MWAIT_HINT_AUTO; 3033 cx_idx = CPU_MWAIT_C2; 3034 goto done; 3035 } 3036 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3037 hint = CPU_MWAIT_HINT_AUTODEEP; 3038 cx_idx = CPU_MWAIT_C3; 3039 goto done; 3040 } 3041 3042 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3043 return -1; 3044 start = &name[1]; 3045 ptr = NULL; 3046 3047 cx_idx = strtol(start, &ptr, 10); 3048 if (ptr == start || *ptr != '/') 3049 return -1; 3050 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3051 return -1; 3052 3053 start = ptr + 1; 3054 ptr = NULL; 3055 3056 sub = strtol(start, &ptr, 10); 3057 if (*ptr != '\0') 3058 return -1; 3059 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3060 return -1; 3061 3062 hint = MWAIT_EAX_HINT(cx_idx, sub); 3063 done: 3064 *hint0 = hint; 3065 return cx_idx; 3066 } 3067 3068 static int 3069 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3070 { 3071 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3072 return EOPNOTSUPP; 3073 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3074 int error; 3075 3076 error = cputimer_intr_powersave_addreq(); 3077 if (error) 3078 return error; 3079 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3080 cputimer_intr_powersave_remreq(); 3081 } 3082 return 0; 3083 } 3084 3085 static int 3086 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3087 boolean_t allow_auto) 3088 { 3089 int error, cx_idx, old_cx_idx, hint; 3090 char name[CPU_MWAIT_CX_NAMELEN]; 3091 3092 hint = *hint0; 3093 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3094 allow_auto); 3095 3096 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3097 if (error != 0 || req->newptr == NULL) 3098 return error; 3099 3100 if (!CPU_MWAIT_HAS_CX) 3101 return EOPNOTSUPP; 3102 3103 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3104 if (cx_idx < 0) 3105 return EINVAL; 3106 3107 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3108 if (error) 3109 return error; 3110 3111 *hint0 = hint; 3112 return 0; 3113 } 3114 3115 static int 3116 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3117 { 3118 int error, cx_idx, old_cx_idx, hint; 3119 char name[CPU_MWAIT_CX_NAMELEN]; 3120 3121 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3122 3123 hint = stat->hint; 3124 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3125 3126 strlcpy(name, cx_name, sizeof(name)); 3127 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3128 if (cx_idx < 0) 3129 return EINVAL; 3130 3131 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3132 if (error) 3133 return error; 3134 3135 stat->hint = hint; 3136 return 0; 3137 } 3138 3139 static int 3140 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3141 { 3142 int hint = cpu_mwait_halt_global; 3143 int error, cx_idx, cpu; 3144 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3145 3146 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3147 3148 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3149 if (error != 0 || req->newptr == NULL) 3150 return error; 3151 3152 if (!CPU_MWAIT_HAS_CX) 3153 return EOPNOTSUPP; 3154 3155 /* Save name for later per-cpu CX configuration */ 3156 strlcpy(cx_name, name, sizeof(cx_name)); 3157 3158 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3159 if (cx_idx < 0) 3160 return EINVAL; 3161 3162 /* Change per-cpu CX configuration */ 3163 for (cpu = 0; cpu < ncpus; ++cpu) { 3164 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3165 if (error) 3166 return error; 3167 } 3168 3169 cpu_mwait_halt_global = hint; 3170 return 0; 3171 } 3172 3173 static int 3174 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3175 { 3176 struct cpu_idle_stat *stat = arg1; 3177 int error; 3178 3179 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3180 &stat->hint, TRUE); 3181 return error; 3182 } 3183 3184 static int 3185 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3186 { 3187 int error; 3188 3189 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3190 &cpu_mwait_spin, FALSE); 3191 return error; 3192 } 3193 3194 /* 3195 * This manual debugging code is called unconditionally from Xtimer 3196 * (the per-cpu timer interrupt) whether the current thread is in a 3197 * critical section or not) and can be useful in tracking down lockups. 3198 * 3199 * NOTE: MANUAL DEBUG CODE 3200 */ 3201 #if 0 3202 static int saveticks[SMP_MAXCPU]; 3203 static int savecounts[SMP_MAXCPU]; 3204 #endif 3205 3206 void 3207 pcpu_timer_always(struct intrframe *frame) 3208 { 3209 #if 0 3210 globaldata_t gd = mycpu; 3211 int cpu = gd->gd_cpuid; 3212 char buf[64]; 3213 short *gptr; 3214 int i; 3215 3216 if (cpu <= 20) { 3217 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3218 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3219 ++gptr; 3220 3221 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3222 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3223 gd->gd_infomsg); 3224 for (i = 0; buf[i]; ++i) { 3225 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3226 } 3227 } 3228 #if 0 3229 if (saveticks[gd->gd_cpuid] != ticks) { 3230 saveticks[gd->gd_cpuid] = ticks; 3231 savecounts[gd->gd_cpuid] = 0; 3232 } 3233 ++savecounts[gd->gd_cpuid]; 3234 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3235 panic("cpud %d panicing on ticks failure", 3236 gd->gd_cpuid); 3237 } 3238 for (i = 0; i < ncpus; ++i) { 3239 int delta; 3240 if (saveticks[i] && panicstr == NULL) { 3241 delta = saveticks[i] - ticks; 3242 if (delta < -10 || delta > 10) { 3243 panic("cpu %d panicing on cpu %d watchdog", 3244 gd->gd_cpuid, i); 3245 } 3246 } 3247 } 3248 #endif 3249 #endif 3250 } 3251