1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_compat.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_directio.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_msgbuf.h" 52 #include "opt_swap.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysproto.h> 57 #include <sys/signalvar.h> 58 #include <sys/kernel.h> 59 #include <sys/linker.h> 60 #include <sys/malloc.h> 61 #include <sys/proc.h> 62 #include <sys/priv.h> 63 #include <sys/buf.h> 64 #include <sys/reboot.h> 65 #include <sys/mbuf.h> 66 #include <sys/msgbuf.h> 67 #include <sys/sysent.h> 68 #include <sys/sysctl.h> 69 #include <sys/vmmeter.h> 70 #include <sys/bus.h> 71 #include <sys/usched.h> 72 #include <sys/reg.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <sys/lock.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_page.h> 80 #include <vm/vm_map.h> 81 #include <vm/vm_pager.h> 82 #include <vm/vm_extern.h> 83 84 #include <sys/thread2.h> 85 #include <sys/mplock2.h> 86 #include <sys/mutex2.h> 87 88 #include <sys/user.h> 89 #include <sys/exec.h> 90 #include <sys/cons.h> 91 92 #include <ddb/ddb.h> 93 94 #include <machine/cpu.h> 95 #include <machine/clock.h> 96 #include <machine/specialreg.h> 97 #if JG 98 #include <machine/bootinfo.h> 99 #endif 100 #include <machine/md_var.h> 101 #include <machine/metadata.h> 102 #include <machine/pc/bios.h> 103 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 104 #include <machine/globaldata.h> /* CPU_prvspace */ 105 #include <machine/smp.h> 106 #ifdef PERFMON 107 #include <machine/perfmon.h> 108 #endif 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 112 #ifdef OLD_BUS_ARCH 113 #include <bus/isa/isa_device.h> 114 #endif 115 #include <machine_base/isa/isa_intr.h> 116 #include <bus/isa/rtc.h> 117 #include <sys/random.h> 118 #include <sys/ptrace.h> 119 #include <machine/sigframe.h> 120 121 #include <sys/machintr.h> 122 #include <machine_base/icu/icu_abi.h> 123 #include <machine_base/icu/elcr_var.h> 124 #include <machine_base/apic/lapic.h> 125 #include <machine_base/apic/ioapic.h> 126 #include <machine_base/apic/ioapic_abi.h> 127 #include <machine/mptable.h> 128 129 #define PHYSMAP_ENTRIES 10 130 131 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 132 133 extern void printcpuinfo(void); /* XXX header file */ 134 extern void identify_cpu(void); 135 #if JG 136 extern void finishidentcpu(void); 137 #endif 138 extern void panicifcpuunsupported(void); 139 140 static void cpu_startup(void *); 141 static void pic_finish(void *); 142 static void cpu_finish(void *); 143 144 #ifndef CPU_DISABLE_SSE 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 #endif /* CPU_DISABLE_SSE */ 148 #ifdef DIRECTIO 149 extern void ffs_rawread_setup(void); 150 #endif /* DIRECTIO */ 151 static void init_locks(void); 152 153 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL) 154 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL) 155 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL) 156 157 #ifdef DDB 158 extern vm_offset_t ksym_start, ksym_end; 159 #endif 160 161 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */ 162 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 167 #if defined(SWTCH_OPTIM_STATS) 168 extern int swtch_optim_stats; 169 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 170 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 171 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 172 CTLFLAG_RD, &tlb_flush_count, 0, ""); 173 #endif 174 175 long physmem = 0; 176 177 u_long ebda_addr = 0; 178 179 int imcr_present = 0; 180 181 int naps = 0; /* # of Applications processors */ 182 183 u_int base_memory; 184 struct mtx dt_lock; /* lock for GDT and LDT */ 185 186 static int 187 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 188 { 189 u_long pmem = ctob(physmem); 190 191 int error = sysctl_handle_long(oidp, &pmem, 0, req); 192 return (error); 193 } 194 195 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 196 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 197 198 static int 199 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 200 { 201 int error = sysctl_handle_int(oidp, 0, 202 ctob(physmem - vmstats.v_wire_count), req); 203 return (error); 204 } 205 206 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 207 0, 0, sysctl_hw_usermem, "IU", ""); 208 209 static int 210 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 211 { 212 int error = sysctl_handle_int(oidp, 0, 213 x86_64_btop(avail_end - avail_start), req); 214 return (error); 215 } 216 217 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 218 0, 0, sysctl_hw_availpages, "I", ""); 219 220 vm_paddr_t Maxmem; 221 vm_paddr_t Realmem; 222 223 /* 224 * The number of PHYSMAP entries must be one less than the number of 225 * PHYSSEG entries because the PHYSMAP entry that spans the largest 226 * physical address that is accessible by ISA DMA is split into two 227 * PHYSSEG entries. 228 */ 229 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 230 231 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 232 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 233 234 /* must be 2 less so 0 0 can signal end of chunks */ 235 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2) 236 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2) 237 238 static vm_offset_t buffer_sva, buffer_eva; 239 vm_offset_t clean_sva, clean_eva; 240 static vm_offset_t pager_sva, pager_eva; 241 static struct trapframe proc0_tf; 242 243 static void 244 cpu_startup(void *dummy) 245 { 246 caddr_t v; 247 vm_size_t size = 0; 248 vm_offset_t firstaddr; 249 250 /* 251 * Good {morning,afternoon,evening,night}. 252 */ 253 kprintf("%s", version); 254 startrtclock(); 255 printcpuinfo(); 256 panicifcpuunsupported(); 257 #ifdef PERFMON 258 perfmon_init(); 259 #endif 260 kprintf("real memory = %ju (%ju MB)\n", 261 (intmax_t)Realmem, 262 (intmax_t)Realmem / 1024 / 1024); 263 /* 264 * Display any holes after the first chunk of extended memory. 265 */ 266 if (bootverbose) { 267 int indx; 268 269 kprintf("Physical memory chunk(s):\n"); 270 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 271 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx]; 272 273 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 274 (intmax_t)phys_avail[indx], 275 (intmax_t)phys_avail[indx + 1] - 1, 276 (intmax_t)size1, 277 (intmax_t)(size1 / PAGE_SIZE)); 278 } 279 } 280 281 /* 282 * Allocate space for system data structures. 283 * The first available kernel virtual address is in "v". 284 * As pages of kernel virtual memory are allocated, "v" is incremented. 285 * As pages of memory are allocated and cleared, 286 * "firstaddr" is incremented. 287 * An index into the kernel page table corresponding to the 288 * virtual memory address maintained in "v" is kept in "mapaddr". 289 */ 290 291 /* 292 * Make two passes. The first pass calculates how much memory is 293 * needed and allocates it. The second pass assigns virtual 294 * addresses to the various data structures. 295 */ 296 firstaddr = 0; 297 again: 298 v = (caddr_t)firstaddr; 299 300 #define valloc(name, type, num) \ 301 (name) = (type *)v; v = (caddr_t)((name)+(num)) 302 #define valloclim(name, type, num, lim) \ 303 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 304 305 /* 306 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE. 307 * For the first 64MB of ram nominally allocate sufficient buffers to 308 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 309 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 310 * the buffer cache we limit the eventual kva reservation to 311 * maxbcache bytes. 312 * 313 * factor represents the 1/4 x ram conversion. 314 */ 315 if (nbuf == 0) { 316 long factor = 4 * BKVASIZE / 1024; 317 long kbytes = physmem * (PAGE_SIZE / 1024); 318 319 nbuf = 50; 320 if (kbytes > 4096) 321 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 322 if (kbytes > 65536) 323 nbuf += (kbytes - 65536) * 2 / (factor * 5); 324 if (maxbcache && nbuf > maxbcache / BKVASIZE) 325 nbuf = maxbcache / BKVASIZE; 326 } 327 328 /* 329 * Do not allow the buffer_map to be more then 1/2 the size of the 330 * kernel_map. 331 */ 332 if (nbuf > (virtual_end - virtual_start + 333 virtual2_end - virtual2_start) / (BKVASIZE * 2)) { 334 nbuf = (virtual_end - virtual_start + 335 virtual2_end - virtual2_start) / (BKVASIZE * 2); 336 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 337 } 338 339 /* 340 * Do not allow the buffer_map to use more than 50% of available 341 * physical-equivalent memory. Since the VM pages which back 342 * individual buffers are typically wired, having too many bufs 343 * can prevent the system from paging properly. 344 */ 345 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) { 346 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2); 347 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 348 } 349 350 /* 351 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 352 * the valloc space which is just the virtual_end - virtual_start 353 * section. We use valloc() to allocate the buf header array. 354 */ 355 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 356 nbuf = (virtual_end - virtual_start) / 357 sizeof(struct buf) / 2; 358 kprintf("Warning: nbufs capped at %ld due to valloc " 359 "considerations", nbuf); 360 } 361 362 nswbuf = lmax(lmin(nbuf / 4, 256), 16); 363 #ifdef NSWBUF_MIN 364 if (nswbuf < NSWBUF_MIN) 365 nswbuf = NSWBUF_MIN; 366 #endif 367 #ifdef DIRECTIO 368 ffs_rawread_setup(); 369 #endif 370 371 valloc(swbuf, struct buf, nswbuf); 372 valloc(buf, struct buf, nbuf); 373 374 /* 375 * End of first pass, size has been calculated so allocate memory 376 */ 377 if (firstaddr == 0) { 378 size = (vm_size_t)(v - firstaddr); 379 firstaddr = kmem_alloc(&kernel_map, round_page(size)); 380 if (firstaddr == 0) 381 panic("startup: no room for tables"); 382 goto again; 383 } 384 385 /* 386 * End of second pass, addresses have been assigned 387 * 388 * nbuf is an int, make sure we don't overflow the field. 389 * 390 * On 64-bit systems fragmentation can create serious performance 391 * loss due to the large number of buffers the system is likely 392 * going to maintain. The easiest solution is to create a KVA 393 * section that is twice as big as the nominal buffer cache size, 394 * hence the multiplication by 2 below. 395 */ 396 if ((vm_size_t)(v - firstaddr) != size) 397 panic("startup: table size inconsistency"); 398 399 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 400 ((vm_offset_t)nbuf * BKVASIZE * 2) + 401 (nswbuf * MAXPHYS) + pager_map_size); 402 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 403 ((vm_offset_t)nbuf * BKVASIZE * 2)); 404 buffer_map.system_map = 1; 405 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 406 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size); 407 pager_map.system_map = 1; 408 409 #if defined(USERCONFIG) 410 userconfig(); 411 cninit(); /* the preferred console may have changed */ 412 #endif 413 414 kprintf("avail memory = %ju (%ju MB)\n", 415 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 416 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 417 1024 / 1024); 418 419 /* 420 * Set up buffers, so they can be used to read disk labels. 421 */ 422 bufinit(); 423 vm_pager_bufferinit(); 424 } 425 426 static void 427 cpu_finish(void *dummy __unused) 428 { 429 cpu_setregs(); 430 } 431 432 static void 433 pic_finish(void *dummy __unused) 434 { 435 /* Log ELCR information */ 436 elcr_dump(); 437 438 /* Log MPTABLE information */ 439 mptable_pci_int_dump(); 440 441 /* Finalize PCI */ 442 MachIntrABI.finalize(); 443 } 444 445 /* 446 * Send an interrupt to process. 447 * 448 * Stack is set up to allow sigcode stored 449 * at top to call routine, followed by kcall 450 * to sigreturn routine below. After sigreturn 451 * resets the signal mask, the stack, and the 452 * frame pointer, it returns to the user 453 * specified pc, psl. 454 */ 455 void 456 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 457 { 458 struct lwp *lp = curthread->td_lwp; 459 struct proc *p = lp->lwp_proc; 460 struct trapframe *regs; 461 struct sigacts *psp = p->p_sigacts; 462 struct sigframe sf, *sfp; 463 int oonstack; 464 char *sp; 465 466 regs = lp->lwp_md.md_regs; 467 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 468 469 /* Save user context */ 470 bzero(&sf, sizeof(struct sigframe)); 471 sf.sf_uc.uc_sigmask = *mask; 472 sf.sf_uc.uc_stack = lp->lwp_sigstk; 473 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 474 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 475 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 476 477 /* Make the size of the saved context visible to userland */ 478 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 479 480 /* Allocate and validate space for the signal handler context. */ 481 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 482 SIGISMEMBER(psp->ps_sigonstack, sig)) { 483 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 484 sizeof(struct sigframe)); 485 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 486 } else { 487 /* We take red zone into account */ 488 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 489 } 490 491 /* 492 * XXX AVX needs 64-byte alignment but sigframe has other fields and 493 * the embedded ucontext is not at the front, so aligning this won't 494 * help us. Fortunately we bcopy in/out of the sigframe, so the 495 * kernel is ok. 496 * 497 * The problem though is if userland winds up trying to use the 498 * context directly. 499 */ 500 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 501 502 /* Translate the signal is appropriate */ 503 if (p->p_sysent->sv_sigtbl) { 504 if (sig <= p->p_sysent->sv_sigsize) 505 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 506 } 507 508 /* 509 * Build the argument list for the signal handler. 510 * 511 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 512 */ 513 regs->tf_rdi = sig; /* argument 1 */ 514 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 515 516 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 517 /* 518 * Signal handler installed with SA_SIGINFO. 519 * 520 * action(signo, siginfo, ucontext) 521 */ 522 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 523 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 524 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 525 526 /* fill siginfo structure */ 527 sf.sf_si.si_signo = sig; 528 sf.sf_si.si_code = code; 529 sf.sf_si.si_addr = (void *)regs->tf_addr; 530 } else { 531 /* 532 * Old FreeBSD-style arguments. 533 * 534 * handler (signo, code, [uc], addr) 535 */ 536 regs->tf_rsi = (register_t)code; /* argument 2 */ 537 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 538 sf.sf_ahu.sf_handler = catcher; 539 } 540 541 /* 542 * If we're a vm86 process, we want to save the segment registers. 543 * We also change eflags to be our emulated eflags, not the actual 544 * eflags. 545 */ 546 #if JG 547 if (regs->tf_eflags & PSL_VM) { 548 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 549 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 550 551 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 552 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 553 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 554 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 555 556 if (vm86->vm86_has_vme == 0) 557 sf.sf_uc.uc_mcontext.mc_eflags = 558 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 559 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 560 561 /* 562 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 563 * syscalls made by the signal handler. This just avoids 564 * wasting time for our lazy fixup of such faults. PSL_NT 565 * does nothing in vm86 mode, but vm86 programs can set it 566 * almost legitimately in probes for old cpu types. 567 */ 568 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 569 } 570 #endif 571 572 /* 573 * Save the FPU state and reinit the FP unit 574 */ 575 npxpush(&sf.sf_uc.uc_mcontext); 576 577 /* 578 * Copy the sigframe out to the user's stack. 579 */ 580 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 581 /* 582 * Something is wrong with the stack pointer. 583 * ...Kill the process. 584 */ 585 sigexit(lp, SIGILL); 586 } 587 588 regs->tf_rsp = (register_t)sfp; 589 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 590 591 /* 592 * i386 abi specifies that the direction flag must be cleared 593 * on function entry 594 */ 595 regs->tf_rflags &= ~(PSL_T|PSL_D); 596 597 /* 598 * 64 bit mode has a code and stack selector but 599 * no data or extra selector. %fs and %gs are not 600 * stored in-context. 601 */ 602 regs->tf_cs = _ucodesel; 603 regs->tf_ss = _udatasel; 604 clear_quickret(); 605 } 606 607 /* 608 * Sanitize the trapframe for a virtual kernel passing control to a custom 609 * VM context. Remove any items that would otherwise create a privilage 610 * issue. 611 * 612 * XXX at the moment we allow userland to set the resume flag. Is this a 613 * bad idea? 614 */ 615 int 616 cpu_sanitize_frame(struct trapframe *frame) 617 { 618 frame->tf_cs = _ucodesel; 619 frame->tf_ss = _udatasel; 620 /* XXX VM (8086) mode not supported? */ 621 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 622 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 623 624 return(0); 625 } 626 627 /* 628 * Sanitize the tls so loading the descriptor does not blow up 629 * on us. For x86_64 we don't have to do anything. 630 */ 631 int 632 cpu_sanitize_tls(struct savetls *tls) 633 { 634 return(0); 635 } 636 637 /* 638 * sigreturn(ucontext_t *sigcntxp) 639 * 640 * System call to cleanup state after a signal 641 * has been taken. Reset signal mask and 642 * stack state from context left by sendsig (above). 643 * Return to previous pc and psl as specified by 644 * context left by sendsig. Check carefully to 645 * make sure that the user has not modified the 646 * state to gain improper privileges. 647 * 648 * MPSAFE 649 */ 650 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 651 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 652 653 int 654 sys_sigreturn(struct sigreturn_args *uap) 655 { 656 struct lwp *lp = curthread->td_lwp; 657 struct trapframe *regs; 658 ucontext_t uc; 659 ucontext_t *ucp; 660 register_t rflags; 661 int cs; 662 int error; 663 664 /* 665 * We have to copy the information into kernel space so userland 666 * can't modify it while we are sniffing it. 667 */ 668 regs = lp->lwp_md.md_regs; 669 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 670 if (error) 671 return (error); 672 ucp = &uc; 673 rflags = ucp->uc_mcontext.mc_rflags; 674 675 /* VM (8086) mode not supported */ 676 rflags &= ~PSL_VM_UNSUPP; 677 678 #if JG 679 if (eflags & PSL_VM) { 680 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 681 struct vm86_kernel *vm86; 682 683 /* 684 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 685 * set up the vm86 area, and we can't enter vm86 mode. 686 */ 687 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 688 return (EINVAL); 689 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 690 if (vm86->vm86_inited == 0) 691 return (EINVAL); 692 693 /* go back to user mode if both flags are set */ 694 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 695 trapsignal(lp, SIGBUS, 0); 696 697 if (vm86->vm86_has_vme) { 698 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 699 (eflags & VME_USERCHANGE) | PSL_VM; 700 } else { 701 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 702 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 703 (eflags & VM_USERCHANGE) | PSL_VM; 704 } 705 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 706 tf->tf_eflags = eflags; 707 tf->tf_vm86_ds = tf->tf_ds; 708 tf->tf_vm86_es = tf->tf_es; 709 tf->tf_vm86_fs = tf->tf_fs; 710 tf->tf_vm86_gs = tf->tf_gs; 711 tf->tf_ds = _udatasel; 712 tf->tf_es = _udatasel; 713 tf->tf_fs = _udatasel; 714 tf->tf_gs = _udatasel; 715 } else 716 #endif 717 { 718 /* 719 * Don't allow users to change privileged or reserved flags. 720 */ 721 /* 722 * XXX do allow users to change the privileged flag PSL_RF. 723 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 724 * should sometimes set it there too. tf_eflags is kept in 725 * the signal context during signal handling and there is no 726 * other place to remember it, so the PSL_RF bit may be 727 * corrupted by the signal handler without us knowing. 728 * Corruption of the PSL_RF bit at worst causes one more or 729 * one less debugger trap, so allowing it is fairly harmless. 730 */ 731 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 732 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 733 return(EINVAL); 734 } 735 736 /* 737 * Don't allow users to load a valid privileged %cs. Let the 738 * hardware check for invalid selectors, excess privilege in 739 * other selectors, invalid %eip's and invalid %esp's. 740 */ 741 cs = ucp->uc_mcontext.mc_cs; 742 if (!CS_SECURE(cs)) { 743 kprintf("sigreturn: cs = 0x%x\n", cs); 744 trapsignal(lp, SIGBUS, T_PROTFLT); 745 return(EINVAL); 746 } 747 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 748 } 749 750 /* 751 * Restore the FPU state from the frame 752 */ 753 crit_enter(); 754 npxpop(&ucp->uc_mcontext); 755 756 if (ucp->uc_mcontext.mc_onstack & 1) 757 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 758 else 759 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 760 761 lp->lwp_sigmask = ucp->uc_sigmask; 762 SIG_CANTMASK(lp->lwp_sigmask); 763 clear_quickret(); 764 crit_exit(); 765 return(EJUSTRETURN); 766 } 767 768 /* 769 * Machine dependent boot() routine 770 * 771 * I haven't seen anything to put here yet 772 * Possibly some stuff might be grafted back here from boot() 773 */ 774 void 775 cpu_boot(int howto) 776 { 777 } 778 779 /* 780 * Shutdown the CPU as much as possible 781 */ 782 void 783 cpu_halt(void) 784 { 785 for (;;) 786 __asm__ __volatile("hlt"); 787 } 788 789 /* 790 * cpu_idle() represents the idle LWKT. You cannot return from this function 791 * (unless you want to blow things up!). Instead we look for runnable threads 792 * and loop or halt as appropriate. Giant is not held on entry to the thread. 793 * 794 * The main loop is entered with a critical section held, we must release 795 * the critical section before doing anything else. lwkt_switch() will 796 * check for pending interrupts due to entering and exiting its own 797 * critical section. 798 * 799 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 800 * However, there are cases where the idlethread will be entered with 801 * the possibility that no IPI will occur and in such cases 802 * lwkt_switch() sets TDF_IDLE_NOHLT. 803 * 804 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to 805 * 1 to just use hlt and for debugging purposes. 806 * 807 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 808 * must occur before it starts using ACPI halt. 809 */ 810 static int cpu_idle_hlt = 2; 811 static int cpu_idle_hltcnt; 812 static int cpu_idle_spincnt; 813 static u_int cpu_idle_repeat = 750; 814 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 815 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 816 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW, 817 &cpu_idle_hltcnt, 0, "Idle loop entry halts"); 818 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW, 819 &cpu_idle_spincnt, 0, "Idle loop entry spins"); 820 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 821 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 822 823 static void 824 cpu_idle_default_hook(void) 825 { 826 /* 827 * We must guarentee that hlt is exactly the instruction 828 * following the sti. 829 */ 830 __asm __volatile("sti; hlt"); 831 } 832 833 /* Other subsystems (e.g., ACPI) can hook this later. */ 834 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 835 836 void 837 cpu_idle(void) 838 { 839 globaldata_t gd = mycpu; 840 struct thread *td __debugvar = gd->gd_curthread; 841 int reqflags; 842 int quick; 843 844 crit_exit(); 845 KKASSERT(td->td_critcount == 0); 846 for (;;) { 847 /* 848 * See if there are any LWKTs ready to go. 849 */ 850 lwkt_switch(); 851 852 /* 853 * When halting inside a cli we must check for reqflags 854 * races, particularly [re]schedule requests. Running 855 * splz() does the job. 856 * 857 * cpu_idle_hlt: 858 * 0 Never halt, just spin 859 * 860 * 1 Always use HLT (or MONITOR/MWAIT if avail). 861 * This typically eats more power than the 862 * ACPI halt. 863 * 864 * 2 Use HLT/MONITOR/MWAIT up to a point and then 865 * use the ACPI halt (default). This is a hybrid 866 * approach. See machdep.cpu_idle_repeat. 867 * 868 * 3 Always use the ACPI halt. This typically 869 * eats the least amount of power but the cpu 870 * will be slow waking up. Slows down e.g. 871 * compiles and other pipe/event oriented stuff. 872 * 873 * NOTE: Interrupts are enabled and we are not in a critical 874 * section. 875 * 876 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 877 * don't bother capping gd_idle_repeat, it is ok if 878 * it overflows. 879 */ 880 ++gd->gd_idle_repeat; 881 reqflags = gd->gd_reqflags; 882 quick = (cpu_idle_hlt == 1) || 883 (cpu_idle_hlt < 3 && 884 gd->gd_idle_repeat < cpu_idle_repeat); 885 886 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 887 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 888 splz(); /* XXX */ 889 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags); 890 ++cpu_idle_hltcnt; 891 } else if (cpu_idle_hlt) { 892 __asm __volatile("cli"); 893 splz(); 894 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 895 if (quick) 896 cpu_idle_default_hook(); 897 else 898 cpu_idle_hook(); 899 } 900 __asm __volatile("sti"); 901 ++cpu_idle_hltcnt; 902 } else { 903 splz(); 904 __asm __volatile("sti"); 905 ++cpu_idle_spincnt; 906 } 907 } 908 } 909 910 /* 911 * This routine is called if a spinlock has been held through the 912 * exponential backoff period and is seriously contested. On a real cpu 913 * we let it spin. 914 */ 915 void 916 cpu_spinlock_contested(void) 917 { 918 cpu_pause(); 919 } 920 921 /* 922 * Clear registers on exec 923 */ 924 void 925 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 926 { 927 struct thread *td = curthread; 928 struct lwp *lp = td->td_lwp; 929 struct pcb *pcb = td->td_pcb; 930 struct trapframe *regs = lp->lwp_md.md_regs; 931 932 /* was i386_user_cleanup() in NetBSD */ 933 user_ldt_free(pcb); 934 935 clear_quickret(); 936 bzero((char *)regs, sizeof(struct trapframe)); 937 regs->tf_rip = entry; 938 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 939 regs->tf_rdi = stack; /* argv */ 940 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 941 regs->tf_ss = _udatasel; 942 regs->tf_cs = _ucodesel; 943 regs->tf_rbx = ps_strings; 944 945 /* 946 * Reset the hardware debug registers if they were in use. 947 * They won't have any meaning for the newly exec'd process. 948 */ 949 if (pcb->pcb_flags & PCB_DBREGS) { 950 pcb->pcb_dr0 = 0; 951 pcb->pcb_dr1 = 0; 952 pcb->pcb_dr2 = 0; 953 pcb->pcb_dr3 = 0; 954 pcb->pcb_dr6 = 0; 955 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 956 if (pcb == td->td_pcb) { 957 /* 958 * Clear the debug registers on the running 959 * CPU, otherwise they will end up affecting 960 * the next process we switch to. 961 */ 962 reset_dbregs(); 963 } 964 pcb->pcb_flags &= ~PCB_DBREGS; 965 } 966 967 /* 968 * Initialize the math emulator (if any) for the current process. 969 * Actually, just clear the bit that says that the emulator has 970 * been initialized. Initialization is delayed until the process 971 * traps to the emulator (if it is done at all) mainly because 972 * emulators don't provide an entry point for initialization. 973 */ 974 pcb->pcb_flags &= ~FP_SOFTFP; 975 976 /* 977 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 978 * gd_npxthread. Otherwise a preemptive interrupt thread 979 * may panic in npxdna(). 980 */ 981 crit_enter(); 982 load_cr0(rcr0() | CR0_MP); 983 984 /* 985 * NOTE: The MSR values must be correct so we can return to 986 * userland. gd_user_fs/gs must be correct so the switch 987 * code knows what the current MSR values are. 988 */ 989 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 990 pcb->pcb_gsbase = 0; 991 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 992 mdcpu->gd_user_gs = 0; 993 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 994 wrmsr(MSR_KGSBASE, 0); 995 996 /* Initialize the npx (if any) for the current process. */ 997 npxinit(__INITIAL_FPUCW__); 998 crit_exit(); 999 1000 pcb->pcb_ds = _udatasel; 1001 pcb->pcb_es = _udatasel; 1002 pcb->pcb_fs = _udatasel; 1003 pcb->pcb_gs = _udatasel; 1004 } 1005 1006 void 1007 cpu_setregs(void) 1008 { 1009 register_t cr0; 1010 1011 cr0 = rcr0(); 1012 cr0 |= CR0_NE; /* Done by npxinit() */ 1013 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1014 cr0 |= CR0_WP | CR0_AM; 1015 load_cr0(cr0); 1016 load_gs(_udatasel); 1017 } 1018 1019 static int 1020 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1021 { 1022 int error; 1023 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1024 req); 1025 if (!error && req->newptr) 1026 resettodr(); 1027 return (error); 1028 } 1029 1030 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1031 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1032 1033 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1034 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1035 1036 #if JG 1037 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1038 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1039 #endif 1040 1041 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1042 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1043 1044 extern u_long bootdev; /* not a cdev_t - encoding is different */ 1045 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 1046 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)"); 1047 1048 /* 1049 * Initialize 386 and configure to run kernel 1050 */ 1051 1052 /* 1053 * Initialize segments & interrupt table 1054 */ 1055 1056 int _default_ldt; 1057 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1058 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1059 #if JG 1060 union descriptor ldt[NLDT]; /* local descriptor table */ 1061 #endif 1062 1063 /* table descriptors - used to load tables by cpu */ 1064 struct region_descriptor r_gdt; 1065 struct region_descriptor r_idt_arr[MAXCPU]; 1066 1067 /* JG proc0paddr is a virtual address */ 1068 void *proc0paddr; 1069 /* JG alignment? */ 1070 char proc0paddr_buff[LWKT_THREAD_STACK]; 1071 1072 1073 /* software prototypes -- in more palatable form */ 1074 struct soft_segment_descriptor gdt_segs[] = { 1075 /* GNULL_SEL 0 Null Descriptor */ 1076 { 0x0, /* segment base address */ 1077 0x0, /* length */ 1078 0, /* segment type */ 1079 0, /* segment descriptor priority level */ 1080 0, /* segment descriptor present */ 1081 0, /* long */ 1082 0, /* default 32 vs 16 bit size */ 1083 0 /* limit granularity (byte/page units)*/ }, 1084 /* GCODE_SEL 1 Code Descriptor for kernel */ 1085 { 0x0, /* segment base address */ 1086 0xfffff, /* length - all address space */ 1087 SDT_MEMERA, /* segment type */ 1088 SEL_KPL, /* segment descriptor priority level */ 1089 1, /* segment descriptor present */ 1090 1, /* long */ 1091 0, /* default 32 vs 16 bit size */ 1092 1 /* limit granularity (byte/page units)*/ }, 1093 /* GDATA_SEL 2 Data Descriptor for kernel */ 1094 { 0x0, /* segment base address */ 1095 0xfffff, /* length - all address space */ 1096 SDT_MEMRWA, /* segment type */ 1097 SEL_KPL, /* segment descriptor priority level */ 1098 1, /* segment descriptor present */ 1099 1, /* long */ 1100 0, /* default 32 vs 16 bit size */ 1101 1 /* limit granularity (byte/page units)*/ }, 1102 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1103 { 0x0, /* segment base address */ 1104 0xfffff, /* length - all address space */ 1105 SDT_MEMERA, /* segment type */ 1106 SEL_UPL, /* segment descriptor priority level */ 1107 1, /* segment descriptor present */ 1108 0, /* long */ 1109 1, /* default 32 vs 16 bit size */ 1110 1 /* limit granularity (byte/page units)*/ }, 1111 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1112 { 0x0, /* segment base address */ 1113 0xfffff, /* length - all address space */ 1114 SDT_MEMRWA, /* segment type */ 1115 SEL_UPL, /* segment descriptor priority level */ 1116 1, /* segment descriptor present */ 1117 0, /* long */ 1118 1, /* default 32 vs 16 bit size */ 1119 1 /* limit granularity (byte/page units)*/ }, 1120 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1121 { 0x0, /* segment base address */ 1122 0xfffff, /* length - all address space */ 1123 SDT_MEMERA, /* segment type */ 1124 SEL_UPL, /* segment descriptor priority level */ 1125 1, /* segment descriptor present */ 1126 1, /* long */ 1127 0, /* default 32 vs 16 bit size */ 1128 1 /* limit granularity (byte/page units)*/ }, 1129 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1130 { 1131 0x0, /* segment base address */ 1132 sizeof(struct x86_64tss)-1,/* length - all address space */ 1133 SDT_SYSTSS, /* segment type */ 1134 SEL_KPL, /* segment descriptor priority level */ 1135 1, /* segment descriptor present */ 1136 0, /* long */ 1137 0, /* unused - default 32 vs 16 bit size */ 1138 0 /* limit granularity (byte/page units)*/ }, 1139 /* Actually, the TSS is a system descriptor which is double size */ 1140 { 0x0, /* segment base address */ 1141 0x0, /* length */ 1142 0, /* segment type */ 1143 0, /* segment descriptor priority level */ 1144 0, /* segment descriptor present */ 1145 0, /* long */ 1146 0, /* default 32 vs 16 bit size */ 1147 0 /* limit granularity (byte/page units)*/ }, 1148 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1149 { 0x0, /* segment base address */ 1150 0xfffff, /* length - all address space */ 1151 SDT_MEMRWA, /* segment type */ 1152 SEL_UPL, /* segment descriptor priority level */ 1153 1, /* segment descriptor present */ 1154 0, /* long */ 1155 1, /* default 32 vs 16 bit size */ 1156 1 /* limit granularity (byte/page units)*/ }, 1157 }; 1158 1159 void 1160 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1161 { 1162 int cpu; 1163 1164 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1165 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1166 1167 ip->gd_looffset = (uintptr_t)func; 1168 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1169 ip->gd_ist = ist; 1170 ip->gd_xx = 0; 1171 ip->gd_type = typ; 1172 ip->gd_dpl = dpl; 1173 ip->gd_p = 1; 1174 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1175 } 1176 } 1177 1178 void 1179 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1180 { 1181 struct gate_descriptor *ip; 1182 1183 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1184 1185 ip = &idt_arr[cpu][idx]; 1186 ip->gd_looffset = (uintptr_t)func; 1187 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1188 ip->gd_ist = ist; 1189 ip->gd_xx = 0; 1190 ip->gd_type = typ; 1191 ip->gd_dpl = dpl; 1192 ip->gd_p = 1; 1193 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1194 } 1195 1196 #define IDTVEC(name) __CONCAT(X,name) 1197 1198 extern inthand_t 1199 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1200 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1201 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1202 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1203 IDTVEC(xmm), IDTVEC(dblfault), 1204 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1205 1206 #ifdef DEBUG_INTERRUPTS 1207 extern inthand_t *Xrsvdary[256]; 1208 #endif 1209 1210 void 1211 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1212 { 1213 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1214 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1215 ssd->ssd_type = sd->sd_type; 1216 ssd->ssd_dpl = sd->sd_dpl; 1217 ssd->ssd_p = sd->sd_p; 1218 ssd->ssd_def32 = sd->sd_def32; 1219 ssd->ssd_gran = sd->sd_gran; 1220 } 1221 1222 void 1223 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1224 { 1225 1226 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1227 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1228 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1229 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1230 sd->sd_type = ssd->ssd_type; 1231 sd->sd_dpl = ssd->ssd_dpl; 1232 sd->sd_p = ssd->ssd_p; 1233 sd->sd_long = ssd->ssd_long; 1234 sd->sd_def32 = ssd->ssd_def32; 1235 sd->sd_gran = ssd->ssd_gran; 1236 } 1237 1238 void 1239 ssdtosyssd(struct soft_segment_descriptor *ssd, 1240 struct system_segment_descriptor *sd) 1241 { 1242 1243 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1244 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1245 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1246 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1247 sd->sd_type = ssd->ssd_type; 1248 sd->sd_dpl = ssd->ssd_dpl; 1249 sd->sd_p = ssd->ssd_p; 1250 sd->sd_gran = ssd->ssd_gran; 1251 } 1252 1253 /* 1254 * Populate the (physmap) array with base/bound pairs describing the 1255 * available physical memory in the system, then test this memory and 1256 * build the phys_avail array describing the actually-available memory. 1257 * 1258 * If we cannot accurately determine the physical memory map, then use 1259 * value from the 0xE801 call, and failing that, the RTC. 1260 * 1261 * Total memory size may be set by the kernel environment variable 1262 * hw.physmem or the compile-time define MAXMEM. 1263 * 1264 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1265 * of PAGE_SIZE. This also greatly reduces the memory test time 1266 * which would otherwise be excessive on machines with > 8G of ram. 1267 * 1268 * XXX first should be vm_paddr_t. 1269 */ 1270 1271 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1272 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1273 1274 static void 1275 getmemsize(caddr_t kmdp, u_int64_t first) 1276 { 1277 int off, physmap_idx, pa_indx, da_indx; 1278 int i, j; 1279 vm_paddr_t physmap[PHYSMAP_SIZE]; 1280 vm_paddr_t pa; 1281 vm_paddr_t msgbuf_size; 1282 u_long physmem_tunable; 1283 pt_entry_t *pte; 1284 struct bios_smap *smapbase, *smap, *smapend; 1285 u_int32_t smapsize; 1286 quad_t dcons_addr, dcons_size; 1287 1288 bzero(physmap, sizeof(physmap)); 1289 physmap_idx = 0; 1290 1291 /* 1292 * get memory map from INT 15:E820, kindly supplied by the loader. 1293 * 1294 * subr_module.c says: 1295 * "Consumer may safely assume that size value precedes data." 1296 * ie: an int32_t immediately precedes smap. 1297 */ 1298 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1299 MODINFO_METADATA | MODINFOMD_SMAP); 1300 if (smapbase == NULL) 1301 panic("No BIOS smap info from loader!"); 1302 1303 smapsize = *((u_int32_t *)smapbase - 1); 1304 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1305 1306 for (smap = smapbase; smap < smapend; smap++) { 1307 if (boothowto & RB_VERBOSE) 1308 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1309 smap->type, smap->base, smap->length); 1310 1311 if (smap->type != SMAP_TYPE_MEMORY) 1312 continue; 1313 1314 if (smap->length == 0) 1315 continue; 1316 1317 for (i = 0; i <= physmap_idx; i += 2) { 1318 if (smap->base < physmap[i + 1]) { 1319 if (boothowto & RB_VERBOSE) { 1320 kprintf("Overlapping or non-monotonic " 1321 "memory region, ignoring " 1322 "second region\n"); 1323 } 1324 break; 1325 } 1326 } 1327 if (i <= physmap_idx) 1328 continue; 1329 1330 Realmem += smap->length; 1331 1332 if (smap->base == physmap[physmap_idx + 1]) { 1333 physmap[physmap_idx + 1] += smap->length; 1334 continue; 1335 } 1336 1337 physmap_idx += 2; 1338 if (physmap_idx == PHYSMAP_SIZE) { 1339 kprintf("Too many segments in the physical " 1340 "address map, giving up\n"); 1341 break; 1342 } 1343 physmap[physmap_idx] = smap->base; 1344 physmap[physmap_idx + 1] = smap->base + smap->length; 1345 } 1346 1347 base_memory = physmap[1] / 1024; 1348 /* make hole for AP bootstrap code */ 1349 physmap[1] = mp_bootaddress(base_memory); 1350 1351 /* Save EBDA address, if any */ 1352 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1353 ebda_addr <<= 4; 1354 1355 /* 1356 * Maxmem isn't the "maximum memory", it's one larger than the 1357 * highest page of the physical address space. It should be 1358 * called something like "Maxphyspage". We may adjust this 1359 * based on ``hw.physmem'' and the results of the memory test. 1360 */ 1361 Maxmem = atop(physmap[physmap_idx + 1]); 1362 1363 #ifdef MAXMEM 1364 Maxmem = MAXMEM / 4; 1365 #endif 1366 1367 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1368 Maxmem = atop(physmem_tunable); 1369 1370 /* 1371 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1372 * in the system. 1373 */ 1374 if (Maxmem > atop(physmap[physmap_idx + 1])) 1375 Maxmem = atop(physmap[physmap_idx + 1]); 1376 1377 /* 1378 * Blowing out the DMAP will blow up the system. 1379 */ 1380 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1381 kprintf("Limiting Maxmem due to DMAP size\n"); 1382 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1383 } 1384 1385 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1386 (boothowto & RB_VERBOSE)) { 1387 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1388 } 1389 1390 /* 1391 * Call pmap initialization to make new kernel address space 1392 * 1393 * Mask off page 0. 1394 */ 1395 pmap_bootstrap(&first); 1396 physmap[0] = PAGE_SIZE; 1397 1398 /* 1399 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1400 * exceeding Maxmem. 1401 */ 1402 for (i = j = 0; i <= physmap_idx; i += 2) { 1403 if (physmap[i+1] > ptoa(Maxmem)) 1404 physmap[i+1] = ptoa(Maxmem); 1405 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1406 ~PHYSMAP_ALIGN_MASK; 1407 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1408 1409 physmap[j] = physmap[i]; 1410 physmap[j+1] = physmap[i+1]; 1411 1412 if (physmap[i] < physmap[i+1]) 1413 j += 2; 1414 } 1415 physmap_idx = j - 2; 1416 1417 /* 1418 * Align anything else used in the validation loop. 1419 */ 1420 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1421 1422 /* 1423 * Size up each available chunk of physical memory. 1424 */ 1425 pa_indx = 0; 1426 da_indx = 1; 1427 phys_avail[pa_indx++] = physmap[0]; 1428 phys_avail[pa_indx] = physmap[0]; 1429 dump_avail[da_indx] = physmap[0]; 1430 pte = CMAP1; 1431 1432 /* 1433 * Get dcons buffer address 1434 */ 1435 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 1436 kgetenv_quad("dcons.size", &dcons_size) == 0) 1437 dcons_addr = 0; 1438 1439 /* 1440 * Validate the physical memory. The physical memory segments 1441 * have already been aligned to PHYSMAP_ALIGN which is a multiple 1442 * of PAGE_SIZE. 1443 */ 1444 for (i = 0; i <= physmap_idx; i += 2) { 1445 vm_paddr_t end; 1446 1447 end = physmap[i + 1]; 1448 1449 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) { 1450 int tmp, page_bad, full; 1451 int *ptr = (int *)CADDR1; 1452 1453 full = FALSE; 1454 /* 1455 * block out kernel memory as not available. 1456 */ 1457 if (pa >= 0x200000 && pa < first) 1458 goto do_dump_avail; 1459 1460 /* 1461 * block out dcons buffer 1462 */ 1463 if (dcons_addr > 0 1464 && pa >= trunc_page(dcons_addr) 1465 && pa < dcons_addr + dcons_size) { 1466 goto do_dump_avail; 1467 } 1468 1469 page_bad = FALSE; 1470 1471 /* 1472 * map page into kernel: valid, read/write,non-cacheable 1473 */ 1474 *pte = pa | PG_V | PG_RW | PG_N; 1475 cpu_invltlb(); 1476 1477 tmp = *ptr; 1478 /* 1479 * Test for alternating 1's and 0's 1480 */ 1481 *(volatile int *)ptr = 0xaaaaaaaa; 1482 cpu_mfence(); 1483 if (*(volatile int *)ptr != 0xaaaaaaaa) 1484 page_bad = TRUE; 1485 /* 1486 * Test for alternating 0's and 1's 1487 */ 1488 *(volatile int *)ptr = 0x55555555; 1489 cpu_mfence(); 1490 if (*(volatile int *)ptr != 0x55555555) 1491 page_bad = TRUE; 1492 /* 1493 * Test for all 1's 1494 */ 1495 *(volatile int *)ptr = 0xffffffff; 1496 cpu_mfence(); 1497 if (*(volatile int *)ptr != 0xffffffff) 1498 page_bad = TRUE; 1499 /* 1500 * Test for all 0's 1501 */ 1502 *(volatile int *)ptr = 0x0; 1503 cpu_mfence(); 1504 if (*(volatile int *)ptr != 0x0) 1505 page_bad = TRUE; 1506 /* 1507 * Restore original value. 1508 */ 1509 *ptr = tmp; 1510 1511 /* 1512 * Adjust array of valid/good pages. 1513 */ 1514 if (page_bad == TRUE) 1515 continue; 1516 /* 1517 * If this good page is a continuation of the 1518 * previous set of good pages, then just increase 1519 * the end pointer. Otherwise start a new chunk. 1520 * Note that "end" points one higher than end, 1521 * making the range >= start and < end. 1522 * If we're also doing a speculative memory 1523 * test and we at or past the end, bump up Maxmem 1524 * so that we keep going. The first bad page 1525 * will terminate the loop. 1526 */ 1527 if (phys_avail[pa_indx] == pa) { 1528 phys_avail[pa_indx] += PHYSMAP_ALIGN; 1529 } else { 1530 pa_indx++; 1531 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1532 kprintf( 1533 "Too many holes in the physical address space, giving up\n"); 1534 pa_indx--; 1535 full = TRUE; 1536 goto do_dump_avail; 1537 } 1538 phys_avail[pa_indx++] = pa; 1539 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN; 1540 } 1541 physmem += PHYSMAP_ALIGN / PAGE_SIZE; 1542 do_dump_avail: 1543 if (dump_avail[da_indx] == pa) { 1544 dump_avail[da_indx] += PHYSMAP_ALIGN; 1545 } else { 1546 da_indx++; 1547 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1548 da_indx--; 1549 goto do_next; 1550 } 1551 dump_avail[da_indx++] = pa; 1552 dump_avail[da_indx] = pa + PHYSMAP_ALIGN; 1553 } 1554 do_next: 1555 if (full) 1556 break; 1557 } 1558 } 1559 *pte = 0; 1560 cpu_invltlb(); 1561 1562 /* 1563 * The last chunk must contain at least one page plus the message 1564 * buffer to avoid complicating other code (message buffer address 1565 * calculation, etc.). 1566 */ 1567 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1568 1569 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN + 1570 msgbuf_size >= phys_avail[pa_indx]) { 1571 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1572 phys_avail[pa_indx--] = 0; 1573 phys_avail[pa_indx--] = 0; 1574 } 1575 1576 Maxmem = atop(phys_avail[pa_indx]); 1577 1578 /* Trim off space for the message buffer. */ 1579 phys_avail[pa_indx] -= msgbuf_size; 1580 1581 avail_end = phys_avail[pa_indx]; 1582 1583 /* Map the message buffer. */ 1584 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 1585 pmap_kenter((vm_offset_t)msgbufp + off, 1586 phys_avail[pa_indx] + off); 1587 } 1588 } 1589 1590 struct machintr_abi MachIntrABI; 1591 1592 /* 1593 * IDT VECTORS: 1594 * 0 Divide by zero 1595 * 1 Debug 1596 * 2 NMI 1597 * 3 BreakPoint 1598 * 4 OverFlow 1599 * 5 Bound-Range 1600 * 6 Invalid OpCode 1601 * 7 Device Not Available (x87) 1602 * 8 Double-Fault 1603 * 9 Coprocessor Segment overrun (unsupported, reserved) 1604 * 10 Invalid-TSS 1605 * 11 Segment not present 1606 * 12 Stack 1607 * 13 General Protection 1608 * 14 Page Fault 1609 * 15 Reserved 1610 * 16 x87 FP Exception pending 1611 * 17 Alignment Check 1612 * 18 Machine Check 1613 * 19 SIMD floating point 1614 * 20-31 reserved 1615 * 32-255 INTn/external sources 1616 */ 1617 u_int64_t 1618 hammer_time(u_int64_t modulep, u_int64_t physfree) 1619 { 1620 caddr_t kmdp; 1621 int gsel_tss, x, cpu; 1622 #if JG 1623 int metadata_missing, off; 1624 #endif 1625 struct mdglobaldata *gd; 1626 u_int64_t msr; 1627 1628 /* 1629 * Prevent lowering of the ipl if we call tsleep() early. 1630 */ 1631 gd = &CPU_prvspace[0].mdglobaldata; 1632 bzero(gd, sizeof(*gd)); 1633 1634 /* 1635 * Note: on both UP and SMP curthread must be set non-NULL 1636 * early in the boot sequence because the system assumes 1637 * that 'curthread' is never NULL. 1638 */ 1639 1640 gd->mi.gd_curthread = &thread0; 1641 thread0.td_gd = &gd->mi; 1642 1643 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 1644 1645 #if JG 1646 metadata_missing = 0; 1647 if (bootinfo.bi_modulep) { 1648 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 1649 preload_bootstrap_relocate(KERNBASE); 1650 } else { 1651 metadata_missing = 1; 1652 } 1653 if (bootinfo.bi_envp) 1654 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 1655 #endif 1656 1657 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 1658 preload_bootstrap_relocate(PTOV_OFFSET); 1659 kmdp = preload_search_by_type("elf kernel"); 1660 if (kmdp == NULL) 1661 kmdp = preload_search_by_type("elf64 kernel"); 1662 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1663 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 1664 #ifdef DDB 1665 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1666 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1667 #endif 1668 1669 if (boothowto & RB_VERBOSE) 1670 bootverbose++; 1671 1672 /* 1673 * Default MachIntrABI to ICU 1674 */ 1675 MachIntrABI = MachIntrABI_ICU; 1676 1677 /* 1678 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask, 1679 * and ncpus_fit_mask remain 0. 1680 */ 1681 ncpus = 1; 1682 ncpus2 = 1; 1683 ncpus_fit = 1; 1684 /* Init basic tunables, hz etc */ 1685 init_param1(); 1686 1687 /* 1688 * make gdt memory segments 1689 */ 1690 gdt_segs[GPROC0_SEL].ssd_base = 1691 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss; 1692 1693 gd->mi.gd_prvspace = &CPU_prvspace[0]; 1694 1695 for (x = 0; x < NGDT; x++) { 1696 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 1697 ssdtosd(&gdt_segs[x], &gdt[x]); 1698 } 1699 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1700 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1701 1702 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1703 r_gdt.rd_base = (long) gdt; 1704 lgdt(&r_gdt); 1705 1706 wrmsr(MSR_FSBASE, 0); /* User value */ 1707 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 1708 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1709 1710 mi_gdinit(&gd->mi, 0); 1711 cpu_gdinit(gd, 0); 1712 proc0paddr = proc0paddr_buff; 1713 mi_proc0init(&gd->mi, proc0paddr); 1714 safepri = TDPRI_MAX; 1715 1716 /* spinlocks and the BGL */ 1717 init_locks(); 1718 1719 /* exceptions */ 1720 for (x = 0; x < NIDT; x++) 1721 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1722 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1723 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1724 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 1725 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1726 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1727 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1728 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1729 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1730 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1731 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1732 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1733 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1734 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1735 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1736 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1737 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1738 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1739 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1740 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1741 1742 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1743 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 1744 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 1745 } 1746 1747 lidt(&r_idt_arr[0]); 1748 1749 /* 1750 * Initialize the console before we print anything out. 1751 */ 1752 cninit(); 1753 1754 #if JG 1755 if (metadata_missing) 1756 kprintf("WARNING: loader(8) metadata is missing!\n"); 1757 #endif 1758 1759 #if NISA >0 1760 elcr_probe(); 1761 isa_defaultirq(); 1762 #endif 1763 rand_initialize(); 1764 1765 /* 1766 * Initialize IRQ mapping 1767 * 1768 * NOTE: 1769 * SHOULD be after elcr_probe() 1770 */ 1771 MachIntrABI_ICU.initmap(); 1772 MachIntrABI_IOAPIC.initmap(); 1773 1774 #ifdef DDB 1775 kdb_init(); 1776 if (boothowto & RB_KDB) 1777 Debugger("Boot flags requested debugger"); 1778 #endif 1779 1780 #if JG 1781 finishidentcpu(); /* Final stage of CPU initialization */ 1782 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1783 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1784 #endif 1785 identify_cpu(); /* Final stage of CPU initialization */ 1786 initializecpu(); /* Initialize CPU registers */ 1787 1788 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 1789 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 1790 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 1791 1792 /* 1793 * Some of the virtual machines do not work w/ I/O APIC 1794 * enabled. If the user does not explicitly enable or 1795 * disable the I/O APIC (ioapic_enable < 0), then we 1796 * disable I/O APIC on all virtual machines. 1797 * 1798 * NOTE: 1799 * This must be done after identify_cpu(), which sets 1800 * 'cpu_feature2' 1801 */ 1802 if (ioapic_enable < 0) { 1803 if (cpu_feature2 & CPUID2_VMM) 1804 ioapic_enable = 0; 1805 else 1806 ioapic_enable = 1; 1807 } 1808 1809 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1810 gd->gd_common_tss.tss_rsp0 = 1811 (register_t)(thread0.td_kstack + 1812 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 1813 /* Ensure the stack is aligned to 16 bytes */ 1814 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 1815 1816 /* double fault stack */ 1817 gd->gd_common_tss.tss_ist1 = 1818 (long)&gd->mi.gd_prvspace->idlestack[ 1819 sizeof(gd->mi.gd_prvspace->idlestack)]; 1820 1821 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1822 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 1823 1824 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1825 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 1826 gd->gd_common_tssd = *gd->gd_tss_gdt; 1827 ltr(gsel_tss); 1828 1829 /* Set up the fast syscall stuff */ 1830 msr = rdmsr(MSR_EFER) | EFER_SCE; 1831 wrmsr(MSR_EFER, msr); 1832 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1833 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1834 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1835 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1836 wrmsr(MSR_STAR, msr); 1837 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 1838 1839 getmemsize(kmdp, physfree); 1840 init_param2(physmem); 1841 1842 /* now running on new page tables, configured,and u/iom is accessible */ 1843 1844 /* Map the message buffer. */ 1845 #if JG 1846 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1847 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 1848 #endif 1849 1850 msgbufinit(msgbufp, MSGBUF_SIZE); 1851 1852 1853 /* transfer to user mode */ 1854 1855 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1856 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1857 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1858 1859 load_ds(_udatasel); 1860 load_es(_udatasel); 1861 load_fs(_udatasel); 1862 1863 /* setup proc 0's pcb */ 1864 thread0.td_pcb->pcb_flags = 0; 1865 thread0.td_pcb->pcb_cr3 = KPML4phys; 1866 thread0.td_pcb->pcb_ext = NULL; 1867 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 1868 1869 /* Location of kernel stack for locore */ 1870 return ((u_int64_t)thread0.td_pcb); 1871 } 1872 1873 /* 1874 * Initialize machine-dependant portions of the global data structure. 1875 * Note that the global data area and cpu0's idlestack in the private 1876 * data space were allocated in locore. 1877 * 1878 * Note: the idlethread's cpl is 0 1879 * 1880 * WARNING! Called from early boot, 'mycpu' may not work yet. 1881 */ 1882 void 1883 cpu_gdinit(struct mdglobaldata *gd, int cpu) 1884 { 1885 if (cpu) 1886 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 1887 1888 lwkt_init_thread(&gd->mi.gd_idlethread, 1889 gd->mi.gd_prvspace->idlestack, 1890 sizeof(gd->mi.gd_prvspace->idlestack), 1891 0, &gd->mi); 1892 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 1893 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 1894 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 1895 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 1896 } 1897 1898 int 1899 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 1900 { 1901 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 1902 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 1903 return (TRUE); 1904 } 1905 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 1906 return (TRUE); 1907 return (FALSE); 1908 } 1909 1910 struct globaldata * 1911 globaldata_find(int cpu) 1912 { 1913 KKASSERT(cpu >= 0 && cpu < ncpus); 1914 return(&CPU_prvspace[cpu].mdglobaldata.mi); 1915 } 1916 1917 int 1918 ptrace_set_pc(struct lwp *lp, unsigned long addr) 1919 { 1920 lp->lwp_md.md_regs->tf_rip = addr; 1921 return (0); 1922 } 1923 1924 int 1925 ptrace_single_step(struct lwp *lp) 1926 { 1927 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 1928 return (0); 1929 } 1930 1931 int 1932 fill_regs(struct lwp *lp, struct reg *regs) 1933 { 1934 struct trapframe *tp; 1935 1936 if ((tp = lp->lwp_md.md_regs) == NULL) 1937 return EINVAL; 1938 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 1939 return (0); 1940 } 1941 1942 int 1943 set_regs(struct lwp *lp, struct reg *regs) 1944 { 1945 struct trapframe *tp; 1946 1947 tp = lp->lwp_md.md_regs; 1948 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 1949 !CS_SECURE(regs->r_cs)) 1950 return (EINVAL); 1951 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 1952 clear_quickret(); 1953 return (0); 1954 } 1955 1956 #ifndef CPU_DISABLE_SSE 1957 static void 1958 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 1959 { 1960 struct env87 *penv_87 = &sv_87->sv_env; 1961 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1962 int i; 1963 1964 /* FPU control/status */ 1965 penv_87->en_cw = penv_xmm->en_cw; 1966 penv_87->en_sw = penv_xmm->en_sw; 1967 penv_87->en_tw = penv_xmm->en_tw; 1968 penv_87->en_fip = penv_xmm->en_fip; 1969 penv_87->en_fcs = penv_xmm->en_fcs; 1970 penv_87->en_opcode = penv_xmm->en_opcode; 1971 penv_87->en_foo = penv_xmm->en_foo; 1972 penv_87->en_fos = penv_xmm->en_fos; 1973 1974 /* FPU registers */ 1975 for (i = 0; i < 8; ++i) 1976 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 1977 } 1978 1979 static void 1980 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 1981 { 1982 struct env87 *penv_87 = &sv_87->sv_env; 1983 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1984 int i; 1985 1986 /* FPU control/status */ 1987 penv_xmm->en_cw = penv_87->en_cw; 1988 penv_xmm->en_sw = penv_87->en_sw; 1989 penv_xmm->en_tw = penv_87->en_tw; 1990 penv_xmm->en_fip = penv_87->en_fip; 1991 penv_xmm->en_fcs = penv_87->en_fcs; 1992 penv_xmm->en_opcode = penv_87->en_opcode; 1993 penv_xmm->en_foo = penv_87->en_foo; 1994 penv_xmm->en_fos = penv_87->en_fos; 1995 1996 /* FPU registers */ 1997 for (i = 0; i < 8; ++i) 1998 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 1999 } 2000 #endif /* CPU_DISABLE_SSE */ 2001 2002 int 2003 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2004 { 2005 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2006 return EINVAL; 2007 #ifndef CPU_DISABLE_SSE 2008 if (cpu_fxsr) { 2009 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2010 (struct save87 *)fpregs); 2011 return (0); 2012 } 2013 #endif /* CPU_DISABLE_SSE */ 2014 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2015 return (0); 2016 } 2017 2018 int 2019 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2020 { 2021 #ifndef CPU_DISABLE_SSE 2022 if (cpu_fxsr) { 2023 set_fpregs_xmm((struct save87 *)fpregs, 2024 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2025 return (0); 2026 } 2027 #endif /* CPU_DISABLE_SSE */ 2028 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2029 return (0); 2030 } 2031 2032 int 2033 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2034 { 2035 struct pcb *pcb; 2036 2037 if (lp == NULL) { 2038 dbregs->dr[0] = rdr0(); 2039 dbregs->dr[1] = rdr1(); 2040 dbregs->dr[2] = rdr2(); 2041 dbregs->dr[3] = rdr3(); 2042 dbregs->dr[4] = rdr4(); 2043 dbregs->dr[5] = rdr5(); 2044 dbregs->dr[6] = rdr6(); 2045 dbregs->dr[7] = rdr7(); 2046 return (0); 2047 } 2048 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2049 return EINVAL; 2050 dbregs->dr[0] = pcb->pcb_dr0; 2051 dbregs->dr[1] = pcb->pcb_dr1; 2052 dbregs->dr[2] = pcb->pcb_dr2; 2053 dbregs->dr[3] = pcb->pcb_dr3; 2054 dbregs->dr[4] = 0; 2055 dbregs->dr[5] = 0; 2056 dbregs->dr[6] = pcb->pcb_dr6; 2057 dbregs->dr[7] = pcb->pcb_dr7; 2058 return (0); 2059 } 2060 2061 int 2062 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2063 { 2064 if (lp == NULL) { 2065 load_dr0(dbregs->dr[0]); 2066 load_dr1(dbregs->dr[1]); 2067 load_dr2(dbregs->dr[2]); 2068 load_dr3(dbregs->dr[3]); 2069 load_dr4(dbregs->dr[4]); 2070 load_dr5(dbregs->dr[5]); 2071 load_dr6(dbregs->dr[6]); 2072 load_dr7(dbregs->dr[7]); 2073 } else { 2074 struct pcb *pcb; 2075 struct ucred *ucred; 2076 int i; 2077 uint64_t mask1, mask2; 2078 2079 /* 2080 * Don't let an illegal value for dr7 get set. Specifically, 2081 * check for undefined settings. Setting these bit patterns 2082 * result in undefined behaviour and can lead to an unexpected 2083 * TRCTRAP. 2084 */ 2085 /* JG this loop looks unreadable */ 2086 /* Check 4 2-bit fields for invalid patterns. 2087 * These fields are R/Wi, for i = 0..3 2088 */ 2089 /* Is 10 in LENi allowed when running in compatibility mode? */ 2090 /* Pattern 10 in R/Wi might be used to indicate 2091 * breakpoint on I/O. Further analysis should be 2092 * carried to decide if it is safe and useful to 2093 * provide access to that capability 2094 */ 2095 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2096 i++, mask1 <<= 4, mask2 <<= 4) 2097 if ((dbregs->dr[7] & mask1) == mask2) 2098 return (EINVAL); 2099 2100 pcb = lp->lwp_thread->td_pcb; 2101 ucred = lp->lwp_proc->p_ucred; 2102 2103 /* 2104 * Don't let a process set a breakpoint that is not within the 2105 * process's address space. If a process could do this, it 2106 * could halt the system by setting a breakpoint in the kernel 2107 * (if ddb was enabled). Thus, we need to check to make sure 2108 * that no breakpoints are being enabled for addresses outside 2109 * process's address space, unless, perhaps, we were called by 2110 * uid 0. 2111 * 2112 * XXX - what about when the watched area of the user's 2113 * address space is written into from within the kernel 2114 * ... wouldn't that still cause a breakpoint to be generated 2115 * from within kernel mode? 2116 */ 2117 2118 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2119 if (dbregs->dr[7] & 0x3) { 2120 /* dr0 is enabled */ 2121 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2122 return (EINVAL); 2123 } 2124 2125 if (dbregs->dr[7] & (0x3<<2)) { 2126 /* dr1 is enabled */ 2127 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2128 return (EINVAL); 2129 } 2130 2131 if (dbregs->dr[7] & (0x3<<4)) { 2132 /* dr2 is enabled */ 2133 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2134 return (EINVAL); 2135 } 2136 2137 if (dbregs->dr[7] & (0x3<<6)) { 2138 /* dr3 is enabled */ 2139 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2140 return (EINVAL); 2141 } 2142 } 2143 2144 pcb->pcb_dr0 = dbregs->dr[0]; 2145 pcb->pcb_dr1 = dbregs->dr[1]; 2146 pcb->pcb_dr2 = dbregs->dr[2]; 2147 pcb->pcb_dr3 = dbregs->dr[3]; 2148 pcb->pcb_dr6 = dbregs->dr[6]; 2149 pcb->pcb_dr7 = dbregs->dr[7]; 2150 2151 pcb->pcb_flags |= PCB_DBREGS; 2152 } 2153 2154 return (0); 2155 } 2156 2157 /* 2158 * Return > 0 if a hardware breakpoint has been hit, and the 2159 * breakpoint was in user space. Return 0, otherwise. 2160 */ 2161 int 2162 user_dbreg_trap(void) 2163 { 2164 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2165 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2166 int nbp; /* number of breakpoints that triggered */ 2167 caddr_t addr[4]; /* breakpoint addresses */ 2168 int i; 2169 2170 dr7 = rdr7(); 2171 if ((dr7 & 0xff) == 0) { 2172 /* 2173 * all GE and LE bits in the dr7 register are zero, 2174 * thus the trap couldn't have been caused by the 2175 * hardware debug registers 2176 */ 2177 return 0; 2178 } 2179 2180 nbp = 0; 2181 dr6 = rdr6(); 2182 bp = dr6 & 0xf; 2183 2184 if (bp == 0) { 2185 /* 2186 * None of the breakpoint bits are set meaning this 2187 * trap was not caused by any of the debug registers 2188 */ 2189 return 0; 2190 } 2191 2192 /* 2193 * at least one of the breakpoints were hit, check to see 2194 * which ones and if any of them are user space addresses 2195 */ 2196 2197 if (bp & 0x01) { 2198 addr[nbp++] = (caddr_t)rdr0(); 2199 } 2200 if (bp & 0x02) { 2201 addr[nbp++] = (caddr_t)rdr1(); 2202 } 2203 if (bp & 0x04) { 2204 addr[nbp++] = (caddr_t)rdr2(); 2205 } 2206 if (bp & 0x08) { 2207 addr[nbp++] = (caddr_t)rdr3(); 2208 } 2209 2210 for (i=0; i<nbp; i++) { 2211 if (addr[i] < 2212 (caddr_t)VM_MAX_USER_ADDRESS) { 2213 /* 2214 * addr[i] is in user space 2215 */ 2216 return nbp; 2217 } 2218 } 2219 2220 /* 2221 * None of the breakpoints are in user space. 2222 */ 2223 return 0; 2224 } 2225 2226 2227 #ifndef DDB 2228 void 2229 Debugger(const char *msg) 2230 { 2231 kprintf("Debugger(\"%s\") called.\n", msg); 2232 } 2233 #endif /* no DDB */ 2234 2235 #ifdef DDB 2236 2237 /* 2238 * Provide inb() and outb() as functions. They are normally only 2239 * available as macros calling inlined functions, thus cannot be 2240 * called inside DDB. 2241 * 2242 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2243 */ 2244 2245 #undef inb 2246 #undef outb 2247 2248 /* silence compiler warnings */ 2249 u_char inb(u_int); 2250 void outb(u_int, u_char); 2251 2252 u_char 2253 inb(u_int port) 2254 { 2255 u_char data; 2256 /* 2257 * We use %%dx and not %1 here because i/o is done at %dx and not at 2258 * %edx, while gcc generates inferior code (movw instead of movl) 2259 * if we tell it to load (u_short) port. 2260 */ 2261 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2262 return (data); 2263 } 2264 2265 void 2266 outb(u_int port, u_char data) 2267 { 2268 u_char al; 2269 /* 2270 * Use an unnecessary assignment to help gcc's register allocator. 2271 * This make a large difference for gcc-1.40 and a tiny difference 2272 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2273 * best results. gcc-2.6.0 can't handle this. 2274 */ 2275 al = data; 2276 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2277 } 2278 2279 #endif /* DDB */ 2280 2281 2282 2283 #include "opt_cpu.h" 2284 2285 2286 /* 2287 * initialize all the SMP locks 2288 */ 2289 2290 /* critical region when masking or unmasking interupts */ 2291 struct spinlock_deprecated imen_spinlock; 2292 2293 /* critical region for old style disable_intr/enable_intr */ 2294 struct spinlock_deprecated mpintr_spinlock; 2295 2296 /* critical region around INTR() routines */ 2297 struct spinlock_deprecated intr_spinlock; 2298 2299 /* lock region used by kernel profiling */ 2300 struct spinlock_deprecated mcount_spinlock; 2301 2302 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2303 struct spinlock_deprecated com_spinlock; 2304 2305 /* lock regions around the clock hardware */ 2306 struct spinlock_deprecated clock_spinlock; 2307 2308 static void 2309 init_locks(void) 2310 { 2311 /* 2312 * Get the initial mplock with a count of 1 for the BSP. 2313 * This uses a LOGICAL cpu ID, ie BSP == 0. 2314 */ 2315 cpu_get_initial_mplock(); 2316 /* DEPRECATED */ 2317 spin_lock_init(&mcount_spinlock); 2318 spin_lock_init(&intr_spinlock); 2319 spin_lock_init(&mpintr_spinlock); 2320 spin_lock_init(&imen_spinlock); 2321 spin_lock_init(&com_spinlock); 2322 spin_lock_init(&clock_spinlock); 2323 2324 /* our token pool needs to work early */ 2325 lwkt_token_pool_init(); 2326 } 2327 2328