1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008-2017 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 extern void panicifcpuunsupported(void); 137 138 static void cpu_startup(void *); 139 static void pic_finish(void *); 140 static void cpu_finish(void *); 141 142 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 143 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 144 static void init_locks(void); 145 146 extern void pcpu_timer_always(struct intrframe *); 147 148 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 149 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 150 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 151 152 #ifdef DDB 153 extern vm_offset_t ksym_start, ksym_end; 154 #endif 155 156 struct privatespace CPU_prvspace_bsp __aligned(4096); 157 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 158 159 vm_paddr_t efi_systbl_phys; 160 int _udatasel, _ucodesel, _ucode32sel; 161 u_long atdevbase; 162 int64_t tsc_offsets[MAXCPU]; 163 cpumask_t smp_idleinvl_mask; 164 cpumask_t smp_idleinvl_reqs; 165 166 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 167 168 #if defined(SWTCH_OPTIM_STATS) 169 extern int swtch_optim_stats; 170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 171 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 173 CTLFLAG_RD, &tlb_flush_count, 0, ""); 174 #endif 175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 176 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 177 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, 178 CTLFLAG_RD, &cpu_mwait_spin, 0, "monitor/mwait target state"); 179 180 #define CPU_MWAIT_HAS_CX \ 181 ((cpu_feature2 & CPUID2_MON) && \ 182 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 183 184 #define CPU_MWAIT_CX_NAMELEN 16 185 186 #define CPU_MWAIT_C1 1 187 #define CPU_MWAIT_C2 2 188 #define CPU_MWAIT_C3 3 189 #define CPU_MWAIT_CX_MAX 8 190 191 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 192 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 193 194 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 195 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 196 197 struct cpu_mwait_cx { 198 int subcnt; 199 char name[4]; 200 struct sysctl_ctx_list sysctl_ctx; 201 struct sysctl_oid *sysctl_tree; 202 }; 203 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 204 static char cpu_mwait_cx_supported[256]; 205 206 static int cpu_mwait_c1_hints_cnt; 207 static int cpu_mwait_hints_cnt; 208 static int *cpu_mwait_hints; 209 210 static int cpu_mwait_deep_hints_cnt; 211 static int *cpu_mwait_deep_hints; 212 213 #define CPU_IDLE_REPEAT_DEFAULT 750 214 215 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 216 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 217 static u_int cpu_mwait_repeat_shift = 1; 218 219 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 220 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 221 222 static int cpu_mwait_c3_preamble = 223 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 224 CPU_MWAIT_C3_PREAMBLE_BM_STS; 225 226 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 227 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 228 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 229 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 230 231 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 232 int *, boolean_t); 233 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 234 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 235 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 236 237 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 238 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 239 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 240 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 241 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 242 &cpu_mwait_repeat_shift, 0, ""); 243 244 long physmem = 0; 245 246 u_long ebda_addr = 0; 247 248 int imcr_present = 0; 249 250 int naps = 0; /* # of Applications processors */ 251 252 u_int base_memory; 253 254 static int 255 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 256 { 257 u_long pmem = ctob(physmem); 258 int error; 259 260 error = sysctl_handle_long(oidp, &pmem, 0, req); 261 262 return (error); 263 } 264 265 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 266 0, 0, sysctl_hw_physmem, "LU", 267 "Total system memory in bytes (number of pages * page size)"); 268 269 static int 270 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 271 { 272 u_long usermem = ctob(physmem - vmstats.v_wire_count); 273 int error; 274 275 error = sysctl_handle_long(oidp, &usermem, 0, req); 276 277 return (error); 278 } 279 280 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_ULONG|CTLFLAG_RD, 281 0, 0, sysctl_hw_usermem, "LU", ""); 282 283 static int 284 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 285 { 286 int error; 287 u_long availpages; 288 289 availpages = x86_64_btop(avail_end - avail_start); 290 error = sysctl_handle_long(oidp, &availpages, 0, req); 291 292 return (error); 293 } 294 295 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_ULONG|CTLFLAG_RD, 296 0, 0, sysctl_hw_availpages, "LU", ""); 297 298 vm_paddr_t Maxmem; 299 vm_paddr_t Realmem; 300 301 /* 302 * The number of PHYSMAP entries must be one less than the number of 303 * PHYSSEG entries because the PHYSMAP entry that spans the largest 304 * physical address that is accessible by ISA DMA is split into two 305 * PHYSSEG entries. 306 */ 307 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 308 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 309 310 /* must be 1 less so 0 0 can signal end of chunks */ 311 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 312 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 313 314 static vm_offset_t buffer_sva, buffer_eva; 315 vm_offset_t clean_sva, clean_eva; 316 static vm_offset_t pager_sva, pager_eva; 317 static struct trapframe proc0_tf; 318 319 static void 320 cpu_startup(void *dummy) 321 { 322 caddr_t v; 323 vm_size_t size = 0; 324 vm_offset_t firstaddr; 325 326 /* 327 * Good {morning,afternoon,evening,night}. 328 */ 329 kprintf("%s", version); 330 startrtclock(); 331 printcpuinfo(); 332 panicifcpuunsupported(); 333 kprintf("real memory = %ju (%ju MB)\n", 334 (intmax_t)Realmem, 335 (intmax_t)Realmem / 1024 / 1024); 336 /* 337 * Display any holes after the first chunk of extended memory. 338 */ 339 if (bootverbose) { 340 int indx; 341 342 kprintf("Physical memory chunk(s):\n"); 343 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 344 vm_paddr_t size1; 345 346 size1 = phys_avail[indx].phys_end - 347 phys_avail[indx].phys_beg; 348 349 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 350 (intmax_t)phys_avail[indx].phys_beg, 351 (intmax_t)phys_avail[indx].phys_end - 1, 352 (intmax_t)size1, 353 (intmax_t)(size1 / PAGE_SIZE)); 354 } 355 } 356 357 /* 358 * Allocate space for system data structures. 359 * The first available kernel virtual address is in "v". 360 * As pages of kernel virtual memory are allocated, "v" is incremented. 361 * As pages of memory are allocated and cleared, 362 * "firstaddr" is incremented. 363 * An index into the kernel page table corresponding to the 364 * virtual memory address maintained in "v" is kept in "mapaddr". 365 */ 366 367 /* 368 * Make two passes. The first pass calculates how much memory is 369 * needed and allocates it. The second pass assigns virtual 370 * addresses to the various data structures. 371 */ 372 firstaddr = 0; 373 again: 374 v = (caddr_t)firstaddr; 375 376 #define valloc(name, type, num) \ 377 (name) = (type *)v; v = (caddr_t)((name)+(num)) 378 #define valloclim(name, type, num, lim) \ 379 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 380 381 /* 382 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 383 * For the first 64MB of ram nominally allocate sufficient buffers to 384 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 385 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 386 * the buffer cache we limit the eventual kva reservation to 387 * maxbcache bytes. 388 * 389 * factor represents the 1/4 x ram conversion. 390 */ 391 if (nbuf == 0) { 392 long factor = 4 * NBUFCALCSIZE / 1024; 393 long kbytes = physmem * (PAGE_SIZE / 1024); 394 395 nbuf = 50; 396 if (kbytes > 4096) 397 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 398 if (kbytes > 65536) 399 nbuf += (kbytes - 65536) * 2 / (factor * 5); 400 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 401 nbuf = maxbcache / NBUFCALCSIZE; 402 } 403 404 /* 405 * Do not allow the buffer_map to be more then 1/2 the size of the 406 * kernel_map. 407 */ 408 if (nbuf > (virtual_end - virtual_start + 409 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 410 nbuf = (virtual_end - virtual_start + 411 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 412 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 413 } 414 415 /* 416 * Do not allow the buffer_map to use more than 50% of available 417 * physical-equivalent memory. Since the VM pages which back 418 * individual buffers are typically wired, having too many bufs 419 * can prevent the system from paging properly. 420 */ 421 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 422 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 423 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 424 } 425 426 /* 427 * Do not allow the sizeof(struct buf) * nbuf to exceed 1/4 of 428 * the valloc space which is just the virtual_end - virtual_start 429 * section. This is typically ~2GB regardless of the amount of 430 * memory, so we use 500MB as a metric. 431 * 432 * This is because we use valloc() to allocate the buf header array. 433 * 434 * NOTE: buffer space in bytes is limited by vfs.*bufspace sysctls. 435 */ 436 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 4) { 437 nbuf = (virtual_end - virtual_start) / 438 sizeof(struct buf) / 2; 439 kprintf("Warning: nbufs capped at %ld due to " 440 "valloc considerations\n", 441 nbuf); 442 } 443 444 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 445 #ifdef NSWBUF_MIN 446 if (nswbuf_mem < NSWBUF_MIN) 447 nswbuf_mem = NSWBUF_MIN; 448 #endif 449 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 450 #ifdef NSWBUF_MIN 451 if (nswbuf_kva < NSWBUF_MIN) 452 nswbuf_kva = NSWBUF_MIN; 453 #endif 454 455 valloc(swbuf_mem, struct buf, nswbuf_mem); 456 valloc(swbuf_kva, struct buf, nswbuf_kva); 457 valloc(buf, struct buf, nbuf); 458 459 /* 460 * End of first pass, size has been calculated so allocate memory 461 */ 462 if (firstaddr == 0) { 463 size = (vm_size_t)(v - firstaddr); 464 firstaddr = kmem_alloc(&kernel_map, round_page(size), 465 VM_SUBSYS_BUF); 466 if (firstaddr == 0) 467 panic("startup: no room for tables"); 468 goto again; 469 } 470 471 /* 472 * End of second pass, addresses have been assigned 473 * 474 * nbuf is an int, make sure we don't overflow the field. 475 * 476 * On 64-bit systems we always reserve maximal allocations for 477 * buffer cache buffers and there are no fragmentation issues, 478 * so the KVA segment does not have to be excessively oversized. 479 */ 480 if ((vm_size_t)(v - firstaddr) != size) 481 panic("startup: table size inconsistency"); 482 483 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 484 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 485 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 486 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 487 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 488 buffer_map.system_map = 1; 489 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 490 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 491 pager_map_size); 492 pager_map.system_map = 1; 493 kprintf("avail memory = %ju (%ju MB)\n", 494 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 495 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 496 1024 / 1024); 497 } 498 499 struct cpu_idle_stat { 500 int hint; 501 int reserved; 502 u_long halt; 503 u_long spin; 504 u_long repeat; 505 u_long repeat_last; 506 u_long repeat_delta; 507 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 508 } __cachealign; 509 510 #define CPU_IDLE_STAT_HALT -1 511 #define CPU_IDLE_STAT_SPIN -2 512 513 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 514 515 static int 516 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 517 { 518 int idx = arg2, cpu, error; 519 u_long val = 0; 520 521 if (idx == CPU_IDLE_STAT_HALT) { 522 for (cpu = 0; cpu < ncpus; ++cpu) 523 val += cpu_idle_stats[cpu].halt; 524 } else if (idx == CPU_IDLE_STAT_SPIN) { 525 for (cpu = 0; cpu < ncpus; ++cpu) 526 val += cpu_idle_stats[cpu].spin; 527 } else { 528 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 529 ("invalid index %d", idx)); 530 for (cpu = 0; cpu < ncpus; ++cpu) 531 val += cpu_idle_stats[cpu].mwait_cx[idx]; 532 } 533 534 error = sysctl_handle_quad(oidp, &val, 0, req); 535 if (error || req->newptr == NULL) 536 return error; 537 538 if (idx == CPU_IDLE_STAT_HALT) { 539 for (cpu = 0; cpu < ncpus; ++cpu) 540 cpu_idle_stats[cpu].halt = 0; 541 cpu_idle_stats[0].halt = val; 542 } else if (idx == CPU_IDLE_STAT_SPIN) { 543 for (cpu = 0; cpu < ncpus; ++cpu) 544 cpu_idle_stats[cpu].spin = 0; 545 cpu_idle_stats[0].spin = val; 546 } else { 547 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 548 ("invalid index %d", idx)); 549 for (cpu = 0; cpu < ncpus; ++cpu) 550 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 551 cpu_idle_stats[0].mwait_cx[idx] = val; 552 } 553 return 0; 554 } 555 556 static void 557 cpu_mwait_attach(void) 558 { 559 struct sbuf sb; 560 int hint_idx, i; 561 562 if (!CPU_MWAIT_HAS_CX) 563 return; 564 565 if (cpu_vendor_id == CPU_VENDOR_INTEL && 566 (CPUID_TO_FAMILY(cpu_id) > 0xf || 567 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 568 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 569 int bm_sts = 1; 570 571 /* 572 * Pentium dual-core, Core 2 and beyond do not need any 573 * additional activities to enter deep C-state, i.e. C3(+). 574 */ 575 cpu_mwait_cx_no_bmarb(); 576 577 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 578 if (!bm_sts) 579 cpu_mwait_cx_no_bmsts(); 580 } 581 582 sbuf_new(&sb, cpu_mwait_cx_supported, 583 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 584 585 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 586 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 587 int sub; 588 589 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 590 591 sysctl_ctx_init(&cx->sysctl_ctx); 592 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 593 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 594 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 595 if (cx->sysctl_tree == NULL) 596 continue; 597 598 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 599 SYSCTL_ADD_INT(&cx->sysctl_ctx, 600 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 601 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 602 "sub-state count"); 603 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 604 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 605 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 606 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 607 608 for (sub = 0; sub < cx->subcnt; ++sub) 609 sbuf_printf(&sb, "C%d/%d ", i, sub); 610 } 611 sbuf_trim(&sb); 612 sbuf_finish(&sb); 613 614 /* 615 * Non-deep C-states 616 */ 617 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 618 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 619 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 620 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 621 M_DEVBUF, M_WAITOK); 622 623 hint_idx = 0; 624 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 625 int j, subcnt; 626 627 subcnt = cpu_mwait_cx_info[i].subcnt; 628 for (j = 0; j < subcnt; ++j) { 629 KASSERT(hint_idx < cpu_mwait_hints_cnt, 630 ("invalid mwait hint index %d", hint_idx)); 631 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 632 ++hint_idx; 633 } 634 } 635 KASSERT(hint_idx == cpu_mwait_hints_cnt, 636 ("mwait hint count %d != index %d", 637 cpu_mwait_hints_cnt, hint_idx)); 638 639 if (bootverbose) { 640 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 641 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 642 int hint = cpu_mwait_hints[i]; 643 644 kprintf(" C%d/%d hint 0x%04x\n", 645 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 646 hint); 647 } 648 } 649 650 /* 651 * Deep C-states 652 */ 653 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 654 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 655 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 656 M_DEVBUF, M_WAITOK); 657 658 hint_idx = 0; 659 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 660 int j, subcnt; 661 662 subcnt = cpu_mwait_cx_info[i].subcnt; 663 for (j = 0; j < subcnt; ++j) { 664 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 665 ("invalid mwait deep hint index %d", hint_idx)); 666 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 667 ++hint_idx; 668 } 669 } 670 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 671 ("mwait deep hint count %d != index %d", 672 cpu_mwait_deep_hints_cnt, hint_idx)); 673 674 if (bootverbose) { 675 kprintf("MWAIT deep hints:\n"); 676 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 677 int hint = cpu_mwait_deep_hints[i]; 678 679 kprintf(" C%d/%d hint 0x%04x\n", 680 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 681 hint); 682 } 683 } 684 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 685 686 for (i = 0; i < ncpus; ++i) { 687 char name[16]; 688 689 ksnprintf(name, sizeof(name), "idle%d", i); 690 SYSCTL_ADD_PROC(NULL, 691 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 692 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 693 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 694 } 695 } 696 697 static void 698 cpu_finish(void *dummy __unused) 699 { 700 cpu_setregs(); 701 cpu_mwait_attach(); 702 } 703 704 static void 705 pic_finish(void *dummy __unused) 706 { 707 /* Log ELCR information */ 708 elcr_dump(); 709 710 /* Log MPTABLE information */ 711 mptable_pci_int_dump(); 712 713 /* Finalize PCI */ 714 MachIntrABI.finalize(); 715 } 716 717 /* 718 * Send an interrupt to process. 719 * 720 * Stack is set up to allow sigcode stored 721 * at top to call routine, followed by kcall 722 * to sigreturn routine below. After sigreturn 723 * resets the signal mask, the stack, and the 724 * frame pointer, it returns to the user 725 * specified pc, psl. 726 */ 727 void 728 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 729 { 730 struct lwp *lp = curthread->td_lwp; 731 struct proc *p = lp->lwp_proc; 732 struct trapframe *regs; 733 struct sigacts *psp = p->p_sigacts; 734 struct sigframe sf, *sfp; 735 int oonstack; 736 char *sp; 737 738 regs = lp->lwp_md.md_regs; 739 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 740 741 /* Save user context */ 742 bzero(&sf, sizeof(struct sigframe)); 743 sf.sf_uc.uc_sigmask = *mask; 744 sf.sf_uc.uc_stack = lp->lwp_sigstk; 745 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 746 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 747 /* gcc errors out on optimized bcopy */ 748 _bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 749 750 /* Make the size of the saved context visible to userland */ 751 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 752 753 /* Allocate and validate space for the signal handler context. */ 754 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 755 SIGISMEMBER(psp->ps_sigonstack, sig)) { 756 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 757 sizeof(struct sigframe)); 758 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 759 } else { 760 /* We take red zone into account */ 761 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 762 } 763 764 /* 765 * XXX AVX needs 64-byte alignment but sigframe has other fields and 766 * the embedded ucontext is not at the front, so aligning this won't 767 * help us. Fortunately we bcopy in/out of the sigframe, so the 768 * kernel is ok. 769 * 770 * The problem though is if userland winds up trying to use the 771 * context directly. 772 */ 773 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 774 775 /* Translate the signal is appropriate */ 776 if (p->p_sysent->sv_sigtbl) { 777 if (sig <= p->p_sysent->sv_sigsize) 778 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 779 } 780 781 /* 782 * Build the argument list for the signal handler. 783 * 784 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 785 */ 786 regs->tf_rdi = sig; /* argument 1 */ 787 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 788 789 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 790 /* 791 * Signal handler installed with SA_SIGINFO. 792 * 793 * action(signo, siginfo, ucontext) 794 */ 795 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 796 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 797 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 798 799 /* fill siginfo structure */ 800 sf.sf_si.si_signo = sig; 801 sf.sf_si.si_pid = psp->ps_frominfo[sig].pid; 802 sf.sf_si.si_uid = psp->ps_frominfo[sig].uid; 803 sf.sf_si.si_code = code; 804 sf.sf_si.si_addr = (void *)regs->tf_addr; 805 } else { 806 /* 807 * Old FreeBSD-style arguments. 808 * 809 * handler (signo, code, [uc], addr) 810 */ 811 regs->tf_rsi = (register_t)code; /* argument 2 */ 812 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 813 sf.sf_ahu.sf_handler = catcher; 814 } 815 816 /* 817 * If we're a vm86 process, we want to save the segment registers. 818 * We also change eflags to be our emulated eflags, not the actual 819 * eflags. 820 */ 821 #if 0 /* JG */ 822 if (regs->tf_eflags & PSL_VM) { 823 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 824 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 825 826 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 827 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 828 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 829 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 830 831 if (vm86->vm86_has_vme == 0) 832 sf.sf_uc.uc_mcontext.mc_eflags = 833 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 834 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 835 836 /* 837 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 838 * syscalls made by the signal handler. This just avoids 839 * wasting time for our lazy fixup of such faults. PSL_NT 840 * does nothing in vm86 mode, but vm86 programs can set it 841 * almost legitimately in probes for old cpu types. 842 */ 843 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 844 } 845 #endif 846 847 /* 848 * Save the FPU state and reinit the FP unit 849 */ 850 npxpush(&sf.sf_uc.uc_mcontext); 851 852 /* 853 * Copy the sigframe out to the user's stack. 854 */ 855 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 856 /* 857 * Something is wrong with the stack pointer. 858 * ...Kill the process. 859 */ 860 sigexit(lp, SIGILL); 861 } 862 863 regs->tf_rsp = (register_t)sfp; 864 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 865 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 866 867 /* 868 * x86 abi specifies that the direction flag must be cleared 869 * on function entry 870 */ 871 regs->tf_rflags &= ~(PSL_T | PSL_D); 872 873 /* 874 * 64 bit mode has a code and stack selector but 875 * no data or extra selector. %fs and %gs are not 876 * stored in-context. 877 */ 878 regs->tf_cs = _ucodesel; 879 regs->tf_ss = _udatasel; 880 clear_quickret(); 881 } 882 883 /* 884 * Sanitize the trapframe for a virtual kernel passing control to a custom 885 * VM context. Remove any items that would otherwise create a privilage 886 * issue. 887 * 888 * XXX at the moment we allow userland to set the resume flag. Is this a 889 * bad idea? 890 */ 891 int 892 cpu_sanitize_frame(struct trapframe *frame) 893 { 894 frame->tf_cs = _ucodesel; 895 frame->tf_ss = _udatasel; 896 /* XXX VM (8086) mode not supported? */ 897 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 898 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 899 900 return(0); 901 } 902 903 /* 904 * Sanitize the tls so loading the descriptor does not blow up 905 * on us. For x86_64 we don't have to do anything. 906 */ 907 int 908 cpu_sanitize_tls(struct savetls *tls) 909 { 910 return(0); 911 } 912 913 /* 914 * sigreturn(ucontext_t *sigcntxp) 915 * 916 * System call to cleanup state after a signal 917 * has been taken. Reset signal mask and 918 * stack state from context left by sendsig (above). 919 * Return to previous pc and psl as specified by 920 * context left by sendsig. Check carefully to 921 * make sure that the user has not modified the 922 * state to gain improper privileges. 923 * 924 * MPSAFE 925 */ 926 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 927 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 928 929 int 930 sys_sigreturn(struct sigreturn_args *uap) 931 { 932 struct lwp *lp = curthread->td_lwp; 933 struct trapframe *regs; 934 ucontext_t uc; 935 ucontext_t *ucp; 936 register_t rflags; 937 int cs; 938 int error; 939 940 /* 941 * We have to copy the information into kernel space so userland 942 * can't modify it while we are sniffing it. 943 */ 944 regs = lp->lwp_md.md_regs; 945 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 946 if (error) 947 return (error); 948 ucp = &uc; 949 rflags = ucp->uc_mcontext.mc_rflags; 950 951 /* VM (8086) mode not supported */ 952 rflags &= ~PSL_VM_UNSUPP; 953 954 #if 0 /* JG */ 955 if (eflags & PSL_VM) { 956 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 957 struct vm86_kernel *vm86; 958 959 /* 960 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 961 * set up the vm86 area, and we can't enter vm86 mode. 962 */ 963 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 964 return (EINVAL); 965 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 966 if (vm86->vm86_inited == 0) 967 return (EINVAL); 968 969 /* go back to user mode if both flags are set */ 970 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 971 trapsignal(lp, SIGBUS, 0); 972 973 if (vm86->vm86_has_vme) { 974 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 975 (eflags & VME_USERCHANGE) | PSL_VM; 976 } else { 977 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 978 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 979 (eflags & VM_USERCHANGE) | PSL_VM; 980 } 981 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 982 tf->tf_eflags = eflags; 983 tf->tf_vm86_ds = tf->tf_ds; 984 tf->tf_vm86_es = tf->tf_es; 985 tf->tf_vm86_fs = tf->tf_fs; 986 tf->tf_vm86_gs = tf->tf_gs; 987 tf->tf_ds = _udatasel; 988 tf->tf_es = _udatasel; 989 tf->tf_fs = _udatasel; 990 tf->tf_gs = _udatasel; 991 } else 992 #endif 993 { 994 /* 995 * Don't allow users to change privileged or reserved flags. 996 */ 997 /* 998 * XXX do allow users to change the privileged flag PSL_RF. 999 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 1000 * should sometimes set it there too. tf_eflags is kept in 1001 * the signal context during signal handling and there is no 1002 * other place to remember it, so the PSL_RF bit may be 1003 * corrupted by the signal handler without us knowing. 1004 * Corruption of the PSL_RF bit at worst causes one more or 1005 * one less debugger trap, so allowing it is fairly harmless. 1006 */ 1007 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 1008 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 1009 return(EINVAL); 1010 } 1011 1012 /* 1013 * Don't allow users to load a valid privileged %cs. Let the 1014 * hardware check for invalid selectors, excess privilege in 1015 * other selectors, invalid %eip's and invalid %esp's. 1016 */ 1017 cs = ucp->uc_mcontext.mc_cs; 1018 if (!CS_SECURE(cs)) { 1019 kprintf("sigreturn: cs = 0x%x\n", cs); 1020 trapsignal(lp, SIGBUS, T_PROTFLT); 1021 return(EINVAL); 1022 } 1023 /* gcc errors out on optimized bcopy */ 1024 _bcopy(&ucp->uc_mcontext.mc_rdi, regs, 1025 sizeof(struct trapframe)); 1026 } 1027 1028 /* 1029 * Restore the FPU state from the frame 1030 */ 1031 crit_enter(); 1032 npxpop(&ucp->uc_mcontext); 1033 1034 if (ucp->uc_mcontext.mc_onstack & 1) 1035 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1036 else 1037 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1038 1039 lp->lwp_sigmask = ucp->uc_sigmask; 1040 SIG_CANTMASK(lp->lwp_sigmask); 1041 clear_quickret(); 1042 crit_exit(); 1043 return(EJUSTRETURN); 1044 } 1045 1046 /* 1047 * Machine dependent boot() routine 1048 * 1049 * I haven't seen anything to put here yet 1050 * Possibly some stuff might be grafted back here from boot() 1051 */ 1052 void 1053 cpu_boot(int howto) 1054 { 1055 } 1056 1057 /* 1058 * Shutdown the CPU as much as possible 1059 */ 1060 void 1061 cpu_halt(void) 1062 { 1063 for (;;) 1064 __asm__ __volatile("hlt"); 1065 } 1066 1067 /* 1068 * cpu_idle() represents the idle LWKT. You cannot return from this function 1069 * (unless you want to blow things up!). Instead we look for runnable threads 1070 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1071 * 1072 * The main loop is entered with a critical section held, we must release 1073 * the critical section before doing anything else. lwkt_switch() will 1074 * check for pending interrupts due to entering and exiting its own 1075 * critical section. 1076 * 1077 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1078 * However, there are cases where the idlethread will be entered with 1079 * the possibility that no IPI will occur and in such cases 1080 * lwkt_switch() sets TDF_IDLE_NOHLT. 1081 * 1082 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1083 * must occur before it starts using ACPI halt. 1084 * 1085 * NOTE: Value overridden in hammer_time(). 1086 */ 1087 static int cpu_idle_hlt = 2; 1088 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1089 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1090 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1091 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1092 1093 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1094 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1095 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1096 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1097 1098 static void 1099 cpu_idle_default_hook(void) 1100 { 1101 /* 1102 * We must guarentee that hlt is exactly the instruction 1103 * following the sti. 1104 */ 1105 __asm __volatile("sti; hlt"); 1106 } 1107 1108 /* Other subsystems (e.g., ACPI) can hook this later. */ 1109 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1110 1111 static __inline int 1112 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1113 { 1114 int hint, cx_idx; 1115 u_int idx; 1116 1117 hint = stat->hint; 1118 if (hint >= 0) 1119 goto done; 1120 1121 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1122 cpu_mwait_repeat_shift; 1123 if (idx >= cpu_mwait_c1_hints_cnt) { 1124 /* Step up faster, once we walked through all C1 states */ 1125 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1126 } 1127 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1128 if (idx >= cpu_mwait_deep_hints_cnt) 1129 idx = cpu_mwait_deep_hints_cnt - 1; 1130 hint = cpu_mwait_deep_hints[idx]; 1131 } else { 1132 if (idx >= cpu_mwait_hints_cnt) 1133 idx = cpu_mwait_hints_cnt - 1; 1134 hint = cpu_mwait_hints[idx]; 1135 } 1136 done: 1137 cx_idx = MWAIT_EAX_TO_CX(hint); 1138 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1139 stat->mwait_cx[cx_idx]++; 1140 return hint; 1141 } 1142 1143 void 1144 cpu_idle(void) 1145 { 1146 globaldata_t gd = mycpu; 1147 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1148 struct thread *td __debugvar = gd->gd_curthread; 1149 int reqflags; 1150 1151 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1152 1153 crit_exit(); 1154 KKASSERT(td->td_critcount == 0); 1155 1156 for (;;) { 1157 /* 1158 * See if there are any LWKTs ready to go. 1159 */ 1160 lwkt_switch(); 1161 1162 /* 1163 * When halting inside a cli we must check for reqflags 1164 * races, particularly [re]schedule requests. Running 1165 * splz() does the job. 1166 * 1167 * cpu_idle_hlt: 1168 * 0 Never halt, just spin 1169 * 1170 * 1 Always use MONITOR/MWAIT if avail, HLT 1171 * otherwise. 1172 * 1173 * Better default for modern (Haswell+) Intel 1174 * cpus. 1175 * 1176 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1177 * use the ACPI halt (default). This is a hybrid 1178 * approach. See machdep.cpu_idle_repeat. 1179 * 1180 * Better default for modern AMD cpus and older 1181 * Intel cpus. 1182 * 1183 * 3 Always use the ACPI halt. This typically 1184 * eats the least amount of power but the cpu 1185 * will be slow waking up. Slows down e.g. 1186 * compiles and other pipe/event oriented stuff. 1187 * 1188 * Usually the best default for AMD cpus. 1189 * 1190 * 4 Always use HLT. 1191 * 1192 * 5 Always spin. 1193 * 1194 * NOTE: Interrupts are enabled and we are not in a critical 1195 * section. 1196 * 1197 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1198 * don't bother capping gd_idle_repeat, it is ok if 1199 * it overflows (we do make it unsigned, however). 1200 * 1201 * Implement optimized invltlb operations when halted 1202 * in idle. By setting the bit in smp_idleinvl_mask 1203 * we inform other cpus that they can set _reqs to 1204 * request an invltlb. Current the code to do that 1205 * sets the bits in _reqs anyway, but then check _mask 1206 * to determine if they can assume the invltlb will execute. 1207 * 1208 * A critical section is required to ensure that interrupts 1209 * do not fully run until after we've had a chance to execute 1210 * the request. 1211 */ 1212 if (gd->gd_idle_repeat == 0) { 1213 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1214 if (stat->repeat > cpu_idle_repeat_max) 1215 stat->repeat = cpu_idle_repeat_max; 1216 stat->repeat_last = 0; 1217 stat->repeat_delta = 0; 1218 } 1219 ++stat->repeat_last; 1220 1221 /* 1222 * General idle thread halt code 1223 * 1224 * IBRS NOTES - IBRS is a SPECTRE mitigation. When going 1225 * idle, disable IBRS to reduce hyperthread 1226 * overhead. 1227 */ 1228 ++gd->gd_idle_repeat; 1229 1230 switch(cpu_idle_hlt) { 1231 default: 1232 case 0: 1233 /* 1234 * Always spin 1235 */ 1236 ; 1237 do_spin: 1238 splz(); 1239 __asm __volatile("sti"); 1240 stat->spin++; 1241 crit_enter_gd(gd); 1242 crit_exit_gd(gd); 1243 break; 1244 case 2: 1245 /* 1246 * Use MONITOR/MWAIT (or HLT) for a few cycles, 1247 * then start using the ACPI halt code if we 1248 * continue to be idle. 1249 */ 1250 if (gd->gd_idle_repeat >= cpu_idle_repeat) 1251 goto do_acpi; 1252 /* FALL THROUGH */ 1253 case 1: 1254 /* 1255 * Always use MONITOR/MWAIT (will use HLT if 1256 * MONITOR/MWAIT not available). 1257 */ 1258 if (cpu_mi_feature & CPU_MI_MONITOR) { 1259 splz(); /* XXX */ 1260 reqflags = gd->gd_reqflags; 1261 if (reqflags & RQF_IDLECHECK_WK_MASK) 1262 goto do_spin; 1263 crit_enter_gd(gd); 1264 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1265 /* 1266 * IBRS/STIBP 1267 */ 1268 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1269 SPEC_CTRL_DUMMY_ENABLE) { 1270 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1271 } 1272 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1273 cpu_mwait_cx_hint(stat), 0); 1274 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1275 SPEC_CTRL_DUMMY_ENABLE) { 1276 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1277 } 1278 stat->halt++; 1279 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1280 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1281 gd->gd_cpuid)) { 1282 cpu_invltlb(); 1283 cpu_mfence(); 1284 } 1285 crit_exit_gd(gd); 1286 break; 1287 } 1288 /* FALLTHROUGH */ 1289 case 4: 1290 /* 1291 * Use HLT 1292 */ 1293 __asm __volatile("cli"); 1294 splz(); 1295 crit_enter_gd(gd); 1296 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1297 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1298 gd->gd_cpuid); 1299 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1300 SPEC_CTRL_DUMMY_ENABLE) { 1301 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1302 } 1303 cpu_idle_default_hook(); 1304 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1305 SPEC_CTRL_DUMMY_ENABLE) { 1306 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1307 } 1308 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1309 gd->gd_cpuid); 1310 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1311 gd->gd_cpuid)) { 1312 cpu_invltlb(); 1313 cpu_mfence(); 1314 } 1315 } 1316 __asm __volatile("sti"); 1317 stat->halt++; 1318 crit_exit_gd(gd); 1319 break; 1320 case 3: 1321 /* 1322 * Use ACPI halt 1323 */ 1324 ; 1325 do_acpi: 1326 __asm __volatile("cli"); 1327 splz(); 1328 crit_enter_gd(gd); 1329 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1330 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, 1331 gd->gd_cpuid); 1332 if (pscpu->trampoline.tr_pcb_spec_ctrl[1] & 1333 SPEC_CTRL_DUMMY_ENABLE) { 1334 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1335 } 1336 cpu_idle_hook(); 1337 if (pscpu->trampoline.tr_pcb_spec_ctrl[0] & 1338 SPEC_CTRL_DUMMY_ENABLE) { 1339 wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 1340 } 1341 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, 1342 gd->gd_cpuid); 1343 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1344 gd->gd_cpuid)) { 1345 cpu_invltlb(); 1346 cpu_mfence(); 1347 } 1348 } 1349 __asm __volatile("sti"); 1350 stat->halt++; 1351 crit_exit_gd(gd); 1352 break; 1353 } 1354 } 1355 } 1356 1357 /* 1358 * Called from deep ACPI via cpu_idle_hook() (see above) to actually halt 1359 * the cpu in C1. ACPI might use other halt methods for deeper states 1360 * and not reach here. 1361 * 1362 * For now we always use HLT as we are not sure what ACPI may have actually 1363 * done. MONITOR/MWAIT might not be appropriate. 1364 * 1365 * NOTE: MONITOR/MWAIT does not appear to throttle AMD cpus, while HLT 1366 * does. On Intel, MONITOR/MWAIT does appear to throttle the cpu. 1367 */ 1368 void 1369 cpu_idle_halt(void) 1370 { 1371 globaldata_t gd; 1372 1373 gd = mycpu; 1374 #if 0 1375 /* DISABLED FOR NOW */ 1376 struct cpu_idle_stat *stat; 1377 int reqflags; 1378 1379 1380 if ((cpu_idle_hlt == 1 || cpu_idle_hlt == 2) && 1381 (cpu_mi_feature & CPU_MI_MONITOR) && 1382 cpu_vendor_id != CPU_VENDOR_AMD) { 1383 /* 1384 * Use MONITOR/MWAIT 1385 * 1386 * (NOTE: On ryzen, MWAIT does not throttle clocks, so we 1387 * have to use HLT) 1388 */ 1389 stat = &cpu_idle_stats[gd->gd_cpuid]; 1390 reqflags = gd->gd_reqflags; 1391 if ((reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1392 __asm __volatile("sti"); 1393 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1394 cpu_mwait_cx_hint(stat), 0); 1395 } else { 1396 __asm __volatile("sti; pause"); 1397 } 1398 } else 1399 #endif 1400 { 1401 /* 1402 * Use HLT 1403 */ 1404 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1405 __asm __volatile("sti; hlt"); 1406 else 1407 __asm __volatile("sti; pause"); 1408 } 1409 } 1410 1411 1412 /* 1413 * Called in a loop indirectly via Xcpustop 1414 */ 1415 void 1416 cpu_smp_stopped(void) 1417 { 1418 globaldata_t gd = mycpu; 1419 volatile __uint64_t *ptr; 1420 __uint64_t ovalue; 1421 1422 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1423 ovalue = *ptr; 1424 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1425 if (cpu_mi_feature & CPU_MI_MONITOR) { 1426 if (cpu_mwait_hints) { 1427 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1428 ovalue, 1429 cpu_mwait_hints[ 1430 cpu_mwait_hints_cnt - 1], 0); 1431 } else { 1432 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1433 ovalue, 0, 0); 1434 } 1435 } else { 1436 cpu_halt(); /* depend on lapic timer */ 1437 } 1438 } 1439 } 1440 1441 /* 1442 * This routine is called if a spinlock has been held through the 1443 * exponential backoff period and is seriously contested. On a real cpu 1444 * we let it spin. 1445 */ 1446 void 1447 cpu_spinlock_contested(void) 1448 { 1449 cpu_pause(); 1450 } 1451 1452 /* 1453 * Clear registers on exec 1454 */ 1455 void 1456 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1457 { 1458 struct thread *td = curthread; 1459 struct lwp *lp = td->td_lwp; 1460 struct pcb *pcb = td->td_pcb; 1461 struct trapframe *regs = lp->lwp_md.md_regs; 1462 1463 user_ldt_free(pcb); 1464 1465 clear_quickret(); 1466 bzero((char *)regs, sizeof(struct trapframe)); 1467 regs->tf_rip = entry; 1468 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1469 regs->tf_rdi = stack; /* argv */ 1470 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1471 regs->tf_ss = _udatasel; 1472 regs->tf_cs = _ucodesel; 1473 regs->tf_rbx = ps_strings; 1474 1475 /* 1476 * Reset the hardware debug registers if they were in use. 1477 * They won't have any meaning for the newly exec'd process. 1478 */ 1479 if (pcb->pcb_flags & PCB_DBREGS) { 1480 pcb->pcb_dr0 = 0; 1481 pcb->pcb_dr1 = 0; 1482 pcb->pcb_dr2 = 0; 1483 pcb->pcb_dr3 = 0; 1484 pcb->pcb_dr6 = 0; 1485 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1486 if (pcb == td->td_pcb) { 1487 /* 1488 * Clear the debug registers on the running 1489 * CPU, otherwise they will end up affecting 1490 * the next process we switch to. 1491 */ 1492 reset_dbregs(); 1493 } 1494 pcb->pcb_flags &= ~PCB_DBREGS; 1495 } 1496 1497 /* 1498 * Initialize the math emulator (if any) for the current process. 1499 * Actually, just clear the bit that says that the emulator has 1500 * been initialized. Initialization is delayed until the process 1501 * traps to the emulator (if it is done at all) mainly because 1502 * emulators don't provide an entry point for initialization. 1503 */ 1504 pcb->pcb_flags &= ~FP_SOFTFP; 1505 1506 /* 1507 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1508 * gd_npxthread. Otherwise a preemptive interrupt thread 1509 * may panic in npxdna(). 1510 */ 1511 crit_enter(); 1512 load_cr0(rcr0() | CR0_MP); 1513 1514 /* 1515 * NOTE: The MSR values must be correct so we can return to 1516 * userland. gd_user_fs/gs must be correct so the switch 1517 * code knows what the current MSR values are. 1518 */ 1519 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1520 pcb->pcb_gsbase = 0; 1521 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1522 mdcpu->gd_user_gs = 0; 1523 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1524 wrmsr(MSR_KGSBASE, 0); 1525 1526 /* Initialize the npx (if any) for the current process. */ 1527 npxinit(); 1528 crit_exit(); 1529 1530 pcb->pcb_ds = _udatasel; 1531 pcb->pcb_es = _udatasel; 1532 pcb->pcb_fs = _udatasel; 1533 pcb->pcb_gs = _udatasel; 1534 } 1535 1536 void 1537 cpu_setregs(void) 1538 { 1539 register_t cr0; 1540 1541 cr0 = rcr0(); 1542 cr0 |= CR0_NE; /* Done by npxinit() */ 1543 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1544 cr0 |= CR0_WP | CR0_AM; 1545 load_cr0(cr0); 1546 load_gs(_udatasel); 1547 } 1548 1549 static int 1550 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1551 { 1552 int error; 1553 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1554 req); 1555 if (!error && req->newptr) 1556 resettodr(); 1557 return (error); 1558 } 1559 1560 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1561 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1562 1563 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1564 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1565 1566 #if 0 /* JG */ 1567 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1568 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1569 #endif 1570 1571 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1572 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1573 1574 static int 1575 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1576 { 1577 struct efi_map_header *efihdr; 1578 caddr_t kmdp; 1579 uint32_t efisize; 1580 1581 kmdp = preload_search_by_type("elf kernel"); 1582 if (kmdp == NULL) 1583 kmdp = preload_search_by_type("elf64 kernel"); 1584 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1585 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1586 if (efihdr == NULL) 1587 return (0); 1588 efisize = *((uint32_t *)efihdr - 1); 1589 return (SYSCTL_OUT(req, efihdr, efisize)); 1590 } 1591 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1592 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1593 1594 /* 1595 * Initialize x86 and configure to run kernel 1596 */ 1597 1598 /* 1599 * Initialize segments & interrupt table 1600 */ 1601 1602 int _default_ldt; 1603 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1604 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1605 #if 0 /* JG */ 1606 union descriptor ldt[NLDT]; /* local descriptor table */ 1607 #endif 1608 1609 /* table descriptors - used to load tables by cpu */ 1610 struct region_descriptor r_gdt; 1611 struct region_descriptor r_idt_arr[MAXCPU]; 1612 1613 /* JG proc0paddr is a virtual address */ 1614 void *proc0paddr; 1615 /* JG alignment? */ 1616 char proc0paddr_buff[LWKT_THREAD_STACK]; 1617 1618 1619 /* software prototypes -- in more palatable form */ 1620 struct soft_segment_descriptor gdt_segs[] = { 1621 /* GNULL_SEL 0 Null Descriptor */ 1622 { 0x0, /* segment base address */ 1623 0x0, /* length */ 1624 0, /* segment type */ 1625 0, /* segment descriptor priority level */ 1626 0, /* segment descriptor present */ 1627 0, /* long */ 1628 0, /* default 32 vs 16 bit size */ 1629 0 /* limit granularity (byte/page units)*/ }, 1630 /* GCODE_SEL 1 Code Descriptor for kernel */ 1631 { 0x0, /* segment base address */ 1632 0xfffff, /* length - all address space */ 1633 SDT_MEMERA, /* segment type */ 1634 SEL_KPL, /* segment descriptor priority level */ 1635 1, /* segment descriptor present */ 1636 1, /* long */ 1637 0, /* default 32 vs 16 bit size */ 1638 1 /* limit granularity (byte/page units)*/ }, 1639 /* GDATA_SEL 2 Data Descriptor for kernel */ 1640 { 0x0, /* segment base address */ 1641 0xfffff, /* length - all address space */ 1642 SDT_MEMRWA, /* segment type */ 1643 SEL_KPL, /* segment descriptor priority level */ 1644 1, /* segment descriptor present */ 1645 1, /* long */ 1646 0, /* default 32 vs 16 bit size */ 1647 1 /* limit granularity (byte/page units)*/ }, 1648 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1649 { 0x0, /* segment base address */ 1650 0xfffff, /* length - all address space */ 1651 SDT_MEMERA, /* segment type */ 1652 SEL_UPL, /* segment descriptor priority level */ 1653 1, /* segment descriptor present */ 1654 0, /* long */ 1655 1, /* default 32 vs 16 bit size */ 1656 1 /* limit granularity (byte/page units)*/ }, 1657 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1658 { 0x0, /* segment base address */ 1659 0xfffff, /* length - all address space */ 1660 SDT_MEMRWA, /* segment type */ 1661 SEL_UPL, /* segment descriptor priority level */ 1662 1, /* segment descriptor present */ 1663 0, /* long */ 1664 1, /* default 32 vs 16 bit size */ 1665 1 /* limit granularity (byte/page units)*/ }, 1666 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1667 { 0x0, /* segment base address */ 1668 0xfffff, /* length - all address space */ 1669 SDT_MEMERA, /* segment type */ 1670 SEL_UPL, /* segment descriptor priority level */ 1671 1, /* segment descriptor present */ 1672 1, /* long */ 1673 0, /* default 32 vs 16 bit size */ 1674 1 /* limit granularity (byte/page units)*/ }, 1675 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1676 { 1677 0x0, /* segment base address */ 1678 sizeof(struct x86_64tss)-1,/* length - all address space */ 1679 SDT_SYSTSS, /* segment type */ 1680 SEL_KPL, /* segment descriptor priority level */ 1681 1, /* segment descriptor present */ 1682 0, /* long */ 1683 0, /* unused - default 32 vs 16 bit size */ 1684 0 /* limit granularity (byte/page units)*/ }, 1685 /* Actually, the TSS is a system descriptor which is double size */ 1686 { 0x0, /* segment base address */ 1687 0x0, /* length */ 1688 0, /* segment type */ 1689 0, /* segment descriptor priority level */ 1690 0, /* segment descriptor present */ 1691 0, /* long */ 1692 0, /* default 32 vs 16 bit size */ 1693 0 /* limit granularity (byte/page units)*/ }, 1694 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1695 { 0x0, /* segment base address */ 1696 0xfffff, /* length - all address space */ 1697 SDT_MEMRWA, /* segment type */ 1698 SEL_UPL, /* segment descriptor priority level */ 1699 1, /* segment descriptor present */ 1700 0, /* long */ 1701 1, /* default 32 vs 16 bit size */ 1702 1 /* limit granularity (byte/page units)*/ }, 1703 }; 1704 1705 void 1706 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1707 { 1708 int cpu; 1709 1710 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1711 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1712 1713 ip->gd_looffset = (uintptr_t)func; 1714 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1715 ip->gd_ist = ist; 1716 ip->gd_xx = 0; 1717 ip->gd_type = typ; 1718 ip->gd_dpl = dpl; 1719 ip->gd_p = 1; 1720 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1721 } 1722 } 1723 1724 void 1725 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1726 { 1727 struct gate_descriptor *ip; 1728 1729 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1730 1731 ip = &idt_arr[cpu][idx]; 1732 ip->gd_looffset = (uintptr_t)func; 1733 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1734 ip->gd_ist = ist; 1735 ip->gd_xx = 0; 1736 ip->gd_type = typ; 1737 ip->gd_dpl = dpl; 1738 ip->gd_p = 1; 1739 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1740 } 1741 1742 #define IDTVEC(name) __CONCAT(X,name) 1743 1744 extern inthand_t 1745 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1746 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1747 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1748 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1749 IDTVEC(xmm), IDTVEC(dblfault), 1750 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1751 1752 void 1753 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1754 { 1755 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1756 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1757 ssd->ssd_type = sd->sd_type; 1758 ssd->ssd_dpl = sd->sd_dpl; 1759 ssd->ssd_p = sd->sd_p; 1760 ssd->ssd_def32 = sd->sd_def32; 1761 ssd->ssd_gran = sd->sd_gran; 1762 } 1763 1764 void 1765 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1766 { 1767 1768 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1769 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1770 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1771 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1772 sd->sd_type = ssd->ssd_type; 1773 sd->sd_dpl = ssd->ssd_dpl; 1774 sd->sd_p = ssd->ssd_p; 1775 sd->sd_long = ssd->ssd_long; 1776 sd->sd_def32 = ssd->ssd_def32; 1777 sd->sd_gran = ssd->ssd_gran; 1778 } 1779 1780 void 1781 ssdtosyssd(struct soft_segment_descriptor *ssd, 1782 struct system_segment_descriptor *sd) 1783 { 1784 1785 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1786 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1787 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1788 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1789 sd->sd_type = ssd->ssd_type; 1790 sd->sd_dpl = ssd->ssd_dpl; 1791 sd->sd_p = ssd->ssd_p; 1792 sd->sd_gran = ssd->ssd_gran; 1793 } 1794 1795 /* 1796 * Populate the (physmap) array with base/bound pairs describing the 1797 * available physical memory in the system, then test this memory and 1798 * build the phys_avail array describing the actually-available memory. 1799 * 1800 * If we cannot accurately determine the physical memory map, then use 1801 * value from the 0xE801 call, and failing that, the RTC. 1802 * 1803 * Total memory size may be set by the kernel environment variable 1804 * hw.physmem or the compile-time define MAXMEM. 1805 * 1806 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1807 * of PAGE_SIZE. This also greatly reduces the memory test time 1808 * which would otherwise be excessive on machines with > 8G of ram. 1809 * 1810 * XXX first should be vm_paddr_t. 1811 */ 1812 1813 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1814 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1815 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1816 1817 vm_paddr_t physmap[PHYSMAP_SIZE]; 1818 struct bios_smap *smapbase, *smap, *smapend; 1819 struct efi_map_header *efihdrbase; 1820 u_int32_t smapsize; 1821 1822 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1823 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1824 1825 static void 1826 add_smap_entries(int *physmap_idx) 1827 { 1828 int i; 1829 1830 smapsize = *((u_int32_t *)smapbase - 1); 1831 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1832 1833 for (smap = smapbase; smap < smapend; smap++) { 1834 if (boothowto & RB_VERBOSE) 1835 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1836 smap->type, smap->base, smap->length); 1837 1838 if (smap->type != SMAP_TYPE_MEMORY) 1839 continue; 1840 1841 if (smap->length == 0) 1842 continue; 1843 1844 for (i = 0; i <= *physmap_idx; i += 2) { 1845 if (smap->base < physmap[i + 1]) { 1846 if (boothowto & RB_VERBOSE) { 1847 kprintf("Overlapping or non-monotonic " 1848 "memory region, ignoring " 1849 "second region\n"); 1850 } 1851 break; 1852 } 1853 } 1854 if (i <= *physmap_idx) 1855 continue; 1856 1857 Realmem += smap->length; 1858 1859 if (smap->base == physmap[*physmap_idx + 1]) { 1860 physmap[*physmap_idx + 1] += smap->length; 1861 continue; 1862 } 1863 1864 *physmap_idx += 2; 1865 if (*physmap_idx == PHYSMAP_SIZE) { 1866 kprintf("Too many segments in the physical " 1867 "address map, giving up\n"); 1868 break; 1869 } 1870 physmap[*physmap_idx] = smap->base; 1871 physmap[*physmap_idx + 1] = smap->base + smap->length; 1872 } 1873 } 1874 1875 static void 1876 add_efi_map_entries(int *physmap_idx) 1877 { 1878 struct efi_md *map, *p; 1879 const char *type; 1880 size_t efisz; 1881 int i, ndesc; 1882 1883 static const char *types[] = { 1884 "Reserved", 1885 "LoaderCode", 1886 "LoaderData", 1887 "BootServicesCode", 1888 "BootServicesData", 1889 "RuntimeServicesCode", 1890 "RuntimeServicesData", 1891 "ConventionalMemory", 1892 "UnusableMemory", 1893 "ACPIReclaimMemory", 1894 "ACPIMemoryNVS", 1895 "MemoryMappedIO", 1896 "MemoryMappedIOPortSpace", 1897 "PalCode" 1898 }; 1899 1900 /* 1901 * Memory map data provided by UEFI via the GetMemoryMap 1902 * Boot Services API. 1903 */ 1904 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1905 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1906 1907 if (efihdrbase->descriptor_size == 0) 1908 return; 1909 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1910 1911 if (boothowto & RB_VERBOSE) 1912 kprintf("%23s %12s %12s %8s %4s\n", 1913 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1914 1915 for (i = 0, p = map; i < ndesc; i++, 1916 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1917 if (boothowto & RB_VERBOSE) { 1918 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1919 type = types[p->md_type]; 1920 else 1921 type = "<INVALID>"; 1922 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1923 p->md_virt, p->md_pages); 1924 if (p->md_attr & EFI_MD_ATTR_UC) 1925 kprintf("UC "); 1926 if (p->md_attr & EFI_MD_ATTR_WC) 1927 kprintf("WC "); 1928 if (p->md_attr & EFI_MD_ATTR_WT) 1929 kprintf("WT "); 1930 if (p->md_attr & EFI_MD_ATTR_WB) 1931 kprintf("WB "); 1932 if (p->md_attr & EFI_MD_ATTR_UCE) 1933 kprintf("UCE "); 1934 if (p->md_attr & EFI_MD_ATTR_WP) 1935 kprintf("WP "); 1936 if (p->md_attr & EFI_MD_ATTR_RP) 1937 kprintf("RP "); 1938 if (p->md_attr & EFI_MD_ATTR_XP) 1939 kprintf("XP "); 1940 if (p->md_attr & EFI_MD_ATTR_RT) 1941 kprintf("RUNTIME"); 1942 kprintf("\n"); 1943 } 1944 1945 switch (p->md_type) { 1946 case EFI_MD_TYPE_CODE: 1947 case EFI_MD_TYPE_DATA: 1948 case EFI_MD_TYPE_BS_CODE: 1949 case EFI_MD_TYPE_BS_DATA: 1950 case EFI_MD_TYPE_FREE: 1951 /* 1952 * We're allowed to use any entry with these types. 1953 */ 1954 break; 1955 default: 1956 continue; 1957 } 1958 1959 Realmem += p->md_pages * PAGE_SIZE; 1960 1961 if (p->md_phys == physmap[*physmap_idx + 1]) { 1962 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1963 continue; 1964 } 1965 1966 *physmap_idx += 2; 1967 if (*physmap_idx == PHYSMAP_SIZE) { 1968 kprintf("Too many segments in the physical " 1969 "address map, giving up\n"); 1970 break; 1971 } 1972 physmap[*physmap_idx] = p->md_phys; 1973 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1974 } 1975 } 1976 1977 struct fb_info efi_fb_info; 1978 static int have_efi_framebuffer = 0; 1979 1980 static void 1981 efi_fb_init_vaddr(int direct_map) 1982 { 1983 uint64_t sz; 1984 vm_offset_t addr, v; 1985 1986 v = efi_fb_info.vaddr; 1987 sz = efi_fb_info.stride * efi_fb_info.height; 1988 1989 if (direct_map) { 1990 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1991 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1992 efi_fb_info.vaddr = addr; 1993 } else { 1994 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1995 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1996 } 1997 } 1998 1999 static u_int 2000 efifb_color_depth(struct efi_fb *efifb) 2001 { 2002 uint32_t mask; 2003 u_int depth; 2004 2005 mask = efifb->fb_mask_red | efifb->fb_mask_green | 2006 efifb->fb_mask_blue | efifb->fb_mask_reserved; 2007 if (mask == 0) 2008 return (0); 2009 for (depth = 1; mask != 1; depth++) 2010 mask >>= 1; 2011 return (depth); 2012 } 2013 2014 int 2015 probe_efi_fb(int early) 2016 { 2017 struct efi_fb *efifb; 2018 caddr_t kmdp; 2019 u_int depth; 2020 2021 if (have_efi_framebuffer) { 2022 if (!early && 2023 (efi_fb_info.vaddr == 0 || 2024 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 2025 efi_fb_init_vaddr(0); 2026 return 0; 2027 } 2028 2029 kmdp = preload_search_by_type("elf kernel"); 2030 if (kmdp == NULL) 2031 kmdp = preload_search_by_type("elf64 kernel"); 2032 efifb = (struct efi_fb *)preload_search_info(kmdp, 2033 MODINFO_METADATA | MODINFOMD_EFI_FB); 2034 if (efifb == NULL) 2035 return 1; 2036 2037 depth = efifb_color_depth(efifb); 2038 /* 2039 * Our bootloader should already notice, when we won't be able to 2040 * use the UEFI framebuffer. 2041 */ 2042 if (depth != 24 && depth != 32) 2043 return 1; 2044 2045 have_efi_framebuffer = 1; 2046 2047 efi_fb_info.is_vga_boot_display = 1; 2048 efi_fb_info.width = efifb->fb_width; 2049 efi_fb_info.height = efifb->fb_height; 2050 efi_fb_info.depth = depth; 2051 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 2052 efi_fb_info.paddr = efifb->fb_addr; 2053 if (early) { 2054 efi_fb_info.vaddr = 0; 2055 } else { 2056 efi_fb_init_vaddr(0); 2057 } 2058 efi_fb_info.fbops.fb_set_par = NULL; 2059 efi_fb_info.fbops.fb_blank = NULL; 2060 efi_fb_info.fbops.fb_debug_enter = NULL; 2061 efi_fb_info.device = NULL; 2062 2063 return 0; 2064 } 2065 2066 static void 2067 efifb_startup(void *arg) 2068 { 2069 probe_efi_fb(0); 2070 } 2071 2072 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 2073 2074 static void 2075 getmemsize(caddr_t kmdp, u_int64_t first) 2076 { 2077 int off, physmap_idx, pa_indx, da_indx; 2078 int i, j; 2079 vm_paddr_t pa; 2080 vm_paddr_t msgbuf_size; 2081 u_long physmem_tunable; 2082 pt_entry_t *pte; 2083 quad_t dcons_addr, dcons_size; 2084 2085 bzero(physmap, sizeof(physmap)); 2086 physmap_idx = 0; 2087 2088 /* 2089 * get memory map from INT 15:E820, kindly supplied by the loader. 2090 * 2091 * subr_module.c says: 2092 * "Consumer may safely assume that size value precedes data." 2093 * ie: an int32_t immediately precedes smap. 2094 */ 2095 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 2096 MODINFO_METADATA | MODINFOMD_EFI_MAP); 2097 smapbase = (struct bios_smap *)preload_search_info(kmdp, 2098 MODINFO_METADATA | MODINFOMD_SMAP); 2099 if (smapbase == NULL && efihdrbase == NULL) 2100 panic("No BIOS smap or EFI map info from loader!"); 2101 2102 if (efihdrbase == NULL) 2103 add_smap_entries(&physmap_idx); 2104 else 2105 add_efi_map_entries(&physmap_idx); 2106 2107 base_memory = physmap[1] / 1024; 2108 /* make hole for AP bootstrap code */ 2109 physmap[1] = mp_bootaddress(base_memory); 2110 2111 /* Save EBDA address, if any */ 2112 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 2113 ebda_addr <<= 4; 2114 2115 /* 2116 * Maxmem isn't the "maximum memory", it's one larger than the 2117 * highest page of the physical address space. It should be 2118 * called something like "Maxphyspage". We may adjust this 2119 * based on ``hw.physmem'' and the results of the memory test. 2120 */ 2121 Maxmem = atop(physmap[physmap_idx + 1]); 2122 2123 #ifdef MAXMEM 2124 Maxmem = MAXMEM / 4; 2125 #endif 2126 2127 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 2128 Maxmem = atop(physmem_tunable); 2129 2130 /* 2131 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 2132 * in the system. 2133 */ 2134 if (Maxmem > atop(physmap[physmap_idx + 1])) 2135 Maxmem = atop(physmap[physmap_idx + 1]); 2136 2137 /* 2138 * Blowing out the DMAP will blow up the system. 2139 */ 2140 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 2141 kprintf("Limiting Maxmem due to DMAP size\n"); 2142 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 2143 } 2144 2145 if (atop(physmap[physmap_idx + 1]) != Maxmem && 2146 (boothowto & RB_VERBOSE)) { 2147 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 2148 } 2149 2150 /* 2151 * Call pmap initialization to make new kernel address space 2152 * 2153 * Mask off page 0. 2154 */ 2155 pmap_bootstrap(&first); 2156 physmap[0] = PAGE_SIZE; 2157 2158 /* 2159 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2160 * exceeding Maxmem. 2161 */ 2162 for (i = j = 0; i <= physmap_idx; i += 2) { 2163 if (physmap[i+1] > ptoa(Maxmem)) 2164 physmap[i+1] = ptoa(Maxmem); 2165 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2166 ~PHYSMAP_ALIGN_MASK; 2167 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2168 2169 physmap[j] = physmap[i]; 2170 physmap[j+1] = physmap[i+1]; 2171 2172 if (physmap[i] < physmap[i+1]) 2173 j += 2; 2174 } 2175 physmap_idx = j - 2; 2176 2177 /* 2178 * Align anything else used in the validation loop. 2179 * 2180 * Also make sure that our 2MB kernel text+data+bss mappings 2181 * do not overlap potentially allocatable space. 2182 */ 2183 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2184 2185 /* 2186 * Size up each available chunk of physical memory. 2187 */ 2188 pa_indx = 0; 2189 da_indx = 0; 2190 phys_avail[pa_indx].phys_beg = physmap[0]; 2191 phys_avail[pa_indx].phys_end = physmap[0]; 2192 dump_avail[da_indx].phys_beg = 0; 2193 dump_avail[da_indx].phys_end = physmap[0]; 2194 pte = CMAP1; 2195 2196 /* 2197 * Get dcons buffer address 2198 */ 2199 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2200 kgetenv_quad("dcons.size", &dcons_size) == 0) 2201 dcons_addr = 0; 2202 2203 /* 2204 * Validate the physical memory. The physical memory segments 2205 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2206 * of PAGE_SIZE. 2207 * 2208 * We no longer perform an exhaustive memory test. Instead we 2209 * simply test the first and last word in each physmap[] 2210 * segment. 2211 */ 2212 for (i = 0; i <= physmap_idx; i += 2) { 2213 vm_paddr_t end; 2214 vm_paddr_t incr; 2215 2216 end = physmap[i + 1]; 2217 2218 for (pa = physmap[i]; pa < end; pa += incr) { 2219 int page_bad, full; 2220 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2221 uint64_t tmp; 2222 2223 full = FALSE; 2224 2225 /* 2226 * Calculate incr. Just test the first and 2227 * last page in each physmap[] segment. 2228 */ 2229 if (pa == end - PAGE_SIZE) 2230 incr = PAGE_SIZE; 2231 else 2232 incr = end - pa - PAGE_SIZE; 2233 2234 /* 2235 * Make sure we don't skip blacked out areas. 2236 */ 2237 if (pa < 0x200000 && 0x200000 < end) { 2238 incr = 0x200000 - pa; 2239 } 2240 if (dcons_addr > 0 && 2241 pa < dcons_addr && 2242 dcons_addr < end) { 2243 incr = dcons_addr - pa; 2244 } 2245 2246 /* 2247 * Block out kernel memory as not available. 2248 */ 2249 if (pa >= 0x200000 && pa < first) { 2250 incr = first - pa; 2251 if (pa + incr > end) 2252 incr = end - pa; 2253 goto do_dump_avail; 2254 } 2255 2256 /* 2257 * Block out the dcons buffer if it exists. 2258 */ 2259 if (dcons_addr > 0 && 2260 pa >= trunc_page(dcons_addr) && 2261 pa < dcons_addr + dcons_size) { 2262 incr = dcons_addr + dcons_size - pa; 2263 incr = (incr + PAGE_MASK) & 2264 ~(vm_paddr_t)PAGE_MASK; 2265 if (pa + incr > end) 2266 incr = end - pa; 2267 goto do_dump_avail; 2268 } 2269 2270 page_bad = FALSE; 2271 2272 /* 2273 * Map the page non-cacheable for the memory 2274 * test. 2275 */ 2276 *pte = pa | 2277 kernel_pmap.pmap_bits[PG_V_IDX] | 2278 kernel_pmap.pmap_bits[PG_RW_IDX] | 2279 kernel_pmap.pmap_bits[PG_N_IDX]; 2280 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2281 cpu_mfence(); 2282 2283 /* 2284 * Save original value for restoration later. 2285 */ 2286 tmp = *ptr; 2287 2288 /* 2289 * Test for alternating 1's and 0's 2290 */ 2291 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2292 cpu_mfence(); 2293 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2294 page_bad = TRUE; 2295 /* 2296 * Test for alternating 0's and 1's 2297 */ 2298 *ptr = 0x5555555555555555LLU; 2299 cpu_mfence(); 2300 if (*ptr != 0x5555555555555555LLU) 2301 page_bad = TRUE; 2302 /* 2303 * Test for all 1's 2304 */ 2305 *ptr = 0xffffffffffffffffLLU; 2306 cpu_mfence(); 2307 if (*ptr != 0xffffffffffffffffLLU) 2308 page_bad = TRUE; 2309 /* 2310 * Test for all 0's 2311 */ 2312 *ptr = 0x0; 2313 cpu_mfence(); 2314 if (*ptr != 0x0) 2315 page_bad = TRUE; 2316 2317 /* 2318 * Restore original value. 2319 */ 2320 *ptr = tmp; 2321 2322 /* 2323 * Adjust array of valid/good pages. 2324 */ 2325 if (page_bad == TRUE) { 2326 incr = PAGE_SIZE; 2327 continue; 2328 } 2329 2330 /* 2331 * Collapse page address into phys_avail[]. Do a 2332 * continuation of the current phys_avail[] index 2333 * when possible. 2334 */ 2335 if (phys_avail[pa_indx].phys_end == pa) { 2336 /* 2337 * Continuation 2338 */ 2339 phys_avail[pa_indx].phys_end += incr; 2340 } else if (phys_avail[pa_indx].phys_beg == 2341 phys_avail[pa_indx].phys_end) { 2342 /* 2343 * Current phys_avail is completely empty, 2344 * reuse the index. 2345 */ 2346 phys_avail[pa_indx].phys_beg = pa; 2347 phys_avail[pa_indx].phys_end = pa + incr; 2348 } else { 2349 /* 2350 * Allocate next phys_avail index. 2351 */ 2352 ++pa_indx; 2353 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2354 kprintf( 2355 "Too many holes in the physical address space, giving up\n"); 2356 --pa_indx; 2357 full = TRUE; 2358 goto do_dump_avail; 2359 } 2360 phys_avail[pa_indx].phys_beg = pa; 2361 phys_avail[pa_indx].phys_end = pa + incr; 2362 } 2363 physmem += incr / PAGE_SIZE; 2364 2365 /* 2366 * pa available for dumping 2367 */ 2368 do_dump_avail: 2369 if (dump_avail[da_indx].phys_end == pa) { 2370 dump_avail[da_indx].phys_end += incr; 2371 } else { 2372 ++da_indx; 2373 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2374 --da_indx; 2375 goto do_next; 2376 } 2377 dump_avail[da_indx].phys_beg = pa; 2378 dump_avail[da_indx].phys_end = pa + incr; 2379 } 2380 do_next: 2381 if (full) 2382 break; 2383 } 2384 } 2385 *pte = 0; 2386 cpu_invltlb(); 2387 cpu_mfence(); 2388 2389 /* 2390 * The last chunk must contain at least one page plus the message 2391 * buffer to avoid complicating other code (message buffer address 2392 * calculation, etc.). 2393 */ 2394 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2395 2396 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2397 phys_avail[pa_indx].phys_end) { 2398 physmem -= atop(phys_avail[pa_indx].phys_end - 2399 phys_avail[pa_indx].phys_beg); 2400 phys_avail[pa_indx].phys_beg = 0; 2401 phys_avail[pa_indx].phys_end = 0; 2402 --pa_indx; 2403 } 2404 2405 Maxmem = atop(phys_avail[pa_indx].phys_end); 2406 2407 /* Trim off space for the message buffer. */ 2408 phys_avail[pa_indx].phys_end -= msgbuf_size; 2409 2410 avail_end = phys_avail[pa_indx].phys_end; 2411 2412 /* Map the message buffer. */ 2413 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2414 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2415 } 2416 2417 /* Try to get EFI framebuffer working as early as possible */ 2418 { 2419 /* 2420 * HACK: Setting machdep.hack_efifb_probe_early=1 works around 2421 * an issue that occurs on some recent systems where there is 2422 * no system console when booting via UEFI. Bug #3167. 2423 * 2424 * NOTE: This is not intended to be a permant fix. 2425 */ 2426 2427 int hack_efifb_probe_early = 0; 2428 TUNABLE_INT_FETCH("machdep.hack_efifb_probe_early", &hack_efifb_probe_early); 2429 2430 if (hack_efifb_probe_early) 2431 probe_efi_fb(1); 2432 else if (have_efi_framebuffer) 2433 efi_fb_init_vaddr(1); 2434 } 2435 } 2436 2437 struct machintr_abi MachIntrABI; 2438 2439 /* 2440 * IDT VECTORS: 2441 * 0 Divide by zero 2442 * 1 Debug 2443 * 2 NMI 2444 * 3 BreakPoint 2445 * 4 OverFlow 2446 * 5 Bound-Range 2447 * 6 Invalid OpCode 2448 * 7 Device Not Available (x87) 2449 * 8 Double-Fault 2450 * 9 Coprocessor Segment overrun (unsupported, reserved) 2451 * 10 Invalid-TSS 2452 * 11 Segment not present 2453 * 12 Stack 2454 * 13 General Protection 2455 * 14 Page Fault 2456 * 15 Reserved 2457 * 16 x87 FP Exception pending 2458 * 17 Alignment Check 2459 * 18 Machine Check 2460 * 19 SIMD floating point 2461 * 20-31 reserved 2462 * 32-255 INTn/external sources 2463 */ 2464 u_int64_t 2465 hammer_time(u_int64_t modulep, u_int64_t physfree) 2466 { 2467 caddr_t kmdp; 2468 int gsel_tss, x, cpu; 2469 #if 0 /* JG */ 2470 int metadata_missing, off; 2471 #endif 2472 struct mdglobaldata *gd; 2473 struct privatespace *ps; 2474 u_int64_t msr; 2475 2476 /* 2477 * Prevent lowering of the ipl if we call tsleep() early. 2478 */ 2479 gd = &CPU_prvspace[0]->mdglobaldata; 2480 ps = (struct privatespace *)gd; 2481 bzero(gd, sizeof(*gd)); 2482 bzero(&ps->common_tss, sizeof(ps->common_tss)); 2483 2484 /* 2485 * Note: on both UP and SMP curthread must be set non-NULL 2486 * early in the boot sequence because the system assumes 2487 * that 'curthread' is never NULL. 2488 */ 2489 2490 gd->mi.gd_curthread = &thread0; 2491 thread0.td_gd = &gd->mi; 2492 2493 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2494 2495 #if 0 /* JG */ 2496 metadata_missing = 0; 2497 if (bootinfo.bi_modulep) { 2498 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2499 preload_bootstrap_relocate(KERNBASE); 2500 } else { 2501 metadata_missing = 1; 2502 } 2503 if (bootinfo.bi_envp) 2504 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2505 #endif 2506 2507 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2508 preload_bootstrap_relocate(PTOV_OFFSET); 2509 kmdp = preload_search_by_type("elf kernel"); 2510 if (kmdp == NULL) 2511 kmdp = preload_search_by_type("elf64 kernel"); 2512 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2513 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2514 #ifdef DDB 2515 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2516 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2517 #endif 2518 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2519 2520 if (boothowto & RB_VERBOSE) 2521 bootverbose++; 2522 2523 /* 2524 * Default MachIntrABI to ICU 2525 */ 2526 MachIntrABI = MachIntrABI_ICU; 2527 2528 /* 2529 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2530 */ 2531 ncpus = 1; 2532 ncpus_fit = 1; 2533 /* Init basic tunables, hz etc */ 2534 init_param1(); 2535 2536 /* 2537 * make gdt memory segments 2538 */ 2539 gdt_segs[GPROC0_SEL].ssd_base = 2540 (uintptr_t) &CPU_prvspace[0]->common_tss; 2541 2542 gd->mi.gd_prvspace = CPU_prvspace[0]; 2543 2544 for (x = 0; x < NGDT; x++) { 2545 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2546 ssdtosd(&gdt_segs[x], &gdt[x]); 2547 } 2548 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2549 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2550 2551 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2552 r_gdt.rd_base = (long) gdt; 2553 lgdt(&r_gdt); 2554 2555 wrmsr(MSR_FSBASE, 0); /* User value */ 2556 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2557 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2558 2559 mi_gdinit(&gd->mi, 0); 2560 cpu_gdinit(gd, 0); 2561 proc0paddr = proc0paddr_buff; 2562 mi_proc0init(&gd->mi, proc0paddr); 2563 safepri = TDPRI_MAX; 2564 2565 /* spinlocks and the BGL */ 2566 init_locks(); 2567 2568 /* exceptions */ 2569 for (x = 0; x < NIDT; x++) 2570 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2571 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2572 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 2); 2573 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2574 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2575 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2576 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2577 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2578 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2579 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2580 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2581 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2582 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2583 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2584 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2585 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2586 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2587 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2588 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2589 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2590 2591 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2592 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2593 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2594 } 2595 2596 lidt(&r_idt_arr[0]); 2597 2598 /* 2599 * Initialize the console before we print anything out. 2600 */ 2601 cninit(); 2602 2603 #if 0 /* JG */ 2604 if (metadata_missing) 2605 kprintf("WARNING: loader(8) metadata is missing!\n"); 2606 #endif 2607 2608 #if NISA >0 2609 elcr_probe(); 2610 isa_defaultirq(); 2611 #endif 2612 rand_initialize(); 2613 2614 /* 2615 * Initialize IRQ mapping 2616 * 2617 * NOTE: 2618 * SHOULD be after elcr_probe() 2619 */ 2620 MachIntrABI_ICU.initmap(); 2621 MachIntrABI_IOAPIC.initmap(); 2622 2623 #ifdef DDB 2624 kdb_init(); 2625 if (boothowto & RB_KDB) 2626 Debugger("Boot flags requested debugger"); 2627 #endif 2628 2629 identify_cpu(); /* Final stage of CPU initialization */ 2630 initializecpu(0); /* Initialize CPU registers */ 2631 2632 /* 2633 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2634 * because the cpu does significant power management in MWAIT 2635 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2636 * 2637 * On many AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2638 * significant power management only when using ACPI halt mode. 2639 * (However, on Ryzen, mode 4 (HLT) also does power management). 2640 * 2641 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2642 * is needed to reduce power consumption, but wakeup times are often 2643 * too long. 2644 */ 2645 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2646 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2647 cpu_idle_hlt = 1; 2648 } 2649 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2650 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2651 /* Ryzen or later */ 2652 cpu_idle_hlt = 3; 2653 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2654 /* Bobcat or later */ 2655 cpu_idle_hlt = 3; 2656 } 2657 } 2658 2659 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2660 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2661 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2662 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2663 2664 /* 2665 * Some of the virtual machines do not work w/ I/O APIC 2666 * enabled. If the user does not explicitly enable or 2667 * disable the I/O APIC (ioapic_enable < 0), then we 2668 * disable I/O APIC on all virtual machines. 2669 * 2670 * NOTE: 2671 * This must be done after identify_cpu(), which sets 2672 * 'cpu_feature2' 2673 */ 2674 if (ioapic_enable < 0) { 2675 if (cpu_feature2 & CPUID2_VMM) 2676 ioapic_enable = 0; 2677 else 2678 ioapic_enable = 1; 2679 } 2680 2681 /* 2682 * TSS entry point for interrupts, traps, and exceptions 2683 * (sans NMI). This will always go to near the top of the pcpu 2684 * trampoline area. Hardware-pushed data will be copied into 2685 * the trap-frame on entry, and (if necessary) returned to the 2686 * trampoline on exit. 2687 * 2688 * We store some pcb data for the trampoline code above the 2689 * stack the cpu hw pushes into, and arrange things so the 2690 * address of tr_pcb_rsp is the same as the desired top of 2691 * stack. 2692 */ 2693 ps->common_tss.tss_rsp0 = (register_t)&ps->trampoline.tr_pcb_rsp; 2694 ps->trampoline.tr_pcb_rsp = ps->common_tss.tss_rsp0; 2695 ps->trampoline.tr_pcb_gs_kernel = (register_t)gd; 2696 ps->trampoline.tr_pcb_cr3 = KPML4phys; /* adj to user cr3 live */ 2697 ps->dbltramp.tr_pcb_gs_kernel = (register_t)gd; 2698 ps->dbltramp.tr_pcb_cr3 = KPML4phys; 2699 ps->dbgtramp.tr_pcb_gs_kernel = (register_t)gd; 2700 ps->dbgtramp.tr_pcb_cr3 = KPML4phys; 2701 2702 /* double fault stack */ 2703 ps->common_tss.tss_ist1 = (register_t)&ps->dbltramp.tr_pcb_rsp; 2704 /* #DB debugger needs its own stack */ 2705 ps->common_tss.tss_ist2 = (register_t)&ps->dbgtramp.tr_pcb_rsp; 2706 2707 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2708 ps->common_tss.tss_iobase = sizeof(struct x86_64tss); 2709 2710 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2711 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2712 gd->gd_common_tssd = *gd->gd_tss_gdt; 2713 ltr(gsel_tss); 2714 2715 /* Set up the fast syscall stuff */ 2716 msr = rdmsr(MSR_EFER) | EFER_SCE; 2717 wrmsr(MSR_EFER, msr); 2718 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2719 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2720 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2721 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2722 wrmsr(MSR_STAR, msr); 2723 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2724 2725 getmemsize(kmdp, physfree); 2726 init_param2(physmem); 2727 2728 /* now running on new page tables, configured,and u/iom is accessible */ 2729 2730 /* Map the message buffer. */ 2731 #if 0 /* JG */ 2732 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2733 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2734 #endif 2735 2736 msgbufinit(msgbufp, MSGBUF_SIZE); 2737 2738 2739 /* transfer to user mode */ 2740 2741 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2742 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2743 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2744 2745 load_ds(_udatasel); 2746 load_es(_udatasel); 2747 load_fs(_udatasel); 2748 2749 /* setup proc 0's pcb */ 2750 thread0.td_pcb->pcb_flags = 0; 2751 thread0.td_pcb->pcb_cr3 = KPML4phys; 2752 thread0.td_pcb->pcb_cr3_iso = 0; 2753 thread0.td_pcb->pcb_ext = NULL; 2754 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2755 2756 /* Location of kernel stack for locore */ 2757 return ((u_int64_t)thread0.td_pcb); 2758 } 2759 2760 /* 2761 * Initialize machine-dependant portions of the global data structure. 2762 * Note that the global data area and cpu0's idlestack in the private 2763 * data space were allocated in locore. 2764 * 2765 * Note: the idlethread's cpl is 0 2766 * 2767 * WARNING! Called from early boot, 'mycpu' may not work yet. 2768 */ 2769 void 2770 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2771 { 2772 if (cpu) 2773 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2774 2775 lwkt_init_thread(&gd->mi.gd_idlethread, 2776 gd->mi.gd_prvspace->idlestack, 2777 sizeof(gd->mi.gd_prvspace->idlestack), 2778 0, &gd->mi); 2779 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2780 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2781 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2782 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2783 } 2784 2785 /* 2786 * We only have to check for DMAP bounds, the globaldata space is 2787 * actually part of the kernel_map so we don't have to waste time 2788 * checking CPU_prvspace[*]. 2789 */ 2790 int 2791 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2792 { 2793 #if 0 2794 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2795 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2796 return (TRUE); 2797 } 2798 #endif 2799 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2800 return (TRUE); 2801 return (FALSE); 2802 } 2803 2804 struct globaldata * 2805 globaldata_find(int cpu) 2806 { 2807 KKASSERT(cpu >= 0 && cpu < ncpus); 2808 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2809 } 2810 2811 /* 2812 * This path should be safe from the SYSRET issue because only stopped threads 2813 * can have their %rip adjusted this way (and all heavy weight thread switches 2814 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2815 * convoluted so add a safety by forcing %rip to be cannonical. 2816 */ 2817 int 2818 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2819 { 2820 if (addr & 0x0000800000000000LLU) 2821 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2822 else 2823 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2824 return (0); 2825 } 2826 2827 int 2828 ptrace_single_step(struct lwp *lp) 2829 { 2830 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2831 return (0); 2832 } 2833 2834 int 2835 fill_regs(struct lwp *lp, struct reg *regs) 2836 { 2837 struct trapframe *tp; 2838 2839 if ((tp = lp->lwp_md.md_regs) == NULL) 2840 return EINVAL; 2841 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2842 return (0); 2843 } 2844 2845 int 2846 set_regs(struct lwp *lp, struct reg *regs) 2847 { 2848 struct trapframe *tp; 2849 2850 tp = lp->lwp_md.md_regs; 2851 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2852 !CS_SECURE(regs->r_cs)) 2853 return (EINVAL); 2854 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2855 clear_quickret(); 2856 return (0); 2857 } 2858 2859 static void 2860 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2861 { 2862 struct env87 *penv_87 = &sv_87->sv_env; 2863 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2864 int i; 2865 2866 /* FPU control/status */ 2867 penv_87->en_cw = penv_xmm->en_cw; 2868 penv_87->en_sw = penv_xmm->en_sw; 2869 penv_87->en_tw = penv_xmm->en_tw; 2870 penv_87->en_fip = penv_xmm->en_fip; 2871 penv_87->en_fcs = penv_xmm->en_fcs; 2872 penv_87->en_opcode = penv_xmm->en_opcode; 2873 penv_87->en_foo = penv_xmm->en_foo; 2874 penv_87->en_fos = penv_xmm->en_fos; 2875 2876 /* FPU registers */ 2877 for (i = 0; i < 8; ++i) 2878 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2879 } 2880 2881 static void 2882 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2883 { 2884 struct env87 *penv_87 = &sv_87->sv_env; 2885 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2886 int i; 2887 2888 /* FPU control/status */ 2889 penv_xmm->en_cw = penv_87->en_cw; 2890 penv_xmm->en_sw = penv_87->en_sw; 2891 penv_xmm->en_tw = penv_87->en_tw; 2892 penv_xmm->en_fip = penv_87->en_fip; 2893 penv_xmm->en_fcs = penv_87->en_fcs; 2894 penv_xmm->en_opcode = penv_87->en_opcode; 2895 penv_xmm->en_foo = penv_87->en_foo; 2896 penv_xmm->en_fos = penv_87->en_fos; 2897 2898 /* FPU registers */ 2899 for (i = 0; i < 8; ++i) 2900 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2901 } 2902 2903 int 2904 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2905 { 2906 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2907 return EINVAL; 2908 if (cpu_fxsr) { 2909 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2910 (struct save87 *)fpregs); 2911 return (0); 2912 } 2913 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2914 return (0); 2915 } 2916 2917 int 2918 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2919 { 2920 if (cpu_fxsr) { 2921 set_fpregs_xmm((struct save87 *)fpregs, 2922 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2923 return (0); 2924 } 2925 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2926 return (0); 2927 } 2928 2929 int 2930 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2931 { 2932 struct pcb *pcb; 2933 2934 if (lp == NULL) { 2935 dbregs->dr[0] = rdr0(); 2936 dbregs->dr[1] = rdr1(); 2937 dbregs->dr[2] = rdr2(); 2938 dbregs->dr[3] = rdr3(); 2939 dbregs->dr[4] = rdr4(); 2940 dbregs->dr[5] = rdr5(); 2941 dbregs->dr[6] = rdr6(); 2942 dbregs->dr[7] = rdr7(); 2943 return (0); 2944 } 2945 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2946 return EINVAL; 2947 dbregs->dr[0] = pcb->pcb_dr0; 2948 dbregs->dr[1] = pcb->pcb_dr1; 2949 dbregs->dr[2] = pcb->pcb_dr2; 2950 dbregs->dr[3] = pcb->pcb_dr3; 2951 dbregs->dr[4] = 0; 2952 dbregs->dr[5] = 0; 2953 dbregs->dr[6] = pcb->pcb_dr6; 2954 dbregs->dr[7] = pcb->pcb_dr7; 2955 return (0); 2956 } 2957 2958 int 2959 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2960 { 2961 if (lp == NULL) { 2962 load_dr0(dbregs->dr[0]); 2963 load_dr1(dbregs->dr[1]); 2964 load_dr2(dbregs->dr[2]); 2965 load_dr3(dbregs->dr[3]); 2966 load_dr4(dbregs->dr[4]); 2967 load_dr5(dbregs->dr[5]); 2968 load_dr6(dbregs->dr[6]); 2969 load_dr7(dbregs->dr[7]); 2970 } else { 2971 struct pcb *pcb; 2972 struct ucred *ucred; 2973 int i; 2974 uint64_t mask1, mask2; 2975 2976 /* 2977 * Don't let an illegal value for dr7 get set. Specifically, 2978 * check for undefined settings. Setting these bit patterns 2979 * result in undefined behaviour and can lead to an unexpected 2980 * TRCTRAP. 2981 */ 2982 /* JG this loop looks unreadable */ 2983 /* Check 4 2-bit fields for invalid patterns. 2984 * These fields are R/Wi, for i = 0..3 2985 */ 2986 /* Is 10 in LENi allowed when running in compatibility mode? */ 2987 /* Pattern 10 in R/Wi might be used to indicate 2988 * breakpoint on I/O. Further analysis should be 2989 * carried to decide if it is safe and useful to 2990 * provide access to that capability 2991 */ 2992 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2993 i++, mask1 <<= 4, mask2 <<= 4) 2994 if ((dbregs->dr[7] & mask1) == mask2) 2995 return (EINVAL); 2996 2997 pcb = lp->lwp_thread->td_pcb; 2998 ucred = lp->lwp_proc->p_ucred; 2999 3000 /* 3001 * Don't let a process set a breakpoint that is not within the 3002 * process's address space. If a process could do this, it 3003 * could halt the system by setting a breakpoint in the kernel 3004 * (if ddb was enabled). Thus, we need to check to make sure 3005 * that no breakpoints are being enabled for addresses outside 3006 * process's address space, unless, perhaps, we were called by 3007 * uid 0. 3008 * 3009 * XXX - what about when the watched area of the user's 3010 * address space is written into from within the kernel 3011 * ... wouldn't that still cause a breakpoint to be generated 3012 * from within kernel mode? 3013 */ 3014 3015 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 3016 if (dbregs->dr[7] & 0x3) { 3017 /* dr0 is enabled */ 3018 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 3019 return (EINVAL); 3020 } 3021 3022 if (dbregs->dr[7] & (0x3<<2)) { 3023 /* dr1 is enabled */ 3024 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 3025 return (EINVAL); 3026 } 3027 3028 if (dbregs->dr[7] & (0x3<<4)) { 3029 /* dr2 is enabled */ 3030 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 3031 return (EINVAL); 3032 } 3033 3034 if (dbregs->dr[7] & (0x3<<6)) { 3035 /* dr3 is enabled */ 3036 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 3037 return (EINVAL); 3038 } 3039 } 3040 3041 pcb->pcb_dr0 = dbregs->dr[0]; 3042 pcb->pcb_dr1 = dbregs->dr[1]; 3043 pcb->pcb_dr2 = dbregs->dr[2]; 3044 pcb->pcb_dr3 = dbregs->dr[3]; 3045 pcb->pcb_dr6 = dbregs->dr[6]; 3046 pcb->pcb_dr7 = dbregs->dr[7]; 3047 3048 pcb->pcb_flags |= PCB_DBREGS; 3049 } 3050 3051 return (0); 3052 } 3053 3054 /* 3055 * Return > 0 if a hardware breakpoint has been hit, and the 3056 * breakpoint was in user space. Return 0, otherwise. 3057 */ 3058 int 3059 user_dbreg_trap(void) 3060 { 3061 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 3062 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 3063 int nbp; /* number of breakpoints that triggered */ 3064 caddr_t addr[4]; /* breakpoint addresses */ 3065 int i; 3066 3067 dr7 = rdr7(); 3068 if ((dr7 & 0xff) == 0) { 3069 /* 3070 * all GE and LE bits in the dr7 register are zero, 3071 * thus the trap couldn't have been caused by the 3072 * hardware debug registers 3073 */ 3074 return 0; 3075 } 3076 3077 nbp = 0; 3078 dr6 = rdr6(); 3079 bp = dr6 & 0xf; 3080 3081 if (bp == 0) { 3082 /* 3083 * None of the breakpoint bits are set meaning this 3084 * trap was not caused by any of the debug registers 3085 */ 3086 return 0; 3087 } 3088 3089 /* 3090 * at least one of the breakpoints were hit, check to see 3091 * which ones and if any of them are user space addresses 3092 */ 3093 3094 if (bp & 0x01) { 3095 addr[nbp++] = (caddr_t)rdr0(); 3096 } 3097 if (bp & 0x02) { 3098 addr[nbp++] = (caddr_t)rdr1(); 3099 } 3100 if (bp & 0x04) { 3101 addr[nbp++] = (caddr_t)rdr2(); 3102 } 3103 if (bp & 0x08) { 3104 addr[nbp++] = (caddr_t)rdr3(); 3105 } 3106 3107 for (i = 0; i < nbp; i++) { 3108 if (addr[i] < (caddr_t)VM_MAX_USER_ADDRESS) { 3109 /* 3110 * addr[i] is in user space 3111 */ 3112 return nbp; 3113 } 3114 } 3115 3116 /* 3117 * None of the breakpoints are in user space. 3118 */ 3119 return 0; 3120 } 3121 3122 3123 #ifndef DDB 3124 void 3125 Debugger(const char *msg) 3126 { 3127 kprintf("Debugger(\"%s\") called.\n", msg); 3128 } 3129 #endif /* no DDB */ 3130 3131 #ifdef DDB 3132 3133 /* 3134 * Provide inb() and outb() as functions. They are normally only 3135 * available as macros calling inlined functions, thus cannot be 3136 * called inside DDB. 3137 * 3138 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 3139 */ 3140 3141 #undef inb 3142 #undef outb 3143 3144 /* silence compiler warnings */ 3145 u_char inb(u_int); 3146 void outb(u_int, u_char); 3147 3148 u_char 3149 inb(u_int port) 3150 { 3151 u_char data; 3152 /* 3153 * We use %%dx and not %1 here because i/o is done at %dx and not at 3154 * %edx, while gcc generates inferior code (movw instead of movl) 3155 * if we tell it to load (u_short) port. 3156 */ 3157 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 3158 return (data); 3159 } 3160 3161 void 3162 outb(u_int port, u_char data) 3163 { 3164 u_char al; 3165 /* 3166 * Use an unnecessary assignment to help gcc's register allocator. 3167 * This make a large difference for gcc-1.40 and a tiny difference 3168 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 3169 * best results. gcc-2.6.0 can't handle this. 3170 */ 3171 al = data; 3172 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 3173 } 3174 3175 #endif /* DDB */ 3176 3177 3178 3179 /* 3180 * initialize all the SMP locks 3181 */ 3182 3183 /* critical region when masking or unmasking interupts */ 3184 struct spinlock_deprecated imen_spinlock; 3185 3186 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 3187 struct spinlock_deprecated com_spinlock; 3188 3189 /* lock regions around the clock hardware */ 3190 struct spinlock_deprecated clock_spinlock; 3191 3192 static void 3193 init_locks(void) 3194 { 3195 /* 3196 * Get the initial mplock with a count of 1 for the BSP. 3197 * This uses a LOGICAL cpu ID, ie BSP == 0. 3198 */ 3199 cpu_get_initial_mplock(); 3200 /* DEPRECATED */ 3201 spin_init_deprecated(&imen_spinlock); 3202 spin_init_deprecated(&com_spinlock); 3203 spin_init_deprecated(&clock_spinlock); 3204 3205 /* our token pool needs to work early */ 3206 lwkt_token_pool_init(); 3207 } 3208 3209 boolean_t 3210 cpu_mwait_hint_valid(uint32_t hint) 3211 { 3212 int cx_idx, sub; 3213 3214 cx_idx = MWAIT_EAX_TO_CX(hint); 3215 if (cx_idx >= CPU_MWAIT_CX_MAX) 3216 return FALSE; 3217 3218 sub = MWAIT_EAX_TO_CX_SUB(hint); 3219 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3220 return FALSE; 3221 3222 return TRUE; 3223 } 3224 3225 void 3226 cpu_mwait_cx_no_bmsts(void) 3227 { 3228 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3229 } 3230 3231 void 3232 cpu_mwait_cx_no_bmarb(void) 3233 { 3234 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3235 } 3236 3237 static int 3238 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3239 { 3240 int old_cx_idx, sub = 0; 3241 3242 if (hint >= 0) { 3243 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3244 sub = MWAIT_EAX_TO_CX_SUB(hint); 3245 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3246 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3247 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3248 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3249 } else { 3250 old_cx_idx = CPU_MWAIT_CX_MAX; 3251 } 3252 3253 if (!CPU_MWAIT_HAS_CX) 3254 strlcpy(name, "NONE", namelen); 3255 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3256 strlcpy(name, "AUTO", namelen); 3257 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3258 strlcpy(name, "AUTODEEP", namelen); 3259 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3260 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3261 strlcpy(name, "INVALID", namelen); 3262 else 3263 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3264 3265 return old_cx_idx; 3266 } 3267 3268 static int 3269 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3270 { 3271 int cx_idx, sub, hint; 3272 char *ptr, *start; 3273 3274 if (allow_auto && strcmp(name, "AUTO") == 0) { 3275 hint = CPU_MWAIT_HINT_AUTO; 3276 cx_idx = CPU_MWAIT_C2; 3277 goto done; 3278 } 3279 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3280 hint = CPU_MWAIT_HINT_AUTODEEP; 3281 cx_idx = CPU_MWAIT_C3; 3282 goto done; 3283 } 3284 3285 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3286 return -1; 3287 start = &name[1]; 3288 ptr = NULL; 3289 3290 cx_idx = strtol(start, &ptr, 10); 3291 if (ptr == start || *ptr != '/') 3292 return -1; 3293 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3294 return -1; 3295 3296 start = ptr + 1; 3297 ptr = NULL; 3298 3299 sub = strtol(start, &ptr, 10); 3300 if (*ptr != '\0') 3301 return -1; 3302 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3303 return -1; 3304 3305 hint = MWAIT_EAX_HINT(cx_idx, sub); 3306 done: 3307 *hint0 = hint; 3308 return cx_idx; 3309 } 3310 3311 static int 3312 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3313 { 3314 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3315 return EOPNOTSUPP; 3316 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3317 int error; 3318 3319 error = cputimer_intr_powersave_addreq(); 3320 if (error) 3321 return error; 3322 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3323 cputimer_intr_powersave_remreq(); 3324 } 3325 return 0; 3326 } 3327 3328 static int 3329 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3330 boolean_t allow_auto) 3331 { 3332 int error, cx_idx, old_cx_idx, hint; 3333 char name[CPU_MWAIT_CX_NAMELEN]; 3334 3335 hint = *hint0; 3336 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3337 allow_auto); 3338 3339 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3340 if (error != 0 || req->newptr == NULL) 3341 return error; 3342 3343 if (!CPU_MWAIT_HAS_CX) 3344 return EOPNOTSUPP; 3345 3346 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3347 if (cx_idx < 0) 3348 return EINVAL; 3349 3350 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3351 if (error) 3352 return error; 3353 3354 *hint0 = hint; 3355 return 0; 3356 } 3357 3358 static int 3359 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3360 { 3361 int error, cx_idx, old_cx_idx, hint; 3362 char name[CPU_MWAIT_CX_NAMELEN]; 3363 3364 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3365 3366 hint = stat->hint; 3367 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3368 3369 strlcpy(name, cx_name, sizeof(name)); 3370 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3371 if (cx_idx < 0) 3372 return EINVAL; 3373 3374 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3375 if (error) 3376 return error; 3377 3378 stat->hint = hint; 3379 return 0; 3380 } 3381 3382 static int 3383 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3384 { 3385 int hint = cpu_mwait_halt_global; 3386 int error, cx_idx, cpu; 3387 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3388 3389 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3390 3391 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3392 if (error != 0 || req->newptr == NULL) 3393 return error; 3394 3395 if (!CPU_MWAIT_HAS_CX) 3396 return EOPNOTSUPP; 3397 3398 /* Save name for later per-cpu CX configuration */ 3399 strlcpy(cx_name, name, sizeof(cx_name)); 3400 3401 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3402 if (cx_idx < 0) 3403 return EINVAL; 3404 3405 /* Change per-cpu CX configuration */ 3406 for (cpu = 0; cpu < ncpus; ++cpu) { 3407 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3408 if (error) 3409 return error; 3410 } 3411 3412 cpu_mwait_halt_global = hint; 3413 return 0; 3414 } 3415 3416 static int 3417 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3418 { 3419 struct cpu_idle_stat *stat = arg1; 3420 int error; 3421 3422 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3423 &stat->hint, TRUE); 3424 return error; 3425 } 3426 3427 static int 3428 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3429 { 3430 int error; 3431 3432 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3433 &cpu_mwait_spin, FALSE); 3434 return error; 3435 } 3436 3437 /* 3438 * This manual debugging code is called unconditionally from Xtimer 3439 * (the per-cpu timer interrupt) whether the current thread is in a 3440 * critical section or not) and can be useful in tracking down lockups. 3441 * 3442 * NOTE: MANUAL DEBUG CODE 3443 */ 3444 #if 0 3445 static int saveticks[SMP_MAXCPU]; 3446 static int savecounts[SMP_MAXCPU]; 3447 #endif 3448 3449 void 3450 pcpu_timer_always(struct intrframe *frame) 3451 { 3452 #if 0 3453 globaldata_t gd = mycpu; 3454 int cpu = gd->gd_cpuid; 3455 char buf[64]; 3456 short *gptr; 3457 int i; 3458 3459 if (cpu <= 20) { 3460 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3461 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3462 ++gptr; 3463 3464 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3465 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3466 gd->gd_infomsg); 3467 for (i = 0; buf[i]; ++i) { 3468 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3469 } 3470 } 3471 #if 0 3472 if (saveticks[gd->gd_cpuid] != ticks) { 3473 saveticks[gd->gd_cpuid] = ticks; 3474 savecounts[gd->gd_cpuid] = 0; 3475 } 3476 ++savecounts[gd->gd_cpuid]; 3477 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3478 panic("cpud %d panicing on ticks failure", 3479 gd->gd_cpuid); 3480 } 3481 for (i = 0; i < ncpus; ++i) { 3482 int delta; 3483 if (saveticks[i] && panicstr == NULL) { 3484 delta = saveticks[i] - ticks; 3485 if (delta < -10 || delta > 10) { 3486 panic("cpu %d panicing on cpu %d watchdog", 3487 gd->gd_cpuid, i); 3488 } 3489 } 3490 } 3491 #endif 3492 #endif 3493 } 3494