1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $ 26 */ 27 28 #include "opt_cpu.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/sysctl.h> 34 #include <sys/malloc.h> 35 #include <sys/memrange.h> 36 #include <sys/cons.h> /* cngetc() */ 37 #include <sys/machintr.h> 38 39 #include <sys/mplock2.h> 40 41 #include <vm/vm.h> 42 #include <vm/vm_param.h> 43 #include <vm/pmap.h> 44 #include <vm/vm_kern.h> 45 #include <vm/vm_extern.h> 46 #include <sys/lock.h> 47 #include <vm/vm_map.h> 48 #include <sys/user.h> 49 #ifdef GPROF 50 #include <sys/gmon.h> 51 #endif 52 53 #include <machine/smp.h> 54 #include <machine_base/apic/apicreg.h> 55 #include <machine/atomic.h> 56 #include <machine/cpufunc.h> 57 #include <machine/cputypes.h> 58 #include <machine_base/apic/lapic.h> 59 #include <machine_base/apic/ioapic.h> 60 #include <machine/psl.h> 61 #include <machine/segments.h> 62 #include <machine/tss.h> 63 #include <machine/specialreg.h> 64 #include <machine/globaldata.h> 65 #include <machine/pmap_inval.h> 66 67 #include <machine/md_var.h> /* setidt() */ 68 #include <machine_base/icu/icu.h> /* IPIs */ 69 #include <machine_base/icu/icu_var.h> 70 #include <machine_base/apic/ioapic_abi.h> 71 #include <machine/intr_machdep.h> /* IPIs */ 72 73 #define WARMBOOT_TARGET 0 74 #define WARMBOOT_OFF (KERNBASE + 0x0467) 75 #define WARMBOOT_SEG (KERNBASE + 0x0469) 76 77 #define CMOS_REG (0x70) 78 #define CMOS_DATA (0x71) 79 #define BIOS_RESET (0x0f) 80 #define BIOS_WARM (0x0a) 81 82 /* 83 * this code MUST be enabled here and in mpboot.s. 84 * it follows the very early stages of AP boot by placing values in CMOS ram. 85 * it NORMALLY will never be needed and thus the primitive method for enabling. 86 * 87 */ 88 #if defined(CHECK_POINTS) 89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 91 92 #define CHECK_INIT(D); \ 93 CHECK_WRITE(0x34, (D)); \ 94 CHECK_WRITE(0x35, (D)); \ 95 CHECK_WRITE(0x36, (D)); \ 96 CHECK_WRITE(0x37, (D)); \ 97 CHECK_WRITE(0x38, (D)); \ 98 CHECK_WRITE(0x39, (D)); 99 100 #define CHECK_PRINT(S); \ 101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \ 102 (S), \ 103 CHECK_READ(0x34), \ 104 CHECK_READ(0x35), \ 105 CHECK_READ(0x36), \ 106 CHECK_READ(0x37), \ 107 CHECK_READ(0x38), \ 108 CHECK_READ(0x39)); 109 110 #else /* CHECK_POINTS */ 111 112 #define CHECK_INIT(D) 113 #define CHECK_PRINT(S) 114 115 #endif /* CHECK_POINTS */ 116 117 /* 118 * Values to send to the POST hardware. 119 */ 120 #define MP_BOOTADDRESS_POST 0x10 121 #define MP_PROBE_POST 0x11 122 #define MPTABLE_PASS1_POST 0x12 123 124 #define MP_START_POST 0x13 125 #define MP_ENABLE_POST 0x14 126 #define MPTABLE_PASS2_POST 0x15 127 128 #define START_ALL_APS_POST 0x16 129 #define INSTALL_AP_TRAMP_POST 0x17 130 #define START_AP_POST 0x18 131 132 #define MP_ANNOUNCE_POST 0x19 133 134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 135 int current_postcode; 136 137 /** XXX FIXME: what system files declare these??? */ 138 extern struct region_descriptor r_gdt; 139 140 extern int nkpt; 141 extern int naps; 142 143 int64_t tsc0_offset; 144 extern int64_t tsc_offsets[]; 145 146 /* AP uses this during bootstrap. Do not staticize. */ 147 char *bootSTK; 148 static int bootAP; 149 150 struct pcb stoppcbs[MAXCPU]; 151 152 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 153 154 /* 155 * Local data and functions. 156 */ 157 158 static u_int boot_address; 159 static int mp_finish; 160 static int mp_finish_lapic; 161 162 static int start_all_aps(u_int boot_addr); 163 #if 0 164 static void install_ap_tramp(u_int boot_addr); 165 #endif 166 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest); 167 static int smitest(void); 168 static void mp_bsp_simple_setup(void); 169 170 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */ 171 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */ 172 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */ 173 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, ""); 174 static u_int bootMP_size; 175 176 /* Local data for detecting CPU TOPOLOGY */ 177 static int core_bits = 0; 178 static int logical_CPU_bits = 0; 179 180 181 /* 182 * Calculate usable address in base memory for AP trampoline code. 183 */ 184 u_int 185 mp_bootaddress(u_int basemem) 186 { 187 POSTCODE(MP_BOOTADDRESS_POST); 188 189 bootMP_size = mptramp_end - mptramp_start; 190 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 191 if (((basemem * 1024) - boot_address) < bootMP_size) 192 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 193 /* 3 levels of page table pages */ 194 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 195 196 return mptramp_pagetables; 197 } 198 199 /* 200 * Print various information about the SMP system hardware and setup. 201 */ 202 void 203 mp_announce(void) 204 { 205 int x; 206 207 POSTCODE(MP_ANNOUNCE_POST); 208 209 kprintf("DragonFly/MP: Multiprocessor motherboard\n"); 210 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0)); 211 for (x = 1; x <= naps; ++x) 212 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x)); 213 214 if (!ioapic_enable) 215 kprintf(" Warning: APIC I/O disabled\n"); 216 } 217 218 /* 219 * AP cpu's call this to sync up protected mode. 220 * 221 * WARNING! %gs is not set up on entry. This routine sets up %gs. 222 */ 223 void 224 init_secondary(void) 225 { 226 int gsel_tss; 227 int x, myid = bootAP; 228 u_int64_t msr, cr0; 229 struct mdglobaldata *md; 230 struct privatespace *ps; 231 232 ps = &CPU_prvspace[myid]; 233 234 gdt_segs[GPROC0_SEL].ssd_base = 235 (long) &ps->mdglobaldata.gd_common_tss; 236 ps->mdglobaldata.mi.gd_prvspace = ps; 237 238 /* We fill the 32-bit segment descriptors */ 239 for (x = 0; x < NGDT; x++) { 240 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 241 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]); 242 } 243 /* And now a 64-bit one */ 244 ssdtosyssd(&gdt_segs[GPROC0_SEL], 245 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]); 246 247 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 248 r_gdt.rd_base = (long) &gdt[myid * NGDT]; 249 lgdt(&r_gdt); /* does magic intra-segment return */ 250 251 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */ 252 wrmsr(MSR_FSBASE, 0); /* User value */ 253 wrmsr(MSR_GSBASE, (u_int64_t)ps); 254 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */ 255 256 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]); 257 258 #if 0 259 lldt(_default_ldt); 260 mdcpu->gd_currentldt = _default_ldt; 261 #endif 262 263 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 264 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS; 265 266 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/ 267 268 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */ 269 #if 0 /* JG XXX */ 270 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16; 271 #endif 272 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL]; 273 md->gd_common_tssd = *md->gd_tss_gdt; 274 275 /* double fault stack */ 276 md->gd_common_tss.tss_ist1 = 277 (long)&md->mi.gd_prvspace->idlestack[ 278 sizeof(md->mi.gd_prvspace->idlestack)]; 279 280 ltr(gsel_tss); 281 282 /* 283 * Set to a known state: 284 * Set by mpboot.s: CR0_PG, CR0_PE 285 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 286 */ 287 cr0 = rcr0(); 288 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 289 load_cr0(cr0); 290 291 /* Set up the fast syscall stuff */ 292 msr = rdmsr(MSR_EFER) | EFER_SCE; 293 wrmsr(MSR_EFER, msr); 294 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 295 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 296 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 297 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 298 wrmsr(MSR_STAR, msr); 299 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 300 301 pmap_set_opt(); /* PSE/4MB pages, etc */ 302 #if JGXXX 303 /* Initialize the PAT MSR. */ 304 pmap_init_pat(); 305 #endif 306 307 /* set up CPU registers and state */ 308 cpu_setregs(); 309 310 /* set up SSE/NX registers */ 311 initializecpu(); 312 313 /* set up FPU state on the AP */ 314 npxinit(__INITIAL_FPUCW__); 315 316 /* disable the APIC, just to be SURE */ 317 lapic->svr &= ~APIC_SVR_ENABLE; 318 } 319 320 /******************************************************************* 321 * local functions and data 322 */ 323 324 /* 325 * Start the SMP system 326 */ 327 static void 328 mp_start_aps(void *dummy __unused) 329 { 330 if (lapic_enable) { 331 /* start each Application Processor */ 332 start_all_aps(boot_address); 333 } else { 334 mp_bsp_simple_setup(); 335 } 336 } 337 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL) 338 339 /* 340 * start each AP in our list 341 */ 342 static int 343 start_all_aps(u_int boot_addr) 344 { 345 vm_offset_t va = boot_address + KERNBASE; 346 u_int64_t *pt4, *pt3, *pt2; 347 int x, i, pg; 348 int shift; 349 int smicount; 350 int smibest; 351 int smilast; 352 u_char mpbiosreason; 353 u_long mpbioswarmvec; 354 struct mdglobaldata *gd; 355 struct privatespace *ps; 356 357 POSTCODE(START_ALL_APS_POST); 358 359 /* install the AP 1st level boot code */ 360 pmap_kenter(va, boot_address); 361 cpu_invlpg((void *)va); /* JG XXX */ 362 bcopy(mptramp_start, (void *)va, bootMP_size); 363 364 /* Locate the page tables, they'll be below the trampoline */ 365 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 366 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 367 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 368 369 /* Create the initial 1GB replicated page tables */ 370 for (i = 0; i < 512; i++) { 371 /* Each slot of the level 4 pages points to the same level 3 page */ 372 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 373 pt4[i] |= PG_V | PG_RW | PG_U; 374 375 /* Each slot of the level 3 pages points to the same level 2 page */ 376 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 377 pt3[i] |= PG_V | PG_RW | PG_U; 378 379 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 380 pt2[i] = i * (2 * 1024 * 1024); 381 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 382 } 383 384 /* save the current value of the warm-start vector */ 385 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 386 outb(CMOS_REG, BIOS_RESET); 387 mpbiosreason = inb(CMOS_DATA); 388 389 /* setup a vector to our boot code */ 390 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 391 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 392 outb(CMOS_REG, BIOS_RESET); 393 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 394 395 /* 396 * If we have a TSC we can figure out the SMI interrupt rate. 397 * The SMI does not necessarily use a constant rate. Spend 398 * up to 250ms trying to figure it out. 399 */ 400 smibest = 0; 401 if (cpu_feature & CPUID_TSC) { 402 set_apic_timer(275000); 403 smilast = read_apic_timer(); 404 for (x = 0; x < 20 && read_apic_timer(); ++x) { 405 smicount = smitest(); 406 if (smibest == 0 || smilast - smicount < smibest) 407 smibest = smilast - smicount; 408 smilast = smicount; 409 } 410 if (smibest > 250000) 411 smibest = 0; 412 if (smibest) { 413 smibest = smibest * (int64_t)1000000 / 414 get_apic_timer_frequency(); 415 } 416 } 417 if (smibest) 418 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n", 419 1000000 / smibest, smibest); 420 421 /* start each AP */ 422 for (x = 1; x <= naps; ++x) { 423 424 /* This is a bit verbose, it will go away soon. */ 425 426 /* first page of AP's private space */ 427 pg = x * x86_64_btop(sizeof(struct privatespace)); 428 429 /* allocate new private data page(s) */ 430 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map, 431 MDGLOBALDATA_BASEALLOC_SIZE); 432 433 gd = &CPU_prvspace[x].mdglobaldata; /* official location */ 434 bzero(gd, sizeof(*gd)); 435 gd->mi.gd_prvspace = ps = &CPU_prvspace[x]; 436 437 /* prime data page for it to use */ 438 mi_gdinit(&gd->mi, x); 439 cpu_gdinit(gd, x); 440 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (naps + 1)); 441 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (naps + 1)); 442 443 /* setup a vector to our boot code */ 444 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 445 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 446 outb(CMOS_REG, BIOS_RESET); 447 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 448 449 /* 450 * Setup the AP boot stack 451 */ 452 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2]; 453 bootAP = x; 454 455 /* attempt to start the Application Processor */ 456 CHECK_INIT(99); /* setup checkpoints */ 457 if (!start_ap(gd, boot_addr, smibest)) { 458 kprintf("\nAP #%d (PHY# %d) failed!\n", 459 x, CPUID_TO_APICID(x)); 460 CHECK_PRINT("trace"); /* show checkpoints */ 461 /* better panic as the AP may be running loose */ 462 kprintf("panic y/n? [y] "); 463 if (cngetc() != 'n') 464 panic("bye-bye"); 465 } 466 CHECK_PRINT("trace"); /* show checkpoints */ 467 } 468 469 /* set ncpus to 1 + highest logical cpu. Not all may have come up */ 470 ncpus = x; 471 472 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */ 473 for (shift = 0; (1 << shift) <= ncpus; ++shift) 474 ; 475 --shift; 476 ncpus2_shift = shift; 477 ncpus2 = 1 << shift; 478 ncpus2_mask = ncpus2 - 1; 479 480 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */ 481 if ((1 << shift) < ncpus) 482 ++shift; 483 ncpus_fit = 1 << shift; 484 ncpus_fit_mask = ncpus_fit - 1; 485 486 /* build our map of 'other' CPUs */ 487 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 488 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 489 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 490 491 /* restore the warmstart vector */ 492 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 493 outb(CMOS_REG, BIOS_RESET); 494 outb(CMOS_DATA, mpbiosreason); 495 496 /* 497 * NOTE! The idlestack for the BSP was setup by locore. Finish 498 * up, clean out the P==V mapping we did earlier. 499 */ 500 pmap_set_opt(); 501 502 /* 503 * Wait all APs to finish initializing LAPIC 504 */ 505 mp_finish_lapic = 1; 506 if (bootverbose) 507 kprintf("SMP: Waiting APs LAPIC initialization\n"); 508 if (cpu_feature & CPUID_TSC) 509 tsc0_offset = rdtsc(); 510 tsc_offsets[0] = 0; 511 rel_mplock(); 512 while (smp_lapic_mask != smp_startup_mask) { 513 cpu_lfence(); 514 if (cpu_feature & CPUID_TSC) 515 tsc0_offset = rdtsc(); 516 } 517 while (try_mplock() == 0) 518 ; 519 520 /* number of APs actually started */ 521 return ncpus - 1; 522 } 523 524 525 /* 526 * load the 1st level AP boot code into base memory. 527 */ 528 529 /* targets for relocation */ 530 extern void bigJump(void); 531 extern void bootCodeSeg(void); 532 extern void bootDataSeg(void); 533 extern void MPentry(void); 534 extern u_int MP_GDT; 535 extern u_int mp_gdtbase; 536 537 #if 0 538 539 static void 540 install_ap_tramp(u_int boot_addr) 541 { 542 int x; 543 int size = *(int *) ((u_long) & bootMP_size); 544 u_char *src = (u_char *) ((u_long) bootMP); 545 u_char *dst = (u_char *) boot_addr + KERNBASE; 546 u_int boot_base = (u_int) bootMP; 547 u_int8_t *dst8; 548 u_int16_t *dst16; 549 u_int32_t *dst32; 550 551 POSTCODE(INSTALL_AP_TRAMP_POST); 552 553 for (x = 0; x < size; ++x) 554 *dst++ = *src++; 555 556 /* 557 * modify addresses in code we just moved to basemem. unfortunately we 558 * need fairly detailed info about mpboot.s for this to work. changes 559 * to mpboot.s might require changes here. 560 */ 561 562 /* boot code is located in KERNEL space */ 563 dst = (u_char *) boot_addr + KERNBASE; 564 565 /* modify the lgdt arg */ 566 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 567 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 568 569 /* modify the ljmp target for MPentry() */ 570 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 571 *dst32 = ((u_int) MPentry - KERNBASE); 572 573 /* modify the target for boot code segment */ 574 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 575 dst8 = (u_int8_t *) (dst16 + 1); 576 *dst16 = (u_int) boot_addr & 0xffff; 577 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 578 579 /* modify the target for boot data segment */ 580 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 581 dst8 = (u_int8_t *) (dst16 + 1); 582 *dst16 = (u_int) boot_addr & 0xffff; 583 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 584 } 585 586 #endif 587 588 /* 589 * This function starts the AP (application processor) identified 590 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 591 * to accomplish this. This is necessary because of the nuances 592 * of the different hardware we might encounter. It ain't pretty, 593 * but it seems to work. 594 * 595 * NOTE: eventually an AP gets to ap_init(), which is called just 596 * before the AP goes into the LWKT scheduler's idle loop. 597 */ 598 static int 599 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest) 600 { 601 int physical_cpu; 602 int vector; 603 u_long icr_lo, icr_hi; 604 605 POSTCODE(START_AP_POST); 606 607 /* get the PHYSICAL APIC ID# */ 608 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid); 609 610 /* calculate the vector */ 611 vector = (boot_addr >> 12) & 0xff; 612 613 /* We don't want anything interfering */ 614 cpu_disable_intr(); 615 616 /* Make sure the target cpu sees everything */ 617 wbinvd(); 618 619 /* 620 * Try to detect when a SMI has occurred, wait up to 200ms. 621 * 622 * If a SMI occurs during an AP reset but before we issue 623 * the STARTUP command, the AP may brick. To work around 624 * this problem we hold off doing the AP startup until 625 * after we have detected the SMI. Hopefully another SMI 626 * will not occur before we finish the AP startup. 627 * 628 * Retries don't seem to help. SMIs have a window of opportunity 629 * and if USB->legacy keyboard emulation is enabled in the BIOS 630 * the interrupt rate can be quite high. 631 * 632 * NOTE: Don't worry about the L1 cache load, it might bloat 633 * ldelta a little but ndelta will be so huge when the SMI 634 * occurs the detection logic will still work fine. 635 */ 636 if (smibest) { 637 set_apic_timer(200000); 638 smitest(); 639 } 640 641 /* 642 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 643 * and running the target CPU. OR this INIT IPI might be latched (P5 644 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 645 * ignored. 646 * 647 * see apic/apicreg.h for icr bit definitions. 648 * 649 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH. 650 */ 651 652 /* 653 * Setup the address for the target AP. We can setup 654 * icr_hi once and then just trigger operations with 655 * icr_lo. 656 */ 657 icr_hi = lapic->icr_hi & ~APIC_ID_MASK; 658 icr_hi |= (physical_cpu << 24); 659 icr_lo = lapic->icr_lo & 0xfff00000; 660 lapic->icr_hi = icr_hi; 661 662 /* 663 * Do an INIT IPI: assert RESET 664 * 665 * Use edge triggered mode to assert INIT 666 */ 667 lapic->icr_lo = icr_lo | 0x00004500; 668 while (lapic->icr_lo & APIC_DELSTAT_MASK) 669 /* spin */ ; 670 671 /* 672 * The spec calls for a 10ms delay but we may have to use a 673 * MUCH lower delay to avoid bricking an AP due to a fast SMI 674 * interrupt. We have other loops here too and dividing by 2 675 * doesn't seem to be enough even after subtracting 350us, 676 * so we divide by 4. 677 * 678 * Our minimum delay is 150uS, maximum is 10ms. If no SMI 679 * interrupt was detected we use the full 10ms. 680 */ 681 if (smibest == 0) 682 u_sleep(10000); 683 else if (smibest < 150 * 4 + 350) 684 u_sleep(150); 685 else if ((smibest - 350) / 4 < 10000) 686 u_sleep((smibest - 350) / 4); 687 else 688 u_sleep(10000); 689 690 /* 691 * Do an INIT IPI: deassert RESET 692 * 693 * Use level triggered mode to deassert. It is unclear 694 * why we need to do this. 695 */ 696 lapic->icr_lo = icr_lo | 0x00008500; 697 while (lapic->icr_lo & APIC_DELSTAT_MASK) 698 /* spin */ ; 699 u_sleep(150); /* wait 150us */ 700 701 /* 702 * Next we do a STARTUP IPI: the previous INIT IPI might still be 703 * latched, (P5 bug) this 1st STARTUP would then terminate 704 * immediately, and the previously started INIT IPI would continue. OR 705 * the previous INIT IPI has already run. and this STARTUP IPI will 706 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 707 * will run. 708 */ 709 lapic->icr_lo = icr_lo | 0x00000600 | vector; 710 while (lapic->icr_lo & APIC_DELSTAT_MASK) 711 /* spin */ ; 712 u_sleep(200); /* wait ~200uS */ 713 714 /* 715 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 716 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 717 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 718 * recognized after hardware RESET or INIT IPI. 719 */ 720 lapic->icr_lo = icr_lo | 0x00000600 | vector; 721 while (lapic->icr_lo & APIC_DELSTAT_MASK) 722 /* spin */ ; 723 724 /* Resume normal operation */ 725 cpu_enable_intr(); 726 727 /* wait for it to start, see ap_init() */ 728 set_apic_timer(5000000);/* == 5 seconds */ 729 while (read_apic_timer()) { 730 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid)) 731 return 1; /* return SUCCESS */ 732 } 733 734 return 0; /* return FAILURE */ 735 } 736 737 static 738 int 739 smitest(void) 740 { 741 int64_t ltsc; 742 int64_t ntsc; 743 int64_t ldelta; 744 int64_t ndelta; 745 int count; 746 747 ldelta = 0; 748 ndelta = 0; 749 while (read_apic_timer()) { 750 ltsc = rdtsc(); 751 for (count = 0; count < 100; ++count) 752 ntsc = rdtsc(); /* force loop to occur */ 753 if (ldelta) { 754 ndelta = ntsc - ltsc; 755 if (ldelta > ndelta) 756 ldelta = ndelta; 757 if (ndelta > ldelta * 2) 758 break; 759 } else { 760 ldelta = ntsc - ltsc; 761 } 762 } 763 return(read_apic_timer()); 764 } 765 766 /* 767 * Synchronously flush the TLB on all other CPU's. The current cpu's 768 * TLB is not flushed. If the caller wishes to flush the current cpu's 769 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb(). 770 * 771 * NOTE: If for some reason we were unable to start all cpus we cannot 772 * safely use broadcast IPIs. 773 */ 774 775 static cpumask_t smp_invltlb_req; 776 777 #define SMP_INVLTLB_DEBUG 778 779 void 780 smp_invltlb(void) 781 { 782 struct mdglobaldata *md = mdcpu; 783 #ifdef SMP_INVLTLB_DEBUG 784 long count = 0; 785 long xcount = 0; 786 #endif 787 788 crit_enter_gd(&md->mi); 789 md->gd_invltlb_ret = 0; 790 ++md->mi.gd_cnt.v_smpinvltlb; 791 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 792 #ifdef SMP_INVLTLB_DEBUG 793 again: 794 #endif 795 if (smp_startup_mask == smp_active_mask) { 796 all_but_self_ipi(XINVLTLB_OFFSET); 797 } else { 798 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask, 799 XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 800 } 801 802 #ifdef SMP_INVLTLB_DEBUG 803 if (xcount) 804 kprintf("smp_invltlb: ipi sent\n"); 805 #endif 806 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) != 807 (smp_active_mask & ~md->mi.gd_cpumask)) { 808 cpu_mfence(); 809 cpu_pause(); 810 #ifdef SMP_INVLTLB_DEBUG 811 /* DEBUGGING */ 812 if (++count == 400000000) { 813 print_backtrace(-1); 814 kprintf("smp_invltlb: endless loop %08lx %08lx, " 815 "rflags %016jx retry", 816 (long)md->gd_invltlb_ret, 817 (long)smp_invltlb_req, 818 (intmax_t)read_rflags()); 819 __asm __volatile ("sti"); 820 ++xcount; 821 if (xcount > 2) 822 lwkt_process_ipiq(); 823 if (xcount > 3) { 824 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret & 825 ~md->mi.gd_cpumask & 826 smp_active_mask); 827 globaldata_t xgd; 828 829 kprintf("bcpu %d\n", bcpu); 830 xgd = globaldata_find(bcpu); 831 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm); 832 } 833 if (xcount > 5) 834 Debugger("giving up"); 835 count = 0; 836 goto again; 837 } 838 #endif 839 } 840 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 841 crit_exit_gd(&md->mi); 842 } 843 844 /* 845 * Called from Xinvltlb assembly with interrupts disabled. We didn't 846 * bother to bump the critical section count or nested interrupt count 847 * so only do very low level operations here. 848 */ 849 void 850 smp_invltlb_intr(void) 851 { 852 struct mdglobaldata *md = mdcpu; 853 struct mdglobaldata *omd; 854 cpumask_t mask; 855 int cpu; 856 857 cpu_mfence(); 858 mask = smp_invltlb_req; 859 cpu_invltlb(); 860 while (mask) { 861 cpu = BSFCPUMASK(mask); 862 mask &= ~CPUMASK(cpu); 863 omd = (struct mdglobaldata *)globaldata_find(cpu); 864 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask); 865 } 866 } 867 868 void 869 cpu_wbinvd_on_all_cpus_callback(void *arg) 870 { 871 wbinvd(); 872 } 873 874 /* 875 * When called the executing CPU will send an IPI to all other CPUs 876 * requesting that they halt execution. 877 * 878 * Usually (but not necessarily) called with 'other_cpus' as its arg. 879 * 880 * - Signals all CPUs in map to stop. 881 * - Waits for each to stop. 882 * 883 * Returns: 884 * -1: error 885 * 0: NA 886 * 1: ok 887 * 888 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 889 * from executing at same time. 890 */ 891 int 892 stop_cpus(cpumask_t map) 893 { 894 map &= smp_active_mask; 895 896 /* send the Xcpustop IPI to all CPUs in map */ 897 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 898 899 while ((stopped_cpus & map) != map) 900 /* spin */ ; 901 902 return 1; 903 } 904 905 906 /* 907 * Called by a CPU to restart stopped CPUs. 908 * 909 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 910 * 911 * - Signals all CPUs in map to restart. 912 * - Waits for each to restart. 913 * 914 * Returns: 915 * -1: error 916 * 0: NA 917 * 1: ok 918 */ 919 int 920 restart_cpus(cpumask_t map) 921 { 922 /* signal other cpus to restart */ 923 started_cpus = map & smp_active_mask; 924 925 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 926 /* spin */ ; 927 928 return 1; 929 } 930 931 /* 932 * This is called once the mpboot code has gotten us properly relocated 933 * and the MMU turned on, etc. ap_init() is actually the idle thread, 934 * and when it returns the scheduler will call the real cpu_idle() main 935 * loop for the idlethread. Interrupts are disabled on entry and should 936 * remain disabled at return. 937 */ 938 void 939 ap_init(void) 940 { 941 int cpu_id; 942 943 /* 944 * Adjust smp_startup_mask to signal the BSP that we have started 945 * up successfully. Note that we do not yet hold the BGL. The BSP 946 * is waiting for our signal. 947 * 948 * We can't set our bit in smp_active_mask yet because we are holding 949 * interrupts physically disabled and remote cpus could deadlock 950 * trying to send us an IPI. 951 */ 952 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid); 953 cpu_mfence(); 954 955 /* 956 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is 957 * non-zero, then get the MP lock. 958 * 959 * Note: We are in a critical section. 960 * 961 * Note: we are the idle thread, we can only spin. 962 * 963 * Note: The load fence is memory volatile and prevents the compiler 964 * from improperly caching mp_finish_lapic, and the cpu from improperly 965 * caching it. 966 */ 967 while (mp_finish_lapic == 0) 968 cpu_lfence(); 969 while (try_mplock() == 0) 970 ; 971 972 if (cpu_feature & CPUID_TSC) { 973 /* 974 * The BSP is constantly updating tsc0_offset, figure out 975 * the relative difference to synchronize ktrdump. 976 */ 977 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset; 978 } 979 980 /* BSP may have changed PTD while we're waiting for the lock */ 981 cpu_invltlb(); 982 983 /* Build our map of 'other' CPUs. */ 984 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 985 986 /* A quick check from sanity claus */ 987 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24); 988 if (mycpu->gd_cpuid != cpu_id) { 989 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid); 990 kprintf("SMP: actual cpuid = %d lapicid %d\n", 991 cpu_id, (lapic->id & 0xff000000) >> 24); 992 #if JGXXX 993 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 994 #endif 995 panic("cpuid mismatch! boom!!"); 996 } 997 998 /* Initialize AP's local APIC for irq's */ 999 lapic_init(FALSE); 1000 1001 /* LAPIC initialization is done */ 1002 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid); 1003 cpu_mfence(); 1004 1005 /* Let BSP move onto the next initialization stage */ 1006 rel_mplock(); 1007 1008 /* 1009 * Interlock for finalization. Wait until mp_finish is non-zero, 1010 * then get the MP lock. 1011 * 1012 * Note: We are in a critical section. 1013 * 1014 * Note: we are the idle thread, we can only spin. 1015 * 1016 * Note: The load fence is memory volatile and prevents the compiler 1017 * from improperly caching mp_finish, and the cpu from improperly 1018 * caching it. 1019 */ 1020 while (mp_finish == 0) 1021 cpu_lfence(); 1022 while (try_mplock() == 0) 1023 ; 1024 1025 /* BSP may have changed PTD while we're waiting for the lock */ 1026 cpu_invltlb(); 1027 1028 /* Set memory range attributes for this CPU to match the BSP */ 1029 mem_range_AP_init(); 1030 1031 /* 1032 * Once we go active we must process any IPIQ messages that may 1033 * have been queued, because no actual IPI will occur until we 1034 * set our bit in the smp_active_mask. If we don't the IPI 1035 * message interlock could be left set which would also prevent 1036 * further IPIs. 1037 * 1038 * The idle loop doesn't expect the BGL to be held and while 1039 * lwkt_switch() normally cleans things up this is a special case 1040 * because we returning almost directly into the idle loop. 1041 * 1042 * The idle thread is never placed on the runq, make sure 1043 * nothing we've done put it there. 1044 */ 1045 KKASSERT(get_mplock_count(curthread) == 1); 1046 smp_active_mask |= CPUMASK(mycpu->gd_cpuid); 1047 1048 /* 1049 * Enable interrupts here. idle_restore will also do it, but 1050 * doing it here lets us clean up any strays that got posted to 1051 * the CPU during the AP boot while we are still in a critical 1052 * section. 1053 */ 1054 __asm __volatile("sti; pause; pause"::); 1055 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 1056 1057 initclocks_pcpu(); /* clock interrupts (via IPIs) */ 1058 lwkt_process_ipiq(); 1059 1060 /* 1061 * Releasing the mp lock lets the BSP finish up the SMP init 1062 */ 1063 rel_mplock(); 1064 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0); 1065 } 1066 1067 /* 1068 * Get SMP fully working before we start initializing devices. 1069 */ 1070 static 1071 void 1072 ap_finish(void) 1073 { 1074 mp_finish = 1; 1075 if (bootverbose) 1076 kprintf("Finish MP startup\n"); 1077 rel_mplock(); 1078 while (smp_active_mask != smp_startup_mask) 1079 cpu_lfence(); 1080 while (try_mplock() == 0) 1081 ; 1082 if (bootverbose) { 1083 kprintf("Active CPU Mask: %016jx\n", 1084 (uintmax_t)smp_active_mask); 1085 } 1086 } 1087 1088 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL) 1089 1090 void 1091 cpu_send_ipiq(int dcpu) 1092 { 1093 if (CPUMASK(dcpu) & smp_active_mask) 1094 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED); 1095 } 1096 1097 #if 0 /* single_apic_ipi_passive() not working yet */ 1098 /* 1099 * Returns 0 on failure, 1 on success 1100 */ 1101 int 1102 cpu_send_ipiq_passive(int dcpu) 1103 { 1104 int r = 0; 1105 if (CPUMASK(dcpu) & smp_active_mask) { 1106 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET, 1107 APIC_DELMODE_FIXED); 1108 } 1109 return(r); 1110 } 1111 #endif 1112 1113 static void 1114 mp_bsp_simple_setup(void) 1115 { 1116 /* build our map of 'other' CPUs */ 1117 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 1118 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 1119 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 1120 1121 pmap_set_opt(); 1122 1123 if (cpu_feature & CPUID_TSC) 1124 tsc0_offset = rdtsc(); 1125 } 1126 1127 1128 /* 1129 * CPU TOPOLOGY DETECTION FUNCTIONS 1130 */ 1131 1132 /* Detect intel topology using CPUID 1133 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41 1134 */ 1135 static void 1136 detect_intel_topology(int count_htt_cores) 1137 { 1138 int shift = 0; 1139 int ecx_index = 0; 1140 int core_plus_logical_bits = 0; 1141 int cores_per_package; 1142 int logical_per_package; 1143 int logical_per_core; 1144 unsigned int p[4]; 1145 1146 if (cpu_high >= 0xb) { 1147 goto FUNC_B; 1148 1149 } else if (cpu_high >= 0x4) { 1150 goto FUNC_4; 1151 1152 } else { 1153 core_bits = 0; 1154 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1155 ; 1156 logical_CPU_bits = 1 << shift; 1157 return; 1158 } 1159 1160 FUNC_B: 1161 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p); 1162 1163 /* if 0xb not supported - fallback to 0x4 */ 1164 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) { 1165 goto FUNC_4; 1166 } 1167 1168 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1169 1170 ecx_index = FUNC_B_THREAD_LEVEL + 1; 1171 do { 1172 cpuid_count(0xb, ecx_index, p); 1173 1174 /* Check for the Core type in the implemented sub leaves. */ 1175 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) { 1176 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1177 break; 1178 } 1179 1180 ecx_index++; 1181 1182 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE); 1183 1184 core_bits = core_plus_logical_bits - logical_CPU_bits; 1185 1186 return; 1187 1188 FUNC_4: 1189 cpuid_count(0x4, 0, p); 1190 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1; 1191 1192 logical_per_package = count_htt_cores; 1193 logical_per_core = logical_per_package / cores_per_package; 1194 1195 for (shift = 0; (1 << shift) < logical_per_core; ++shift) 1196 ; 1197 logical_CPU_bits = shift; 1198 1199 for (shift = 0; (1 << shift) < cores_per_package; ++shift) 1200 ; 1201 core_bits = shift; 1202 1203 return; 1204 } 1205 1206 /* Detect AMD topology using CPUID 1207 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page 1208 */ 1209 static void 1210 detect_amd_topology(int count_htt_cores) 1211 { 1212 int shift = 0; 1213 if ((cpu_feature & CPUID_HTT) 1214 && (amd_feature2 & AMDID2_CMP)) { 1215 1216 if (cpu_procinfo2 & AMDID_COREID_SIZE) { 1217 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) 1218 >> AMDID_COREID_SIZE_SHIFT; 1219 } else { 1220 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 1221 for (shift = 0; (1 << shift) < core_bits; ++shift) 1222 ; 1223 core_bits = shift; 1224 } 1225 1226 logical_CPU_bits = count_htt_cores >> core_bits; 1227 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift) 1228 ; 1229 logical_CPU_bits = shift; 1230 } else { 1231 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1232 ; 1233 core_bits = shift; 1234 logical_CPU_bits = 0; 1235 } 1236 } 1237 1238 /* Calculate 1239 * - logical_CPU_bits 1240 * - core_bits 1241 * With the values above (for AMD or INTEL) we are able to generally 1242 * detect the CPU topology (number of cores for each level): 1243 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1244 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf 1245 */ 1246 void 1247 detect_cpu_topology(void) 1248 { 1249 static int topology_detected = 0; 1250 int count = 0; 1251 1252 if (topology_detected) { 1253 goto OUT; 1254 } 1255 1256 if ((cpu_feature & CPUID_HTT) == 0) { 1257 core_bits = 0; 1258 logical_CPU_bits = 0; 1259 goto OUT; 1260 } else { 1261 count = (cpu_procinfo & CPUID_HTT_CORES) 1262 >> CPUID_HTT_CORE_SHIFT; 1263 } 1264 1265 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 1266 detect_intel_topology(count); 1267 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 1268 detect_amd_topology(count); 1269 } 1270 1271 OUT: 1272 if (bootverbose) 1273 kprintf("BITS within APICID: logical_CPU_bits: %d; core_bits: %d\n", 1274 logical_CPU_bits, core_bits); 1275 1276 topology_detected = 1; 1277 } 1278 1279 /* Interface functions to calculate chip_ID, 1280 * core_number and logical_number 1281 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1282 */ 1283 int 1284 get_chip_ID(int cpuid) 1285 { 1286 return get_apicid_from_cpuid(cpuid) >> 1287 (logical_CPU_bits + core_bits); 1288 } 1289 1290 int 1291 get_core_number_within_chip(int cpuid) 1292 { 1293 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) & 1294 ( (1 << core_bits) -1); 1295 } 1296 1297 int 1298 get_logical_CPU_number_within_core(int cpuid) 1299 { 1300 return get_apicid_from_cpuid(cpuid) & 1301 ( (1 << logical_CPU_bits) -1); 1302 } 1303